JPS63209169A - Insulated-gate thyristor - Google Patents

Abstract

PURPOSE:To increase the turn off capacity and the inverse breakdown strength by a method wherein the first gate electrode for torn-on in a MOS structure and the second gate electrode for turn-off in direct contact with the second base layer are provided while a region held by the second gate electrode of the second base layer and the second emitter layer region is formed into a low concentration layer. CONSTITUTION:The first n type base layer 2 is formed in contact with the first n type emitter layer 1 while the second base layer 3 and the second emitter layer 4 are successively formed in the first layer 2 to form a pnpn structure. An anode electrode (the first main electrode)9 is formed on the rear of the first emitter layer 1 while a cathode electrode (the second main electrode)7 is formed on the surface of the second emitter layer 4. The second base layer 3 is composed of a low concentration p type layer 31 and a high concentration p<+>type layer 32 while the first electrode 6 is formed on a channel region CH held by the second emitter layer 4 on the surface of p type layer 31 and the first base layer 2 through the intermediary of a gate insulating film 5. Through these procedures, the turn off capacity can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an insulated gate thyristor that performs turn-on control using an insulated gate.

(Prior Art) A self-turn-off thigh lifter that performs on-off control using an insulated gate is conventionally known as shown in FIG. 10. This has a pnpn thyristor structure in which an n-type base layer 22 is formed in contact with an n-type emitter layer 21, and a p-type base 1123 and an n-type emitter layer 24 are sequentially diffused into this n-type base 1) 22. . An anode electrode 32 is formed on the n-type emitter layer 21, and a cathode electrode 27 is formed on the n-type emitter R24. The surface of the p-type base layer 23 sandwiched between the n-type emitter layer 24 and the n-type base R22 is used as a channel region CH1, and a gate electrode 26 is formed thereon via a gate insulating film 25 to form an n-channel MOS for turn-on. It constitutes FET. Further, a p-type base layer 23 is adjacent to the n-type emitter layer 24.
An n-type layer 28 is provided inside, and the surface portion of the p-type base layer 23 between this n-type layer 28 and the n-type emitter layer 24 is used as a channel region CH.
Gate insulation M on top of this as 2! A gate electrode 30 is formed through the gate electrode 29, and the n-channel MO8FE for turn-off is formed.
It constitutes T. The n-type layer 28 is short-circuited to the n-type base layer 23 by an electrode 31.

The operation of this element is as follows. MO for turn-on
When a positive voltage is applied to the gate electrode 26 (Gt) of S F E T, the channel region 1CH1 under it becomes conductive, and n
Electrons are injected from the type emitter layer 24 into the n-type base layer 22, and corresponding holes are injected from the n-type emitter layer 21, resulting in the thyristor being turned on. When the voltage of the gate electrode 26 is set to zero and a positive voltage is applied to the gate electrode 30 (G2) of the turn-off MO8FET, n
The type emitter layer 24 is a channel region C under the gate electrode 30.
It is short-circuited with the n-type layer 28 through H2, and further short-circuited with the p-type base P23 through the electrode 31. This turns off the thyristor.

Figure 10 shows an example in which both the MO8FET for turn-on and the MO8FET for turn-off are n-channel, but the MO8FET for turn-on is n-channel, and the MO8FET for turn-off is
A structure in which the O8FET is an n-channel is also known. Its structure is shown in FIG. p-type emitter [121, n-type base layer 22°n-type base layer 23. N-type emitter layer 24
It has a pnpnll structure, and the anode electrode 32. The basic structure including the cathode electrode 27 is the same as in FIG. 1st
The difference from Figure 0 is that an n-type layer 33 is provided in the n-type emitter layer 24 (actually, as shown in the figure, a low-concentration n-type layer is diffused and formed continuously outside the high-concentration n-type emitter layer). This PO 33 is short-circuited with the n-type emitter layer 24 by the cathode electrode 27, and is continuously formed on the surface of the region sandwiched between the n-type layer 33 and the n-type base 1122 via the gate insulating film 25. One gate electrode 26 is formed. That is, p-type 1133 and p-type base II! The n-channel MO8FET for turn-off uses the surface of the n-type emitter layer 24 in the region sandwiched between the two as the channel region CH2, and the surface of the p-type base 123 between the n-type emitter layer 24 and the n-type base layer 22 as the channel region CH1. A turn-on n-channel MO8FET is formed using the gate electrode 26 in common.

In this device, when a positive voltage is applied to the gate electrode 26, the n-channel MO8FET becomes conductive and the thyristor is turned on. When a negative voltage is applied to the same gate electrode 26, the p-channel MO8FET becomes conductive and the thyristor is turned off.

In such a self-turn-off thyristor that performs on/off operations using an insulated gate (MOS gate), the turn-off M, which should originally be on both sides of the n-type emitter layer,
One of the OS gates must be replaced with a turn-on MOS gate, and there is a problem in that the turn-off ability is reduced to approximately 1/2 compared to the case where turn-off MOS gates are provided on both sides of the n-type emitter layer. .

Immediately, the structure in which the n-channel MO8FET shown in Fig. 10 is provided for turn-off (n-channel MO8GTO)
In this case, since only one channel region CH2 of the MOSFET channel regions CH1 and 0H2, which is located on both sides of the n-type emitter layer and accounts for most of the short-circuit resistance, is used for turn-off, the short-circuit resistance is lower than when both sides are used for turn-off. The current is doubled, and the peak turn-off current is halved. Further, since there is lateral resistance in the n-type base layer 23 under the n-type emitter F124, when a turn-off operation is performed, the portion close to the channel region CH1 under the turn-on gate electrode 26 turns off the latest. Therefore, if the lateral resistance of the n-type base layer 23 is greater than a certain level, turn-off will not be possible.

In the thyristor (p-channel MO8GTO) shown in FIG. 11, which has a structure in which the p-channel MO8FET short-circuits the n-type emitter layer 24 and the p-type base 1823, the turn-off channel region CH2 is on both sides.

However, in this case as well, the channel region CH1 for turn-on
The channel region CH2 in contact with the channel region CH2 hardly contributes to the turn-off operation. This is because during turn-off, the channel region C
The surface part of the p-type base layer 23 that is electrically connected to the p-type layer 33 through H2 serves as a turn-on channel region CH1, so the resistance of this part is quite large, and almost no short-circuit current can flow through it. be. Therefore, in this structure as well, the portion close to the channel region CH1 turns off the latest, and if the lateral resistance of the p-type base W423 is large, it cannot be turned off.

Furthermore, in both the structures shown in FIGS. 10 and 11, the resistance of the p-type base layer 23 is large. This is because the channel region CH1 is formed on the surface of the p-type base layer, so the impurity concentration cannot be increased to set the threshold value to an appropriate value, and if the diffusion depth of the p-type base layer is increased,
This is because the channel length of the turn-on channel region CH1 increases, and the resistance of the turn-on MO8FET increases.

(Problems to be Solved by the Invention) As described above, the conventional insulated gate self-turn-off thyristor has a problem in that the turn-off ability is significantly reduced by providing a turn-on MOS gate.

It is an object of the present invention to provide an insulated gate thyristor which solves these problems and improves turn-off performance.

[Structure of the Invention] (Means for Solving the Problems) An insulated gate thyristor according to the present invention has a first base layer of a second conductivity type in contact with a first emitter layer of the first conductivity type, A second base layer of a first conductivity type and a second emitter layer of a second conductivity type are formed by diffusion on the surface of the first base layer, and a first main N pole is formed in the first emitter layer and a first main N pole is formed in the second emitter layer. A second main electrode is provided respectively, and a region sandwiched between the second emitter layer and the first base layer on the surface of the second base layer is used as a channel region, and a first gate electrode for turn-on is disposed on the channel region via a gate insulating film. is formed, and a second gate electrode for turn-off is provided directly on the surface of the second base layer, and at least a region of the second base layer sandwiched between the second main electrode and the second gate electrode is formed. A feature is that the surface portion has a lower concentration layer than the region under the second gate electrode.

(Function) With such a configuration, during turn-off, the second gate electrode is used to apply a reverse bias between the second base layer and the second emitter layer, thereby directing the current flowing from the first emitter layer to the second emitter layer. By bypassing the second gate electrode through the second base layer, large currents can be turned off. In addition, in this case, by making the surface portion of the region sandwiched between the second gate electrode of the second base layer and the second emitter layer have a lower impurity concentration than other regions, the second base layer The breakdown voltage between the second emitters can be increased.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. In all of the following examples, p type is used as the first conductivity type, and n type is used as the second conductivity type.

FIG. 1 is a sectional view showing a MOS gate type thyristor of a first embodiment. n in contact with the p-type first emitter layer 1
A p-type second base layer 3 and an n-type second emitter layer 4 are formed in the first base layer 2.
are sequentially diffused to form a pnpn structure. An anode N pole (first main electrode) 9 is formed in the first emitter layer 1 , and a cathode electrode (second main electrode) 7 is formed in the second emitter layer 4 . The second base layer 3 consists of a low concentration p-type wJ3t and a high concentration p+ type layer 32,
The second emitter layer 4 and the first base in the surface region of the p-type layer 31! A first gate electrode 6 is formed on the region sandwiched by the gate electrode 12 as a channel region CH with a gate insulating film 5 interposed therebetween. This makes the second emitter layer 4 the source and the first emitter layer 4 the source.
A turn-on MOS transistor having the base layer 2 as a drain is configured. High concentration p of second base 113
A second gate electrode 8 is formed in direct contact with the type 1 layer 32 .

The operation of this element will be explained using FIG. 2. In Figure 2 (
(a) shows changes in voltage and current between the anode and cathode, and (b) shows changes in voltage between the gate and cathode. When a positive voltage with respect to the cathode electrode 7 is applied to the first gate R pole 6 at time t1, an inversion layer is formed in the channel region CH, and the turn-on MOS transistor is triggered. As a result, the element starts turning on at time t2, and the turn-on is completed by time t3. In the turn-off operation, a negative voltage is applied to the second gate electrode 8 with respect to the cathode electrode 7 at time t4. As a result, carriers in the second base li3 are sucked out from the second gate electrode 8, and turn-off is completed between time ts and time t6.

The turn-off ability of the MOS gated thyristor of this example becomes low when the lateral resistance of the second base layer, especially the lateral resistance of the portion immediately below the second emitter layer, is large, as described in the conventional example. . However, in the present invention,
Unlike the conventional example shown in FIG. 10 or 11, which is turned off by a MOS t-transistor that uses a surface channel, carriers are extracted by directly reverse biasing between the second base layer and the second emitter layer. Therefore, it has a high turn-off ability.

FIG. 3 shows the turn-off ability of the MOS gate type thyristor of this embodiment in comparison with the conventional example shown in FIG. The horizontal axis in the figure is the lateral resistance of the second base layer directly under the second emitter layer. As is clear from the figure, in this embodiment, the second
Assuming that the lateral resistance of the base layer is the same as that of the conventional example, the turn-off ability is about three times higher. In other words, if the maximum turn-off current is the same as in the conventional example, the second base layer lateral resistance can be made sufficiently higher in this embodiment than in the conventional example. Therefore, according to this embodiment, the area of the second base layer where the second gate electrode 8 is provided is 81
By forming a single p+ type layer 32 and providing a high resistance between this and the second emitter WJ4, the withstand voltage between the gate and the cathode can be made sufficiently high.

Other embodiments of the invention will now be described. In the following embodiments, parts corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted.

FIG. 4 shows a MOS gate type thyristor according to a second embodiment of the present invention. In this embodiment, the second base layer 3 is composed of three parts: a lightly doped p-type layer 31, a heavily doped p+ type 132 which is a contact portion of the second gate electrode 8, and a heavily doped p+ type buried layer 39. It is composed of: p-type layer 3
! For example, lX10"/cx3~2X10"'
/1ya3. Moreover, the p+ type layer 33 is 2×1
The channel region CH of the MOS transistor is formed in the lightly doped p-type layer 3!.

With the structure of this embodiment, the resistance immediately below the second emitter 114 can be made lower, and therefore a higher turn-off ability can be provided.

Furthermore, since the high-resistance p-type layer 31 is inserted between the second gate electrode 8 and the cathode electrode 7, the reverse breakdown voltage therebetween can be made even higher, and a breakdown voltage of about 50 KV can be obtained.

FIG. 5 shows the relationship between the reverse breakdown voltage between the cathode and the second gate and the maximum turn-off current. It can be seen that the maximum turn-off current increases as the reverse withstand voltage between the cathode and the second gate increases by making the p-type second base high in resistance.

FIG. 6 shows a MOS gate type thyristor according to a third embodiment of the present invention. This is a modification of the structure shown in FIG. 4, in which the second emitter layer 4 is formed to a depth that reaches the buried p+ type N33. P-type layer 3 on the surface! This is the same as in the previous embodiment. Although the channel region 08 portion needs to be p-type, the surface region between the second gate electrode 8 and second emitter layer 4 may be p-type or n-type.

According to this embodiment as well, the reverse breakdown voltage between the second gate and the cathode can be kept sufficiently large, and the old turn-off ability can be exhibited.

FIG. 7 shows a MOS gate type thyristor according to a fourth embodiment of the present invention. In this example, the structure shown in Fig. 4 is modified,
Regarding the second base layer 3, the height 5r below the second gate electrode 8
The f1p" type H32 is diffused over a relatively wide range and sufficiently deep, and the buried p+ type layer 32 is omitted.

This embodiment also provides the same effects as those of the previous embodiments.

The present invention can be further modified in various ways. For example, FIG. 8 shows an n+ type buffer between the first base layer 2 and the first emitter 1111 in contrast to the structure shown in FIG. A layer 10 is provided. The average i11 of this n+ type buffer layer 10
For example, by setting the degree to 1X101'/ClR3 or more and the thickness to 10 μm or more, the thickness of the n-type first base layer 2 can be reduced by 2/2 without deteriorating the forward blocking voltage.
The blocking on-state voltage can be lowered by making it as thin as 3.3 mm.

Further, in FIG. 9, a part of the n+ type buffer layer 10 in FIG. 8 is exposed on the anode side surface, and a third gate electrode 1 is attached to this.
1 in contact. In this structure, at the time of turn-on, by applying a voltage that is negative with respect to the anode to the third gate electrode 11 at the same time as applying a voltage to the first gate electrode 6 or prior to that, the first emitter layer 1 to M1 Holes are injected into the base layer 2, thereby improving the turn-on switching speed.

[Effects of the Invention] As described above, according to the present invention, the structure includes a first gate electrode for turn-on having an MO8 structure and a second gate electrode for turn-off that directly contacts the second base layer. and a second gate N pole of the second base layer and a second gate N pole of the second base layer.
By making the region sandwiched between the emitter layer regions a lightly doped layer, it is possible to obtain an MO8 type thyristor with high turn-off ability and high reverse breakdown voltage between the second gate and the cathode.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the MO8 type thyristor of the first embodiment of the present invention, Fig. 2 is a waveform diagram for explaining its operation, and Fig. 3 is a diagram showing its turn-off ability in comparison with a conventional example. ,
FIG. 4 is a diagram showing the MO3 type thyristor according to the second embodiment of the present invention, and FIG. 5 is a diagram showing the maximum turn-off current and the cathode/second
FIG. 6, which is a diagram showing the relationship between gate-to-gate reverse breakdown voltage, is the third embodiment of the present invention.
FIG. 7 is a diagram showing an MO3 type thyristor according to the fourth embodiment of the present invention, and FIG.
9 and 9 show a MO8 type thyristor according to another embodiment, and FIGS. 10 and 11 show a conventional MO8 type thyristor. 1...p-type cylinder 1 emitter layer, 2...n-type first base 1.3...p-type box 2 base layer, 31...low concentration p-type layer, 32.33...high concentration Concentration p-type layer, 4...n-type second layer
Emitter layer, 5... Gate insulating film, 6... First gate N pole, 7... Cathode electrode (first main electrode), 8...
. . . second gate electrode, 9 . . . anode electrode (second main electrode), 10 . . . n+ type buffer 11! , 11...
Third gate electrode. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 3 Figure 4 Figure 5 Figure 7 Figure 8 Figure 9 Figure 10

Claims (2)

[Claims] (1) A first base layer of a second conductivity type is provided in contact with a first emitter layer of a first conductivity type, and a first emitter layer is provided on the surface of the first base layer.
A second base layer of a conductivity type and a second emitter layer of a second conductivity type are formed by diffusion, a first main electrode and a second main electrode are formed in the first emitter layer and the second emitter layer, respectively; The second emitter layer on the surface of the second base layer and the first
A first gate electrode is formed on the region sandwiched between the base layers as a channel region via a gate insulating film, a second gate electrode is formed on the second base layer, and the second gate electrode is formed on the second base layer. An insulated gate thyristor characterized in that the impurity concentration of at least a surface portion of a region sandwiched between a second main electrode and a second gate electrode is set to be lower than that of a region below the second gate electrode. (2) In the second base layer, the channel region and the surface region between the second main electrode and the second gate electrode are low concentration regions formed separately from other regions. The insulated gate thyristor according to item 1.