CN109860171B

CN109860171B - Bipolar silicon carbide semiconductor power device integrated with high-speed reverse freewheeling diode

Info

Publication number: CN109860171B
Application number: CN201910098138.2A
Authority: CN
Inventors: 孔谋夫
Original assignee: University of Electronic Science and Technology of China
Current assignee: LESHAN SHARE ELECTRONIC CO Ltd
Priority date: 2019-01-31
Filing date: 2019-01-31
Publication date: 2021-03-30
Anticipated expiration: 2039-01-31
Also published as: CN109860171A

Abstract

The invention belongs to the technical field of semiconductor power devices, and relates to a silicon carbide power semiconductor device, in particular to a bipolar silicon carbide semiconductor power device integrated with a high-speed reverse freewheeling diode, which is used for realizing the integration of the silicon carbide power device and the reverse freewheeling diode, and the integrated Schottky barrier FWD can realize lower diode conduction voltage drop and reduce reverse recovery time and loss. The invention can well reduce the application cost of the silicon carbide power semiconductor device and the number of peripheral devices when the device is applied, and has great application value.

Description

Bipolar silicon carbide semiconductor power device integrated with high-speed reverse freewheeling diode

Technical Field

The invention belongs to the technical field of semiconductor power devices, and particularly relates to a silicon carbide power semiconductor device, in particular to a bipolar silicon carbide semiconductor power device integrated with a high-speed reverse freewheeling diode.

Background

Compared with silicon materials, the silicon carbide material has the excellent characteristics of larger forbidden bandwidth, higher carrier saturation rate, larger thermal conductivity and the like, so that the performance of a power electronic device made of the silicon carbide material is far superior to that of the silicon material; the power device made of the silicon carbide material has lower conduction loss, lower switching loss and better voltage blocking capability, thereby having wide application prospect.

Typically, most power devices are used in switching circuits with inductive loads, which requires a Free-wheeling diode (FWD) to be connected in anti-parallel with the power device. The traditional method is to connect a FWD in parallel outside the power device, or to package the FWD and the power device together; for a silicon carbide power device, because the conventional silicon carbide PN junction diode has higher conduction voltage drop, and meanwhile, for the power device, the power device has a thicker drift region with lower doping concentration, the reverse freewheeling PIN diode manufactured by utilizing the body of the power device has higher conduction voltage drop, reverse recovery time and loss.

Disclosure of Invention

The invention aims to provide a bipolar silicon carbide semiconductor power device integrated with a high-speed reverse freewheeling diode, which is used for realizing the integration of the silicon carbide power device and an FWD (field-effect transistor), and simultaneously reducing the conduction voltage drop of the integrated silicon carbide diode and the reverse recovery time and loss.

In order to achieve the purpose, the technical scheme of the invention is as follows:

the utility model provides an integrated high-speed reverse freewheel diode's bipolar type carborundum semiconductor power device, includes that top-down stacks gradually the metallized cathode 1 that sets up, N type drift region 2, metallized anode 3, wherein:

the lower surface of the N-type drift region 2 is a back structure, and the back structure includes: an N-type buffer layer 4, an N-type anode region 17 and a P-type anode region 18; the N-type anode region 17 is adjacent to the P-type anode region 18 and is positioned below the N-type buffer layer 4, and the N-type anode region and the P-type anode region form ohmic contact with the upper surface of the metallized anode;

the upper surface of the N-type drift region 2 is a front structure, and the front structure includes: a first P type region 5, a P type cathode region 6, a first N type region 7, a second P type region 8, a second N type region 12, a groove 9, an oxide layer 10 in the groove and a grid 11; the trench 9 is formed in one side of the upper surface of the N-type drift region 2, an oxide layer 10 is filled in the trench 9, a grid 11 is arranged in the oxide layer 10, and a second P-type region 8 is arranged below the oxide layer 10; the first P-type region 5 is positioned above the N-type drift region 2, the P-type cathode region 6 is adjacent to the first N-type region 7 and is positioned above the first P-type region 5, ohmic contact is formed between the P-type cathode region 6 and the first N-type region 7 and the metallized cathode 1, and the first P-type region 5 and the first N-type region 7 are both contacted with the oxide layer 10; the second N-type region 12 penetrates through the first P-type region 5 and the P-type cathode region 6, and the upper part of the second N-type region 12 forms a schottky barrier contact with the metallized cathode 1, and the lower part of the second N-type region is in contact with the N-type drift region.

Further, the device further comprises a third N-type region 13, wherein the third N-type region 13 is in contact with the first N-type region 7 and the N-type drift region 2 from top to bottom, and the left and right are in contact with the first P-type region 5 and the oxide layer 10 from left to right.

The utility model provides an integrated high-speed reverse freewheel diode's bipolar type carborundum semiconductor power device, includes that top-down stacks gradually metallized cathode (K), N type drift region, metallized anode (A) that sets up, wherein:

the upper surface of the N-type drift region 2 is a front structure, and the front structure includes: a first P type cathode region 6-1, a second P type cathode region 6-2, a first N type region 7, a second P type region 8, a second N type region 12, a first groove 9, an oxide layer 10 and a grid 11 in the groove, and a second groove 15; the first trench 9 is formed in one side of the upper surface of the N-type drift region 2, an oxide layer 10 is filled in the first trench 9, a grid 11 is arranged in the oxide layer 10, and a second P-type region 8 is arranged below the oxide layer 10; the second trench 15 is formed on the other side of the upper surface of the N-type drift region 2, the first P-type cathode region 6-1 and the second P-type cathode region 6-2 are respectively located below and on the side of the second trench, the first N-type region 7 is located between the second P-type cathode region 6-2 and the oxide layer, and ohmic contact is formed between the first P-type cathode region 6-1, the second P-type cathode region 6-2 and the first N-type region 7 and the metalized source electrode 1; the second N-type region 12 is arranged between the first P-type cathode region 6-1 and the second P-type cathode region 6-2, is contacted with the first P-type cathode region 6-1, the second P-type cathode region 6-2, the first N-type region 7 and the oxide layer 10, forms Schottky barrier contact with the metalized source electrode 1 at the upper part, and is contacted with the N-type drift region at the lower part.

Furthermore, the device also comprises a first P-type region 5, wherein the upper part and the lower part of the first P-type region 5 are respectively contacted with the first N-type region 7 and the second N-type region 12, and the left part and the right part are respectively contacted with the second P-type cathode region 6-2 and the oxide layer 10.

The bipolar silicon carbide semiconductor power device integrated with the high-speed reverse freewheeling diode further comprises a third P-type region 14, and the third P-type region 14 is arranged below the second P-type region 8.

The utility model provides an integrated high-speed reverse freewheel diode's bipolar type carborundum semiconductor power device, includes that top-down stacks gradually the metallized source 1 that sets up, N type drift region 2, metallized drain 3, wherein:

the upper surface of the N-type drift region 2 is a front structure, and the front structure includes: a first P-type region 5, a P-type source region 6, a first N-type region 7, a second N-type region 12, a fourth N-type region 16, an oxide layer 10 and a gate 11; the first P-type region 5 is positioned above the N-type drift region 2, the P-type source region 6 is adjacent to the first N-type region 7 and is positioned in the first P-type region 5, and ohmic contact is formed between the metalized source electrode 1 and the upper parts of the P-type source region 6 and the first N-type region 7; the second N-type region 12 and the fourth N-type region 16 are respectively positioned at two sides of the first P-type region 5, and a Schottky barrier contact is formed between the upper part of the second N-type region 12 and the metalized source electrode 1; the oxide layer is located above the fourth N-type region 16 and contacts the first P-type region 5, and a gate 11 is disposed above the oxide layer 10.

Preferably, the silicon carbide material in the device is replaced by a silicon, gallium arsenide, indium phosphide or silicon germanium semiconductor material.

The invention has the beneficial effects that:

the invention provides a bipolar silicon carbide semiconductor power device integrated with a high-speed reverse freewheeling diode, and provides a novel structure for integrating a Schottky barrier diode in a silicon carbide power device cell in order to realize the integration of the silicon carbide power device and an FWD, reduce the conduction voltage drop of the silicon carbide diode and reduce the reverse recovery time and loss. Meanwhile, in order to reduce the channel resistance of the SiC inversion layer, an accumulation type channel is used in part of the device structure in the invention to replace an inversion layer channel in a traditional device, and for an electronic conduction type device, compared with a traditional inversion layer electronic channel device, the channel of the device adopting the accumulation type electronic channel can improve the channel carrier (electron) mobility and reduce the channel resistance of the device, namely the characteristic resistance of the device can be reduced, and meanwhile, the threshold voltage of the device can also be reduced. The accumulation-type insulated gate semiconductor field effect transistor structure can be better compromised between channel mobility and threshold voltage; compared with the traditional inversion layer electronic channel device, the accumulation type insulated gate semiconductor field effect transistor device has higher channel mobility and lower on-resistance and on-voltage drop under the acceptable threshold voltage, so the new structure of the device has wide application prospect.

For the protection of the gate oxide of the groove gate silicon carbide device, a P-type shielding structure can be formed at the bottom of the groove gate by injecting P-type impurities into the bottom of the groove gate, so that the electric field concentration effect at the corner of the bottom of a gate oxide layer is reduced, and an electric field peak is transferred from the gate oxide to a PN junction formed by the P-type shielding layer and an N-type drift region, thereby reducing the electric field at the oxide layer and improving the withstand voltage and the reliability of the device.

The voltage resistance of the power semiconductor device is realized by a layer of semiconductor material with lower doping in the device, and the doping concentration and the thickness of the semiconductor material determine the voltage resistance of the device and also determine the on-resistance of the device. When the doping concentration is lower, the withstand voltage of the device is higher, but the on-resistance is increased. The adoption of the super junction structure can effectively improve the compromise in the aspect, the concentration and the width of the composite buffer layer formed by the P column and the N column are designed, and when the composite buffer layer is exhausted, most of electric fields generated between the P column and the N column are mutually offset, so that the doping concentration of the super junction structure can be higher than that of a common voltage-resistant area, and the on-resistance of a device is reduced.

For a bipolar device, the bottom is simultaneously thinned with N + and P + regions to achieve both conductance modulation of the device and to provide a current path for the FWD in reverse.

In conclusion, the structure provided by the invention can obtain higher channel mobility and lower on-resistance, integrates the reverse follow current Schottky barrier diode, and improves the integration level and application cost of the device.

Drawings

Fig. 1 is a schematic structural diagram of a bipolar silicon carbide semiconductor power device integrated with a high-speed reverse freewheeling diode in example 1.

Fig. 2 is a schematic structural diagram of the bipolar silicon carbide semiconductor power device integrated with the high-speed reverse freewheeling diode in embodiment 1 after the cell area is optimized.

Fig. 3 is a schematic structural diagram of an accumulation-mode channel bipolar silicon carbide semiconductor power device integrated with a high-speed reverse freewheeling diode in embodiment 2.

Fig. 4 is a schematic structural diagram of an accumulation-mode channel bipolar silicon carbide semiconductor power device integrated with a high-speed reverse freewheeling diode in embodiment 2 after the cell area is optimized.

Fig. 5 is a schematic structural diagram of a bipolar sic semiconductor power device integrated with a high-speed reverse freewheeling diode according to embodiment 3, which uses the charge compensation principle.

Fig. 6 is a schematic structural diagram of an accumulation-mode channel bipolar sic semiconductor power device integrated with a high-speed reverse freewheeling diode according to embodiment 4, which uses the charge compensation principle.

Fig. 7 is a schematic structural view of a bipolar silicon carbide semiconductor power device in which a high-speed reverse freewheeling diode is integrated and which employs a trench-type cathode region and an accumulation-type channel in embodiment 5.

Fig. 8 is a schematic structural view of a bipolar sic semiconductor power device in which a high-speed reverse freewheeling diode is integrated and a trench-type cathode region is used in embodiment 6.

Fig. 9 is a schematic structural view of a trench bipolar sic semiconductor power device integrated with a high-speed reverse freewheeling diode in example 7.

Fig. 10 is a schematic structural view of a planar gate bipolar silicon carbide semiconductor power device integrated with a high-speed reverse freewheeling diode in example 8.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and its several details are capable of modifications and variations in various respects, all without departing from the spirit of the invention.

Example 1

The present embodiment provides a novel insulated gate power device integrating an inversion layer channel of a high-speed reverse freewheeling diode, which has a structure as shown in fig. 1, and includes a metallized cathode 1, an N-type drift region 2, and a metallized anode 3, which are sequentially stacked from top to bottom, wherein:

The working principle of the embodiment is as follows:

in the embodiment of the present invention, a novel insulated gate power device integrating an inversion layer channel of a high-speed reverse freewheeling diode, an electrode connection mode when conducting in a forward direction is as follows: the metallized anode (A) is connected with a high potential, the metallized cathode (K) is connected with a low potential, and the grid (G) is connected with a high potential relative to the metallized cathode (K); when the forward bias applied by the gate (G) with respect to the metallized cathode (K) reaches or exceeds the threshold voltage of the device, an inversion layer channel is formed in the first P-type region 5 near the oxide layer 10 sidewalls; at the same time, when a forward bias is applied to the metallized anode (a) with respect to the metallized cathode (K), electrons flow from the metallized cathode (K), through the first N-type region 7 and the first P-type region 5, into the N-type drift region 2, toward the N-type buffer layer 4, and finally through the N-type anode region 17 to the metallized anode (a), thereby forming a forward conduction current. In the N-type buffer layer 4 above the P-type anode region 18, due to a lateral voltage drop caused by the lateral flow of electrons, the P-type anode region 18 is conducted with the PN junction portion formed by the N-type buffer layer 4, and plays a role in conductivity modulation. At this time, holes are injected from the P-type anode region 18 into the N-type buffer layer 4, flow into the first P-type region 5 through the N-type drift region 2, and finally reach the metallized cathode (K) through the P-type cathode region 6. When conducting in the forward direction, the second N-type region 12 is depleted by the cooperation of the first P-type region 5 and the P-type cathode region 6 on both sides, and almost no electrons flow into the N-type drift region 2 through the second N-type region 12.

The electrode connection mode when the device is blocked is as follows: the metallized anode (A) is connected with a high potential, the metallized cathode (K) is connected with a low potential, and the grid (G) is connected with a zero or negative potential relative to the metallized cathode (K); at this time, no inversion layer is formed in the first P-type region 5, i.e., no conductive channel is formed; the second N-type region 12 is depleted under the combined action of the first P-type region 5 and the P-type cathode region 6 on two sides; the first P-type region 5 and the second P-type region 8 are commonly resistant to the pressure of the PN junction of the N-type drift region 2, and the depletion region expands downwards and can consume energy to reach the N-type drain region 4 and terminate at the N-type drain region 4. The second P-type region 8 is located at the bottom of the trench oxide layer 10, so that the bottom of the oxide layer can be prevented from being broken down, and the reliability of the oxide layer is improved.

At the moment when the device is switched from the on state to the off state, under the action of induced back electromotive force of the inductive load, the potential of the metallized anode (A) is negative relative to the potential of the metallized cathode (K); the concentration of the first P-type region 5 and the width of the second N-type region 12 are set such that the second N-type region 12 is not completely depleted at this time, and thus the Schottky Barrier Diode (SBD) formed by the metalized cathode (K) and the second N-type region 12 is turned on to function as a reverse freewheeling. At this time, the paths through which the electron current flows are: electrons are injected from the metallized anode (a) through the N-type anode region 17 into the N-type buffer layer 4, flow through the N-type buffer layer 4, the N-type drift region 2, and the second N-type region 12, and finally reach the metallized cathode (K). Since the metalized cathode (K) and the second N-type region 12 form a schottky barrier diode with P-type regions (the first P-type region 5 and the P-type cathode region 6) on both sides, the Schottky Barrier Diode (SBD) operates in a manner similar to the junction barrier schottky diode (JBS).

Further, in the present embodiment, the second N-type region 12 penetrates the first P-type region 5 and the P-type cathode region 6, and in an extreme case, that is, the second N-type region 12 is located at one side of the first P-type region 5 and the P-type cathode region 6, as shown in fig. 2, at this time, the cell area of the device can be further reduced, and further, the specific on-resistance of the device is reduced.

Example 2

The present embodiment provides a novel insulated gate power device integrating an accumulation-mode channel of a high-speed reverse freewheeling diode, whose structure is shown in fig. 3, and the difference from embodiment 1 is that the device further includes a third N-type region 13, where the third N-type region 13 is in contact with the first N-type region 7 and the N-type drift region 2 at the top and bottom, and the left and right are in contact with the first P-type region 5 and the oxide layer 10, respectively.

The working principle of the embodiment is as follows:

in this embodiment, a novel integrated high-speed reverse freewheeling diode's insulated gate power device with accumulation-type channel, the electrode connection mode when conducting in the forward direction is: the metallized anode (A) is connected with a high potential, the metallized cathode (K) is connected with a low potential, and the grid (G) is connected with a high potential relative to the metallized cathode (K); when the forward bias applied by the gate (G) with respect to the metallized cathode (K) reaches or exceeds the threshold voltage of the device, an accumulation channel is formed in the third N-type region 13 near the oxide layer 10 sidewalls; at the same time, when a forward bias is applied to the metallized anode (a) with respect to the metallized cathode (K), electrons flow from the metallized cathode (K), through the first N-type region 7 and the third N-type region 13, into the N-type drift region 2, toward the N-type buffer layer 4, and finally through the N-type anode region 18 to the metallized anode (a)3, thereby forming a forward conduction current. In the N-type buffer layer 4 above the P-type anode region 19, due to the lateral voltage drop caused by the lateral flow of electrons, the P-type anode region 18 is conducted with the PN junction portion formed by the N-type buffer layer 4, and plays a role in conductivity modulation. At this time, holes are injected from the P-type anode region 18 into the N-type buffer layer 4, flow into the first P-type region 5 through the N-type drift region 2, and finally reach the metallized cathode (K) through the P-type cathode region 6. When conducting in the forward direction, the second N-type region 12 is depleted by the cooperation of the first P-type region 5 and the P-type cathode region 6 on both sides, and almost no electrons flow into the N-type drift region 2 through the second N-type region 12.

The electrode connection mode when the device is blocked is as follows: the metallized anode (A) is connected with a high potential, the metallized cathode (K) is connected with a low potential, and the grid (G) is connected with a zero or negative potential relative to the metallized cathode (K); at this time, the gate (G) and the first P-type region 5 together deplete the third N-type region 13, i.e., the conduction channel is pinched off; the second N-type region 12 is depleted under the combined action of the first P-type region 5 and the P-type cathode region 6 on two sides; the first P-type region 5 and the second P-type region 8 are commonly resistant to the pressure of the PN junction of the N-type drift region 2, and the depletion region expands downwards and can consume energy to reach the N-type drain region 4 and terminate at the N-type drain region 4. In addition, the second P-type region 8 is located at the bottom of the trench oxide layer 10, so that the bottom of the oxide layer can be prevented from being broken down, and the reliability of the oxide layer is improved.

At the moment when the device is switched from the on state to the off state, the potential of the metallized anode (A) is negative relative to the potential of the metallized cathode (K) under the action of the induced back electromotive force of the inductive load. The concentration of the first P-type region 5 and the width of the second N-type region 12 are set such that the second N-type region 12 is not completely depleted at this time, and thus the Schottky Barrier Diode (SBD) formed by the metalized source (S) and the second N-type region 12 is turned on to function as a reverse freewheeling. At this time, the paths through which the electron current flows are: electrons are injected from the metallized anode (a) through the N-type anode region 17 into the N-type buffer layer 4, flow through the N-type buffer layer 4, the N-type drift region 2, and the second N-type region 12, and finally reach the metallized cathode (K). Since the metalized cathode (K) and the second N-type region 12 form a schottky barrier diode with P-type regions (the first P-type region 5 and the P-type cathode region 6) on both sides, the Schottky Barrier Diode (SBD) operates in a manner similar to the junction barrier schottky diode (JBS).

Further, in the present embodiment, the second N-type region 12 penetrates the first P-type region 5 and the P-type cathode region 6, and in an extreme case, that is, the second N-type region 12 is located at one side of the first P-type region 5 and the P-type cathode region 6, as shown in fig. 4, at this time, the cell area of the device can be further reduced, and further, the specific on-resistance of the device is reduced.

Example 3

The present embodiment provides a novel insulated gate power device integrating an inversion layer channel of a high-speed reverse freewheeling diode, whose structure is shown in fig. 5, and it is different from embodiment 1 in that the device further includes a third P-type region 14, and the third P-type region 14 is disposed below the second P-type region 8.

The working principle of the device of this embodiment is the same as that of embodiment 1, wherein when the device is turned off, the PN junctions of the first P-type region 5, the second P-type region 8, the third P-type region 14 and the N-type drift region 2 have a common withstand voltage, and the third P-type region 14 is introduced, so that the withstand voltage of the device can be higher, and meanwhile, the on-resistance of the forward conduction can be reduced under the condition that the turn-off withstand voltage is not changed.

Example 4

This embodiment provides a novel insulated gate power device integrating an accumulation-mode channel of a high-speed reverse freewheeling diode, whose structure is shown in fig. 6, and it is different from embodiment 2 in that the device further includes a third P-type region 14, and the third P-type region 14 is disposed below the second P-type region 8.

The working principle of the device of this embodiment is the same as that of embodiment 2, wherein when the device is blocked, the PN junctions of the first P-type region 5, the second P-type region 8, the third P-type region 14 and the N-type drift region 2 have a common withstand voltage, and the third P-type region 14 is introduced, so that the withstand voltage of the device can be higher, and meanwhile, the on-resistance of the forward conduction can be reduced under the condition that the blocking withstand voltage is not changed.

Example 5

The present embodiment provides a novel insulated gate power device integrating an accumulation-mode channel of a high-speed reverse freewheeling diode, which has a structure as shown in fig. 7, and includes a metallized cathode (K), an N-type drift region, and a metallized anode (a) stacked in sequence from top to bottom, where:

The working principle of the embodiment is as follows:

in this embodiment, a novel integrated high-speed reverse freewheeling diode's insulated gate power device with accumulation-type channel, the electrode connection mode when conducting in the forward direction is: the metallized anode (A) is connected with a high potential, the metallized cathode (K) is connected with a low potential, and the grid (G) is connected with a high potential relative to the metallized cathode (K); when the forward bias applied by the gate (G) with respect to the metallized cathode (K) reaches or exceeds the threshold voltage of the device, an accumulation channel is formed in the second N-type region 12 near the oxide layer 10 sidewalls; at the same time, when a forward bias is applied to the metallized anode (a) relative to the metallized cathode (K), electrons flow from the metallized source (S), through the first N-type region 7 and the second N-type region 12, into the N-type drift region 2, into the N-type drain region 4, and finally to the metallized anode (a), forming a forward conduction current. In the N-type buffer layer 4 above the P-type anode region 18, due to a lateral voltage drop caused by the lateral flow of electrons, the P-type anode region 18 is conducted with the PN junction portion formed by the N-type buffer layer 4, and plays a role in conductivity modulation. At this time, holes are injected into the N-type buffer layer 4 from the P-type anode region 18, and flow into the first P-type cathode region 6-1 and the second P-type cathode region 6-2 through the N-type drift region 2, respectively, and finally reach the metalized cathode (K). When conducting in the forward direction, the left side of the second N-type region 12 is depleted by the cooperation of the first P-type cathode region 6-1 and the second P-type cathode region 6-2, and almost no electrons directly flow from the metallized source (S) into the N-type drift region 2 from the left side of the second N-type region 12.

The electrode connection mode when the device is blocked is as follows: the metallized anode (A) is connected with a high potential, the metallized cathode (K) is connected with a low potential, and the grid (G) is connected with a zero or negative potential relative to the metallized cathode (K); at this time, no accumulation layer is formed in the second N-type region 12 near the sidewall of the oxide layer 10, i.e., no conductive channel can be formed; the second N-type region 12 is depleted under the combined action of the first P-type cathode region 6-1, the second P-type cathode region 6-2 and the second P-type region 8; the PN junctions of the first P type cathode region 6-1, the second P type region 8 and the N type drift region 2 are resistant to pressure together, the depletion region expands downwards and can consume energy to the N type buffer layer 4 and is terminated at the N type buffer layer 4. In addition, the second P-type region 8 is located at the bottom of the trench oxide layer 10, so that the bottom of the oxide layer can be prevented from being broken down, and the reliability of the oxide layer is improved.

At the moment when the device is switched from the on state to the off state, under the action of induced back electromotive force of the inductive load, the potential of the metallized anode (A) is negative relative to the potential of the metallized cathode (K); the concentration and the area size of the first P-type cathode region 6-1 and the second P-type cathode region 6-2 are set so that the second N-type region 12 is not completely exhausted at this time, and thus a Schottky Barrier Diode (SBD) formed by the metalized cathode (K) and the second N-type region 12 is conducted to play a role of reverse follow current. At this time, the paths through which the electron current flows are: electrons are injected from the metallized anode (a) through the N-type anode region 17 into the N-type buffer layer 4, pass through the N-type buffer layer 4, the N-type drift region 2 and the second N-type region 12, and finally reach the metallized cathode (K). Since the metalized source (S) and the second N-type region 12 form a schottky barrier diode with P-type regions (the first P-type cathode region 6-1 and the second P-type cathode region 6-2) on both sides, the Schottky Barrier Diode (SBD) and the junction barrier schottky diode (JBS) actually work on a similar principle.

Similarly, the device may further include a third P-type region 14, where the third P-type region 14 is disposed below the second P-type region 8; when the device is blocked, the PN junctions of the first P-type cathode region 6-1, the second P-type region 8, the third P-type region 14 and the N-type drift region 2 are jointly withstand voltage and introduced into the third P-type region 14, so that the withstand voltage of the device can be higher, and meanwhile, the on-resistance of forward conduction can be reduced under the condition that the blocking withstand voltage is not changed.

Example 6

This embodiment provides a novel insulated gate power device integrating a high-speed reverse freewheeling diode, the structure of which is shown in fig. 8, and the difference from embodiment 5 is that the device further includes a first P-type region 5, the upper and lower portions of the first P-type region 5 are respectively in contact with a first N-type region 7 and a second N-type region 12, and the left and right portions are respectively in contact with a second P-type cathode region 6-2 and an oxide layer 10.

The working principle of the embodiment is as follows:

in this embodiment, a novel insulated gate power device integrating a high-speed reverse freewheeling diode has an electrode connection mode when conducting in the forward direction: the metallized anode (A) is connected with a high potential, the metallized cathode (K) is connected with a low potential, and the grid (G) is connected with a high potential relative to the metallized cathode (K); when the forward bias applied by the gate (G) with respect to the metallized cathode (K) reaches or exceeds the threshold voltage of the device, an inversion type channel is formed in the first P-type region 5 near the sidewall of the oxide layer 10 and an accumulation type channel is formed in the second N-type region 12 near the sidewall of the oxide layer 10; at the same time, when a forward bias is applied to the metallized anode (a) with respect to the metallized cathode (K), electrons flow from the metallized cathode (K) through the first N-type region 7, the first P-type region 5, and the second N-type region 12, into the N-type drift region 2, toward the N-type buffer layer 4, and finally through the N-type anode region 17 to the metallized anode (a), thereby forming a forward conduction current. In the N-type buffer layer 4 above the P-type anode region 18, due to a lateral voltage drop caused by the lateral flow of electrons, the P-type anode region 18 is conducted with the PN junction portion formed by the N-type buffer layer 4, and plays a role in conductivity modulation. At this time, holes are injected from the P-type anode region 18 into the N-type buffer layer 4, and flow into the first P-type cathode region 6-1, the second P-type cathode region 6-2, the first P-type region 5 through the N-type drift region 2, respectively, and finally reach the metalized cathode (K). When conducting in the forward direction, the left side of the second N-type region 12 is depleted by the combined action of the first P-type cathode region 6-1, the second P-type cathode region 6-2 and the first P-type region 5, and almost no electrons directly flow from the left side of the second N-type region 12 to the N-type drift region 2 through the metalized source (S).

The electrode connection mode when the device is blocked is as follows: the metallized anode (A) is connected with a high potential, the metallized cathode (K) is connected with a low potential, and the grid (G) is connected with a zero or negative potential relative to the metallized cathode (K); at this time, no inversion layer channel is formed in the first P-type region 5 near the sidewall of the oxide layer 10, and no accumulation layer is formed in the second N-type region 12 near the sidewall of the oxide layer 10, i.e. no conductive channel can be formed; the second N-type region 12 is depleted under the combined action of the first P-type cathode region 6-1, the second P-type cathode region 6-2, the first P-type region 5 and the second P-type region 8; the PN junctions of the first P type cathode region 6-1, the second P type region 8 and the N type drift region 2 are resistant to pressure together, the depletion region expands downwards and can consume energy to the N type buffer layer 4 and is terminated at the N type buffer layer 4. In addition, the second P-type region 8 is located at the bottom of the trench oxide layer 10, so that the bottom of the oxide layer can be prevented from being broken down, and the reliability of the oxide layer is improved.

At the moment when the device is switched from the on state to the off state, under the action of induced back electromotive force of the inductive load, the potential of the metallized anode (A) is negative relative to the potential of the metallized cathode (K); the concentration and the area size of the first P type cathode region 6-1, the second P type cathode region 6-2 and the first P type region 5 are set so that the second N type region 12 is not completely exhausted at this time, and thus the Schottky Barrier Diode (SBD) formed by the metalized cathode (K) and the second N type region 12 is conducted to play a role of reverse follow current. At this time, the paths through which the electron current flows are: electrons are injected from the metallized anode (a) through the N-type anode region 17 into the N-type buffer layer 4, pass through the N-type buffer layer 4, the N-type drift region 2 and the second N-type region 12, and finally reach the metallized cathode (K). Since the schottky barrier diode formed by the metalized source (S) and the second N-type region 12 has P-type regions (the first P-type cathode region 6-1, the second P-type cathode region 6-2, the first P-type region 5) on both sides, the operation principle of the Schottky Barrier Diode (SBD) is similar to that of the junction barrier schottky diode (JBS).

Similarly, the device may also include a third P-type region 14, which functions as in the other embodiments.

Example 7

This embodiment provides a novel insulated gate power device integrating accumulation-mode channel of high-speed reverse freewheeling diode, whose structure is shown in fig. 9, and its difference from embodiment 6 is that the second N-type region 12 penetrates through the first P-type cathode region 6-1, and the second N-type region 12 forms schottky barrier contact with the metalized source 1 above and contacts with the N-type drift region below.

The working principle of the embodiment is as follows:

in this embodiment, a novel insulated gate power device integrating a high-speed reverse freewheeling diode has an electrode connection mode when conducting in the forward direction: the metallized anode (A) is connected with a high potential, the metallized cathode (K) is connected with a low potential, and the grid (G) is connected with a high potential relative to the metallized cathode (K); when the forward bias applied by the gate (G) with respect to the metallized cathode (K) reaches or exceeds the threshold voltage of the device, an inversion layer channel is formed in the first P-type region 5 near the oxide layer 10 sidewalls; at the same time, when a forward bias is applied to the metallized anode (a) relative to the metallized cathode (K), electrons flow from the metallized source (S), through the first N-type region 7 and the first P-type region 5, into the N-type drift region 2, toward the N-type buffer layer 4, and finally through the N-type anode region 17 to the metallized anode (a), forming a forward conduction current. In the N-type buffer layer 4 above the P-type anode region 18, due to a lateral voltage drop caused by the lateral flow of electrons, the P-type anode region 18 is conducted with the PN junction portion formed by the N-type buffer layer 4, and plays a role in conductivity modulation. At this time, holes are injected from the P-type anode region 18 into the N-type buffer layer 4, and flow into the first P-type cathode region 6-1, the second P-type cathode region 6-2, the first P-type region 5 through the N-type drift region 2, respectively, and finally reach the metalized cathode (K). When conducting in the forward direction, the second N-type region 12 is depleted by the first P-type cathode regions 6-1 on both sides, and almost no electrons flow directly from the metalized source (S) into the N-type drift region 2 from the left side of the second N-type region 12.

The electrode connection mode when the device is blocked is as follows: the metallized anode (A) is connected with a high potential, the metallized cathode (K) is connected with a low potential, and the grid (G) is connected with a zero or negative potential relative to the metallized cathode (K); at this time, no inversion layer channel is formed in the first P-type region 5 near the sidewall of the oxide layer 10, i.e. no conductive channel can be formed; the second N-type region 12 is depleted by the first P-type cathode region 6-1; the first P type cathode region 6-1, the second P type cathode region 6-2, the first P type region 5 and the second P type region 8 and the PN junction of the N type drift region 2 are jointly resistant to pressure, the depletion region expands downwards and can consume energy to the N type drain region 4 and is terminated at the N type drain region 4. In addition, the second P-type region 8 is located at the bottom of the trench oxide layer 10, so that the bottom of the oxide layer can be prevented from being broken down, and the reliability of the oxide layer is improved.

At the moment when the device is switched from the on state to the off state, under the action of induced back electromotive force of the inductive load, the potential of the metallized anode (A) is negative relative to the potential of the metallized cathode (K); the concentration and the area size of the first P-type cathode region 6-1 are set so that the second N-type region 12 is not completely depleted at this time, and thus the Schottky Barrier Diode (SBD) formed by the metalized cathode (K) and the second N-type region 12 is turned on to play a role of backward follow current. At this time, the paths through which the electron current flows are: electrons are injected from the metallized anode (a) through the N-type anode region 17 into the N-type buffer layer 4, pass through the N-type buffer layer 4, the N-type drift region 2 and the second N-type region 12, and finally reach the metallized cathode (K). Since the schottky barrier diode formed by the metalized cathode (K) and the second N-type region 12 has P-type regions (the first P-type cathode region 6-1) on both sides, the Schottky Barrier Diode (SBD) actually operates in a similar manner to the junction barrier schottky diode (JBS).

Furthermore, in this embodiment, the second N-type region 12 penetrates the first P-type cathode region 6-1, and in an extreme case, that is, the second N-type region 12 is located at one side of the first P-type cathode region 6-1, at this time, the cell area of the device can be further reduced, and further, the specific on-resistance of the device is reduced.

Example 8

The present embodiment provides a novel insulated gate power device integrating a high-speed reverse freewheeling diode, which has a structure as shown in fig. 10, and includes a metalized source 1, an N-type drift region 2, and a metalized drain 3, which are sequentially stacked from top to bottom, where:

The working principle of the embodiment is as follows:

in this embodiment, a novel insulated gate power device integrating a high-speed reverse freewheeling diode has an electrode connection mode when conducting in the forward direction: the metalized drain (D) is connected with a high potential, the metalized source (S) is connected with a low potential, and the grid (G) is connected with a high potential relative to the metalized source (S); when the forward bias applied by the gate (G) with respect to the metalized source (S) reaches or exceeds the threshold voltage of the device, an inversion layer channel is formed in the first P-type region 5 near the oxide layer 10; at the same time, when a forward bias is applied to the metalized drain (D) relative to the metalized source (S), electrons flow from the metalized source (S), through the first N-type region 7, the first P-type region 5 and the fourth N-type region 16, into the N-type drift region 2, to the N-type drain region 4, and finally to the metalized drain (D), forming a forward conduction current. In the N-type buffer layer 4 above the P-type anode region 18, due to a lateral voltage drop caused by the lateral flow of electrons, the P-type anode region 18 is conducted with the PN junction portion formed by the N-type buffer layer 4, and plays a role in conductivity modulation. At this time, holes are injected from the P-type anode region 18 into the N-type buffer layer 4, flow into the first P-type region 5 through the N-type drift region 2, and finally reach the metalized source (S) through the P-type source region 6. In forward conduction, the second N-type region 12 is depleted by the interaction of the P-type source region 6 and the first P-type region 5, and almost no electrons flow directly from the second N-type region 12 into the N-type drift region 2 from the metalized source (S).

The electrode connection mode when the device is blocked is as follows: the metalized drain (D) is connected with a high potential, the metalized source (S) is connected with a low potential, and the grid (G) is connected with a zero or negative potential relative to the metalized source (S); at this time, no inversion layer is formed in the first P-type region 5 near the oxide layer 10, i.e., no conduction channel can be formed; the second N-type region 12 is depleted by the cooperation of the P-type source region 6 and the first P-type region 5; the PN junction of the P-type source region 6, the first P-type region 5 and the second N-type region 12 and the PN junction of the first P-type region 5 and the N-type drift region 2 are jointly resistant to pressure, and the depletion region expands downwards and can consume energy to reach the N-type drain region 4 and is terminated at the N-type drain region 4.

At the moment when the device is switched from the on state to the off state, under the action of induced back electromotive force of the inductive load, the potential of the metalized drain (D) is negative relative to the potential of the metalized source (S); the concentration and the area size of the P-type source region 6 and the first P-type region 5 are set so that the second N-type region 12 is not completely depleted at this time, and thus the Schottky Barrier Diode (SBD) formed by the metalized source (S) and the second N-type region 12 is turned on to play a role of backward follow current. At this time, the paths through which the electron current flows are: electrons are injected from the metalized drain (D) through the N-type anode region 17 into the N-type buffer layer 4, flow through the N-type buffer layer 4, the N-type drift region 2, and the second N-type region 12, and finally reach the metalized source (S). Since the metalized source (S) and the second N-type region 12 form a P-type region on the right side of the schottky barrier diode, the Schottky Barrier Diode (SBD) operates in a manner similar to the junction barrier schottky diode (JBS).

As described above, the silicon carbide material in the device may be replaced with a semiconductor material such as silicon, gallium arsenide, indium phosphide, or silicon germanium, only for the embodiment of the present invention. Any feature disclosed in this specification may, unless stated otherwise, be replaced by alternative features serving equivalent or similar purposes; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.

Claims

1. The bipolar silicon carbide semiconductor power device integrated with the high-speed reverse freewheeling diode comprises a metallized cathode (1), an N-type drift region (2) and a metallized anode (3) which are sequentially stacked from top to bottom, wherein:

the lower surface of the N-type drift region (2) is of a back structure, and the back structure comprises: an N-type buffer layer (4), an N-type anode region (17) and a P-type anode region (18); the N-type anode region (17) is adjacent to the P-type anode region (18) and is positioned below the N-type buffer layer (4), and the N-type anode region and the P-type anode region form ohmic contact with the upper surface of the metallized anode;

the upper surface of N type drift region (2) is positive structure, positive structure includes: a first P type region (5), a P type cathode region (6), a first N type region (7), a second P type region (8), a second N type region (12), a groove (9), an oxide layer (10) in the groove and a grid electrode (11); the groove (9) is formed in one side of the upper surface of the N-type drift region (2), an oxide layer (10) is filled in the groove (9), a grid electrode (11) is arranged in the oxide layer (10), and a second P-type region (8) is arranged below the oxide layer (10); the first P-type region (5) is positioned above the N-type drift region (2), the P-type cathode region (6) is adjacent to the first N-type region (7) and is positioned above the first P-type region (5), ohmic contact is formed between the P-type cathode region (6) and the first N-type region (7) and the metallized cathode (1), and the first P-type region (5) and the first N-type region (7) are both contacted with the oxide layer (10); the second N-type region (12) penetrates through the first P-type region (5) and the P-type cathode region (6), a Schottky barrier contact is formed between the upper part of the second N-type region (12) and the metallized cathode (1), and the lower part of the second N-type region is in contact with the N-type drift region.

2. The bipolar silicon carbide semiconductor power device with an integrated high speed reverse freewheeling diode according to claim 1 wherein the device further comprises a third N-type region (13), the third N-type region (13) is in contact with the first N-type region (7) and the N-type drift region (2) at the top and bottom, respectively, and is in contact with the first P-type region (5) and the oxide layer (10) at the left and right, respectively.

3. The bipolar silicon carbide semiconductor power device integrated with the high-speed reverse freewheeling diode comprises a metallized cathode (K), an N-type drift region and a metallized anode (A) which are sequentially stacked from top to bottom, wherein:

the lower surface of the N-type drift region 2 is a back structure, and the back structure includes: an N-type buffer layer (4), an N-type anode region (17) and a P-type anode region (18); the N-type anode region (17) is adjacent to the P-type anode region (18) and is positioned below the N-type buffer layer (4), and the N-type anode region and the P-type anode region form ohmic contact with the upper surface of the metallized anode;

the upper surface of N type drift region (2) is positive structure, positive structure includes: a first P type cathode region (6-1), a second P type cathode region (6-2), a first N type region (7), a second P type region (8), a second N type region (12), a first groove (9), an oxide layer (10) and a grid electrode (11) in the groove, and a second groove (15); the first groove (9) is formed in one side of the upper surface of the N-type drift region (2), an oxide layer (10) is filled in the first groove (9), a grid electrode (11) is arranged in the oxide layer (10), and a second P-type region (8) is arranged below the oxide layer (10); the second groove (15) is formed in the other side of the upper surface of the N-type drift region (2), the first P-type cathode region (6-1) and the second P-type cathode region (6-2) are located below and on the side of the second groove respectively, the first N-type region (7) is located between the second P-type cathode region (6-2) and the oxide layer, and ohmic contact is formed between the first P-type cathode region (6-1), the second P-type cathode region (6-2) and the first N-type region (7) and the metalized source electrode (1); the second N-type region (12) is arranged between the first P-type cathode region (6-1) and the second P-type cathode region (6-2), is in contact with the first P-type cathode region (6-1), the second P-type cathode region (6-2), the first N-type region (7) and the oxide layer (10) in a homogeneous mode, is in Schottky barrier contact with the metalized source electrode (1) at the upper part, and is in contact with the N-type drift region at the lower part.

4. A bipolar sic semiconductor power device integrating a high-speed reverse freewheeling diode according to claim 3 characterized in that the device further comprises a first P-type region (5), the first P-type region (5) being in contact with the first N-type region (7) and the second N-type region (12) at the top and bottom, respectively, and in contact with the second P-type cathode region (6-2) and the oxide layer (10) at the left and right, respectively.

5. The bipolar silicon carbide semiconductor power device integrated with the high-speed reverse freewheeling diode comprises a metallized cathode (K), an N-type drift region and a metallized anode (A) which are sequentially stacked from top to bottom, wherein:

the upper surface of N type drift region (2) is positive structure, positive structure includes: a first P type cathode region (6-1), a second P type cathode region (6-2), a first N type region (7), a second P type region (8), a second N type region (12), a first P type region (5), a first groove (9), an oxide layer (10) and a grid electrode (11) in the groove, and a second groove (15); the first groove (9) is formed in one side of the upper surface of the N-type drift region (2), an oxide layer (10) is filled in the first groove (9), a grid electrode (11) is arranged in the oxide layer (10), and a second P-type region (8) is arranged below the oxide layer (10); the second groove (15) is formed in the other side of the upper surface of the N-type drift region (2), the first P-type cathode region (6-1) and the second P-type cathode region (6-2) are located below and on the side of the second groove respectively, the first N-type region (7) is located between the second P-type cathode region (6-2) and the oxide layer, and ohmic contact is formed between the first P-type cathode region (6-1), the second P-type cathode region (6-2) and the first N-type region (7) and the metalized source electrode (1); the upper part and the lower part of the first P-type region (5) are respectively contacted with a first N-type region (7) and a second N-type region (12), and the left part and the right part are respectively contacted with a second P-type cathode region (6-2) and an oxide layer (10); the second N-type region (12) penetrates through the first P-type cathode region (6-1), a Schottky barrier contact is formed between the upper part of the second N-type region (12) and the metalized source electrode (1), and the lower part of the second N-type region is in contact with the N-type drift region.

6. A bipolar SiC semiconductor power device incorporating a high speed reverse freewheel diode according to any of claims 1-5 characterized in that it further comprises a third P-type region (14), the third P-type region (14) being located below the second P-type region (8).

7. The bipolar silicon carbide semiconductor power device integrated with the high-speed reverse freewheeling diode comprises a metalized source electrode (1), an N-type drift region (2) and a metalized drain electrode (3) which are sequentially stacked from top to bottom, wherein:

the upper surface of N type drift region (2) is positive structure, positive structure includes: a first P type region (5), a P type source region (6), a first N type region (7), a second N type region (12), a fourth N type region (16), an oxide layer (10) and a grid electrode (11); the first P-type region (5) is positioned above the N-type drift region (2), the P-type source region (6) is adjacent to the first N-type region (7) and is positioned in the first P-type region (5), and ohmic contact is formed between the metalized source electrode (1) and the positions above the P-type source region (6) and the first N-type region (7); the second N-type region (12) and the fourth N-type region (16) are respectively positioned at two sides of the first P-type region (5), and Schottky barrier contact is formed between the upper part of the second N-type region (12) and the metalized source electrode (1); the oxide layer is located above the fourth N-type region (16) and is in contact with the first P-type region (5), and the grid electrode (11) is arranged above the oxide layer (10).