JP2013051345A - Diode, semiconductor device and mosfet - Google Patents

Abstract

PROBLEM TO BE SOLVED: To disclose a technology of enabling reduction of a switching loss in a diode to be achieved by a structure that is not likely to cause variation in quality at the time of manufacturing.SOLUTION: A diode disclosed in the present specification comprises: a cathode electrode; a cathode region composed of a first conductivity type semiconductor; a drift region composed of a low-concentration first conductivity type semiconductor; an anode region composed of a second conductivity type semiconductor; and an anode electrode. The diode comprises: a barrier region formed between the drift region and the anode region, and composed of a first conductivity type semiconductor having a concentration higher than that of the drift region; and a hetero semiconductor region formed so as to electrically connect the barrier region and the anode electrode, and composed of a semiconductor having a band gap smaller than that of the barrier region. In the diode, the hetero semiconductor region and the barrier region form a hetero junction.

Description

  The present invention relates to a diode, a semiconductor device, and a MOSFET.

Techniques for improving reverse recovery characteristics of PN diodes and reducing switching loss have been developed. Patent Document 1 discloses an MPS diode in which a PIN diode and a Schottky diode are combined. In the technique of Patent Document 1, by reducing the size of the p anode region to the reach through limit, hole injection from the p anode region to the n ⁻ drift region is suppressed, and switching loss is reduced. Patent Document 2, p anode region and the n ^- between the drift region n ^- than the drift region PIN diode having a n barrier region having a high concentration n-type impurity are disclosed. In the technique of Patent Document 2, injection of holes from the p anode region to the n ⁻ drift region is suppressed by the n barrier region, and switching loss is reduced.

JP 2003-163357 A JP 2000-323488 A

When Schottky junction is used between the anode electrode and the n ⁻ drift region (or n barrier region), the operating characteristics of the diode vary greatly depending on the quality of the interface of the Schottky junction. However, the quality of the Schottky junction interface is likely to vary during manufacturing. There is a demand for a technology that can reduce the switching loss in a diode with a structure that does not easily cause variations in quality during manufacturing.

  In this specification, the technique which solves said subject is provided. In the present specification, a technology capable of realizing a reduction in switching loss in a diode with a structure in which quality variations are unlikely to occur during manufacturing is disclosed.

  The diode disclosed in the present specification includes a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, and an anode region made of a second conductivity type semiconductor. And an anode electrode. The diode includes a barrier region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a higher concentration than the drift region, and electrically connects the barrier region and the anode electrode. And a hetero semiconductor region made of a semiconductor having a band gap smaller than that of the barrier region. In the diode, the hetero semiconductor region and the barrier region are heterojunctioned.

  In the above diode, when a forward bias is applied between the anode electrode and the cathode electrode, a short circuit occurs via the heterojunction interface between the hetero semiconductor region and the barrier region. Thereby, the potential difference between the barrier region and the anode electrode becomes substantially equal to the voltage drop at the heterojunction interface. Since the voltage drop at the heterojunction interface is sufficiently smaller than the built-in voltage of the pn junction between the anode region and the barrier region, injection of holes from the anode region to the drift region is suppressed.

  Then, when the voltage between the anode electrode and the cathode electrode switches from forward bias to reverse bias, the reverse current is limited by the heterojunction interface between the hetero semiconductor region and the barrier region. In the above diode, since the injection of holes from the anode region to the drift region is suppressed when a forward bias is applied, the reverse recovery current is small and the reverse recovery time is short. According to the above diode, switching loss can be reduced without performing lifetime control of the drift region.

  In the above diode, when a reverse bias is applied between the anode electrode and the cathode electrode, not only a depletion layer extending from the heterojunction interface between the hetero semiconductor region and the barrier region, but also between the anode region and the barrier region. The electric field is also shared by the depletion layer extending from the interface of the pn junction. Thereby, the electric field applied to the heterojunction interface between the hetero semiconductor region and the barrier region is reduced. According to the above diode, the withstand voltage against reverse bias can be improved.

  Further, in the above diode, the rectifying action is realized by using a heterojunction instead of a Schottky junction for the electrical connection between the anode electrode and the barrier region. In general, when a rectifying action is realized using a Schottky junction, the operation is greatly affected by the quality of the interface of the Schottky junction. However, the quality of the Schottky junction interface is likely to vary during manufacturing. On the other hand, even when the rectifying action is realized using a heterojunction, the operation is greatly influenced by the quality of the interface of the heterojunction, but the heterojunction interface is unlikely to vary in quality during manufacturing. According to the above diode, the switching loss can be reduced with a structure in which the quality does not easily vary during manufacture.

  In addition, the barrier region in the above diode may be composed of a single semiconductor region having a uniform impurity concentration, or may be composed of a plurality of semiconductor regions having different impurity concentrations.

  The diode preferably further includes an electric field progress prevention region made of a second conductivity type semiconductor and formed between the barrier region and the drift region.

  In the above diode, when a reverse bias is applied between the anode electrode and the cathode electrode, not only the reverse current is limited at the heterojunction interface between the hetero semiconductor region and the barrier region, but also the drift region and the electric field progress prevention. The reverse current is also limited by the pn junction between the regions. According to the above diode, it is possible to reduce a leakage current when a reverse bias is applied.

  In the above diode, when a reverse bias is applied between the anode electrode and the cathode electrode, not only a depletion layer extending from the heterojunction interface between the hetero semiconductor region and the barrier region, but also between the anode region and the barrier region. The depletion layer extending from the pn junction interface and the pn junction interface between the drift region and the electric field progression prevention region also share the electric field. Thereby, the electric field applied to the heterojunction interface between the hetero semiconductor region and the barrier region and the electric field applied to the pn junction between the anode region and the barrier region are reduced. According to the above diode, the withstand voltage against reverse bias can be further improved.

  In the above diode, it is preferable that a trench extending from the anode region to the drift region is formed, and a trench electrode covered with an insulating film is formed inside the trench.

  In the above diode, when a reverse bias is applied between the anode electrode and the cathode electrode, an electric field concentration occurs at a location near the tip of the trench electrode inside the drift region, thereby causing a gap between the hetero semiconductor region and the barrier region. The electric field applied to the heterojunction interface and the pn junction interface between the anode region and the barrier region is reduced. According to the above diode, the withstand voltage against reverse bias can be further improved.

  The diode preferably further includes a cathode short region made of a second conductivity type semiconductor partially formed in the cathode region.

  In the above diode, when a forward bias is applied between the anode electrode and the cathode electrode, the presence of the cathode short region suppresses the injection of electrons from the cathode region to the drift region. Thereby, the reverse recovery current when switching from the forward bias to the reverse bias can be further reduced, and the reverse recovery time can be further shortened. According to the above diode, the switching loss can be further reduced.

  The present specification further discloses a semiconductor device in which the above diode and IGBT are integrated. In the semiconductor device, the IGBT includes a collector electrode, a collector region made of a second conductivity type semiconductor, a second drift region made of a low concentration first conductivity type semiconductor, which is continuous from the drift region, A body region made of a second conductivity type semiconductor; an emitter region made of a first conductivity type semiconductor; an emitter electrode; and an insulation film for the body region between the emitter region and the second drift region. A gate electrode is provided so as to face each other. In the semiconductor device, the IGBT is formed between the second drift region and the body region, the second barrier region made of a first conductivity type semiconductor having a higher concentration than the second drift region, A second hetero semiconductor region made of a semiconductor having a band gap smaller than that of the second barrier region is formed so as to electrically connect the second barrier region and the emitter electrode. In the semiconductor device, the second hetero semiconductor region and the second barrier region are heterojunctioned.

  In the semiconductor device described above, both the diode and the IGBT parasitic diode have a structure in which the quality does not easily vary during manufacturing, can reduce the switching loss, and can improve the withstand voltage against the reverse bias.

  The semiconductor device preferably further includes a second electric field progress prevention region made of a second conductivity type semiconductor and formed between the second barrier region and the second drift region.

  In the semiconductor device described above, the withstand voltage against reverse bias can be further improved and the leakage current during reverse bias can be reduced for the IGBT parasitic diode. In addition, since the current flowing from the collector electrode to the emitter electrode is suppressed by the pn junction between the electric field progress prevention region and the drift region when the IGBT is driven, the saturation current of the IGBT can be reduced.

  The present specification further discloses a MOSFET. The MOSFET includes a drain electrode, a drain region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, a body region made of a second conductivity type semiconductor, and a first conductivity. A source region made of a semiconductor of a type, a source electrode, and a gate electrode facing the body region between the source region and the drift region with an insulating film interposed therebetween. The MOSFET electrically connects the barrier region and the source electrode formed between the drift region and the body region and made of a first conductivity type semiconductor having a higher concentration than the drift region. And a hetero semiconductor region made of a semiconductor having a band gap smaller than that of the barrier region. In the MOSFET, the hetero semiconductor region and the barrier region are heterojunctioned.

  According to the above-described MOSFET, it is possible to reduce the switching loss of the parasitic diode and to improve the withstand voltage against the reverse bias with a structure in which the quality does not easily vary during manufacturing.

  The MOSFET preferably further includes an electric field progress prevention region made of a second conductivity type semiconductor and formed between the barrier region and the drift region.

  In the MOSFET described above, the withstand voltage against reverse bias can be further improved, and the leakage current at the time of reverse bias can be reduced.

  According to the technology disclosed in this specification, it is possible to realize a reduction in switching loss in a diode with a structure in which quality variation hardly occurs during manufacturing.

FIG. 3 is a diagram schematically illustrating a configuration of a diode 2 according to the first embodiment. 3 is a graph comparing reverse recovery characteristics of a diode 2 of Example 1 and a diode 26 of Comparative Example 1; 6 is a diagram schematically showing a configuration of a diode 26 of Comparative Example 1. FIG. FIG. 6 is a diagram schematically showing a configuration of a diode 32 of Example 2. 6 is a graph comparing the leakage current when reverse bias is applied between the diode 2 of the first embodiment and the diode 32 of the second embodiment. It is a graph which compares the withstand voltage at the time of reverse bias application of the diode 2 of Example 1, and the diode 32 of Example 2. FIG. FIG. 6 is a diagram schematically showing a configuration of a diode 42 of Example 3. FIG. 6 is a diagram schematically showing a configuration of a diode 52 of Example 4. FIG. 6 is a diagram schematically showing a configuration of a diode 62 of Example 5. FIG. 6 is a diagram schematically illustrating a configuration of a modification of the diode 2 according to the first embodiment. FIG. 6 is a diagram schematically showing a configuration of a modified example of a diode 32 of Example 2. FIG. 10 is a diagram schematically illustrating a configuration of a modified example of the diode 42 according to the third embodiment. FIG. 10 is a diagram schematically showing a configuration of a semiconductor device 72 of Example 6. FIG. 10 is a diagram schematically showing a configuration of a semiconductor device 82 of Example 7. FIG. 10 schematically shows a configuration of a semiconductor device 102 according to an eighth embodiment. FIG. 10 is a diagram schematically illustrating a configuration of a semiconductor device 162 according to an embodiment 9; FIG. 10 is a diagram schematically showing a configuration of a semiconductor device 172 of Example 10. FIG. 15 is a diagram schematically showing a configuration of a semiconductor device 182 of Example 11. FIG. 16 is a diagram schematically showing a configuration of a semiconductor device 202 of Example 12. FIG. 16 is a diagram schematically showing a configuration of a semiconductor device 232 of Example 13. FIG. 16 is a diagram schematically showing a configuration of a semiconductor device 242 of Example 14. FIG. 16 is a diagram schematically showing a configuration of a semiconductor device 252 of Example 15. It is a figure which shows typically the structure of the diode 302 of Example 16. FIG. FIG. 15 is a diagram schematically showing a configuration of a diode 304 of Example 17. It is a figure which shows typically the structure of the diode 306 of another Example. It is a figure which shows typically the structure of the diode 308 of another Example. It is a figure which shows typically the structure of the diode 310 of another Example. It is a figure which shows typically the structure of the diode 312 of another Example. It is a figure which shows typically the structure of the diode 314 of another Example. It is a figure which shows typically the structure of the diode 316 of another Example. It is a figure which shows typically the structure of the semiconductor device 318 of another Example. It is a figure which shows typically the structure of the semiconductor device 320 of another Example. It is a figure which shows typically the structure of the semiconductor device 322 of another Example. It is a figure which shows typically the structure of the semiconductor device 324 of another Example. It is a figure which shows typically the structure of the semiconductor device 326 of another Example. It is a figure which shows typically the structure of the semiconductor device 328 of another Example. It is a figure which shows typically the structure of the semiconductor device 330 of another Example. It is a figure which shows typically the structure of the semiconductor device 332 of another Example. It is a figure which shows typically the structure of the semiconductor device 334 of another Example. It is a figure which shows typically the structure of the semiconductor device 336 of another Example.

Example 1
As shown in FIG. 1, the diode 2 of the present embodiment is formed using a silicon semiconductor substrate 4. The semiconductor substrate 4 includes an n ⁺ cathode region 6 that is a high concentration n-type semiconductor region, an n buffer region 8 that is an n-type semiconductor region, an n ⁻ drift region 10 that is a low-concentration n-type semiconductor region, and an n-type. An n barrier region 12 that is a semiconductor region and a p anode region 14 that is a p-type semiconductor region are sequentially stacked. In this embodiment, for example, phosphorus is added as an impurity to the n-type semiconductor region, and boron is added as an impurity to the p-type semiconductor region. In this embodiment, the impurity concentration of the n ⁺ cathode region 6 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ], and the impurity concentration of the n buffer region 8 is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [ cm ⁻³ ], the impurity concentration of the n ⁻ drift region 10 is about 1 × 10 ¹² to 1 × 10 ¹⁵ [cm ⁻³ ], and the impurity concentration of the n barrier region 12 is 1 × 10 ¹⁵ to 1 ×. 10 ¹⁸ is approximately [cm ^-3], the impurity concentration of the p-anode region 14 is approximately ^{1 × 10 16 ~1 × 10 19} [cm -3]. The thickness of the n barrier region 12 is about 0.5 to 3.0 [μm].

A plurality of n-pillar regions 16 that are n-type semiconductor regions are formed on the upper surface of the semiconductor substrate 4 at a predetermined interval. The impurity concentration of the n pillar region 16 is about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [cm ⁻³ ]. The n pillar region 16 is formed so as to penetrate the p anode region 14 and reach the upper surface of the n barrier region 12. A plurality of p ⁺ contact regions 18 that are high-concentration p-type semiconductor regions are formed on the upper surface of the p anode region 14 at a predetermined interval. The impurity concentration of the p ⁺ contact region 18 is about 1 × 10 ¹⁷ to 1 × 10 ²⁰ [cm ⁻³ ].

  On the upper surface of the semiconductor substrate 4, a hetero semiconductor region 23 made of a semiconductor having a smaller band gap than silicon is laminated so as to cover the upper surface of the n pillar region 16. In this embodiment, the hetero semiconductor region 23 is made of, for example, n-type germanium to which phosphorus is added as an impurity. The hetero semiconductor region 23 is formed, for example, by stacking germanium on the upper surface of the semiconductor substrate 4 by epitaxial growth and trimming the stacked germanium. The hetero semiconductor region 23 and the n pillar region 16 are heterojunction through the hetero junction interface 24.

A metal cathode electrode 20 is formed on the lower surface of the semiconductor substrate 4. The cathode electrode 20 is joined to the n ⁺ cathode region 6 by an ohmic junction. A metal anode electrode 22 is formed on the upper surface of the semiconductor substrate 4. The anode electrode 22 is joined to the p anode region 14, the p ⁺ contact region 18 and the hetero semiconductor region 23 through an ohmic junction.

The operation of the diode 2 will be described. When a forward bias is applied between the anode electrode 22 and the cathode electrode 20, a short circuit occurs via the heterojunction interface 24 between the hetero semiconductor region 23 and the n pillar region 16. Since the n pillar region 16 and the n barrier region 12 have substantially the same potential, the potential difference between the n barrier region 12 and the anode electrode 22 becomes substantially equal to the voltage drop at the heterojunction interface 24. Since the voltage drop at the heterojunction interface 24 is sufficiently smaller than the built-in voltage of the pn junction between the p anode region 14 and the n barrier region 12, the n ⁻ drift region 10 extends from the p ⁺ contact region 18 and the p anode region 14. The injection of holes into the is suppressed. Between the anode electrode 22 and the cathode electrode 20, the hetero semiconductor region 23, the heterojunction interface 24 between the hetero semiconductor region 23 and the n pillar region 16, the n pillar region 16, the n barrier region 12, and the n ⁻ drift region are mainly used. 10. A forward current flows through the n buffer region 8 and the n ⁺ cathode region 6.

Next, when the voltage between the anode electrode 22 and the cathode electrode 20 is switched from the forward bias to the reverse bias, the reverse current is limited by the heterojunction interface 24 between the hetero semiconductor region 23 and the n pillar region 16. As described above, in the diode 2 of this embodiment, the injection of holes from the p ⁺ contact region 18 and the p anode region 14 to the n ⁻ drift region 10 is suppressed when a forward bias is applied. Low current and short reverse recovery time. According to the diode 2 of the present embodiment, the switching loss can be reduced without performing lifetime control of the n ⁻ drift region 10.

  In the diode 2 of this embodiment, when a reverse bias is applied between the anode electrode 22 and the cathode electrode 20, only the depletion layer extending from the heterojunction interface 24 between the hetero semiconductor region 23 and the n pillar region 16 is obtained. In addition, the electric field is also shared by the depletion layer extending from the interface of the pn junction between the p anode region 14 and the n barrier region 12. As a result, the electric field applied to the heterojunction interface 24 between the hetero semiconductor region 23 and the n pillar region 16 is reduced. According to the diode 2 of the present embodiment, the breakdown voltage against the reverse bias can be improved.

  FIG. 2 compares the reverse recovery characteristics of the diode 2 of Example 1 and the diode 26 of Comparative Example 1 which is a conventional technique.

FIG. 3 shows the structure of the diode 26 of the first comparative example. The diode 26 includes an n ⁺ cathode region 6 that is a high concentration n-type semiconductor region, an n buffer region 8 that is an n-type semiconductor region, and an n ⁻ drift region 10 that is a low-concentration n-type semiconductor region. It is formed on a silicon semiconductor substrate 28. A plurality of p anode regions 14, which are p type semiconductor regions, are formed on the surface of the n ⁻ drift region 10 at a predetermined interval. A plurality of p ⁺ contact regions 18 that are high-concentration p-type semiconductor regions are formed on the upper surface of the p anode region 14 at a predetermined interval. A metal cathode electrode 20 is formed on the lower surface of the semiconductor substrate 28. The cathode electrode 20 is joined to the n ⁺ cathode region 6 by an ohmic junction. A metal anode electrode 22 is formed on the upper surface of the semiconductor substrate 28. The anode electrode 22 is joined to the n ⁻ drift region 10 by a Schottky junction via the Schottky interface 30. The anode electrode 22 is joined to the p anode region 14 and the p ⁺ contact region 18 by an ohmic junction. That is, the diode 26 of Comparative Example 1 is different from the diode 2 of Example 1 in that the n barrier region 12 and the n pillar region 16 are not provided. The diode 26 of Comparative Example 1 is different from the diode 2 of Example 1 in that the rectifying action is realized not by a heterojunction but by a Schottky junction. This difference is the reverse recovery characteristic shown in FIG. Note that does not have a significant effect.

  As apparent from FIG. 2, the diode 2 of Example 1 has a smaller reverse recovery current and shorter reverse recovery time than the diode 26 of Comparative Example 1. According to the diode 2 of the present embodiment, switching loss can be reduced.

  In the diode 2 of the present embodiment, the impurity concentration in the n pillar region 16 is higher than the impurity concentration in the n barrier region 12. With such a configuration, the potential difference between the n barrier region 12 and the anode electrode 22 when a forward bias is applied can be reduced without reducing the thickness of the p anode region 14. According to the diode 2 of the present embodiment, it is possible to suppress the reach-through with respect to the reverse bias and reduce the switching loss without lowering the breakdown voltage.

  In the diode 2 of the present embodiment, the rectifying action is realized by using a heterojunction instead of a Schottky junction for the electrical connection between the anode electrode 22 and the n barrier region 12. In general, when a rectifying action is realized using a Schottky junction, the operation is greatly affected by the quality of the interface of the Schottky junction. However, the quality of the Schottky junction interface is likely to vary during manufacturing. On the other hand, even when the rectifying action is realized using a heterojunction, the operation is greatly influenced by the quality of the interface of the heterojunction, but the heterojunction interface is unlikely to vary in quality during manufacturing. According to the diode 2 of the present embodiment, the switching loss can be reduced with a structure in which the quality does not easily vary during manufacture.

(Example 2)
As shown in FIG. 4, the diode 32 of this embodiment is formed using a silicon semiconductor substrate 34. The semiconductor substrate 34 includes an n ⁺ cathode region 6 that is a high-concentration n-type semiconductor region, an n buffer region 8 that is an n-type semiconductor region, an n ⁻ drift region 10 that is a low-concentration n-type semiconductor region, and a p-type. A p electric field progress preventing region 36 that is a semiconductor region, an n barrier region 12 that is an n type semiconductor region, and a p anode region 14 that is a p type semiconductor region are sequentially stacked. In the present embodiment, the impurity concentration of the p electric field progress preventing region 36 is about 1 × 10 ¹⁵ to 1 × 10 ¹⁹ [cm ⁻³ ]. The thickness of the p electric field progress preventing region 36 is about 0.5 to 3.0 [μm].

A plurality of n pillar regions 16, which are n type semiconductor regions, are formed on the upper surface of the semiconductor substrate 34 at a predetermined interval. The n pillar region 16 is formed so as to penetrate the p anode region 14 and reach the upper surface of the n barrier region 12. A plurality of p ⁺ contact regions 18 that are high-concentration p-type semiconductor regions are formed on the upper surface of the p anode region 14 at a predetermined interval.

  On the upper surface of the semiconductor substrate 34, a hetero semiconductor region 23 made of a semiconductor having a smaller band gap than silicon is laminated so as to cover the upper surface of the n pillar region 16. The hetero semiconductor region 23 and the n pillar region 16 are heterojunction through the hetero junction interface 24.

A metal cathode electrode 20 is formed on the lower surface of the semiconductor substrate 34. The cathode electrode 20 is joined to the n ⁺ cathode region 6 by an ohmic junction. A metal anode electrode 22 is formed on the upper surface of the semiconductor substrate 34. The anode electrode 22 is joined to the p anode region 14, the p ⁺ contact region 18 and the hetero semiconductor region 23 through an ohmic junction.

The operation of the diode 32 will be described. When a forward bias is applied between the anode electrode 22 and the cathode electrode 20, a short circuit occurs via the heterojunction interface 24 between the hetero semiconductor region 23 and the n pillar region 16. Since the n pillar region 16 and the n barrier region 12 have substantially the same potential, the potential difference between the n barrier region 12 and the anode electrode 22 becomes substantially equal to the voltage drop at the heterojunction interface 24. Since the voltage drop at the heterojunction interface 24 is sufficiently smaller than the built-in voltage of the pn junction between the p anode region 14 and the n barrier region 12, the n ⁻ drift region 10 extends from the p ⁺ contact region 18 and the p anode region 14. The injection of holes into the is suppressed. Between the anode electrode 22 and the cathode electrode 20, the hetero semiconductor region 23, the heterojunction interface 24 between the hetero semiconductor region 23 and the n pillar region 16, the n pillar region 16, the n barrier region 12, and the p electric field progress preventing region 36. , N ⁻ drift region 10, n buffer region 8, and n ⁺ cathode region 6 forward current flows. Although a pn junction exists between the n barrier region 12 and the p electric field progress preventing region 36, the p type impurity concentration of the p electric field progress preventing region 36 is low and the thickness of the p electric field progress preventing region 36 is thin. The influence on the forward current between the anode electrode 22 and the cathode electrode 20 is small.

Next, when the voltage between the anode electrode 22 and the cathode electrode 20 is switched from the forward bias to the reverse bias, the reverse current is limited by the heterojunction interface 24 between the hetero semiconductor region 23 and the n pillar region 16. The reverse current is also limited by the pn junction between the n ⁻ drift region 10 and the p electric field progress preventing region 36. As described above, in the diode 32 of the present embodiment, the injection of holes from the p ⁺ contact region 18 and the p anode region 14 to the n ⁻ drift region 10 is suppressed when a forward bias is applied, and therefore reverse recovery is performed. Low current and short reverse recovery time. According to the diode 32 of this embodiment, the switching loss can be reduced without performing lifetime control of the n ⁻ drift region 10.

In the diode 32 of this embodiment, when a reverse bias is applied between the anode electrode 22 and the cathode electrode 20, only the depletion layer extending from the heterojunction interface 24 between the hetero semiconductor region 23 and the n pillar region 16 is used. In addition, the electric field is also shared by the depletion layer extending from the pn junction interface between the p anode region 14 and the n barrier region 12 and the pn junction interface between the n ⁻ drift region 10 and the p electric field progress preventing region 36. Thereby, the electric field applied to the heterojunction interface 24 between the hetero semiconductor region 23 and the n pillar region 16 and the electric field applied to the pn junction between the p anode region 14 and the n barrier region 12 are reduced. According to the diode 32 of the present embodiment, the breakdown voltage against the reverse bias can be improved.

  FIG. 5 is a comparison of the leakage current when reverse bias is applied to the diode 2 of the first embodiment and the diode 32 of the second embodiment. As is apparent from FIG. 5, the diode 32 of the second embodiment has a reduced leakage current when a reverse bias is applied, as compared with the diode 2 of the first embodiment.

  FIG. 6 is a comparison of the withstand voltage when reverse bias is applied to the diode 2 of the first embodiment and the diode 32 of the second embodiment. As can be seen from FIG. 6, the diode 32 of the second embodiment has a higher breakdown voltage when a reverse bias is applied than the diode 2 of the first embodiment.

(Example 3)
As shown in FIG. 7, the diode 42 of the present embodiment is formed using a silicon semiconductor substrate 4 in the same manner as the diode 2 of the first embodiment. The semiconductor substrate 4 includes an n ⁺ cathode region 6 that is a high concentration n-type semiconductor region, an n buffer region 8 that is an n-type semiconductor region, an n ⁻ drift region 10 that is a low-concentration n-type semiconductor region, and an n-type. An n barrier region 12 that is a semiconductor region and a p anode region 14 that is a p-type semiconductor region are sequentially stacked. A plurality of n-pillar regions 16 that are n-type semiconductor regions are formed on the upper surface of the semiconductor substrate 4 at a predetermined interval. The n pillar region 16 is formed so as to penetrate the p anode region 14 and reach the upper surface of the n barrier region 12. A plurality of trenches 44 are formed at predetermined intervals on the upper side of the semiconductor substrate 4. Each trench 44 penetrates the n barrier region 12 from the upper surface of the p anode region 14 and reaches the inside of the n ⁻ drift region 10. The trench 44 is filled with a trench electrode 48 covered with an insulating film 46. A plurality of p ⁺ contact regions 18 that are high-concentration p-type semiconductor regions are formed on the upper surface of the p anode region 14 at a predetermined interval.

  On the upper surface of the semiconductor substrate 4, a hetero semiconductor region 23 made of a semiconductor having a smaller band gap than silicon is laminated so as to cover the upper surface of the n pillar region 16. The hetero semiconductor region 23 and the n pillar region 16 are heterojunction through the hetero junction interface 24.

A metal cathode electrode 20 is formed on the lower surface of the semiconductor substrate 4. The cathode electrode 20 is joined to the n ⁺ cathode region 6 by an ohmic junction. A metal anode electrode 22 is formed on the upper surface of the semiconductor substrate 4. The anode electrode 22 is joined to the p anode region 14, the p ⁺ contact region 18 and the hetero semiconductor region 23 through an ohmic junction.

The operation of the diode 42 of the present embodiment is almost the same as the operation of the diode 2 of the first embodiment. In the diode 42 of the present embodiment, the withstand voltage can be improved by adjusting the voltage applied to the trench electrode 48 when a reverse bias is applied between the anode electrode 22 and the cathode electrode 20. For example, when the voltage applied to the trench electrode 48 is adjusted so that the trench electrode 48 and the anode electrode 22 have substantially the same potential when a reverse bias is applied, a location near the tip of the trench electrode 48 inside the n ⁻ drift region 10. As a result, the electric field concentration occurs in the heterojunction interface 24 between the hetero semiconductor region 23 and the n pillar region 16 and the electric field applied to the pn junction interface between the p anode region 14 and the n barrier region 12. . Note that the potential of the trench electrode 48 is not necessarily the same as that of the anode electrode 22. By applying the reverse bias so that the potential of the trench electrode 48 becomes lower than the potential of the cathode electrode 20, the heterojunction interface 24 between the hetero semiconductor region 23 and the n pillar region 16, the p anode region 14, The electric field applied to the pn junction interface between the n barrier regions 12 can be reduced. According to the diode 42 of the present embodiment, the breakdown voltage against the reverse bias can be improved.

Example 4
As shown in FIG. 8, the diode 52 of this embodiment is formed using a silicon semiconductor substrate 34, similarly to the diode 32 of the second embodiment. The semiconductor substrate 34 includes an n ⁺ cathode region 6 that is a high-concentration n-type semiconductor region, an n buffer region 8 that is an n-type semiconductor region, an n ⁻ drift region 10 that is a low-concentration n-type semiconductor region, and a p-type. A p electric field progress preventing region 36 that is a semiconductor region, an n barrier region 12 that is an n type semiconductor region, and a p anode region 14 that is a p type semiconductor region are sequentially stacked. A plurality of n pillar regions 16, which are n type semiconductor regions, are formed on the upper surface of the semiconductor substrate 34 at a predetermined interval. The n pillar region 16 is formed so as to penetrate the p anode region 14 and reach the upper surface of the n barrier region 12. A plurality of trenches 44 are formed at predetermined intervals on the upper side of the semiconductor substrate 34. Each trench 44 extends from the upper surface of the p anode region 14 to the inside of the n ⁻ drift region 10 through the n barrier region 12 and the p electric field progress preventing region 36. The trench 44 is filled with a trench electrode 48 covered with an insulating film 46. A plurality of p ⁺ contact regions 18 that are high-concentration p-type semiconductor regions are formed on the upper surface of the p anode region 14 at a predetermined interval.

  On the upper surface of the semiconductor substrate 34, a hetero semiconductor region 23 made of a semiconductor having a smaller band gap than silicon is laminated so as to cover the upper surface of the n pillar region 16. The hetero semiconductor region 23 and the n pillar region 16 are heterojunction through the hetero junction interface 24.

A metal cathode electrode 20 is formed on the lower surface of the semiconductor substrate 34. The cathode electrode 20 is joined to the n ⁺ cathode region 6 by an ohmic junction. A metal anode electrode 22 is formed on the upper surface of the semiconductor substrate 34. The anode electrode 22 is joined to the p anode region 14, the p ⁺ contact region 18 and the hetero semiconductor region 23 through an ohmic junction.

The operation of the diode 52 of the present embodiment is almost the same as the operation of the diode 32 of the second embodiment. In the diode 52 of the present embodiment, similarly to the diode 42 of the third embodiment, when a reverse bias is applied between the anode electrode 22 and the cathode electrode 20, the voltage applied to the trench electrode 48 is adjusted. The breakdown voltage can be improved. For example, when the voltage applied to the trench electrode 48 is adjusted so that the trench electrode 48 and the anode electrode 22 have substantially the same potential when a reverse bias is applied, a location near the tip of the trench electrode 48 inside the n ⁻ drift region 10. As a result, an electric field concentration occurs in the heterojunction interface 24 between the hetero semiconductor region 23 and the n pillar region 16, a pn junction interface between the p anode region 14 and the n barrier region 12, and the n ⁻ drift region 10. And the electric field applied to the interface of the pn junction between the p electric field progress preventing region 36 is reduced. According to the diode 52 of the present embodiment, the breakdown voltage against the reverse bias can be improved.

(Example 5)
As shown in FIG. 10, the diode 62 of the present embodiment has a configuration substantially similar to that of the diode 52 of the fourth embodiment. In the diode 62 of the present embodiment, a plurality of p ⁺ cathode short regions 64 that are high-concentration p-type semiconductor regions are formed in the n ⁺ cathode region 6 at a predetermined interval. 52. In this embodiment, the impurity concentration of the p ⁺ cathode short region 64 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ].

The operation of the diode 62 of this embodiment is substantially the same as that of the diode 52 of the fourth embodiment. In the diode 62 of this embodiment, when a forward bias is applied between the anode electrode 22 and the cathode electrode 20, the p ⁺ cathode short region 64 is formed, so that the n ⁻ drift from the n ⁺ cathode region 6 is formed. Electron injection into the region 10 is suppressed. According to the diode 62 of the present embodiment, not only the injection of holes from the p ⁺ contact region 18 and the p anode region 14 to the n ⁻ drift region 10 is suppressed during forward bias application, but also n ⁺ Since the injection of electrons from the cathode region 6 to the n ⁻ drift region 10 is also suppressed, the reverse recovery current can be further reduced and the reverse recovery time can be further shortened. According to the diode 62 of this embodiment, the switching loss can be further reduced.

Note that the improvement of the reverse recovery characteristic by providing the p ⁺ cathode short region 64 as described above is also effective in other types of diodes. That is, like the diode 66 shown in FIG. 10, the diode 2 of the first embodiment can be configured such that the p ⁺ cathode short region 64 is provided in the n ⁺ cathode region 6, or the diode 68 shown in FIG. As described above, the diode 32 of the second embodiment may be configured such that the p ⁺ cathode short region 64 is provided in the n ⁺ cathode region 6, or the diode 42 of the third embodiment as in the diode 70 shown in FIG. 12. In this case, a p ⁺ cathode short region 64 may be provided in the n ⁺ cathode region 6.

(Example 6)
As shown in FIG. 13, the semiconductor device 72 of the present embodiment has a configuration substantially similar to that of the diode 42 of the third embodiment. In the semiconductor device 72, an n ⁺ emitter region 74 that is a high-concentration n-type semiconductor region is formed at a location adjacent to the trench 44 on the upper surface of the p anode region 14. In this embodiment, the impurity concentration of the n ⁺ emitter region 74 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ]. The n ⁺ emitter region 74 is joined to the anode electrode 22 through an ohmic junction.

The semiconductor device 72 of this embodiment includes a cathode electrode 20 corresponding to a drain electrode, an n ⁺ cathode region 6 corresponding to a drain region, an n buffer region 8, an n ⁻ drift region 10 and a p corresponding to a body region. an anode region 14, the ^{n +} emitter region 74 corresponding to the source region, an anode electrode 22 that corresponds to the source electrode, the ^{n +} emitter region 74 and the n ^- insulating film with respect to the p anode region 14 between the drift region 10 The structure of the vertical MOSFET provided with the trench electrode 48 corresponding to the gate electrode facing each other with the 46 interposed therebetween.

  Similar to the diode 42 of the third embodiment, according to the semiconductor device 72 of the present embodiment, the reverse recovery characteristic of the parasitic diode can be improved and the switching loss can be reduced. Further, similarly to the diode 42 of the third embodiment, the semiconductor device 72 of the present embodiment can improve the breakdown voltage against the reverse bias.

(Example 7)
As shown in FIG. 14, the semiconductor device 82 of the present embodiment has a configuration substantially similar to that of the diode 52 of the fourth embodiment. In the semiconductor device 82, an n ⁺ emitter region 74 is formed at a location adjacent to the trench 44 on the upper surface of the p anode region 14. The n ⁺ emitter region 74 is joined to the anode electrode 22 through an ohmic junction.

The semiconductor device 82 of this example includes a cathode electrode 20 corresponding to a drain electrode, an n ⁺ cathode region 6 corresponding to a drain region, an n buffer region 8, an n ⁻ drift region 10, and a p corresponding to a body region. an anode region 14, the ^{n +} emitter region 74 corresponding to the source region, an anode electrode 22 that corresponds to the source electrode, the ^{n +} emitter region 74 and the n ^- insulating film with respect to the p anode region 14 between the drift region 10 The structure of the vertical MOSFET provided with the trench electrode 48 corresponding to the gate electrode facing each other with the 46 interposed therebetween.

  Similar to the diode 52 of the fourth embodiment, the semiconductor device 82 of the present embodiment can improve the reverse recovery characteristics of the parasitic diode and reduce the switching loss. Further, similarly to the diode 52 of the fourth embodiment, according to the semiconductor device 82 of the present embodiment, the breakdown voltage against the reverse bias can be improved and the leak current at the time of the reverse bias can be suppressed.

(Example 8)
As shown in FIG. 15, the semiconductor device 102 of this embodiment is formed using a silicon semiconductor substrate 104. The semiconductor device 102 includes an IGBT region 106 and a diode region 108. In the IGBT region 106, the semiconductor substrate 104 includes a p ⁺ collector region 110 that is a high concentration p-type semiconductor region, an n buffer region 112 that is an n type semiconductor region, and an n ⁻ drift region 114 that is a low concentration n type semiconductor region. In addition, an n barrier region 116 that is an n-type semiconductor region and a p body region 118 that is a p-type semiconductor region are sequentially stacked. In this embodiment, the impurity concentration of the p ⁺ collector region 110 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ], and the impurity concentration of the n buffer region 112 is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [ cm ⁻³ ], the impurity concentration of the n ⁻ drift region 114 is about 1 × 10 ¹² to 1 × 10 ¹⁵ [cm ⁻³ ], and the impurity concentration of the n barrier region 116 is 1 × 10 ¹⁵ to 1 ×. 10 ¹⁸ is approximately [cm ^-3], the impurity concentration of the p-body region 118 is approximately ^{1 × 10 16 ~1 × 10 19} [cm -3]. The thickness of the n barrier region 116 is about 0.5 to 3.0 [μm]. In the diode region 108, the semiconductor substrate 104 is an n ⁺ cathode region 120 that is a high concentration n-type semiconductor region, an n buffer region 112, an n ⁻ drift region 114, an n barrier region 122, and a p-type semiconductor region. The p anode region 124 is sequentially stacked. In this embodiment, the impurity concentration of the n ⁺ cathode region 120 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ], and the impurity concentration of the n barrier region 122 is 1 × 10 ¹⁵ to 1 × 10 ¹⁸ [ cm ⁻³ ], and the impurity concentration of the p anode region 124 is about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [cm ⁻³ ]. The thickness of the n barrier region 122 is about 0.5 to 3.0 [μm]. A plurality of trenches 126 are formed at predetermined intervals on the upper side of the semiconductor substrate 4.

In IGBT region 106, trench 126 extends from the upper surface of p body region 118 through n barrier region 116 to the inside of n ⁻ drift region 114. The trench 126 is filled with a gate electrode 130 covered with an insulating film 128. On the upper surface of p body region 118, n ⁺ emitter region 132, which is a high concentration n-type semiconductor region, is formed at a location adjacent to trench 126. The impurity concentration of the n ⁺ emitter region 132 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ]. An n-pillar region 134 that is an n-type semiconductor region is formed on the upper surface of the p body region 118. The impurity concentration of the n pillar region 134 is about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [cm ⁻³ ]. N pillar region 134 is formed so as to penetrate p body region 118 and reach the upper surface of n barrier region 116. Further, on the upper surface of the p body region 118, ap ⁺ contact region 136 which is a high concentration p-type semiconductor region is formed. The impurity concentration of the p ⁺ contact region 136 is about 1 × 10 ¹⁷ to 1 × 10 ²⁰ [cm ⁻³ ].

In the diode region 108, the trench 126 penetrates the n barrier region 122 from the upper surface of the p anode region 124 and reaches the inside of the n ⁻ drift region 114. The trench 126 is filled with a gate electrode 140 covered with an insulating film 138. On the upper surface of the p anode region 124, an n pillar region 142 which is an n type semiconductor region is formed. The impurity concentration of the n pillar region 142 is about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [cm ⁻³ ]. The n pillar region 142 is formed so as to penetrate the p anode region 124 and reach the upper surface of the n barrier region 122. A p ⁺ contact region 144 that is a high concentration p-type semiconductor region is formed on the upper surface of the p anode region 124. The impurity concentration of the p ⁺ contact region 144 is about 1 × 10 ¹⁷ to 1 × 10 ²⁰ [cm ⁻³ ].

  On the upper surface of the semiconductor substrate 104, hetero semiconductor regions 149 and 151 made of a semiconductor having a smaller band gap than silicon are stacked. In the IGBT region 106, the hetero semiconductor region 149 is laminated so as to cover the upper surface of the n pillar region 134. The hetero semiconductor region 149 and the n pillar region 134 are heterojunction through the hetero junction interface 150. In the diode region 108, the hetero semiconductor region 151 is stacked so as to cover the upper surface of the n pillar region 142. The hetero semiconductor region 151 and the n pillar region 142 are heterojunction through the hetero junction interface 152. In this embodiment, the hetero semiconductor regions 149 and 151 are made of, for example, n-type germanium to which phosphorus is added as an impurity. The hetero semiconductor regions 149 and 151 are formed, for example, by stacking germanium on the upper surface of the semiconductor substrate 104 by epitaxial growth and trimming the stacked germanium.

A metal collector / cathode electrode 146 is formed on the lower surface of the semiconductor substrate 104. The collector / cathode electrode 146 is joined to the p ⁺ collector region 110 and the n ⁺ cathode region 120 through an ohmic junction. The collector / cathode electrode 146 functions as a collector electrode in the IGBT region 106 and functions as a cathode electrode in the diode region 108.

A metal emitter / anode electrode 148 is formed on the upper surface of the semiconductor substrate 104. The emitter / anode electrode 148 is joined to the n ⁺ emitter region 132, the p ⁺ contact region 136 and the hetero semiconductor region 149 of the IGBT region 106, and the p ⁺ contact region 144 and the hetero semiconductor region 151 of the diode region 108 through an ohmic junction. Yes. The emitter / anode electrode 148 functions as an emitter electrode in the IGBT region 106 and functions as an anode electrode in the diode region 108.

  The gate electrode 130 of the IGBT region 106 is electrically connected to a first gate electrode terminal (not shown). The gate electrode 140 of the diode region 108 is electrically connected to a second gate electrode terminal (not shown).

  As described above, the semiconductor device 102 has a structure in which the IGBT region 106 that functions as a trench IGBT and the diode region 108 that functions as a freewheeling diode are connected in antiparallel.

An operation of the semiconductor device 102 will be described. When no voltage is applied to the gate electrode 130 and thus the IGBT region 106 is not driven, the IGBT region 106 functions as a parasitic diode. In this state, when a forward bias is applied between the emitter / anode electrode 148 and the collector / cathode electrode 146, the diode region 108 passes through the heterojunction interface 152 between the hetero semiconductor region 151 and the n pillar region 142. Short circuit. Since the n pillar region 142 and the n barrier region 122 have substantially the same potential, the potential difference between the n barrier region 122 and the emitter / anode electrode 148 becomes substantially equal to the voltage drop at the heterojunction interface 152. Since the voltage drop at the heterojunction interface 152 is sufficiently smaller than the built-in voltage of the pn junction between the p anode region 124 and the n barrier region 122, the n ⁻ drift region 114 from the p ⁺ contact region 144 and the p anode region 124. The injection of holes into the is suppressed. The IGBT region 106 is short-circuited via the heterojunction interface 150 between the hetero semiconductor region 149 and the n pillar region 134. Since the n pillar region 134 and the n barrier region 116 have substantially the same potential, the potential difference between the n barrier region 116 and the emitter / anode electrode 148 becomes substantially equal to the voltage drop at the heterojunction interface 150. Since the voltage drop at the heterojunction interface 150 is sufficiently smaller than the built-in voltage of the pn junction between the p body region 118 and the n barrier region 116, the n ⁻ drift region 114 from the p ⁺ contact region 136 and the p body region 118. The injection of holes into the is suppressed. Between the emitter / anode electrode 148 and the collector / cathode electrode 146, the hetero semiconductor region 151 of the diode region 108, the heterojunction interface 152 between the hetero semiconductor region 151 and the n pillar region 142, the n pillar region 142, n Forward current passing through the barrier region 122, the n ⁻ drift region 114, the n buffer region 112, and the n ⁺ cathode region 120, and the hetero semiconductor region 149 of the IGBT region 106, and the heterojunction between the hetero semiconductor region 149 and the n pillar region 134 A forward current flows through the interface 150, the n pillar region 134, the n barrier region 116, the n ⁻ drift region 114, the n buffer region 112, and the n ⁺ cathode region 120.

Next, when the voltage between the emitter / anode electrode 148 and the collector / cathode electrode 146 switches from forward bias to reverse bias, reverse current is generated by the heterojunction interface 152 in the diode region 108 and by the heterojunction interface 150 in the IGBT region 106. Limited. As described above, in the diode region 108, injection of holes from the p ⁺ contact region 144 and the p anode region 124 to the n ⁻ drift region 114 is suppressed when a forward bias is applied. When a bias is applied, injection of holes from the p ⁺ contact region 136 and the p body region 118 to the n ⁻ drift region 114 is suppressed. Therefore, the semiconductor device 102 has a small reverse recovery current and a short reverse recovery time. According to the semiconductor device 102 of this embodiment, the switching loss can be reduced without performing lifetime control of the n ⁻ drift region 114.

Further, in the semiconductor device 102 of this embodiment, when a reverse bias is applied between the emitter / anode electrode 148 and the collector / cathode electrode 146, the IGBT region 106 not only has a depletion layer extending from the heterojunction interface 150, The electric field is also shared by the depletion layer extending from the pn junction interface between p body region 118 and n barrier region 116. Furthermore, the electric field is concentrated near the tip of the trench 126 in the n ⁻ drift region 114, thereby reducing the electric field applied to the heterojunction interface 150 and the pn junction between the p body region 118 and the n barrier region 116. Is done. Similarly, when a reverse bias is applied between the emitter / anode electrode 148 and the collector / cathode electrode 146, in the diode region 108, not only the depletion layer extending from the heterojunction interface 152 but also the p anode region 124 and the n barrier region. The electric field is also shared by the depletion layer extending from the interface of the pn junction 122. Furthermore, the electric field is concentrated near the tip of the trench 126 in the n ⁻ drift region 114, thereby reducing the electric field applied to the heterojunction interface 152 and the electric field applied to the pn junction between the p anode region 124 and the n barrier region 122. Is done. According to the semiconductor device 102 of the present embodiment, the breakdown voltage against the reverse bias can be improved.

Example 9
As shown in FIG. 16, the semiconductor device 162 of this example has a configuration substantially similar to that of the semiconductor device 102 of Example 8. The semiconductor device 162 is formed using a silicon semiconductor substrate 164. The semiconductor substrate 164 has substantially the same configuration as the semiconductor substrate 104 of the eighth embodiment. In the semiconductor substrate 164, in the IGBT region 106, a p electric field progress prevention region 166 that is a p-type semiconductor region is formed between the n ⁻ drift region 114 and the n barrier region 116, and in the diode region 108, the n ⁻ drift A p electric field progress preventing region 168 which is a p-type semiconductor region is formed between the region 114 and the n barrier region 122. The impurity concentration of the p electric field progress preventing region 166 and the p electric field progress preventing region 168 is about 1 × 10 ¹⁵ to 1 × 10 ¹⁹ [cm ⁻³ ]. The thickness of the p electric field progress preventing region 166 and the p electric field progress preventing region 168 is about 0.5 to 3.0 [μm]. In IGBT region 106, trench 126 penetrates n barrier region 116 and p electric field progress preventing region 166 from the upper surface of p body region 118 and reaches the inside of n ⁻ drift region 114. In the diode region 108, the trench 126 penetrates the n barrier region 122 and the p electric field progress preventing region 168 from the upper surface of the p anode region 124 and reaches the inside of the n ⁻ drift region 114.

According to the semiconductor device 162 of the present embodiment, when the forward bias is applied between the emitter / anode electrode 148 and the collector / cathode electrode 146, as in the semiconductor device 102 of the eighth embodiment, The injection of holes from the p ⁺ contact region 144 and the p anode region 124 to the n ⁻ drift region 114 is suppressed. In the IGBT region 106, the p ⁺ contact region 136 and the p body region 118 to the n ⁻ drift region 114. Hole injection is suppressed. Therefore, the reverse recovery current when switching from the forward bias to the reverse bias can be reduced, and the reverse recovery time can be shortened. Switching loss can be reduced.

Further, according to the semiconductor device 162 of the present embodiment, when a reverse bias is applied between the emitter / anode electrode 148 and the collector / cathode electrode 146, the IGBT region 106 has only a depletion layer extending from the heterojunction interface 150. The depletion layer extending from the pn junction interface between the p body region 118 and the n barrier region 116 and the depletion layer extending from the pn junction interface between the n ⁻ drift region 114 and the p electric field progress prevention region 166 Is shared. Further, the electric field is concentrated near the tip of the trench 126 in the n ⁻ drift region 114, so that the electric field applied to the heterojunction interface 150 and the electric field applied to the pn junction between the p body region 118 and the n barrier region 116, The electric field applied to the pn junction between n ⁻ drift region 114 and p electric field progress prevention region 166 is reduced. Similarly, when a reverse bias is applied between the emitter / anode electrode 148 and the collector / cathode electrode 146, in the diode region 108, not only the depletion layer extending from the heterojunction interface 152 but also the p anode region 124 and the n barrier region. The electric field is also shared by the depletion layer extending from the pn junction interface 122 between the n ^- drift region 114 and the p pn junction preventing region 168 extending from the pn junction interface. Furthermore, the electric field is concentrated near the tip of the trench 126 in the n ⁻ drift region 114, so that the electric field applied to the heterojunction interface 152 and the electric field applied to the pn junction between the p anode region 124 and the n barrier region 122, The electric field applied to the pn junction between n ⁻ drift region 114 and p electric field progress prevention region 168 is reduced. According to the semiconductor device 162 of this embodiment, the breakdown voltage against the reverse bias can be improved.

  Further, according to the semiconductor device 162 of the present embodiment, when a reverse bias is applied between the emitter / anode electrode 148 and the collector / cathode electrode 146, the p-field progress preventing region 168 and the n barrier region are formed in the diode region 108. Since the reverse current is limited by the pn junction between 122, the leakage current passing through the heterojunction interface 152 is reduced. In the IGBT region 106, the pn junction between the p electric field progress preventing region 166 and the n barrier region 116 is reduced. Since the reverse current is limited, the leakage current passing through the heterojunction interface 150 is reduced. According to the semiconductor device 162 of this embodiment, it is possible to reduce a leakage current when a reverse bias is applied.

  Further, in the semiconductor device 162 of the present embodiment, when the IGBT region 106 is driven by applying a voltage to the gate electrode 130 of the IGBT region 106, the current flows from the collector / cathode electrode 146 to the emitter / anode electrode 148 in the IGBT region 106. Since the current is suppressed by the p electric field progress preventing region 166, the saturation current of the IGBT region 106 can be reduced.

(Example 10)
As shown in FIG. 17, the semiconductor device 172 of this example has a configuration substantially similar to that of the semiconductor device 102 of Example 8. In the semiconductor device 172 of the present embodiment, a plurality of p ⁺ cathode short regions 174 that are high-concentration p-type semiconductor regions are formed in the n ⁺ cathode region 120 of the diode region 108 at a predetermined interval. Different from the semiconductor device 102 of the eighth embodiment. In this embodiment, the impurity concentration of the p ⁺ cathode short region 174 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ]. According to the semiconductor device 172 of the present embodiment, since the injection of electrons from the n ⁺ cathode region 120 to the n ⁻ drift region 114 is suppressed when a forward bias is applied, compared to the semiconductor device 102 of the eighth embodiment. Thus, the reverse recovery current can be further reduced and the reverse recovery time can be further shortened. According to the semiconductor device 172 of this embodiment, the switching loss can be further reduced.

(Example 11)
As shown in FIG. 18, the semiconductor device 182 of the present example has substantially the same configuration as the semiconductor device 162 of the ninth example. The semiconductor device 182 of the present embodiment is different from the semiconductor device 162 of the ninth embodiment in that a plurality of p ⁺ cathode short regions 174 are formed at predetermined intervals in the n ⁺ cathode region 120 of the diode region 108. Different. According to the semiconductor device 182 of the present embodiment, since the injection of electrons from the n ⁺ cathode region 120 to the n ⁻ drift region 114 is suppressed when a forward bias is applied, compared to the semiconductor device 162 of the ninth embodiment. Thus, the reverse recovery current can be further reduced and the reverse recovery time can be further shortened. According to the semiconductor device 182 of this embodiment, the switching loss can be further reduced.

(Example 12)
As shown in FIG. 19, the semiconductor device 202 of this embodiment is formed using a silicon semiconductor substrate 204. The semiconductor substrate 204 includes an n ⁺ cathode region 206 that is a high concentration n-type semiconductor region, an n buffer region 208 that is an n-type semiconductor region, and an n ⁻ drift region 210 that is a low-concentration n-type semiconductor region. Yes. In this embodiment, the impurity concentration of the n ⁺ cathode region 206 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ], and the impurity concentration of the n buffer region 208 is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [ cm ⁻³ ], and the impurity concentration of the n ⁻ drift region 210 is about 1 × 10 ¹² to 1 × 10 ¹⁵ [cm ⁻³ ].

A plurality of n barrier regions 212 that are n-type semiconductor regions are formed on the upper surface of the n ⁻ drift region 210 at a predetermined interval. A p anode region 214 which is a p type semiconductor region is partially formed on the upper surface of the n barrier region 212. An n pillar region 216 that is an n-type semiconductor region is formed on the upper surface of the p anode region 214. The n pillar region 216 is formed to penetrate the p anode region 214 and reach the upper surface of the n barrier region 212. Further, on the upper surface of the p anode region 214, a p ⁺ contact region 218 which is a high concentration p-type semiconductor region and an n ⁺ emitter region 220 which is a high concentration n type semiconductor region are formed. In this embodiment, the impurity concentration of the n barrier region 212 is about 1 × 10 ¹⁵ to 1 × 10 ¹⁸ [cm ⁻³ ], and the impurity concentration of the p anode region 214 is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [cm]. ⁻³ ], the impurity concentration of the n-pillar region 216 is about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [cm ⁻³ ], and the impurity concentration of the p ⁺ contact region 218 is 1 × 10 ¹⁷ to 1 × 10 ²⁰ [cm ^-3] is about, the impurity concentration of ^{n +} emitter region 220 is ^{1 × 10 17 ~5 × 10 20} [cm -3] or so. The thickness of the n barrier region 212 is about 0.5 to 3.0 [μm].

  A hetero semiconductor region 227 made of a semiconductor having a smaller band gap than silicon is stacked on the upper surface of the semiconductor substrate 204 so as to cover the upper surface of the n pillar region 216. In this embodiment, the hetero semiconductor region 227 is made of n-type germanium to which phosphorus is added as an impurity, for example. The hetero semiconductor region 227 is formed, for example, by stacking germanium on the upper surface of the semiconductor substrate 204 by epitaxial growth and trimming the stacked germanium. The hetero semiconductor region 227 and the n pillar region 216 are heterojunction through a hetero junction interface 228.

A metal cathode electrode 222 is formed on the lower surface of the semiconductor substrate 204. The cathode electrode 222 is joined to the n ⁺ cathode region 206 through an ohmic junction. A metal anode electrode 224 and a metal gate electrode 226 are formed on the upper surface of the semiconductor substrate 204. The anode electrode 224 is joined to the p anode region 214, the p ⁺ contact region 218, the hetero semiconductor region 227, and a part of the n ⁺ emitter region 220 through an ohmic junction. The gate electrode 226 is disposed so as to face a part of the n ⁻ drift region 210, the n barrier region 212, the p anode region 214, and the n ⁺ emitter region 220 with the insulating film 230 interposed therebetween. The gate electrode 226 is electrically connected to a gate electrode terminal (not shown).

The semiconductor device 202 of this embodiment includes a cathode electrode 222 corresponding to a drain electrode, an n ⁺ cathode region 206 corresponding to a drain region, an n buffer region 208, an n ⁻ drift region 210, and a p corresponding to a body region. An insulating film with respect to the anode region 214, the n ⁺ emitter region 220 corresponding to the source region, the anode electrode 224 corresponding to the source electrode, and the p anode region 214 between the n ⁺ emitter region 220 and the n ⁻ drift region 210. 230 has a vertical MOSFET structure including gate electrodes 226 opposed to each other with 230 therebetween.

In the semiconductor device 202 of this embodiment, an n barrier region 212 is formed between the n ⁻ drift region 210 and the p anode region 214, and an n pillar region 216 that is heterojunction with the anode electrode 224 via the heterojunction interface 228. , The n barrier region 212 is electrically connected to the anode electrode 224. With such a configuration, the reverse recovery characteristic of the parasitic diode between the anode electrode 224 and the cathode electrode 222 can be improved and the switching loss can be reduced. Further, the withstand voltage against the reverse bias between the anode electrode 224 and the cathode electrode 222 can be improved.

(Example 13)
As shown in FIG. 20, the semiconductor device 232 of the present embodiment has a configuration substantially similar to that of the semiconductor device 202 of the twelfth embodiment. The semiconductor device 232 of this embodiment also has a vertical MOSFET structure, similar to the semiconductor device 202 of the twelfth embodiment. In the semiconductor device 232 of the present embodiment, a p electric field progress preventing region 234 that is a p-type semiconductor region is formed between the n ⁻ drift region 210 and the n barrier region 212. The impurity concentration of the p electric field progress preventing region 234 is about 1 × 10 ¹⁵ to 1 × 10 ¹⁹ [cm ⁻³ ]. The p electric field progress preventing region 234 has a thickness of about 0.5 to 3.0 [μm].

  According to the semiconductor device 232 of the present embodiment, as with the semiconductor device 202 of the twelfth embodiment, the reverse recovery characteristics of the parasitic diode between the anode electrode 224 and the cathode electrode 222 are improved and the switching loss is reduced. Can do.

Further, in the semiconductor device 232 of the present embodiment, since the p electric field progress preventing region 234 is formed between the n ⁻ drift region 210 and the n barrier region 212, the anode electrode is compared with the semiconductor device 202 of the twelfth embodiment. The withstand voltage against reverse bias between 224 and the cathode electrode 222 can be improved, and leakage current at the time of reverse bias can be reduced.

(Example 14)
As shown in FIG. 21, the semiconductor device 242 of the present embodiment has a configuration substantially similar to that of the semiconductor device 202 of the twelfth embodiment. In the semiconductor device 232 of this embodiment, a p ⁺ collector region 244 that is a high-concentration p-type semiconductor region is partially formed in the n ⁺ cathode region 206. In this embodiment, the impurity concentration of the p ⁺ collector region 244 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ].

The semiconductor device 242 has a structure in which a planar IGBT and a freewheeling diode are connected in antiparallel. That is, it corresponds to the cathode electrode 222 corresponding to the collector electrode, the p ⁺ collector region 244, the n buffer region 208, the n ⁻ drift region 210, the p anode region 214, the n ⁺ emitter region 220, and the emitter electrode. The anode electrode 224, the insulating film 230, and the gate electrode 226 constitute a planar IGBT, and includes a cathode electrode 222, an n ⁺ cathode region 206, an n buffer region 208, an n ⁻ drift region 210, The p anode region 214, the p ⁺ contact region 218, and the anode electrode 224 constitute a free wheeling diode. In the semiconductor device 242 of this embodiment, for each of the IGBT and the diode as described above, the n barrier region 212 formed between the n ⁻ drift region 210 and the p anode region 214 and the n barrier region 212 are electrically connected. The n pillar region 216 is connected, and the n pillar region 216 and the anode electrode 224 are electrically connected to each other, and a hetero semiconductor region 227 heterojunction with the n pillar region 216 is added. ing.

In the semiconductor device 242 of this embodiment, when a forward bias is applied between the anode electrode 224 and the cathode electrode 222, holes are injected from the p anode region 214 and the p ⁺ contact region 218 into the n ⁻ drift region 210. Is suppressed. Therefore, reverse recovery characteristics can be improved and switching loss can be reduced.

  In the semiconductor device 242 of this embodiment, when a reverse bias is applied between the anode electrode 224 and the cathode electrode 222, not only the depletion layer extending from the heterojunction interface 228 but also the p anode region 214 and the n barrier region 212. The electric field is also shared by the depletion layer extending from the pn junction interface between the two. Therefore, the breakdown voltage against the reverse bias can be improved.

(Example 15)
As shown in FIG. 23, the semiconductor device 252 of this example has a configuration substantially similar to that of the semiconductor device 242 of Example 14. In the semiconductor device 252 of this example, a p electric field progress preventing region 234 that is a p-type semiconductor region is formed between the n ⁻ drift region 210 and the n barrier region 212. The impurity concentration of the p electric field progress preventing region 234 is about 1 × 10 ¹⁵ to 1 × 10 ¹⁹ [cm ⁻³ ]. The p electric field progress preventing region 234 has a thickness of about 0.5 to 3.0 [μm]. The semiconductor device 252 has a structure in which a planar IGBT and a freewheeling diode are connected in antiparallel.

According to the semiconductor device 252 of this example, when a forward bias is applied between the anode electrode 224 and the cathode electrode 222, holes from the p anode region 214 and the p ⁺ contact region 218 to the n ⁻ drift region 210. Injection is suppressed. Therefore, reverse recovery characteristics can be improved and switching loss can be reduced.

Further, in the semiconductor device 252 of this embodiment, when a reverse bias is applied between the anode electrode 224 and the cathode electrode 222, not only the depletion layer extending from the heterojunction interface 228 but also the p anode region 214 and the n barrier region 212. The electric field is also shared by the depletion layer extending from the interface of the pn junction between and the depletion layer extending from the pn junction between the p electric field progress preventing region 234 and the n ⁻ drift region 210. Therefore, the breakdown voltage against the reverse bias can be improved.

In the semiconductor device 252 of the present embodiment, the reverse current is limited by the pn junction between the p electric field progress preventing region 234 and the n ⁻ drift region 210. Therefore, the leakage current passing through the heterojunction interface 228 is reduced.

  Further, in the semiconductor device 252 of this embodiment, when a voltage is applied to the gate electrode 226 to drive the IGBT, the current flowing from the cathode electrode 222 corresponding to the collector electrode to the anode electrode 224 corresponding to the emitter electrode is a p electric field. Since it is suppressed by the progress prevention region 234, the saturation current of the IGBT can be reduced.

(Example 16)
As shown in FIG. 23, the diode 302 of the present embodiment has a configuration substantially similar to that of the diode 2 of the first embodiment. The diode 302 of this embodiment includes a hetero semiconductor region 16a made of a semiconductor having a band gap smaller than that of silicon, instead of the n pillar region 16 and the hetero semiconductor region 23. In the hetero semiconductor region 16a, for example, a trench reaching the n barrier region 12 through the p anode region 14 is formed on the upper surface of the semiconductor substrate 4, and, for example, n-type germanium doped with phosphorus as an impurity is formed in the trench. It is formed by filling by epitaxial growth. The hetero semiconductor region 16a is in ohmic contact with the anode electrode 22, and is heterojunction with the n barrier region 12 via the hetero junction interface 24a.

In the diode 302 of this embodiment, when a forward bias is applied between the anode electrode 22 and the cathode electrode 20, a short circuit occurs via the heterojunction interface 24 a between the hetero semiconductor region 16 a and the n barrier region 12. At this time, the potential difference between the n barrier region 12 and the anode electrode 22 is substantially equal to the voltage drop at the heterojunction interface 24a. Since the voltage drop at the heterojunction interface 24 a is sufficiently smaller than the built-in voltage of the pn junction between the p anode region 14 and the n barrier region 12, the n ⁻ drift region 10 extends from the p ⁺ contact region 18 and the p anode region 14. The injection of holes into the is suppressed.

Next, when the voltage between the anode electrode 22 and the cathode electrode 20 is switched from the forward bias to the reverse bias, the reverse current is limited by the heterojunction interface 24 a between the hetero semiconductor region 16 a and the n barrier region 12. In the diode 302 of this embodiment, the injection of holes from the p ⁺ contact region 18 and the p anode region 14 to the n ⁻ drift region 10 is suppressed when a forward bias is applied, so that the reverse recovery current is small and the reverse Recovery time is short. According to the diode 302 of this embodiment, the switching loss can be reduced without performing lifetime control of the n ⁻ drift region 10.

  Further, in the diode 302 of this embodiment, when a reverse bias is applied between the anode electrode 22 and the cathode electrode 20, only the depletion layer extending from the heterojunction interface 24a between the hetero semiconductor region 16a and the n barrier region 12 is obtained. In addition, the electric field is also shared by the depletion layer extending from the interface of the pn junction between the p anode region 14 and the n barrier region 12. Thereby, the electric field applied to the heterojunction interface 24a between the hetero semiconductor region 16a and the n barrier region 12 is reduced. According to the diode 302 of this embodiment, the breakdown voltage against reverse bias can be improved.

(Example 17)
As shown in FIG. 24, the diode 304 of the present embodiment has a configuration substantially similar to that of the diode 32 of the second embodiment. The diode 304 of this embodiment includes a hetero semiconductor region 16a made of a semiconductor having a band gap smaller than that of silicon, instead of the n pillar region 16 and the hetero semiconductor region 23. In the hetero semiconductor region 16a, for example, a trench that penetrates the p anode region 14 to reach the n barrier region 12 is formed on the upper surface of the semiconductor substrate 34, and n-type germanium doped with, for example, phosphorus as an impurity is formed in the trench. It is formed by filling by epitaxial growth. The hetero semiconductor region 16a is in ohmic contact with the anode electrode 22, and is heterojunction with the n barrier region 12 via the hetero junction interface 24a.

The operation of the diode 304 will be described. When a forward bias is applied between the anode electrode 22 and the cathode electrode 20, a short circuit occurs via the heterojunction interface 24 a between the hetero semiconductor region 16 a and the n barrier region 12. At this time, the potential difference between the n barrier region 12 and the anode electrode 22 is substantially equal to the voltage drop at the heterojunction interface 24a. Since the voltage drop at the heterojunction interface 24 a is sufficiently smaller than the built-in voltage of the pn junction between the p anode region 14 and the n barrier region 12, the n ⁻ drift region 10 extends from the p ⁺ contact region 18 and the p anode region 14. The injection of holes into the is suppressed. Although a pn junction exists between the n barrier region 12 and the p electric field progress preventing region 36, the p type impurity concentration of the p electric field progress preventing region 36 is low and the thickness of the p electric field progress preventing region 36 is thin. The influence on the forward current between the anode electrode 22 and the cathode electrode 20 is small.

Next, when the voltage between the anode electrode 22 and the cathode electrode 20 is switched from the forward bias to the reverse bias, the reverse current is limited by the heterojunction interface 24 a between the hetero semiconductor region 16 a and the n barrier region 12. The reverse current is also limited by the pn junction between the n ⁻ drift region 10 and the p electric field progress preventing region 36. As described above, in the diode 304 of this embodiment, the injection of holes from the p ⁺ contact region 18 and the p anode region 14 to the n ⁻ drift region 10 is suppressed when a forward bias is applied. Low current and short reverse recovery time. According to the diode 304 of the present embodiment, the switching loss can be reduced without performing lifetime control of the n ⁻ drift region 10.

Further, in the diode 304 of this embodiment, when a reverse bias is applied between the anode electrode 22 and the cathode electrode 20, only the depletion layer extending from the heterojunction interface 24a between the hetero semiconductor region 16a and the n barrier region 12 is obtained. In addition, the electric field is also shared by the depletion layer extending from the pn junction interface between the p anode region 14 and the n barrier region 12 and the pn junction interface between the n ⁻ drift region 10 and the p electric field progress preventing region 36. Thereby, the electric field applied to the heterojunction interface 24a between the hetero semiconductor region 16a and the n barrier region 12 and the electric field applied to the pn junction between the p anode region 14 and the n barrier region 12 are reduced. According to the diode 304 of this embodiment, the breakdown voltage against reverse bias can be improved.

(Other examples)
The diode 42 shown in FIG. 7, the diode 52 shown in FIG. 8, the diode 62 shown in FIG. 9, the diode 66 shown in FIG. 10, the diode 68 shown in FIG. 11, and the diode 70 shown in FIG. By replacing the hetero semiconductor region 23 with the above-described hetero semiconductor region 16a, the diode 306 shown in FIG. 25, the diode 308 shown in FIG. 26, the diode 310 shown in FIG. 27, the diode 312 shown in FIG. 28, and the diode 314 shown in FIG. 30 can also be configured as a diode 316 shown in FIG.

  Further, in each of the semiconductor device 72 shown in FIG. 13 and the semiconductor device 82 shown in FIG. 14, the n-pillar region 16 and the hetero semiconductor region 23 are replaced with the above-described hetero semiconductor region 16a, whereby the semiconductor device 318 shown in FIG. A semiconductor device 320 illustrated in FIG. 32 may be configured.

  15, the semiconductor device 162 illustrated in FIG. 16, the semiconductor device 172 illustrated in FIG. 17, and the semiconductor device 182 illustrated in FIG. 18, the n pillar regions 134 and 142 and the hetero semiconductor regions 149 and 151, respectively. Is replaced with hetero semiconductor regions 134a and 142a made of a semiconductor having a smaller band gap than silicon, thereby the semiconductor device 322 shown in FIG. 33, the semiconductor device 324 shown in FIG. 34, the semiconductor device 326 shown in FIG. A semiconductor device 328 can also be configured. Here, the hetero semiconductor region 134a is in ohmic contact with the emitter / anode electrode 148, penetrates the p body region 118, and is heterojunction with the n barrier region 116 via the hetero junction interface 150a. The hetero semiconductor region 142a is in ohmic contact with the emitter / anode electrode 148, passes through the p anode region 124, and is heterojunction with the n barrier region 122 via the hetero junction interface 152a.

  In each of the semiconductor device 202 shown in FIG. 19, the semiconductor device 232 shown in FIG. 20, the semiconductor device 242 shown in FIG. 21, and the semiconductor device 252 shown in FIG. 22, the n pillar region 216 and the hetero semiconductor region 227 are made of silicon. By replacing the hetero semiconductor region 216a made of a semiconductor having a small band gap, the semiconductor device 330 shown in FIG. 37, the semiconductor device 332 shown in FIG. 38, the semiconductor device 334 shown in FIG. 39, and the semiconductor device 336 shown in FIG. It can also be configured. Here, the hetero semiconductor region 216a is in ohmic contact with the anode electrode 224, passes through the p anode region 214, and is heterojunction with the n barrier region 212 via the hetero junction interface 228a.

  As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

  For example, the case where the semiconductor substrate including the cathode region, the drift region, the anode region, the electric field progress preventing region, the barrier region, and the like is made of silicon and the hetero semiconductor region is made of germanium has been described above. This can also be applied to the combination. For example, the semiconductor substrate may be made of silicon and the hetero semiconductor region may be made of silicon germanium. Alternatively, the semiconductor substrate may be made of silicon carbide and the hetero semiconductor region may be made of silicon. Alternatively, the semiconductor substrate may be made of gallium nitride and the hetero semiconductor region may be made of silicon. Alternatively, the semiconductor substrate may be made of gallium arsenide and the hetero semiconductor region may be made of silicon.

  The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2 diode; 4 semiconductor substrate; 6 ^{n +} cathode region; 8 n buffer region; 10 n ^- drift region; 12 n barrier regions; 14 p anode regions; 16 n pillar region; 16a hetero semiconductor region; 18 ^{p +} contact region; 20 cathode electrode; 22 anode electrode; 23 hetero semiconductor region; 24 hetero junction interface; 24a hetero junction interface; 26 diode; 28 semiconductor substrate; 30 Schottky interface; 32 diode; 34 semiconductor substrate; 44 trench; 46 insulating film; 48 trench electrode; 52 diode; 62 diode; 64 p ⁺ cathode short region; 66 diode; 68 diode; 70 diode; 72 semiconductor device; 74 n ⁺ emitter region; 82 semiconductor device; Semiconductor equipment 104 semiconductor region; 106 IGBT region; 108 diode region; 110 p ⁺ collector region; 112 n buffer region; 114 n ⁻ drift region; 116 n barrier region; 118 p body region; 120 n ⁺ cathode region; 124 p anode region; 126 trench; 128 insulating film; 130 gate electrode; 132 n ⁺ emitter region; 134 n pillar region; 134a hetero semiconductor region; 136 p ⁺ contact region; 138 insulating film; 140 gate electrode; pillar regions; 142a hetero semiconductor region; 144 ^{p +} contact region; 146 collector / cathode; 148 emitter / anode electrode; 149 hetero semiconductor region; 150 heterojunction interface; 150a heterojunction interface; 151 hetero semiconductor region; 52 heterojunction interface; 152a heterojunction interface; 162 semiconductor devices; 164 semiconductor substrate; 166 p electric field progress preventing region; 168 electric field progress preventing region; 172 semiconductor devices; 174 ^{p +} cathode short regions; 182 semiconductor devices; 202 a semiconductor device; 204 a semiconductor substrate; 206 ^{n +} cathode region; 208 n buffer region; 210 n ^- drift region; 212 n barrier region; 214 p anode region; 216 n pillar region; 216a hetero semiconductor region; 218 ^{p +} contact region; 220 ^{n +} 222 cathode electrode; 224 anode electrode; 226 gate electrode; 227 hetero semiconductor region; 228 hetero junction interface; 228a hetero junction interface; 230 insulating film; 232 semiconductor device; 234 p electric field progress prevention region; ; 244 ^{p +} collector region; 252 semiconductor devices; 302 diodes; 304 diodes; 306 diodes; 308 diodes; 310 diodes; 312 diodes; 314 diodes; 316 diodes; 318 semiconductor devices; 320 semiconductor devices; 322 semiconductor devices; 324 semiconductor device 326 Semiconductor device; 328 Semiconductor device; 330 Semiconductor device; 332 Semiconductor device; 334 Semiconductor device; 336 Semiconductor device

Claims (8)

A diode comprising a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, an anode region made of a second conductivity type semiconductor, and an anode electrode. And
A barrier region made of a first conductivity type semiconductor having a higher concentration than the drift region, formed between the drift region and the anode region;
A hetero semiconductor region made of a semiconductor having a smaller band gap than the barrier region, which is formed so as to electrically connect the barrier region and the anode electrode;
The diode characterized in that the hetero semiconductor region and the barrier region are heterojunction.   2. The diode according to claim 1, further comprising an electric field progress preventing region made of a second conductivity type semiconductor formed between the barrier region and the drift region. A trench reaching the drift region from the anode region is formed,
3. The diode according to claim 1, wherein a trench electrode covered with an insulating film is formed inside the trench.   The diode according to any one of claims 1 to 3, further comprising a cathode short region made of a second conductivity type semiconductor partially formed in the cathode region. A semiconductor device in which the diode according to any one of claims 1 to 4 and the IGBT are integrated,
The IGBT includes a collector electrode, a collector region made of a second conductivity type semiconductor, a second drift region made of a low-concentration first conductivity type semiconductor, continuous from the drift region, and a second conductivity type. A body region made of a semiconductor, an emitter region made of a first conductivity type semiconductor, an emitter electrode, and a gate opposed to the body region between the emitter region and the second drift region with an insulating film interposed therebetween With electrodes,
The IGBT is formed between the second drift region and the body region, the second barrier region made of a first conductivity type semiconductor having a higher concentration than the second drift region, the second barrier region, A second hetero semiconductor region made of a semiconductor having a smaller band gap than the second barrier region, which is formed so as to electrically connect the emitter electrode;
The semiconductor device, wherein the second hetero semiconductor region and the second barrier region are heterojunction.   6. The semiconductor device according to claim 5, further comprising a second electric field progress prevention region made of a second conductivity type semiconductor and formed between the second barrier region and the second drift region. From a drain electrode, a drain region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, a body region made of a second conductivity type semiconductor, and a first conductivity type semiconductor A MOSFET comprising a source region, a source electrode, and a gate electrode facing the body region between the source region and the drift region with an insulating film interposed therebetween,
A barrier region made of a first conductivity type semiconductor having a higher concentration than the drift region, formed between the drift region and the body region;
A hetero semiconductor region made of a semiconductor having a smaller band gap than the barrier region, which is formed so as to electrically connect the barrier region and the source electrode;
A MOSFET, wherein the hetero semiconductor region and the barrier region are heterojunction.   8. The MOSFET according to claim 7, further comprising an electric field progress preventing region made of a second conductivity type semiconductor formed between the barrier region and the drift region.

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