CN114937690B - Planar silicon carbide insulated gate bipolar transistor and manufacturing method thereof - Google Patents
Planar silicon carbide insulated gate bipolar transistor and manufacturing method thereof Download PDFInfo
- Publication number
- CN114937690B CN114937690B CN202210631158.3A CN202210631158A CN114937690B CN 114937690 B CN114937690 B CN 114937690B CN 202210631158 A CN202210631158 A CN 202210631158A CN 114937690 B CN114937690 B CN 114937690B
- Authority
- CN
- China
- Prior art keywords
- region
- emitter
- layer
- igbt
- sic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 78
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 37
- 230000008569 process Effects 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims description 48
- 239000002184 metal Substances 0.000 claims description 48
- 238000001259 photo etching Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000003892 spreading Methods 0.000 claims description 5
- 230000007480 spreading Effects 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 239000004411 aluminium Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 12
- 238000002347 injection Methods 0.000 abstract description 5
- 239000007924 injection Substances 0.000 abstract description 5
- 238000005457 optimization Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 5
- 239000002210 silicon-based material Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
Abstract
The invention belongs to the technical field of power semiconductor devices, and relates to a planar silicon carbide insulated gate bipolar transistor and a manufacturing method thereof. The invention optimizes the structure of the back and the surface of the device based on the traditional IGBT. The back surface is provided with two field stop layers, and an N-drift region is reserved between the two layers, so that the failure caused by overlarge dv/dt in the short circuit turn-off process is effectively improved, and the short circuit reliability of the device is improved. The structure optimization is divided into two parts on the surface, namely deep P+ injection is adopted, and the introduction of a P+ region can reduce the resistance of a hole current path, so that the latch-up of a parasitic thyristor in an IGBT structure can be effectively inhibited; and secondly, an alternate surface doping cell structure is adopted, and an N+ emitter region and a P+ base region are alternately distributed on the surface of the emitter region in the y-axis direction, so that the power density of the silicon carbide IGBT during short circuit is effectively reduced, the short circuit characteristic of the silicon carbide IGBT is improved, in addition, the short circuit degree of the emitter region and the base region is enhanced, and the parasitic resistance of the base region is reduced.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) and a manufacturing method thereof.
Background
Today, the proportion of clean renewable energy sources is larger and larger, the whole society has higher expectations on energy conversion efficiency, and higher requirements are put on the performance of power semiconductor devices of an energy control core. Conventional power semiconductor devices are mainly silicon-based devices, and the device types include thyristors, schottky barrier diodes (JBS), power Bipolar Junction Transistors (BJTs), power insulated gate field effect transistors (MOSFETs), and power IGBTs. Currently, silicon-based power semiconductor devices have taken up the dominant market for power semiconductor devices. However, the performance of the conventional silicon-based power device is approaching to the theoretical limit of silicon materials, and it is difficult to greatly improve the performance of the device through structural design and optimization.
Based on the development of SiC power semiconductor devices and SiC semiconductor technology, the more efficient electric energy application requirements are further met. SiC has very excellent physical, chemical and electrical properties as a typical representative of third generation semiconductor materials, with a larger forbidden band width, higher electron saturation velocity, higher thermal conductivity and 10 times the critical breakdown field of silicon materials than silicon materials. These excellent material characteristics make SiC power semiconductor devices have great advantages in terms of reducing power consumption of the power system, improving efficiency, and the like. In addition, the SiC material is one of the most mature wide bandgap semiconductor materials in the current crystal growth technology and device manufacturing technology, is beneficial to realizing the industrial production of the SiC power device and improves the market share of the SiC power device.
As one of the core basic devices, the IGBT device is applied in a large scale in a power grid device, however, due to the limitation of silicon-based materials, the maximum withstand voltage of the commercialized silicon-based IGBT is only 6500V, and a single device is difficult to meet the requirement of high voltage application of the power grid, so that a large number of series connection must be performed in the power grid, which increases the complexity of the power electronic device and the difficulty of system control and reduces the reliability of the system. To achieve a transition from a traditional power system to a flexibly controllable power-electronized power system, silicon-based devices are difficult to perform. If a ten thousand volt kiloampere grade SiC device is adopted, the volume weight of the converter can be reduced by more than half. The SiC IGBT combines the advantages of the SiC material and the IGBT device, has the structure shown in figure 1, has the advantages of high critical breakdown electric field, high breakdown voltage, high temperature resistance, high working frequency and the like of the SiC material, has the advantages of high on-current density, low on-voltage, small switching loss, simple driving and the like of the IGBT device, and is an ideal power switch device applied to high-voltage (> 10 kV) and high-power fields such as a solid-state transformer, a high-voltage pulse power supply, a high-voltage inverter, a flexible alternating current/direct current power transmission system, a high-voltage direct current power transmission system, a static var compensator and the like.
In practical application of the high-voltage SiC IGBT in the power system, when an external load fails, a gate driving signal is abnormal, or a certain IGBT or diode suddenly fails, the IGBT may be shorted. Because the IGBT needs to bear high voltage and high current at the same time in a short circuit state and needs to be maintained for a certain time, if the device is short-circuited and cannot be effectively controlled in time, the radiator, the electrode bus, the IGBT adjacent to the electrode bus, the gate drive and the like will be further damaged, the system failure rate will be increased, and potential reliability problems will be brought to engineering operation. In addition, the dv/dt of the SiC IGBT is very large in the turn-off process, and the device failure is easy to cause. Therefore, it is important to propose a device structure capable of effectively improving the short-circuit and turn-off characteristics of SiC IGBTs.
Disclosure of Invention
The invention aims to solve the technical problems existing in the prior art and provides a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) and a manufacturing method thereof. The invention optimizes the structure of the back and the surface of the device based on the traditional SiC IGBT structure, and improves the reliability of the short circuit of the SiC IGBT and the reliability in the turn-off process under the condition of not affecting other performances of the device.
In order to solve the above technical problems, an embodiment of the present invention provides a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT), in which three dimensions of a device are defined by a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device as the Z-axis direction, wherein the half cell structure comprises: a back collector metal 14, a P+ substrate 1, a first N-type field stop layer 2, a first N-drift region 3, a second N-type field stop layer 4, a second N-drift region 5, an oxide layer 10, a gate electrode 11, a dielectric layer 12 and an emitter metal 13 which are sequentially stacked from bottom to top along the Z-axis direction; along the X-axis direction, a P-type base region 6, a P-channel region 7 and a p+ region 8 are arranged on one side of the top layer of the second N-drift region 5, one side of the P-type base region 6 and one side of the P-channel region 7 are in contact with one side of the p+ region 8, the p+ region 8 is arranged close to the side of the second N-drift region 5, and the P-channel region 7 is arranged on the P-type base region 6; along the Y-axis direction, n+ emitters 9 are arranged in the top layer of the p+ region 8, and the n+ emitters 9 enable the junction depth of the p+ region 8 and the n+ emitters 9,N + emitters 9 to be smaller than the junction depth of the p+ region 8 in an alternating manner;
along the Z-axis direction, the first portion of the p+ region 8, the P-channel region 7 and the second N-drift region 5 have an oxide layer 10 thereon, the oxide layer 10 has a gate electrode 11 thereon, the second portion of the p+ region 8 and the gate electrode 11 have an emitter metal 13 thereon, a dielectric layer 12 is provided between the gate electrode 11 and the emitter metal 13, the emitter metal 13 forms ohmic contact with the n+ emitter 9, and the emitter metal 13 also forms ohmic contact with the p+ region 8.
On the basis of the technical scheme, the invention can be improved as follows.
Further, the junction depth of the p+ region 8 is greater than or equal to the junction depth of the P-type base region 6.
Further, in the Y-axis direction, the top layer of the p+ region 8 also has an N-emitter 15 therein; along the X-axis direction, the n+ emitter 9 and the N-emitter 15 are in lateral contact with each other, and the N-emitter 15 is disposed close to the P-channel region 7, and the n+ emitter 9 and the N-emitter 15 divide the top layer of the p+ region 8 into two discontinuously distributed portions.
Further, the N-emitter 15 has a curved path.
Further, the top layer of the second N-drift region 5 further has an N-type current expansion layer 16, and the junction depth of the N-type current expansion layer 16 is greater than the junction depth of the P-type base region 6.
Further, the gate electrode is a metal gate electrode or a polysilicon gate electrode.
Further, the semiconductor material used in the device may be any one or more of SiC, silicon, germanium, gallium nitride and diamond.
Further, the emitter metal 13 and the back collector metal 14 are formed of one or a combination of a plurality of layers of titanium, nickel, tungsten, silver, copper, gold, aluminum, and titanium nitride.
In order to solve the above technical problems, an embodiment of the present invention provides a method for manufacturing a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT), including the steps of:
step 1: selecting a P-type heavily doped monocrystalline SiC piece as a P-type substrate layer 1 of the device;
step 2: an epitaxial process is adopted, and a first N-type field stop layer 2, a first N-drift region 3, a second N-type field stop layer 4 and a second N-drift region 5 are sequentially formed on a P-type heavily doped monocrystalline SiC wafer;
step 3: forming a P-type base region 6 and a P-channel region 7 by adopting a photoetching process and carrying out ion implantation on P-type impurities for a plurality of times;
step 4: forming a P+ region 8 by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 5: forming an N+ emitter 9 by adopting a photoetching process and implanting N-type impurities for a plurality of times;
step 6: forming a gate oxide layer 10 by an oxidation process, and depositing a layer of polycrystal as a gate electrode 11 on the gate oxide layer 10;
step 7: etching part of the polycrystal and the gate oxide layer through an etching process to form a gate structure, and depositing a dielectric layer 12 to cover the polycrystal;
step 8: forming an emitter metal hole on the front side of the device through a photoetching process, and sputtering a layer of metal to serve as an emitter metal 13;
step 9: the device is flipped over and a layer of metal is sputtered on the back as collector metal 14.
Further, the method further comprises the steps of: and forming an N-type current expansion layer 16 on the top layer of the second N-drift region 5 by adopting a photoetching process and implanting N-type impurities for a plurality of times, wherein the junction depth of the N-type current expansion layer 16 is larger than that of the P-type base region 6.
The working principle of the invention is as follows: the equivalent circuit of the IGBT structure consists of two parts, one part being a pair of coupled PNP and NPN transistors forming a parasitic thyristor and the other part being a MOSFET providing a base drive current to the PNP transistor. Although in the IGBT structure the n+ emitter and the P-type base region are shorted by the emitter metal, the bipolar current still needs to pass through a certain resistance to reach the emitter electrode. When the device works normally, if the resistance is large, the potential difference between the emitter and the base of the parasitic NPN transistor may exceed the potential barrier between the emitter and the base, so that the parasitic NPN transistor is turned on, and the IGBT is latched. The invention adopts deep P+ injection to form the P+ region 8, and adopts a structure that N+ emitter 9 and P+ region 8 are alternately distributed in the y-axis direction, the former can reduce the resistance of a hole current path, the latter enhances the short-circuit degree of the emitter and the base region, reduces the base region resistance, and the reduction of parasitic resistance can effectively inhibit the latch-up of the IGBT.
When the IGBT is in an on state, the gate voltage is larger than the threshold voltage of the IGBT, the device is in a channel inversion state, when the collector is connected with high potential and the emitter is connected with low potential, electron current of the N+ emitter 9 flows to the JFET region through the channel and spreads in the second N-drift region 5. According to the invention, as the structure that the N+ emitter 9 and the P+ region 8 are alternately distributed in the y-axis direction is adopted, the current channel is reduced, which is equivalent to reducing the channel density of the device, and the saturation current of the device is reduced, thereby being beneficial to reducing the power density during the short circuit of the device and improving the short circuit characteristic of the device.
Due to the material characteristics, the drift region 5 of the SiC IGBT is completely depleted under the working voltage, so that in practical application, when the device is turned off, dv/dt at two ends of the device is very large, and the device failure is easily caused. The back surface of the invention adopts a double-FS layer structure, the electric field is cut off at the second N-type field stop layer (FS 1) layer 4, the first N-drift region 3 is not exhausted, and the problem of overlarge dv/dt can be effectively improved when the device is cut off, thereby improving the reliability of the device in the process of cutting off.
The invention has the beneficial effects that the short circuit reliability of the device and the reliability in the turn-off process are effectively improved by carrying out structural optimization on the back and the surface of the device while hardly influencing the performance of the SiC MOSFET, and specifically comprises the following steps:
(1) The planar silicon carbide insulated gate bipolar transistor provided by the invention has the double FS layers (the first N-type field stop layer (FS 2 layer) 2 and the second N-type field stop layer (FS 1 layer) 4) on the back surface, so that the failure caused by overlarge dv/dt in the turn-off process of the device can be effectively improved.
(2) The planar silicon carbide insulated gate bipolar transistor adopts deep P+ injection on the surface, so that the resistance of a hole current path can be reduced, and the latch-up of a parasitic thyristor in an IGBT structure can be effectively inhibited.
(3) In the y-axis direction, the planar silicon carbide insulated gate bipolar transistor of the invention has N+ emitting regions 9 and P+ regions 8 alternately distributed on the surface of the emitter. Because electron current cannot flow from the P+ region 8 to the emitter, the structure is equivalent to reducing the channel density of the device, so that the saturation current of the SiC IGBT is reduced, the power density of the SiC IGBT during short circuit can be effectively reduced, and the short circuit characteristic of the SiC IGBT is improved. In addition, the alternate surface doping cell structure also enhances the short circuit degree of the emitter region and the base region, reduces the parasitic resistance of the base region, and ensures that the latch-up resistance of the cell structure is superior to that of bar-shaped, round and square cell structures.
(4) The structure of the invention is highly compatible with the traditional SiC IGBT manufacturing process.
Drawings
Fig. 1 is a schematic diagram of a half cell structure of a conventional planar gate SiC IGBT;
fig. 2 is a schematic diagram of a half cell structure of a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a first embodiment of the invention;
fig. 3 is a schematic cross-sectional view of a half cell structure of a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) along the AA' direction according to a first embodiment of the invention;
fig. 4 is a schematic diagram of a half cell structure of a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a second embodiment of the invention;
fig. 5 is a schematic diagram of a half cell structure of a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a third embodiment of the invention;
fig. 6 is a schematic cross-sectional view of a half cell structure of a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) along the AA' direction according to a third embodiment of the invention;
fig. 7 is a schematic diagram of a half cell structure of a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a fourth embodiment of the invention;
fig. 8 is a schematic cross-sectional view of a half cell structure of a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a fourth embodiment of the invention along the AA' direction;
fig. 9 is a schematic diagram of a half cell structure of a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a fifth embodiment of the invention;
fig. 10 is a schematic cross-sectional view of a half cell structure of a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a fifth embodiment of the invention along the AA' direction;
fig. 11 is a schematic diagram of a half cell structure of a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a sixth embodiment of the invention;
fig. 12 is a schematic cross-sectional view of a half cell structure of a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a sixth embodiment of the invention along the AA' direction;
fig. 13-20 are schematic process flow diagrams of a method for fabricating a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a seventh embodiment of the invention.
In the drawings, the list of components represented by the various numbers is as follows:
1. p+ substrate, 2, first N-type field stop layer, 3, first N-drift region, 4, second N-type field stop layer, 5, second N-drift region, 6, P-type base region, 7, P-channel region, 8, p+ region, 9, n+ emitter, 10, oxide layer, 11, gate electrode, 12, dielectric layer, 13, emitter metal, 14, back collector metal, 15, N-emitter, 16, N-type current spreading layer.
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
As shown in fig. 2-3, a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a first embodiment of the present invention defines three dimensions of a device in a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device as the Z-axis direction, wherein the half cell structure comprises: a back collector metal 14, a P+ substrate 1, a first N-type field stop layer 2, a first N-drift region 3, a second N-type field stop layer 4, a second N-drift region 5, an oxide layer 10, a gate electrode 11, a dielectric layer 12 and an emitter metal 13 which are sequentially stacked from bottom to top along the Z-axis direction; along the X-axis direction, a P-type base region 6, a P-channel region 7 and a p+ region 8 are arranged on one side of the top layer of the second N-drift region 5, one side of the P-type base region 6 and one side of the P-channel region 7 are in contact with one side of the p+ region 8, the p+ region 8 is arranged close to the side of the second N-drift region 5, and the P-channel region 7 is arranged on the P-type base region 6; along the Y-axis direction, n+ emitters 9 are arranged in the top layer of the p+ region 8, and the n+ emitters 9 enable the junction depth of the p+ region 8 and the n+ emitters 9,N + emitters 9 to be smaller than the junction depth of the p+ region 8 in an alternating manner;
along the Z-axis direction, the first portion of the p+ region 8, the P-channel region 7 and the second N-drift region 5 have an oxide layer 10 thereon, the oxide layer 10 has a gate electrode 11 thereon, the second portion of the p+ region 8 and the gate electrode 11 have an emitter metal 13 thereon, a dielectric layer 12 is provided between the gate electrode 11 and the emitter metal 13, the emitter metal 13 forms ohmic contact with the n+ emitter 9, and the emitter metal 13 also forms ohmic contact with the p+ region 8.
In the above embodiment, siC is selected as the semiconductor material used for the device. In addition, the semiconductor material used in the device may be any one or more of SiC, si, ge, gaN, diamond and gallium oxide.
The invention discloses a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT), which is provided with two Field Stop (FS) layers, namely an FS1 layer 4 and an FS2 layer 2, on the back surface, wherein a first N-drift region 3 is reserved between the two layers. The structure can effectively solve the failure problem caused by overlarge dv/dt in the turn-off process and improve the reliability of the device in the turn-off process.
On the surface, the structural optimization is divided into two parts. Firstly, deep P+ injection is adopted, and the resistance of a hole current path can be reduced by introducing the P+ region 8, so that latch-up of a parasitic thyristor in an IGBT structure can be effectively inhibited. And secondly, an alternate surface doping cell structure is adopted, and N+ emitting areas 9 and P+ areas 8 are alternately distributed on the surface of the emitter in the y-axis direction, so that the channel density of the device is reduced, the saturation current of the device is reduced, and the short circuit characteristic of the SiC IGBT can be effectively improved. In addition, the alternate surface doping cell structure also enhances the short circuit degree of the emitter region and the base region, reduces the parasitic resistance of the base region, and can effectively improve the latch-up resistance of the cell structure.
Optionally, the junction depth of the p+ region 8 is greater than or equal to the junction depth of the P-type base region 6.
As shown in fig. 4, a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a second embodiment of the present invention is based on the first embodiment, and the top layer of the second N-drift region 5 further has an N-type current expansion layer 16, where the junction depth of the N-type current expansion layer 16 is greater than the junction depth of the P-type base region 6.
In the above embodiment, the introduction of the N-type current spreading (Current Spreading, CS) layer 16 is beneficial to improving the JFET effect when the device is turned on, and the higher doping concentration than the second N-drift region 5 is also beneficial to the current circulation, so that the on-voltage drop of the device can be effectively reduced.
As shown in fig. 5-6, a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a third embodiment of the present invention is provided, on the basis of the first embodiment, in a Y-axis direction, an N-emitter 15 is further provided in a top layer of the p+ region 8, in an X-axis direction, the n+ emitter 9 and the N-emitter 15 are laterally contacted with each other, and the N-emitter 15 is disposed near the P-channel region 7, and the n+ emitter 9 and the N-emitter 15 divide the top layer of the p+ region 8 into two discontinuously distributed portions.
In the above embodiment, the N-type emitter has different implantation concentrations in the x-axis direction, and is divided into the N-emitter 15 and the n+ emitter 9. The N-emitter 15 is covered by the oxide layer 10 and the dielectric layer 12 and is not in contact with the emitter metal 13. The N-emitter 15 introduces a resistor due to the low concentration, which can form negative feedback when short circuit occurs, and avoid the failure of the device caused by local hot spot. In addition, the N-emitter 15 and the P+ regions 8 on two sides are jointly introduced into the JFET region, so that the saturation current of the device can be further reduced, and the short circuit reliability is improved.
As shown in fig. 7-8, a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a fourth embodiment of the present invention is based on the third embodiment, and the top layer of the second N-drift region 5 further has an N-type current expansion layer 16, where the junction depth of the N-type current expansion layer 16 is greater than the junction depth of the P-type base region 6.
As shown in fig. 9 to 10, a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a fifth embodiment of the present invention is provided, in which the N-emitter 15 has a curved path on the basis of the third embodiment.
In the above embodiment, the paths of the N-emitter 15 and the n+ emitter 9 are different, the path of the N-emitter 15 is longer to introduce a larger resistance, and the N-emitter 15 is covered by the oxide layer 10 and the dielectric layer 12 and is not in contact with the emitter metal 13. The N-emitter 15 introduces a larger resistance to better form negative feedback when in short circuit, so as to avoid the failure of the device caused by local hot spots.
As shown in fig. 11-12, a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to a sixth embodiment of the present invention is based on the fifth embodiment, and the top layer of the second N-drift region 5 further has an N-type current expansion layer 16, where the junction depth of the N-type current expansion layer 16 is greater than the junction depth of the P-type base region 6.
Alternatively, the gate electrode is a metal gate electrode or a polysilicon gate electrode.
Alternatively, the emitter metal 13 and the back collector metal 14 may be one of titanium, nickel, tungsten, silver, copper, gold, aluminum, and titanium nitride or a multi-layer combination of the foregoing metals.
As shown in fig. 13-20, a seventh embodiment of the present invention provides a method for manufacturing a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT), including the steps of:
step 1: a P-type heavily doped monocrystalline SiC wafer with a certain thickness is selected as a P-type substrate layer 1 of the device;
step 2: adopting an epitaxial process to sequentially form a first N-type field stop layer 2, a first N-drift region 3, a second N-type field stop layer 4 and a second N-drift region 5 on a P-type heavily doped monocrystalline SiC wafer with a certain thickness;
step 3: forming a P-type base region 6 and a P-channel region 7 by adopting a photoetching process and carrying out ion implantation on P-type impurities for a plurality of times;
step 4: forming a P+ region 8 by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 5: forming an N+ emitter 9 by adopting a photoetching process and implanting N-type impurities for a plurality of times;
step 6: forming a gate oxide layer 10 by an oxidation process, and depositing a layer of polycrystal as a gate electrode 11 on the gate oxide layer 10;
step 7: etching part of the polycrystal and the gate oxide layer through an etching process to form a gate structure, and depositing a dielectric layer 12 to cover the polycrystal;
step 8: forming an emitter metal hole on the front side of the device through a photoetching process, and sputtering a layer of metal to serve as an emitter metal 13;
step 9: the device is flipped over and a layer of metal is sputtered on the back as collector metal 14.
The invention optimizes the structure of the back and the surface of the device based on the traditional IGBT. On the back side, there are two Field Stop (FS) layers, between which an N-drift region remains. The back structure can effectively improve the failure caused by the overlarge dv/dt in the short-circuit turn-off process, and improve the short-circuit reliability of the device. The structure optimization is divided into two parts on the surface, namely deep P+ injection is adopted, and the introduction of a P+ region can reduce the resistance of a hole current path, so that the latch-up of a parasitic thyristor in an IGBT structure can be effectively inhibited; and secondly, an alternate surface doping cell structure is adopted, and in the y-axis direction, an N+ emitter region and a P+ base region are alternately distributed on the surface of the emitter, and because electron current cannot flow from the P+ base region to the emitter, the structure is equivalent to reducing the channel density of a device, so that the saturation current of the silicon carbide IGBT is reduced, the power density of the silicon carbide IGBT in short circuit can be effectively reduced, and the short circuit characteristic of the silicon carbide IGBT is improved. In addition, the alternate surface doping cell structure also enhances the short circuit degree of the emitter region and the base region, reduces the parasitic resistance of the base region, and ensures that the latch-up resistance of the cell structure is superior to that of bar-shaped, round and square cell structures.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (10)
1. Planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) defines the three-dimensional direction of the device in a three-dimensional rectangular coordinate system: defining the transverse direction of the device as the X-axis direction, the vertical direction of the device as the Y-axis direction and the longitudinal direction of the device as the Z-axis direction, wherein the half cell structure comprises: a back collector metal (14), a P+ substrate (1), a first N-type field stop layer (2), a first N-drift region (3), a second N-type field stop layer (4), a second N-drift region (5), an oxide layer (10), a gate electrode (11), a dielectric layer (12) and an emitter metal (13) which are sequentially stacked from bottom to top along the Z-axis direction; along the X-axis direction, a P-type base region (6), a P-channel region (7) and a P+ region (8) are arranged on one side of the top layer of the second N-drift region (5), one side of the P-type base region (6) and one side of the P-channel region (7) are in contact with one side of the P+ region (8), the P+ region (8) is arranged close to one side of the second N-drift region (5), and the P-channel region (7) is arranged on the P-type base region (6); along the Y-axis direction, an N+ emitter (9) is arranged in the top layer of the P+ region (8), the N+ emitter (9) enables the P+ region (8) and the N+ emitter (9) to be alternately distributed on the top layer of the P+ region (8), and the junction depth of the N+ emitter (9) is smaller than that of the P+ region (8);
along the Z-axis direction, an oxide layer (10) is arranged on the first part of the P+ region (8), the P-channel region (7) and the second N-drift region (5), a gate electrode (11) is arranged on the oxide layer (10), an emitter metal (13) is arranged on the second part of the P+ region (8) and the gate electrode (11), a dielectric layer (12) is arranged between the gate electrode (11) and the emitter metal (13), ohmic contact is formed between the emitter metal (13) and the N+ emitter (9), and ohmic contact is also formed between the emitter metal (13) and the P+ region (8).
2. A planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to claim 1, characterized in that the junction depth of the p+ region (8) is greater than or equal to the junction depth of the P-type base region (6).
3. A planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to claim 1, characterized in that in the top layer of the p+ region (8) there is also an N-emitter (15) in the Y-axis direction, in that in the X-axis direction the n+ emitter (9) and the N-emitter (15) are in lateral contact with each other and the N-emitter (15) is arranged close to the P-channel region (7), the n+ emitter (9) and the N-emitter (15) dividing the top layer of the p+ region (8) into two discontinuously distributed portions.
4. A planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to claim 3, characterised in that the N-emitter (15) has a curved path.
5. A planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to any of claims 1 to 4, characterized in that the top layer of the second N-drift region (5) further has an N-type current spreading layer (16), the junction depth of the N-type current spreading layer (16) being larger than the junction depth of the P-type base region (6).
6. A planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to any of claims 1 to 4, wherein the gate electrode is a metal gate electrode or a polysilicon gate electrode.
7. A planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to any of claims 1 to 4, wherein the semiconductor material used in the device may be any one or more of SiC, silicon, germanium, gallium nitride and diamond.
8. A planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to any of claims 1 to 4, characterised in that the emitter metal (13) and the back collector metal (14) are made of one or a combination of layers of titanium, nickel, tungsten, silver, copper, gold, aluminium and titanium nitride.
9. A method of fabricating a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) according to any one of claims 1 to 8, comprising the steps of:
step 1: selecting a P-type heavily doped monocrystalline SiC piece as a P-type substrate layer (1) of the device;
step 2: an epitaxial process is adopted, and a first N-type field stop layer (2), a first N-drift region (3), a second N-type field stop layer (4) and a second N-drift region (5) are sequentially formed on a P-type heavily doped monocrystalline SiC wafer;
step 3: forming a P-type base region (6) and a P-channel region (7) by adopting a photoetching process and carrying out ion implantation on P-type impurities for a plurality of times;
step 4: forming a P+ region (8) by adopting a photoetching process and implanting P-type impurities for a plurality of times;
step 5: forming an N+ emitter (9) by adopting a photoetching process and implanting N-type impurities for a plurality of times;
step 6: forming a gate oxide layer (10) through an oxidation process, and depositing a layer of polycrystal on the gate oxide layer (10) as a gate electrode (11);
step 7: etching part of the polycrystal and the gate oxide layer through an etching process to form a gate structure, and depositing a dielectric layer (12) to cover the polycrystal;
step 8: forming an emitter metal hole on the front side of the device through a photoetching process, and sputtering a layer of metal as emitter metal (13);
step 9: the device is flipped over and a layer of metal is sputtered on the back as collector metal (14).
10. The method of fabricating a planar silicon carbide (SiC) Insulated Gate Bipolar Transistor (IGBT) of claim 1, further comprising the steps of: and forming an N-type current expansion layer (16) on the top layer of the second N-drift region (5) by adopting a photoetching process and implanting N-type impurities for a plurality of times, wherein the junction depth of the N-type current expansion layer (16) is larger than that of the P-type base region (6).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210631158.3A CN114937690B (en) | 2022-06-06 | 2022-06-06 | Planar silicon carbide insulated gate bipolar transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210631158.3A CN114937690B (en) | 2022-06-06 | 2022-06-06 | Planar silicon carbide insulated gate bipolar transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114937690A CN114937690A (en) | 2022-08-23 |
| CN114937690B true CN114937690B (en) | 2023-04-28 |
Family
ID=82866413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210631158.3A Active CN114937690B (en) | 2022-06-06 | 2022-06-06 | Planar silicon carbide insulated gate bipolar transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114937690B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101887913A (en) * | 2010-06-04 | 2010-11-17 | 无锡新洁能功率半导体有限公司 | IGBT with improved collector structure |
| JP2014157883A (en) * | 2013-02-14 | 2014-08-28 | Sanken Electric Co Ltd | Semiconductor device |
| JP2016034037A (en) * | 2011-05-16 | 2016-03-10 | ルネサスエレクトロニクス株式会社 | Ie-type trench gate igbt |
| CN105870181A (en) * | 2016-06-13 | 2016-08-17 | 电子科技大学 | Plane gate IGBT (insulated gate bipolar translator) and manufacturing method thereof |
| CN105932055A (en) * | 2016-06-13 | 2016-09-07 | 电子科技大学 | Plane gate IGBT and manufacturing method therefor |
| EP3195369A1 (en) * | 2014-09-17 | 2017-07-26 | Anvil Semiconductors Limited | High voltage semiconductor devices |
| CN109166917A (en) * | 2018-08-29 | 2019-01-08 | 电子科技大学 | A kind of plane insulated gate bipolar transistor and preparation method thereof |
| CN110896098A (en) * | 2019-11-15 | 2020-03-20 | 华中科技大学 | Reverse switch transistor based on silicon carbide base and preparation method thereof |
| CN111048580A (en) * | 2019-12-20 | 2020-04-21 | 中国科学院微电子研究所 | Silicon carbide insulated gate bipolar transistor and manufacturing method thereof |
-
2022
- 2022-06-06 CN CN202210631158.3A patent/CN114937690B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101887913A (en) * | 2010-06-04 | 2010-11-17 | 无锡新洁能功率半导体有限公司 | IGBT with improved collector structure |
| JP2016034037A (en) * | 2011-05-16 | 2016-03-10 | ルネサスエレクトロニクス株式会社 | Ie-type trench gate igbt |
| JP2014157883A (en) * | 2013-02-14 | 2014-08-28 | Sanken Electric Co Ltd | Semiconductor device |
| EP3195369A1 (en) * | 2014-09-17 | 2017-07-26 | Anvil Semiconductors Limited | High voltage semiconductor devices |
| CN105870181A (en) * | 2016-06-13 | 2016-08-17 | 电子科技大学 | Plane gate IGBT (insulated gate bipolar translator) and manufacturing method thereof |
| CN105932055A (en) * | 2016-06-13 | 2016-09-07 | 电子科技大学 | Plane gate IGBT and manufacturing method therefor |
| CN109166917A (en) * | 2018-08-29 | 2019-01-08 | 电子科技大学 | A kind of plane insulated gate bipolar transistor and preparation method thereof |
| CN110896098A (en) * | 2019-11-15 | 2020-03-20 | 华中科技大学 | Reverse switch transistor based on silicon carbide base and preparation method thereof |
| CN111048580A (en) * | 2019-12-20 | 2020-04-21 | 中国科学院微电子研究所 | Silicon carbide insulated gate bipolar transistor and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114937690A (en) | 2022-08-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110797403B (en) | RC-IGBT semiconductor device | |
| CN102593168B (en) | Semiconductor device and a reverse conducting IGBT | |
| KR101309674B1 (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CA2286699C (en) | Latch-up free power mos-bipolar transistor | |
| CN107785415B (en) | SOI-RC-LIGBT device and preparation method thereof | |
| JP3968912B2 (en) | diode | |
| JP5875680B2 (en) | Insulated gate bipolar transistor | |
| JP6139312B2 (en) | Semiconductor device | |
| CN114784108B (en) | Planar gate SiC MOSFET integrated with junction barrier Schottky diode and manufacturing method thereof | |
| CN114664929B (en) | Split gate SiC MOSFET integrated with heterojunction diode and manufacturing method thereof | |
| CN114784107B (en) | SiC MOSFET integrated with junction barrier Schottky diode and manufacturing method thereof | |
| CN110190128B (en) | MOSFET device with silicon carbide double-side deep L-shaped base region structure and preparation method thereof | |
| CN110137250B (en) | High-speed IGBT device with ultralow conduction voltage drop | |
| CN114937689B (en) | Planar SiC IGBT and manufacturing method thereof | |
| CN108155230B (en) | Transverse RC-IGBT device and preparation method thereof | |
| CN114944421B (en) | Groove type silicon carbide insulated gate field effect transistor and manufacturing method thereof | |
| CN112271208A (en) | Silicon carbide single-gate double-channel thyristor transport IGBT and manufacturing method thereof | |
| CN114937690B (en) | Planar silicon carbide insulated gate bipolar transistor and manufacturing method thereof | |
| CN114023815B (en) | Semi-vertical GaN-based reverse conducting IGBT device and preparation method thereof | |
| CN112736134A (en) | Silicon carbide PNPN thyristor injection type IGBT device | |
| CN209804661U (en) | MOSFET device with silicon carbide double-side deep L-shaped base region structure | |
| JP2021168379A (en) | Reverse-conducting igbt having reduced forward recovery voltage | |
| CN109065638B (en) | Power diode device | |
| CN114784109B (en) | Planar gate SiC MOSFET and manufacturing method thereof | |
| CN110444588B (en) | Groove IGBT device capable of reducing forward conduction voltage drop |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |