CN113192842B - CoolMOS device manufacturing method - Google Patents
CoolMOS device manufacturing method Download PDFInfo
- Publication number
- CN113192842B CN113192842B CN202110545584.0A CN202110545584A CN113192842B CN 113192842 B CN113192842 B CN 113192842B CN 202110545584 A CN202110545584 A CN 202110545584A CN 113192842 B CN113192842 B CN 113192842B
- Authority
- CN
- China
- Prior art keywords
- layer
- polysilicon gate
- pwell
- drain layer
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 82
- 229920005591 polysilicon Polymers 0.000 claims abstract description 82
- 238000000151 deposition Methods 0.000 claims abstract description 19
- 238000002347 injection Methods 0.000 claims abstract description 18
- 239000007924 injection Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 17
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 13
- 239000001301 oxygen Substances 0.000 claims abstract description 13
- 238000001259 photo etching Methods 0.000 claims abstract description 13
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000002161 passivation Methods 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 238000001465 metallisation Methods 0.000 claims abstract description 8
- 238000012545 processing Methods 0.000 claims abstract description 7
- 230000008021 deposition Effects 0.000 claims abstract description 6
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000013256 coordination polymer Substances 0.000 claims abstract description 4
- 239000011521 glass Substances 0.000 claims abstract description 4
- 238000010992 reflux Methods 0.000 claims abstract description 4
- 238000012360 testing method Methods 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 230000000903 blocking effect Effects 0.000 claims description 10
- 210000003371 toe Anatomy 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000007142 ring opening reaction Methods 0.000 abstract 1
- 238000000407 epitaxy Methods 0.000 description 4
- 239000011148 porous material Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a manufacturing method of a CoolMOS device, which comprises the following steps of 1) field oxygen growth, partial pressure ring opening, partial pressure ring injection annealing; 2) The active region is opened; 3) Processing deep trenches in the active region; 4) Growing gate oxide, depositing polysilicon gate, photoetching and etching; 5) The PWELL trap layer is injected and annealed; 6) N+ photoetching of a source region, n+ injection and annealing; 7) TEOS deposition, growth of passivation boron phosphorus silicon glass under aluminum, and reflux; 8) Photoetching a lead hole and etching the hole; 9) Front side metallization is formed; 10 Thinning; 11 Back side metallization; 12 CP test warehouse entry. The invention belongs to the technical field of semiconductor manufacturing, and particularly provides a manufacturing method of a CoolMOS device, which is used for carrying out deep trench etching in PWELL, depositing TEOS thick oxygen in a trench, realizing high-voltage output under a concentrated epitaxial condition and reducing internal resistance by utilizing a polycrystalline field plate shielding principle and a bottom PN junction principle.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a manufacturing method of a CoolMOS device.
Background
At present, the COOLMOS structure design mainly comprises two types, namely a P column structure is formed by adopting a processing technology of multiple epitaxy and multiple photoetching, the other type is a P column structure formed by adopting deep trench filling and P type epitaxy, the two methods respectively have the characteristics, the two existing methods at present realize a high-voltage VDMOS of a concentrated epitaxial layer by utilizing a P column and N type current channel charge balance method, and realize the aim of low internal resistance, but the commonality is that epitaxial growth is required, the cost is high, the processing period is long, the requirement on a production line is high, only a few domestic production lines can be processed and have strict patent protection, and the design and processing threshold is higher.
Disclosure of Invention
In order to solve the existing problems, the invention provides a method for manufacturing a CoolMOS device, which comprises the steps of carrying out deep trench etching in a PWELL, depositing TEOS thick oxygen in the deep trench, carrying out plasma etching, etching a TOES film at the bottom of the deep trench completely, then carrying out bottom P-type impurity injection, depositing polysilicon, carrying out polysilicon back etching, and finally carrying out open-pore short circuit on the polysilicon and the PWELL well layer together, wherein the short circuit is equivalent to grounding of the polysilicon in the trench and a source S short circuit, and realizing high-voltage output under the condition of thick epitaxy by utilizing a polysilicon field plate shielding principle and a bottom PN junction principle.
The technical scheme adopted by the invention is as follows: a manufacturing method of a CoolMOS device comprises the following steps:
1) Growing field oxygen, opening a voltage dividing ring, and injecting the voltage dividing ring into annealing;
2) The active region is opened;
3) Processing a deep trench in the active region, forming a TOES film by TEOS thick oxygen deposition in the deep trench, growing and solidifying the TOES film, performing plasma etching, injecting P-type impurities at the bottom of the deep trench, depositing a source trench polysilicon gate in the deep trench, and etching back the source trench polysilicon gate;
4) Growing gate oxide, depositing a polysilicon gate, photoetching the polysilicon gate, and etching the polysilicon gate;
5) The PWELL trap layer is injected and annealed;
6) N+ photoetching of a source region, n+ injection and annealing;
7) TEOS deposition, growth of passivation boron phosphorus silicon glass under aluminum, and reflux;
8) Photoetching a lead hole and etching the hole;
9) Front side metallization is formed;
10 Thinning;
11 Back side metallization;
12 CP test warehouse entry.
The CoolMOS device sequentially comprises a back metal layer, an N+ substrate layer, an N-type high-concentration current layer, an insulating layer and a front metal layer from bottom to top, wherein the upper surface of the N-type high-concentration current layer comprises a polysilicon gate region and a polysilicon opening region which are sequentially arranged at intervals, the lower surface of the front metal layer is provided with lead holes, the lead holes are arranged on the lower surface of the front metal layer at intervals, the upper wall in the lead holes is provided with an aluminum lower passivation layer, the aluminum lower passivation layer is filled with a polysilicon gate layer, the polysilicon gate layer is arranged in the polysilicon gate region, the upper surface of the N-type high-concentration current layer is embedded with a PWELL well layer, the PWELL well layer is arranged on the upper surface of the N-type high-concentration current layer at equal intervals, the middle part of the PWELL well layer is arranged in the polysilicon opening region, the two sides of the polysilicon gate region are arranged between two adjacent groups of PWELL well layers, a gate oxide layer is arranged between the polysilicon gate layer and the PWELL well layer as well as between the polysilicon gate layer and the N-type high concentration current layer, a plurality of groups of OPEN hole areas are arranged in the polysilicon OPEN area, an N+ injection blocking area is arranged in the OPEN hole areas, a deep groove is penetrated and arranged on the PWELL well layer, the lower end of the deep groove is extended and arranged in the N-type high concentration current layer, the deep groove is arranged at the N+ injection blocking area, a source groove polysilicon gate is filled and arranged in the deep groove, TEOS thick oxygen is arranged between the source groove polysilicon gate and the deep groove, the source groove polysilicon gates are uniformly distributed in the N+ injection blocking area at equal intervals, the N+ layer is arranged outside the N+ injection blocking area, when the polycrystalline OPEN area is perforated by the OPEN hole areas, the OPEN hole areas contain three parts of the N-type high concentration current layer, the PWELL well layer and the source groove polysilicon gate, a P+ layer is arranged at the bottom of the deep groove, the upper wall of the P+ layer penetrates and is connected with the source groove polysilicon gate, the bottom wall of the P+ layer is connected with an N-type high-concentration current layer, N+ layers are symmetrically arranged at one side, close to the polysilicon gate layer, of the upper end of the deep groove, the N+ layers are respectively connected with a source groove polysilicon gate and a PWELL well layer, and the source groove polysilicon gate is in short circuit with the PWELL well layer.
Further, two columns of deep trenches are arranged in each polycrystalline OPEN region, and N+ layers are symmetrically arranged on two sides of the two adjacent columns of deep trenches.
By adopting the scheme, the invention has the following beneficial effects: the invention relates to a manufacturing method of a CoolMOS device, which comprises the steps of carrying out deep trench etching in a PWELL trap layer, depositing TEOS thick oxygen in the deep trench to form a TOES film, then carrying out plasma etching to etch the bottom TOES film, carrying out bottom P-type impurity injection, depositing polysilicon, carrying out polysilicon back etching, and finally carrying out open-pore short circuit on the polysilicon and the PWELL trap layer together, wherein the short circuit is equivalent to grounding of the polysilicon in the trench and a source S short circuit, and the high-voltage output under the condition of thick epitaxy is realized by utilizing a polysilicon field plate shielding principle and a bottom PN junction principle, and the internal resistance is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a CoolMOS device of the present invention;
fig. 2 is a schematic cross-sectional view of an N-type high concentration current layer of a CoolMOS device of the present invention.
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings: 1. the back metal layer, 2, N+ substrate layer, 3, N type high concentration current layer, 4, gate oxide layer, 5, polysilicon gate region, 6, polysilicon OPEN region, 7, aluminum lower passivation layer, 8, polysilicon gate layer, 9, PWELL well layer, 10, lead hole, 11, OPEN pore region, 12, deep trench, 13, source trench polysilicon gate, 14, TEOS thick oxygen, 15, P+ layer, 16, N+ layer, 17, front metal layer, 18, N+ injection blocking region.
Detailed Description
The following description of the technical solutions in the embodiments of the present invention will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A manufacturing method of a CoolMOS device comprises the following steps:
1) Growing field oxygen, opening a voltage dividing ring, and injecting the voltage dividing ring into annealing;
2) The active region is opened;
3) Processing a deep trench 12 in the active region, depositing a TOES film by TEOS thick oxygen 14 in the deep trench 12, growing and solidifying the TOES film, performing plasma etching, injecting P-type impurities at the bottom of the deep trench 12, depositing a source electrode trench polysilicon gate 13 in the deep trench 12, and etching back the source electrode trench polysilicon gate 13;
4) Growing gate oxide 4, depositing a polysilicon gate, photoetching the polysilicon gate, and etching the polysilicon gate;
5) The PWELL well layer 9 is subjected to implantation annealing;
6) N+ photoetching of a source region, n+ injection and annealing;
7) TEOS deposition, growth of passivation boron phosphorus silicon glass under aluminum, and reflux;
8) Photoetching a lead hole and etching the hole;
9) Front side metallization is formed;
10 Thinning;
11 Back side metallization;
12 CP test warehouse entry.
As shown in fig. 1-2, a CoolMOS device comprises a back metal layer 1, an n+ substrate layer 2, an N-type high concentration current layer 3 and a front metal layer 17 from bottom to top, wherein the upper surface of the N-type high concentration current layer 3 comprises a polysilicon gate region 5 and a polysilicon OPEN region 6 which are sequentially arranged at intervals, the lower surface of the front metal layer 17 is provided with a lead hole 10, the lead hole 10 is arranged at intervals on the lower surface of the front metal layer 17, the upper wall in the lead hole 10 is provided with an aluminum lower passivation layer 7, the aluminum lower passivation layer 7 is filled with a polysilicon gate layer 8, the polysilicon gate layer 8 is arranged in the polysilicon gate region 5, the upper surface of the N-type high concentration current layer 3 is embedded with a PWELL well layer 9, the PWELL well layer 9 is arranged on the upper surface of the N-type high concentration current layer 3 at equal intervals, the middle of the PWELL well layer 9 is arranged in the polysilicon OPEN region 6, both sides of the polysilicon gate region 5, the polysilicon gate layer 8 is arranged between two adjacent groups of PWELL well layers 9, a gate oxide layer 4 is arranged between the polysilicon gate layer 8 and the PWELL well layers 9 and between the polysilicon gate layer 8 and the N-type high-concentration current layer 3, a plurality of groups of OPEN areas 11 are arranged in the polysilicon OPEN area 6, N+ injection blocking areas 18 are arranged in the OPEN areas 11, deep trenches 12 are penetrated on the PWELL well layers 9, the lower ends of the deep trenches 12 are extended and arranged in the N-type high-concentration current layer 3, the deep trenches 12 are arranged at the N+ injection blocking areas 18, source trench polysilicon gates 13 are filled in the deep trenches 12, TEOS thick oxygen is arranged between the source trench polysilicon gates 13 and the deep trenches 12, the source trench polysilicon gates 13 are uniformly distributed in the N+ injection blocking areas 18 at equal intervals, the N+ layers 16 are arranged outside the N+ injection blocking areas 18, P+ layers 15 are arranged at the bottoms of the deep trenches 12, the upper wall of the P+ layer 15 penetrates through the deep groove 12 to be connected with the source groove polysilicon gate 13, the bottom wall of the P+ layer 15 is connected with the N-type high-concentration current layer 3, an N+ layer 16 is arranged on one side, close to the polysilicon gate layer, of the upper end of the deep groove 12, the N+ layer 16 is respectively connected with the source groove polysilicon gate 13 and the PWELL well layer 9, and the source groove polysilicon gate 13 is in short circuit with the PWELL well layer 9.
Wherein, each polycrystal OPEN region 6 is internally provided with two columns of deep trenches 12, and N+ layers 16 are symmetrically arranged at two sides of two adjacent columns of deep trenches;
through multiple experiments, the method develops a 600V medium-high voltage plane VDMOS product, and compared with the product with the same area, the internal resistance is reduced by 50 percent.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related arts are included in the scope of the present invention.
Claims (2)
1. The manufacturing method of the CoolMOS device is characterized by comprising the following steps of:
1) Growing field oxygen, opening a voltage dividing ring, and injecting the voltage dividing ring into annealing;
2) The active region is opened;
3) Processing a deep trench in the active region, forming a TOES film by TEOS thick oxygen deposition in the deep trench, growing and solidifying the TOES film, performing plasma etching, injecting P-type impurities at the bottom of the deep trench, depositing a source trench polysilicon gate in the deep trench, and etching back the source trench polysilicon gate;
4) Growing gate oxide, depositing a polysilicon gate, photoetching the polysilicon gate, and etching the polysilicon gate;
5) The PWELL trap layer is injected and annealed;
6) N+ photoetching of a source region, n+ injection and annealing;
7) TEOS deposition, growth of passivation boron phosphorus silicon glass under aluminum, and reflux;
8) Photoetching a lead hole and etching the hole;
9) Front side metallization is formed;
10 Thinning;
11 Back side metallization;
12 CP test warehouse entry;
the CoolMOS device sequentially comprises a back metal layer, an N+ substrate layer, an N-type high-concentration current layer, an insulating layer and a front metal layer from bottom to top, wherein the upper surface of the N-type high-concentration current layer comprises a polysilicon gate region and a polysilicon OPEN region which are sequentially arranged at intervals, the lower surface of the front metal layer is provided with lead holes, the lead holes are arranged on the lower surface of the front metal layer at intervals, the upper wall in the lead holes is provided with an aluminum lower passivation layer, the aluminum lower passivation layer is filled with a polysilicon gate layer, the polysilicon gate layer is arranged in the polysilicon gate region, the upper surface of the N-type high-concentration current layer is embedded with a PWELL well layer, the middle part of the PWELL well layer is arranged on the upper surface of the N-type high-concentration current layer at intervals, the two sides of the PWELL well layer are arranged in the polysilicon gate region, the polysilicon gate layer is arranged between two adjacent groups of PWELL well layers, a plurality of groups of injection hole openings are arranged in the polysilicon OPEN hole region, the polysilicon gate layer is filled with a polysilicon gate layer, the bottom of the polysilicon gate layer is arranged in the polysilicon gate layer is connected with the polysilicon gate layer, the bottom of the polysilicon gate layer is connected with the drain layer, the bottom of the drain layer is arranged at intervals, the bottom of the drain layer is connected with the drain layer, the drain layer is arranged at intervals, the drain layer is connected with the drain layer is arranged at one side of the drain layer, the drain layer is connected with the drain layer, the drain layer is arranged at the drain layer, the drain layer is connected with the drain layer, the drain layer is arranged between the drain layer and the drain layer. The N+ layer is respectively connected with the source groove polysilicon gate and the PWELL trap layer, and is arranged outside the N+ injection blocking area, and the source groove polysilicon gate is in short circuit with the PWELL trap layer.
2. The method for fabricating a CoolMOS device as defined in claim 1, wherein two columns of deep trenches are disposed in each group of poly OPEN regions, and n+ layers are symmetrically disposed on both sides of two adjacent columns of deep trenches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110545584.0A CN113192842B (en) | 2021-05-19 | 2021-05-19 | CoolMOS device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110545584.0A CN113192842B (en) | 2021-05-19 | 2021-05-19 | CoolMOS device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113192842A CN113192842A (en) | 2021-07-30 |
| CN113192842B true CN113192842B (en) | 2023-05-09 |
Family
ID=76982359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110545584.0A Active CN113192842B (en) | 2021-05-19 | 2021-05-19 | CoolMOS device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113192842B (en) |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005065385A2 (en) * | 2003-12-30 | 2005-07-21 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
| JP5135759B2 (en) * | 2006-10-19 | 2013-02-06 | 富士電機株式会社 | Manufacturing method of super junction semiconductor device |
| JP2010050161A (en) * | 2008-08-19 | 2010-03-04 | Nec Electronics Corp | Semiconductor device |
| US8354711B2 (en) * | 2010-01-11 | 2013-01-15 | Maxpower Semiconductor, Inc. | Power MOSFET and its edge termination |
| US8564058B1 (en) * | 2012-08-07 | 2013-10-22 | Force Mos Technology Co., Ltd. | Super-junction trench MOSFET with multiple trenched gates in unit cell |
| JP6078390B2 (en) * | 2013-03-25 | 2017-02-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| US8829607B1 (en) * | 2013-07-25 | 2014-09-09 | Fu-Yuan Hsieh | Fast switching super-junction trench MOSFETs |
| CN106024863A (en) * | 2016-06-27 | 2016-10-12 | 电子科技大学 | High-voltage power device terminal structure |
| US10998438B2 (en) * | 2018-03-01 | 2021-05-04 | Ipower Semiconductor | Self-aligned trench MOSFET structures and methods |
-
2021
- 2021-05-19 CN CN202110545584.0A patent/CN113192842B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN113192842A (en) | 2021-07-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107204372B (en) | Trench type semiconductor device with optimized terminal structure and manufacturing method | |
| JP5089284B2 (en) | Semiconductor device having a space-saving edge structure | |
| KR101745776B1 (en) | Power Semiconductor Device | |
| CN102005452A (en) | Integrated schottky diode in high voltage semiconductor device | |
| CN108242467B (en) | LDMOS device and manufacturing method thereof | |
| CN104716177A (en) | Radio frequency LOMOS device for overcoming electricity leakage and manufacturing method of radio frequency LOMOS device for overcoming electricity leakage | |
| CN104637821A (en) | Manufacturing method of super junction device | |
| CN110429134B (en) | IGBT device with asymmetric primitive cells and preparation method | |
| CN114023821B (en) | Super junction device and manufacturing method thereof | |
| CN103050523A (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| KR101315699B1 (en) | Power mosfet having superjunction trench and fabrication method thereof | |
| CN113066865B (en) | Semiconductor device for reducing switching loss and manufacturing method thereof | |
| CN114005877A (en) | Ultrathin super-junction IGBT device and preparation method | |
| CN112216743A (en) | Trench power semiconductor device and manufacturing method | |
| CN113192842B (en) | CoolMOS device manufacturing method | |
| CN111415867A (en) | Semiconductor power device structure and manufacturing method thereof | |
| CN112635331B (en) | Preparation method of super junction power device | |
| CN102214561A (en) | Super-junction semiconductor device and manufacturing method thereof | |
| CN213905364U (en) | Trench power semiconductor device | |
| CN111244158B (en) | Super junction device and manufacturing method thereof | |
| CN112216744A (en) | High-reliability wide-window super-junction MOSFET structure and manufacturing method | |
| CN110047831B (en) | Semiconductor power device and preparation method thereof | |
| CN112420845A (en) | Trench power semiconductor device and manufacturing method | |
| CN113659011A (en) | Integrated device based on super junction MOSFET and manufacturing method thereof | |
| CN111223915A (en) | Multi-time epitaxial super junction device structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |