JP4009825B2 - Insulated gate transistor - Google Patents

Insulated gate transistor Download PDF

Info

Publication number
JP4009825B2
JP4009825B2 JP2002042990A JP2002042990A JP4009825B2 JP 4009825 B2 JP4009825 B2 JP 4009825B2 JP 2002042990 A JP2002042990 A JP 2002042990A JP 2002042990 A JP2002042990 A JP 2002042990A JP 4009825 B2 JP4009825 B2 JP 4009825B2
Authority
JP
Japan
Prior art keywords
semiconductor region
region
semiconductor
insulating film
depletion layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002042990A
Other languages
Japanese (ja)
Other versions
JP2003243655A (en
Inventor
正行 花岡
良治 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP2002042990A priority Critical patent/JP4009825B2/en
Publication of JP2003243655A publication Critical patent/JP2003243655A/en
Application granted granted Critical
Publication of JP4009825B2 publication Critical patent/JP4009825B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、柱状に形成されたボデイ領域を有する絶縁ゲート型トランジスタ及びその製造方法に関する。
【０００２】
【従来の技術】
動作抵抗の低減化と高耐圧化の両方を高水準に達成することを目的として絶縁ゲート型電界効果トランジスタ（以下ＦＥＴと言う。）を図１に示すように構成することは公知である。このＦＥＴは、Ｎ形ドリフト領域１とＮ＋形ドレイン領域２と複数のＰ形ボデイ領域３と複数のソース領域４とから成るシリコン半導体基体５と、ドレイン電極６と、ソース電極７と、ゲート電極８と、ゲート絶縁膜９と、周辺保護絶縁膜１０と、層間絶縁膜１１とを備えている。このＦＥＴのベース領域又はチャネル形成領域と呼ぶことのできるボデイ領域３は特異な形状を有し、ドリフト領域１の厚み方向に深く柱状に形成されており、その底面はドリフト領域１とドレイン領域２との界面近くまで達している。複数のボデイ領域３を柱状に形成すると、ＦＥＴのオフ期間にボデイ領域３とドリフト領域１との間のＰＮ接合に高い逆方向電圧が印加された時に複数のボデイ領域３の相互間のドリフト領域１が空乏層によって埋められ、耐圧が向上する。また、図１の構造の場合、ドリフト領域１の比抵抗を小さくして動作抵抗の低減化を図っても比較的高耐圧を得ることができる。即ち、ドリフト領域１の比抵抗を、浅いボデイ領域を有する従来の標準的な構造のＦＥＴのドレイン領域の抵抗率の１／３〜１／５に設定しても、空乏層の働きで標準的な構造のＦＥＴと同等の耐圧を得ることができる。
【０００３】
【発明が解決しようとする課題】
ところで、図１の絶縁ゲート型ＦＥＴにおけるボデイ領域３は、周知のエピタキシャル成長と不純物拡散を複数回繰り返して形成される。即ち、ドレイン領域２の上に肉薄のＮ形エピタキシャル層を形成し、このエピタキシャル層にＰ形不純物を導入してボデイ領域３のためのＰ形拡散領域を形成する。次に、このＮ形エピタキシャル層とＰ形拡散領域の表面を被覆するように肉薄のＮ形エピタキシャル層を形成し、先に形成した下側のＰ形半導体領域と連続するようにＰ形不純物を導入してボデイ領域３のための上側Ｐ形拡散領域を形成する。これを複数回繰り返すことによって、ボデイ領域３が柱状に素子の厚み方向に延びるように形成された図１の絶縁ゲート型電界効果トランジスタが得られる。
【０００４】
しかし、図１の絶縁ゲート型ＦＥＴでは、エピタキシャル成長と拡散を複数回繰り返して形成する必要があるため、素子の製造工程が複雑であり、比較的コストも高かった。この種の問題はＩＧＢＴ等においても生じる。
【０００５】
そこで、本発明の目的は、上記の問題を解決し、且つ耐圧の向上と動作抵抗の低減化を高水準に達成することができる新規な構造の絶縁ゲート型トランジスタ及びその製造方法を提供することにある。
【０００６】
【課題を解決するための手段】
次に、上記課題を解決し、上記目的を達成するための本発明を実施形態を示す符号を参照して説明する。なお、特許請求の範囲及び本発明の説明で参照する符号は、本発明の理解を助けるためのみのものであって本発明を限定するものではない。
本願請求項１の発明は、複数の絶縁ゲート型トランジスタのセルの集合から成る絶縁ゲート型トランジスタであって、前記複数のセルのための複数のセル部分（１９）を有する半導体基板（２０）と、第１及び第２の主電極（２９、３１）と、ゲート電極（３１）と、ゲート絶縁膜（３３）と、空乏層用絶縁膜（３４）と、空乏層用導体層（３５）と、電圧印加手段とを備え、
前記複数のセル部分（１９）を互いに分離するように前記半導体基板に溝（２７）が形成され、
前記溝（２７）は前記半導体基板の一方の主面に入口を有するように形成され、
前記半導体基板の各セル部分（１９）は、前記溝の壁面に露出する表面を有するように配置された第１導電形の第１の半導体領域（２２）と、前記半導体基板の一方の主面と前記第１の半導体領域（２２）との間に配置され且つ前記一方の主面に露出する表面を有している第２導電形の第２の半導体領域（２３）と、前記一方の主面と前記第２の半導体領域（２３）との間に配置され且つ前記一方の主面に露出する表面を有している第１導電形の第３の半導体領域（２４）とをそれぞれ備えており、
前記第２の半導体領域（２３）は前記第１の半導体領域（２２）と前記第３の半導体領域（２４）との間において露出するチャネル用表面を有し、
前記第１の主電極（２９）は前記半導体基板（２０）の前記一方の主面に配置され且つ各セル部分の前記第２及び第３の半導体領域（２３、２４）にそれぞれ接続され、
前記第２の主電極（３１）は前記第１の半導体領域（２２）に直接に又は別の半導体領域を介して接続され、
前記ゲート絶縁膜（３３）は前記第２の半導体領域（２３）の前記チャネル用表面を覆うように配置され、
前記ゲート電極（３１）は前記ゲート絶縁膜（３３）に隣接配置され、
前記空乏層用絶縁膜（３４）は前記溝の壁面に露出する前記第１の半導体領域（２２）に隣接配置され、
前記空乏層用導体層（３５）は前記溝の中に配置され且つ前記空乏層用絶縁膜（３４）に隣接配置され、
前記電圧印加手段は、前記第１及び第２の半導体領域（２２、２３）間のＰＮ接合に逆方向電圧が印加され且つ前記第２の半導体領域にチャネルが形成されていない状態において前記第１の半導体領域（２２）に空乏層を形成するための電圧を前記空乏層用導体層（３５）に供給するものであって、前記ゲート電極（３２）と前記空乏層用導体層（３５）との間に接続された第１の定電圧素子と、前記空乏層用導体層（３５）と前記第２の主電極（３１）との間に接続された第２の定電圧素子とから成ることを特徴とする絶縁ゲート型トランジスタに係るものである。
【０００７】
なお、請求項２に示すように、更に、前記第１の半導体領域（２２）と前記第２の主電極（３１）との間に配置され且つ前記第１の半導体領域（２２）の第１導電形不純物の濃度よりも高い第１導電形不純物の濃度を有している第４の半導体領域（２１）を備え、前記第２の主電極（３１）が前記第４の半導体領域（２１）に接続されていることが望ましい。
また、請求項３に示すように、更に、前記第１の半導体領域（２２）の前記半導体基板（２０）側の主面に隣接配置され且つ前記第１の半導体領域（２２）の第１導電形不純物の濃度よりも高い第１導電形不純物の濃度を有している第４の半導体領域（２１ａ）と、前記第４の半導体領域（２１ａ）と前記第２の主電極（３１）との間に配置され且つ第２の導電形を有している第５の半導体領域（２１ｂ）とを備え、
前記第２の主電極（３１ａ）は前記第５の半導体領域（２１ｂ）に接続されていることが望ましい。
また、請求項４に示すように、前記第２の半導体領域（２３）の前記チャネル表面は前記溝の中に露出していることが望ましい。
また、請求項５に示すように、前記第２の半導体領域（２３）の前記チャネル表面を前記半導体基板（２０）の一方の主面に露出させることができる。
【０００８】
【発明の効果】
本願各請求項の発明は次の効果を有する。
（１） 半導体基板（２０）の中に溝（２７）が形成され、この溝（２７）の中に少なくとも１つの空乏層用絶縁膜(３４ａ)及び導体層（３５）が配置されている。このため、絶縁ゲ−ト型トランジスタのオフ状態時に空乏層用絶縁膜(３４ａ)及び導体層（３５）の働きで第１の半導体領域（２２）に空乏層を生成することができ、耐圧向上を図ることができる。
なお、耐圧が従来と同一で良い場合には、第１の半導体領域（２２）の抵抗率を従来よりも小さくしてオン状態における第１の半導体領域（２２）の抵抗値を従来よりも小さくすることができる。
（２）第１の半導体領域（２２）の厚みを、複数回のエピタキシャル成長工程を伴わないで容易に厚くすることができる。
（３） 電圧印加手段として、前記ゲート電極（３２）と前記空乏層用導体層（３５）との間に接続された第１の定電圧素子と、前記空乏層用導体層（３５）と前記第２の主電極（３１）との間に接続された第２の定電圧素子とを有するので、前記空乏層用導体層（３５）に所定レベルの電圧を正確に供給できる。
【０００９】
【第１の実施形態】
次に、図２乃至図１１を参照して本発明の実施形態に従う絶縁ゲート型電界効果トランジスタを説明する。
【００１０】
図２は本発明の第１の実施形態に従う複数の微小ＦＥＴ即ちセルの集まりから成る縦形絶縁ゲート型電界効果トランジスタ即ちＦＥＴの半導体基板２０の表面の一部を示す平面図であり、図３はＦＥＴの図２のＡ−Ａ線の一部に相当する部分を示す断面図であり、図４は図２のＢ−Ｂ線に相当する部分を示す断面図である。このＦＥＴを構成するシリコン半導体基板２０は、溝２７によって碁盤の目状に分割された複数のＦＥＴセル部分１９を有する。複数のセル部分１９は図３に示すようにＮ＋形（第１導電形）半導体から成るＮ＋形ドレイン領域２１の上に配置されている。各セル部分１９は、Ｎ形即ち第１導電形の第１の半導体領域としてのドリフト領域２２と、Ｐ形即ち第２導電形の第２の半導体領域としてのボデイ領域２３と、Ｎ形の第３の半導体領域としてのソース領域２４とを備えている。なお、Ｎ＋形ドレイン領域２１を低抵抗又は第１のドレイン領域、Ｎ形ドリフト領域を高抵抗又は第２のドレイン領域と呼ぶこともできる。
【００１１】
半導体基板２０は互いに対向している第１即ち一方の主面２５と第２即ち他方の主面２６とを有する。セル部分１９を電気的に分離するための溝２７は、半導体基板２０の第１の主面２５に図２に示すように格子状に形成されている。この溝２７はトレンチ又は堀とも呼ぶことができるものであって、平面的に見てＮ＋形ソース領域２４を囲むように形成され且つ第１の主面２５に対して垂直方向に延びている。この溝２７の深さは、図３から明らかなように、第１の主面２５を基準にしてＰ形ボデイ領域２３よりも深い。また、この溝２７の深さは第１の主面２５からＮ＋形ドレイン領域２１までの距離よりも浅い。従って、溝２７の底面とＮ＋形ドレイン領域２１との間にＮ形ドリフト領域２２の一部が残存し、各セル部分１９のＮ形ドリフト領域２２はＮ＋形ドレイン領域２１の近くで互いに連続している。
【００１２】
各セル部分１９に対しての共通のドレイン領域２１は半導体基板２０の第２の主面２６に露出するように配置されている。
【００１３】
Ｎ形ドリフト領域２２は、基板として機能するドレイン領域２１上に１回のエピタキシャル成長で形成されたＮ形領域であり、ドレイン領域２１よりも低い不純物濃度及び高い抵抗率を有する。しかし、Ｎ形ドリフト領域２２の不純物濃度は図１の従来のＦＥＴのドリフト領域１の不純物濃度よりも低く、且つドリフト領域２２の抵抗率は図１の従来のＦＥＴの抵抗率の１／５〜１／３である。ドリフト領域２２とドレイン領域２１との境界は半導体基板２０の第１及び第２の主面２５、２６に対して平行である。
【００１４】
Ｐ形ボデイ領域２３は、Ｎ形ドリフト領域２２と第１の主面２５との間に配置されている。１回の不純物拡散で形成されたＰ形ボデイ領域２３とＮ形ドリフト領域２２との境界は第１及び第２の主面２５、２６に対して平行である。Ｐ形ボデイ領域２３のＰ形不純物濃度はＮ形ドリフト領域２２のＮ形不純物濃度よりも高い。ボデイ領域２３は第１の主面２５に露出し且つ溝２７にも露出している。ボデイ領域２３のチャネル部分２８は図３で点線で示すように溝２７に面している。即ち、チャネル部分２８の表面は溝２７に露出し、ソース領域２４からドリフト領域２２に向って縦方向に延びている。格子状溝２７によって区画されたＰ形ボデイ領域２３は平面的に見て四角形である。しかし、ボデイ領域２３の平面形状を円形等の別の形状にすることができる。
【００１５】
Ｎ＋形ソース領域２４はＰ形ボデイ領域２３の中に不純物拡散によって形成されている。このソース領域２４は図２から明らかなように平面的に見て四角形の環状であり、上面が半導体基板２０の第１の主面２５に露出し、その底面及び内周側面がＰ形ボデイ領域２３に隣接し、外周側面が溝２７に露出している。
【００１６】
半導体基板２０の第１の主面２５上に第１の主電極としてのソース電極２９が配置されている。このソース電極２９は例えばアルミニウム蒸着層から成り、各ＦＥＴセルのソース領域２４に接続されていると共にボデイ領域２３にも接続されている。また、ソース電極２９は半導体基板２０の第１の主面２５上の絶縁層３０の上にも延在し、各ＦＥＴセルのソース領域２４を並列に接続している。
【００１７】
例えばアルミニウム蒸着層から成る第２の主電極としてのドレイン電極３１は半導体基板２０の第２の主面２６に配置され且つＮ＋形ドレイン領域２１に接続されている。
【００１８】
ゲート電極３２は、溝２７の中に配置されている。溝２７が平面的に見て格子状であるので、ゲート電極３２も格子状に形成されている。ゲート電極３２は不純物がドープされた多結晶シリコンから成る。
【００１９】
ゲート絶縁膜３３はシリコン酸化膜から成り、溝２７の壁面に形成されている。即ち、ゲート絶縁膜３３は溝２７に露出するボデイ領域２３のチャネル部分２８の露出表面を覆うように形成されている。従って、ゲート電極３１はゲート絶縁膜３３を介してチャネル形成部分２８及びソース領域２４の一部及びドリフト領域２２の一部に対向している。
【００２０】
溝２７は高耐圧ＦＥＴを得るために異方性エッチングによって比較的深く形成されている。溝２７の中には絶縁膜３４で相互に分離された不純物ドープの多結晶シリコンから成る第１、第２及び第３の空乏層用導体層３５、３６、３７が設けられている。
【００２１】
不純物ドープの多結晶シリコンから成るゲート電極３２、第１、第２及び第３の空乏層用導体層３５、３６、３７は、幅及び厚みがそれぞれ等しく、且つ等間隔に配置されている。溝２７内の絶縁膜３４は、Ｎ形ドリフト領域２２に空乏層を生じさせるために溝２７の壁面に配置された空乏層用絶縁膜３４ａと、ゲート電極３２、第１、第２及び第３の空乏層用導体層３５、３６、３７を相互に分離するための層間絶縁膜３４ｂとから成る。空乏層用絶縁膜３４ａはゲート絶縁膜３３に連続している。
【００２２】
第１、第２及び第３の空乏層用導体層３５、３６、３７は、空乏層用絶縁膜３４ａを介してＮ形ドリフト領域２２に対向している。ゲート電極３２、第１、第２及び第３の空乏層用導体層３５、３６、３７は電圧印加手段４０に接続され、ドレイン電極３１よりも低い電位が付与される。これにより、ドリフト領域２２にドレイン電流が流れていない時に、第１、第２及び第３の空乏層用導体層３５，３６、３７が周知のフィールドプレートと同様にＮ形ドリフト領域２２に空乏層を生成するための導体層として機能する。なお、ゲート電極３２もＮ形ドリフト領域２２に空乏層を生成する機能を有する。
【００２３】
半導体基板２０の第1の主面２５上の絶縁膜３０には、ソ−ス接続用開口３８が設けられ、各セル部分１９のソ−ス領域２４、P形ボデイ領域２３にソ−ス電極２９が接続されている。図３には示されていないが図４に示すように絶縁膜３０の上に電圧印加手段４０として多結晶シリコンから成る第１、第２、第３及び第４のツェナ−ダイオ−ド４１、４２、４３、４４が設けられている。定電圧素子としての第１〜第４のツェナ−ダイオ−ド４１〜４４は、図５に示すように互いに直列に接続され、直列回路の一端及び他端の導体４５、４６の他に中間導体４７、４８、４９が設けられている。ツェナ−ダイオ−ド４１、４２、４３、４４とゲ−ト電極３２、第１、第２及び第３の空乏層用導体層３５、３６、３７との間の電気的接続を可能にするために、図４に示すように半導体基板２０の周辺部においてゲ−ト電極３２、第１、第２及び第３の空乏層用導体層３５、３６、３７が階段状に露出され、第１、第２、第３及び第４の接続導体５０、５１、５２、５３が設けられている。導体５０は図示されていないゲ−ト信号入力端子に接続されていると共に導体４５に接続されている。導体５１、５２、５３は中間導体４７、４８、４９に接続されている。ツェナ−ダイオ−ド４４の端子導体４６はドレイン電極３１に接続されている。なお、導体４５〜４９と導体５０〜５３との間の接続は、ワイヤによる接続、又は導体５０〜５３の上に絶縁層を設け,この絶縁層に至る貫通孔を設け、各貫通孔に導体を充填し、この充填導体と導体４５〜４９とを接続することのよって達成される。
【００２４】
次に、図６〜図１１を参照して図２〜図５に示すＦＥＴの製造方法について説明する。
まず、図６に示すように、ドリフト領域２２としてのＮ形シリコン半導体基板２０を用意し、その一方の主面にＰ形不純物を拡散してボデイ領域２３を形成し、更にこのボデイ領域２３にＮ形不純物を拡散して複数のソ−ス領域２４を形成する。ソ−ス領域２４は、図７の工程で溝２７によって除去される部分を含むように形成する。また、Ｎ形半導体基板２０の他方の主面にはＮ形不純物を拡散してドレイン領域２１を形成する。なお、ボデイ領域２３及びソ−ス領域２４は、図７の溝２７の形成工程の後に形成することもできる。
【００２５】
次に、一方の主面２５に垂直方向のエッチング速度が水平方向のエッチング速度よりも速い周知の異方向エッチング方法によって、図７に示すように半導体基板２０の第１の主面２５にトレンチ溝２７を形成する。溝２７は図６のソ−ス領域２４を分断するように形成するので、ソ−ス領域２４の側面を溝２７に確実に露出させることができる。
【００２６】
次に、図７の半導体基板２０に熱処理を施して、図８に示すようにトレンチ溝２７の底面と壁面にシリコン酸化膜から成る絶縁膜６０を形成する。なお、絶縁膜６０の上面はゲ−ト絶縁膜３３として機能し、下部は空乏層用絶縁膜３４ａとして機能する。このとき、半導体基板２０の主面２５，２６等にも絶縁膜が形成されるが、これ等の図示は省略さている。
【００２７】
次に、図９に示すようにドナ−不純物又はアクセプタ不純物がド−プされた多結晶シリコン３７ａをトレンチ溝２７内に埋設する。このとき、半導体基板２０の一方の主面２５にも多結晶シリコンが形成されるが、この図示は省略されている。
【００２８】
次に、図１０に示すようにトレンチ溝２７内に埋設された多結晶シリコン３７ａを所望の厚さまでエッチングして、第３の導体層３７を形成する。
次に、この第３の導体層３７の上面に熱酸化によりシリコン酸化膜から成る 導体層分離用絶縁膜３４ｂを形成する。従って、導体層３７は空乏層用絶縁膜３４ａと層間絶縁膜３４ｂとの組み合せから成る分離絶縁膜３４によって隣の導体層３６と電気的に分離される。
【００２９】
次に、再びトレンチ溝２７内にドナ−不純物又はアクセプタ不純物のド−プされた多結晶シリコン膜を埋設した後、これを所望の厚さまでにエッチングして第２の導体層３６を形成する。
【００３０】
以後、この工程を繰返して第２及び第３の導体層３７、３７と同一の方法で、第３の導体層３５及びゲ−ト電極３１を形成する。
【００３１】
その後、半導体基板２０の一方の主面２５にシリコン酸化膜から成る絶縁膜３０を形成し、更に、この絶縁膜３０の上に図１１に示すようにツェナ−ダイオ−ド４１〜４４を形成する。ツェナ−ダイオ−ド４１〜４４は、多結晶シリコン層６１を形成し、ここに複数のＰ形領域とＮ型領域とを設け、更に端子導体層４５、４６及び中間導体層４７、４８、４９を設けることによって得る。
【００３２】
ソ−ス電極２４は、絶縁膜３０にコンタクト開口３８を設け、更にアルミニウムを蒸着してコンタクト開口３８を通じてボデイ領域２３及びソ−ス領域２４に電気的に接続された導体層を形成することによって得る。ドレイン電極３１は、半導体基板２０の他方の主面にアルミニウムを蒸着することによって得る。
【００３３】
本実施形態のマルチセル構造のＦＥＴは次の効果を有する。
(１) 微小ＦＥＴを構成するセル部分１９が溝２７によって区画され、溝２７の壁面に空乏層用絶縁膜３４ａを介して導体層３５、３６、３７が配置され、導体層３５、３６、３７には電圧が印加されるので、ＦＥＴのオフ期間においてフィ−ルドプレ−トと同様な作用で第１の半導体領域としてのＮ形ドリフト領域２２とＮ+形ドレイン領域２１とに図３で鎖線で示すように空乏層６２が生じ、ＦＥＴの高耐圧化が容易に達成される。即ち、ＦＥＴのオフ時に溝２７で囲まれたＮ形ドリフト領域２２を埋めるような厚い空乏層が形成されるので、ＦＥＴの耐圧が高くなる。なお、ＦＥＴのオン時には、チャネル部分２８を通ってドリフト領域２２にキャリア（電子）が注入されるのでドリフト領域２２の不純物濃度が等価的に低下し、ドレイン電流ンの流を妨害するような空乏層は生じない。また、ドリフト領域２２の抵抗率が従来よりも小さくなっているので、ＦＥＴのオン時の抵抗を小さくすることができる。要するに、ＦＥＴの動作抵抗の低減と高耐圧トの両方又は一方を達成できる。
（２） トレンチ溝２７によって区画された柱状セル部分１９を容易に得ることができる。即ち、図１に示す従来のＦＥＴでは、複数回のエピタキシャル成長と拡散との繰返しでボデイ領域３及びドリフト領域１を形成したので、製造工程が煩雑になり、コスト高になった。これに対して、本実施形態では、溝２７の形成によって柱状のドリフト領域２２を得ることができ、コストの低減を図ることができる。
（３） ボデイ領域２３は１回の拡散で形成されるので、所定の幅のチャネル部分２８を用意に得ることができ、且つデバイスの微細化が可能になる。
（４） 図６のソ−ス領域２４を横切るように溝２７を形成するので、ソ−ス領域２４の側面を溝２７に確実且つ容易に露出させることができる。また、縦方向に延びるチャネル部分２８を容易に形成することができる。
（５） 定電圧素子としてのツェナ−ダイオ−ド４１〜４４によって導体層３５、３６、３７に電圧を供給するので、所定レベルの電圧を正確に供給できる。
（６） ツエナ−ダイオ−ド４１〜４４をＦＥＴに一体化したので、小型化、低コスト化を図ることができる。
【００３４】
【第２の実施形態】
図１２は第２の実施形態のＩＧＢＴ即ち絶縁ゲ−トバイポ−ラトランジスタを図３と同様に示すものである。
図１２のＩＧＢＴは、図３のＦＥＴにＰ+形コレクタ領域２１ｂを付加し、この他は実質的に図２と同一に形成したものである。なお、図３のＮ+形ドレイン領域２１と同様な働きを有するＮ+形領域２１ａがＮ形ドリフト領域２２とＰ+形コレクタ領域２１ｂとの間に配置されている。また、図１２はＩＧＢＴであるので、図３のソ−ス領域２４、ボデイ領域２３、及びソ−ス電極２９に相当するものは図１２においてエミッタ領域、ベ−ス領域、エミッタ電極となる。また、図３のドレイン電極３１に相当するものはコレクタ電極となる。
【００３５】
図１２のＩＧＢＴは、Ｐ+形コレクタ領域２１ｂを有する他は、図３と同一構造であるので、第１の実施形態のＦＥＴと同一の効果を有する。
【００３６】
【第３の実施形態】
図１３の第３の実施形態のＦＥＴは、図３のＦＥＴのゲ−ト電極３２の位置及びこれに対応する部分の位置を変え、この他は図３と同一に構成したものである。即ち、図１３ではゲ−ト電極３２が基板２０の一方の主面２５上にゲ−ト絶縁膜３３を介して配置されている。これに伴いボデイ領域２３はＰ形ドリフト領域２２の中に島状に形成され、上面以外がＮ形ドリフト領域２２で囲まれている。また、Ｎ+形ソ−ス領域２４はボデイ領域２３の中に島状に形成されている。従って、ボデイ領域２３のチャネル部分２８は基板２０の一方の主面２５に露出するように配置されている。
【００３７】
図１３のＦＥＴの基本的構成は図３のＦＥＴと同一であるので、図３のＦＥＴと同一の効果を有する。なお、図１３においてドレイン領域２１に示す鎖線よりも下方に図１２のＰ+形コレクタ領域２１ｂと同様なものを設け、ＩＧＢＴとすることができる。
【００３８】
【変形例】
本発明は上述の実施例に限定されるものでなく、例えば、次の変形が可能なものである。
（１） 図１２に示すＰ+形コレクタ領域２１ｂに相当するものを基板２０の他方の主面２６の一部にのみ設け、他方の主面２６にＮ+形領域２１ａとＰ+形領域２１ｂとの両方を露出させ、ここに電極３１を接続することができる。
（２） 基板２０の一方の主面２５側に至るようにＮ+形ドレイン領域２１に連続するＮ+形引き出し領域即ちプラグ領域を設け、ここに接続されるように基板２０の一方の主面２５側にドレイン電極３１を設けることができる。図１２のＩＧＢＴの場合も同様にＰ+形コレクタ領域２１ｂのＰ+形引き出し領域を基板２０の一方の主面２５に至るように形成し、ここにコレクタ電極を接続することができる。
（３） ツェナ−ダイオ−ド５１、５２、５３、５４の代りに抵抗素子を接続することができる。
（４） 空乏層用導体層３５、３６、３７の数を増減することができる。
（５） 空乏層用絶縁膜３４ａとゲ−ト絶縁膜３３とを同一工程で形成せず、ゲ−ト絶縁膜３３を独立工程で形成することができる。
（６） 溝２７はＮ+形ドレイン領域２１に達するように形成しても差し支えない。
（７） Ｎ形ドリフト領域２２をエピタキシャル成長させる代りに、Ｎ形基板にＮ+形ドレイン領域２１を拡散で形成し、Ｎ形基板の一部をドリフト領域２２とすることができる。
【図面の簡単な説明】
【図１】従来の高耐圧ＦＥＴを示す断面図である。
【図２】本発明の第１の実施形態に従うＦＥＴの半導体基板の表面の一部を示す平面図である。
【図３】第１の実施形態のＦＥＴの図２のＡ-Ａ線に相当する部分を示す断面図である。
【図４】第１の実施形態のＦＥＴの図２のＢ-Ｂ線に相当する部分を示す断面図である。
【図５】図４のツェナ−ダイオ−ドの電気的接続を示す回路図である。
【図６】図３のＦＥＴの溝を形成する前の構成を示す断面図である。
【図７】図６の基板に溝を形成した構成を示す断面図である。
【図８】溝に絶縁膜を形成したものを示す断面図である。
【図９】溝に導体層を埋設した構成を示す断面図である。
【図１０】溝の中に層間絶縁膜を形成したものを示す断面図である。
【図１１】図４のツェナ−ダイオ−ドを詳しく示す断面図である。
【図１２】第２の実施形態のＩＧＢＴを図３と同様に示す断面図である。
【図１３】第３の実施形態のＦＥＴを図３と同様に示す断面図である。
【符号の説明】
２０ 半導体基板
２１ ドレイン領域
２２ ドリフト領域
２３ ボデイ領域
２４ ソ−ス領域
２７ 溝
２９ ソ−ス電極
３１ ドレイン電極
３２ ゲ−ト電極
３３ ゲ−ト絶縁膜
３４ａ 空乏層用絶縁膜
３５、３６、 ３７ 空乏層用導体層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an insulated gate transistor having a body region formed in a columnar shape and a method for manufacturing the same.
[0002]
[Prior art]
It is well known that an insulated gate field effect transistor (hereinafter referred to as FET) is configured as shown in FIG. 1 for the purpose of achieving both high reduction in operating resistance and high breakdown voltage. This FET comprises a silicon semiconductor substrate 5 comprising an N-type drift region 1, an N + -type drain region 2, a plurality of P-type body regions 3 and a plurality of source regions 4, a drain electrode 6, a source electrode 7, a gate An electrode 8, a gate insulating film 9, a peripheral protective insulating film 10, and an interlayer insulating film 11 are provided. The body region 3, which can be called a base region or a channel formation region of the FET, has a peculiar shape and is formed in a columnar shape deep in the thickness direction of the drift region 1, and its bottom surface is the drift region 1 and the drain region 2. It has reached near the interface. When the plurality of body regions 3 are formed in a columnar shape, a drift region between the plurality of body regions 3 when a high reverse voltage is applied to the PN junction between the body region 3 and the drift region 1 during the off period of the FET. 1 is filled with the depletion layer, and the breakdown voltage is improved. In the case of the structure of FIG. 1, a relatively high breakdown voltage can be obtained even if the specific resistance of the drift region 1 is reduced to reduce the operating resistance. That is, even if the specific resistance of the drift region 1 is set to 1/3 to 1/5 of the resistivity of the drain region of a conventional standard structure FET having a shallow body region, it is standard due to the action of the depletion layer. A breakdown voltage equivalent to that of a FET having a simple structure can be obtained.
[0003]
[Problems to be solved by the invention]
Incidentally, the body region 3 in the insulated gate FET of FIG. 1 is formed by repeating well-known epitaxial growth and impurity diffusion a plurality of times. That is, a thin N-type epitaxial layer is formed on the drain region 2, and a P-type diffusion region for the body region 3 is formed by introducing a P-type impurity into the epitaxial layer. Next, a thin N-type epitaxial layer is formed so as to cover the surfaces of the N-type epitaxial layer and the P-type diffusion region, and a P-type impurity is added so as to be continuous with the previously formed lower P-type semiconductor region. Introducing the upper P-type diffusion region for the body region 3. By repeating this a plurality of times, the insulated gate field effect transistor of FIG. 1 in which the body region 3 is formed in a columnar shape extending in the thickness direction of the element can be obtained.
[0004]
However, in the insulated gate FET of FIG. 1, since it is necessary to repeat epitaxial growth and diffusion a plurality of times, the device manufacturing process is complicated and the cost is relatively high. This type of problem also occurs in IGBTs and the like.
[0005]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an insulated gate transistor having a novel structure that can solve the above-described problems and that can achieve a high level of improvement in breakdown voltage and reduction in operating resistance, and a method for manufacturing the same. It is in.
[0006]
[Means for Solving the Problems]
Next, the present invention for solving the above-described problems and achieving the above-described object will be described with reference to reference numerals indicating embodiments. The reference numerals referred to in the claims and the description of the present invention are only for helping the understanding of the present invention, and do not limit the present invention.
The invention of claim 1 is an insulated gate transistor comprising a set of cells of a plurality of insulated gate transistors, a semiconductor substrate (20) having a plurality of cell portions (19) for the plurality of cells; The first and second main electrodes (29, 31), the gate electrode (31), the gate insulating film (33), the depletion layer insulating film (34), and the depletion layer conductor layer (35) A voltage applying means,
A groove (27) is formed in the semiconductor substrate to separate the plurality of cell portions (19) from each other;
The groove (27) is formed to have an entrance on one main surface of the semiconductor substrate,
Each cell portion (19) of the semiconductor substrate has a first semiconductor region (22) of the first conductivity type disposed so as to have a surface exposed to the wall surface of the groove, and one main surface of the semiconductor substrate. And the first semiconductor region (22) and a second semiconductor region (23) of the second conductivity type having a surface exposed to the one main surface, and the one main region And a third semiconductor region (24) of the first conductivity type disposed between the surface and the second semiconductor region (23) and having a surface exposed to the one main surface. And
The second semiconductor region (23) has a channel surface exposed between the first semiconductor region (22) and the third semiconductor region (24);
The first main electrode (29) is disposed on the one main surface of the semiconductor substrate (20) and connected to the second and third semiconductor regions (23, 24) of each cell part,
The second main electrode (31) is connected to the first semiconductor region (22) directly or via another semiconductor region;
The gate insulating film (33) is disposed so as to cover the channel surface of the second semiconductor region (23),
The gate electrode (31) is disposed adjacent to the gate insulating film (33),
The depletion layer insulating film (34) is disposed adjacent to the first semiconductor region (22) exposed on the wall surface of the groove,
The depletion layer conductor layer (35) is disposed in the groove and adjacent to the depletion layer insulating film (34),
The voltage application means applies the reverse voltage to the PN junction between the first and second semiconductor regions (22, 23) and does not form a channel in the second semiconductor region. A voltage for forming a depletion layer in the semiconductor region (22) is supplied to the depletion layer conductor layer (35), the gate electrode (32), the depletion layer conductor layer (35), And a second constant voltage element connected between the depletion layer conductor layer (35) and the second main electrode (31). The present invention relates to an insulated gate transistor characterized by the following.
[0007]
Incidentally, according as shown in claim 2, further first arranged and the first semiconductor region (22) between said first semiconductor region (22) and the second main electrode (31) a fourth semiconductor region which have a high concentration of the first conductivity type impurity (21) than the concentration of conductivity type impurity, the second main electrode (31) said fourth semiconductor region (21) It is desirable to be connected to.
Further, as shown in claim 3, the first semiconductor region (22) is disposed adjacent to a main surface of the first semiconductor region (22) on the semiconductor substrate (20) side, and the first conductivity of the first semiconductor region (22) . a fourth semiconductor region which have a high concentration of the first conductivity type impurity than the concentration of the form impurity (21a), and said fourth semiconductor region (21a) and said second main electrode (31) and a disposed and has a second conductivity type fifth semiconductor region (21b) between,
The second main electrode (31a) is preferably connected to the fifth semiconductor region (21b).
According to a fourth aspect of the present invention, it is desirable that the channel surface of the second semiconductor region (23) is exposed in the groove.
Further, as shown in claim 5, Ru can expose the channel surface of the second semiconductor region (23) on said one main surface of the semiconductor substrate (20).
[0008]
【The invention's effect】
The invention of each claim of the present application has the following effects.
(1) A groove (27) is formed in the semiconductor substrate (20), and at least one depletion layer insulating film (34a) and a conductor layer (35) are disposed in the groove (27). For this reason, a depletion layer can be generated in the first semiconductor region (22) by the action of the depletion layer insulating film (34a) and the conductor layer (35) when the insulating gate type transistor is in an OFF state, and the breakdown voltage is improved. Can be achieved.
In the case where the withstand voltage may be the same as the conventional one, the resistivity of the first semiconductor region (22) is made smaller than the conventional one so that the resistance value of the first semiconductor region (22) in the ON state is smaller than the conventional one. can do.
(2) The thickness of the first semiconductor region (22) can be easily increased without a plurality of epitaxial growth steps.
(3) As a voltage application means, a first constant voltage element connected between the gate electrode (32) and the depletion conductor layer (35), the depletion conductor layer (35), and the Since it has the 2nd constant voltage element connected between the 2nd main electrodes (31), the voltage of a predetermined level can be correctly supplied to the said conductor layer for depletion layers (35) .
[0009]
[First Embodiment]
Next, an insulated gate field effect transistor according to an embodiment of the present invention will be described with reference to FIGS.
[0010]
FIG. 2 is a plan view showing a part of the surface of a semiconductor substrate 20 of a vertical insulated gate field effect transistor or FET composed of a collection of a plurality of minute FETs or cells according to the first embodiment of the present invention. 2 is a cross-sectional view showing a portion corresponding to a part of the AA line in FIG. 2 of the FET, and FIG. 4 is a cross-sectional view showing a portion corresponding to the BB line in FIG. The silicon semiconductor substrate 20 constituting this FET has a plurality of FET cell portions 19 divided into a grid pattern by grooves 27. A plurality of cell portions 19 are arranged on the N + form a drain region 21 made of N + form (first conductivity type) semiconductor as shown in FIG. Each cell portion 19 includes a drift region 22 as a first semiconductor region of N-type or first conductivity type, a body region 23 as a second semiconductor region of P-type or second conductivity type, and an N-type first semiconductor region. 3 and a source region 24 as a semiconductor region. The N + -type drain region 21 can also be called a low resistance or first drain region, and the N-type drift region can be called a high resistance or second drain region.
[0011]
The semiconductor substrate 20 has a first or one main surface 25 and a second or other main surface 26 facing each other. The grooves 27 for electrically separating the cell portions 19 are formed in a lattice shape on the first main surface 25 of the semiconductor substrate 20 as shown in FIG. The groove 27 can also be called a trench or a moat, is formed so as to surround the N + -type source region 24 in a plan view, and extends in a direction perpendicular to the first main surface 25. . As is apparent from FIG. 3, the depth of the groove 27 is deeper than the P-type body region 23 with respect to the first main surface 25. The depth of the groove 27 is shallower than the distance from the first main surface 25 to the N + -type drain region 21. Therefore, a part of the N-type drift region 22 remains between the bottom surface of the groove 27 and the N + -type drain region 21, and the N-type drift region 22 of each cell portion 19 is close to the N + -type drain region 21. It is continuous.
[0012]
A common drain region 21 for each cell portion 19 is arranged so as to be exposed on the second main surface 26 of the semiconductor substrate 20.
[0013]
The N-type drift region 22 is an N-type region formed by one epitaxial growth on the drain region 21 functioning as a substrate, and has a lower impurity concentration and a higher resistivity than the drain region 21. However, the impurity concentration of the N-type drift region 22 is lower than the impurity concentration of the drift region 1 of the conventional FET of FIG. 1, and the resistivity of the drift region 22 is 1/5 of the resistivity of the conventional FET of FIG. 1/3. The boundary between the drift region 22 and the drain region 21 is parallel to the first and second main surfaces 25 and 26 of the semiconductor substrate 20.
[0014]
The P-type body region 23 is disposed between the N-type drift region 22 and the first main surface 25. The boundary between the P-type body region 23 and the N-type drift region 22 formed by one impurity diffusion is parallel to the first and second main surfaces 25 and 26. The P-type impurity concentration in the P-type body region 23 is higher than the N-type impurity concentration in the N-type drift region 22. The body region 23 is exposed on the first main surface 25 and also on the groove 27. The channel portion 28 of the body region 23 faces the groove 27 as shown by the dotted line in FIG. That is, the surface of the channel portion 28 is exposed in the groove 27 and extends in the vertical direction from the source region 24 toward the drift region 22. The P-type body region 23 defined by the lattice-like grooves 27 is a quadrangle when viewed in plan. However, the planar shape of the body region 23 can be changed to another shape such as a circle.
[0015]
The N + -type source region 24 is formed in the P-type body region 23 by impurity diffusion. As is apparent from FIG. 2, the source region 24 has a quadrangular annular shape when viewed in plan, the upper surface is exposed at the first main surface 25 of the semiconductor substrate 20, and the bottom surface and the inner peripheral side surface are P-type body regions. 23, the outer peripheral side surface is exposed in the groove 27.
[0016]
A source electrode 29 as a first main electrode is disposed on the first main surface 25 of the semiconductor substrate 20. The source electrode 29 is made of, for example, an aluminum vapor deposition layer, and is connected to the source region 24 of each FET cell and also to the body region 23. The source electrode 29 also extends on the insulating layer 30 on the first main surface 25 of the semiconductor substrate 20 and connects the source regions 24 of the FET cells in parallel.
[0017]
For example, a drain electrode 31 as a second main electrode made of an aluminum vapor deposition layer is disposed on the second main surface 26 of the semiconductor substrate 20 and connected to the N + -type drain region 21.
[0018]
The gate electrode 32 is disposed in the groove 27. Since the groove 27 has a lattice shape when seen in a plan view, the gate electrode 32 is also formed in a lattice shape. The gate electrode 32 is made of polycrystalline silicon doped with impurities.
[0019]
The gate insulating film 33 is made of a silicon oxide film and is formed on the wall surface of the groove 27. That is, the gate insulating film 33 is formed so as to cover the exposed surface of the channel portion 28 of the body region 23 exposed in the groove 27. Therefore, the gate electrode 31 faces the channel forming portion 28, a part of the source region 24, and a part of the drift region 22 through the gate insulating film 33.
[0020]
The groove 27 is formed relatively deep by anisotropic etching to obtain a high breakdown voltage FET. In the groove 27, first, second and third depletion layer conductor layers 35, 36 and 37 made of impurity-doped polycrystalline silicon separated from each other by an insulating film 34 are provided.
[0021]
The gate electrode 32 made of impurity-doped polycrystalline silicon, and the first, second, and third depletion layer conductor layers 35, 36, and 37 are equal in width and thickness, and are arranged at equal intervals. The insulating film 34 in the groove 27 includes a depletion layer insulating film 34 a disposed on the wall surface of the groove 27 to generate a depletion layer in the N-type drift region 22, the gate electrode 32, the first, second, and third. The depletion layer conductor layers 35, 36 and 37 are formed of an interlayer insulating film 34b for separating the conductor layers 35, 36 and 37 from each other. The depletion layer insulating film 34 a continues to the gate insulating film 33.
[0022]
The first, second, and third depletion layer conductor layers 35, 36, and 37 are opposed to the N-type drift region 22 via the depletion layer insulating film 34a. The gate electrode 32, the first, second, and third depletion layer conductor layers 35, 36, and 37 are connected to the voltage application unit 40 and are applied with a lower potential than the drain electrode 31. As a result, when no drain current flows through the drift region 22, the first, second and third depletion layer conductor layers 35, 36 and 37 are depleted in the N-type drift region 22 in the same manner as a known field plate. It functions as a conductor layer for generating. Note that the gate electrode 32 also has a function of generating a depletion layer in the N-type drift region 22.
[0023]
A source connection opening 38 is provided in the insulating film 30 on the first main surface 25 of the semiconductor substrate 20, and a source electrode is provided in the source region 24 and the P-type body region 23 of each cell portion 19. 29 is connected. Although not shown in FIG. 3, as shown in FIG. 4, first, second, third and fourth Zener diodes 41 made of polycrystalline silicon are used as voltage applying means 40 on the insulating film 30. 42, 43, 44 are provided. The first to fourth Zener diodes 41 to 44 as constant voltage elements are connected to each other in series as shown in FIG. 5, and in addition to the conductors 45 and 46 at one end and the other end of the series circuit, an intermediate conductor 47, 48 and 49 are provided. To enable electrical connection between the Zener diodes 41, 42, 43, 44 and the gate electrode 32, the first, second and third depletion layer conductor layers 35, 36, 37 In addition, as shown in FIG. 4, the gate electrode 32, the first, second, and third depletion layer conductor layers 35, 36, and 37 are exposed stepwise at the periphery of the semiconductor substrate 20, and the first, Second, third, and fourth connection conductors 50, 51, 52, 53 are provided. The conductor 50 is connected to a gate signal input terminal (not shown) and to the conductor 45. The conductors 51, 52 and 53 are connected to the intermediate conductors 47, 48 and 49. A terminal conductor 46 of the Zener diode 44 is connected to the drain electrode 31. In addition, the connection between the conductors 45-49 and the conductors 50-53 is a connection by a wire or an insulating layer is provided on the conductors 50-53, a through hole reaching this insulating layer is provided, and a conductor is provided in each through hole. And this filling conductor and the conductors 45 to 49 are connected.
[0024]
Next, a method for manufacturing the FET shown in FIGS. 2 to 5 will be described with reference to FIGS.
First, as shown in FIG. 6, an N-type silicon semiconductor substrate 20 as a drift region 22 is prepared, and a body region 23 is formed by diffusing P-type impurities on one main surface thereof. A plurality of source regions 24 are formed by diffusing N-type impurities. The source region 24 is formed so as to include a portion removed by the groove 27 in the step of FIG. Further, a drain region 21 is formed by diffusing N-type impurities on the other main surface of the N-type semiconductor substrate 20. The body region 23 and the source region 24 can also be formed after the step of forming the groove 27 in FIG.
[0025]
Next, as shown in FIG. 7, a trench groove is formed on the first main surface 25 of the semiconductor substrate 20 by a known different direction etching method in which the etching rate in the vertical direction on one main surface 25 is higher than the etching rate in the horizontal direction. 27 is formed. Since the groove 27 is formed so as to divide the source region 24 in FIG. 6, the side surface of the source region 24 can be reliably exposed to the groove 27.
[0026]
Next, a heat treatment is performed on the semiconductor substrate 20 of FIG. 7 to form an insulating film 60 made of a silicon oxide film on the bottom and wall surfaces of the trench groove 27 as shown in FIG. The upper surface of the insulating film 60 functions as the gate insulating film 33, and the lower portion functions as the depletion layer insulating film 34a. At this time, an insulating film is also formed on the main surfaces 25 and 26 of the semiconductor substrate 20, but these are not shown.
[0027]
Next, as shown in FIG. 9, polycrystalline silicon 37 a doped with donor impurities or acceptor impurities is buried in the trench groove 27. At this time, polycrystalline silicon is also formed on one main surface 25 of the semiconductor substrate 20, but this illustration is omitted.
[0028]
Next, as shown in FIG. 10, the polycrystalline silicon 37 a embedded in the trench groove 27 is etched to a desired thickness to form a third conductor layer 37.
Next, a conductor layer isolation insulating film 34b made of a silicon oxide film is formed on the upper surface of the third conductor layer 37 by thermal oxidation. Accordingly, the conductor layer 37 is electrically separated from the adjacent conductor layer 36 by the isolation insulating film 34 formed by a combination of the depletion layer insulating film 34a and the interlayer insulating film 34b.
[0029]
Next, a polycrystalline silicon film doped with donor impurities or acceptor impurities is buried again in the trench groove 27, and then etched to a desired thickness to form a second conductor layer.
[0030]
Thereafter, this process is repeated to form the third conductor layer 35 and the gate electrode 31 by the same method as the second and third conductor layers 37 and 37.
[0031]
Thereafter, an insulating film 30 made of a silicon oxide film is formed on one main surface 25 of the semiconductor substrate 20, and Zener diodes 41 to 44 are formed on the insulating film 30 as shown in FIG. . Zener diodes 41 to 44 form a polycrystalline silicon layer 61, provided with a plurality of P-type regions and N-type regions, and further, terminal conductor layers 45, 46 and intermediate conductor layers 47, 48, 49. It is obtained by providing.
[0032]
The source electrode 24 is formed by providing a contact opening 38 in the insulating film 30 and further depositing aluminum to form a conductor layer electrically connected to the body region 23 and the source region 24 through the contact opening 38. obtain. The drain electrode 31 is obtained by evaporating aluminum on the other main surface of the semiconductor substrate 20.
[0033]
The multi-cell FET of this embodiment has the following effects.
(1) The cell portion 19 constituting the micro FET is partitioned by the groove 27, and the conductor layers 35, 36, and 37 are disposed on the wall surface of the groove 27 via the depletion layer insulating film 34a. Since a voltage is applied to the N-type drift region 22 and the N + -type drain region 21 as the first semiconductor region by the same action as the field plate in the OFF period of the FET, a chain line in FIG. As shown, a depletion layer 62 is generated, and a high breakdown voltage of the FET can be easily achieved. That is, since a thick depletion layer is formed so as to fill the N-type drift region 22 surrounded by the groove 27 when the FET is turned off, the breakdown voltage of the FET is increased. When the FET is turned on, carriers (electrons) are injected into the drift region 22 through the channel portion 28, so that the impurity concentration in the drift region 22 is equivalently reduced and depletion that interferes with the drain current flow. Layers do not occur. Further, since the resistivity of the drift region 22 is smaller than the conventional one, it is possible to reduce the resistance when the FET is on. In short, it is possible to achieve a reduction in FET operating resistance and / or a high breakdown voltage.
(2) The columnar cell portion 19 partitioned by the trench groove 27 can be easily obtained. That is, in the conventional FET shown in FIG. 1, since the body region 3 and the drift region 1 are formed by repeating multiple times of epitaxial growth and diffusion, the manufacturing process becomes complicated and the cost increases. On the other hand, in this embodiment, the columnar drift region 22 can be obtained by forming the groove 27, and the cost can be reduced.
(3) Since the body region 23 is formed by one diffusion, the channel portion 28 having a predetermined width can be obtained in advance and the device can be miniaturized.
(4) Since the groove 27 is formed so as to cross the source region 24 in FIG. 6, the side surface of the source region 24 can be surely and easily exposed to the groove 27. Further, the channel portion 28 extending in the vertical direction can be easily formed.
(5) Since the voltage is supplied to the conductor layers 35, 36 and 37 by the Zener diodes 41 to 44 as constant voltage elements, a voltage at a predetermined level can be supplied accurately.
(6) Since the Zener diodes 41 to 44 are integrated with the FET, the size and cost can be reduced.
[0034]
[Second Embodiment]
FIG. 12 shows an IGBT, that is, an insulated gate bipolar transistor according to the second embodiment, as in FIG.
The IGBT shown in FIG. 12 is obtained by adding a P + -type collector region 21b to the FET shown in FIG. Incidentally, it is disposed between the N + form regions 21a are N-type drift region 22 and the P + collector region 21b having the same function as the N + form a drain region 21 of FIG. Since FIG. 12 is an IGBT, those corresponding to the source region 24, the body region 23, and the source electrode 29 in FIG. 3 are an emitter region, a base region, and an emitter electrode in FIG. Further, the one corresponding to the drain electrode 31 in FIG. 3 is a collector electrode.
[0035]
The IGBT of FIG. 12 has the same effect as the FET of the first embodiment because it has the same structure as FIG. 3 except that it has a P + -type collector region 21b.
[0036]
[Third Embodiment]
The FET of the third embodiment shown in FIG. 13 has the same configuration as that of FIG. 3 except that the position of the gate electrode 32 of the FET of FIG. That is, in FIG. 13, the gate electrode 32 is disposed on one main surface 25 of the substrate 20 via the gate insulating film 33. Accordingly, the body region 23 is formed in an island shape in the P-type drift region 22, and the portion other than the upper surface is surrounded by the N-type drift region 22. The N + type source region 24 is formed in an island shape in the body region 23. Accordingly, the channel portion 28 of the body region 23 is disposed so as to be exposed on one main surface 25 of the substrate 20.
[0037]
Since the basic configuration of the FET of FIG. 13 is the same as that of FIG. 3, it has the same effect as the FET of FIG. In FIG. 13, an IGBT similar to the P + -type collector region 21b in FIG. 12 can be provided below the chain line shown in the drain region 21 to form an IGBT.
[0038]
[Modification]
The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.
(1) A portion corresponding to the P + -type collector region 21b shown in FIG. 12 is provided only on a part of the other main surface 26 of the substrate 20, and the N + -type region 21a and the P + -type region 21b are provided on the other main surface 26. And the electrode 31 can be connected here.
(2) An N + -type lead region, that is, a plug region that is continuous with the N + -type drain region 21 is provided so as to reach the one main surface 25 side of the substrate 20, and one main surface of the substrate 20 is connected to the N + -type drain region 21. The drain electrode 31 can be provided on the 25 side. In the case of the IGBT of FIG. 12 as well, a P + -type extraction region of the P + -type collector region 21b is formed so as to reach one main surface 25 of the substrate 20, and a collector electrode can be connected thereto.
(3) A resistance element can be connected in place of the Zener diodes 51, 52, 53, 54.
(4) The number of conductor layers 35, 36, and 37 for the depletion layer can be increased or decreased.
(5) The gate insulating film 33 can be formed in an independent process without forming the depletion layer insulating film 34a and the gate insulating film 33 in the same process.
(6) The groove 27 may be formed so as to reach the N + -type drain region 21.
(7) Instead of epitaxially growing the N-type drift region 22, an N + -type drain region 21 can be formed in the N-type substrate by diffusion, and a part of the N-type substrate can be used as the drift region 22.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a conventional high voltage FET.
FIG. 2 is a plan view showing a part of the surface of the semiconductor substrate of the FET according to the first embodiment of the present invention.
3 is a cross-sectional view showing a portion corresponding to the line AA of FIG. 2 of the FET of the first embodiment. FIG.
4 is a cross-sectional view showing a portion corresponding to the line BB of FIG. 2 of the FET of the first embodiment. FIG.
5 is a circuit diagram showing electrical connection of the Zener diode of FIG. 4. FIG.
6 is a cross-sectional view showing a configuration before forming a trench of the FET of FIG. 3;
7 is a cross-sectional view showing a configuration in which a groove is formed in the substrate of FIG. 6;
FIG. 8 is a cross-sectional view showing an insulating film formed in a groove.
FIG. 9 is a cross-sectional view showing a configuration in which a conductor layer is embedded in a groove.
FIG. 10 is a cross-sectional view showing an interlayer insulating film formed in a trench.
11 is a cross-sectional view showing the Zener diode of FIG. 4 in detail.
12 is a cross-sectional view showing the IGBT according to the second embodiment, similar to FIG.
FIG. 13 is a cross-sectional view showing the FET of the third embodiment in the same manner as in FIG.
[Explanation of symbols]
20 Semiconductor substrate 21 Drain region 22 Drift region 23 Body region 24 Source region 27 Groove 29 Source electrode 31 Drain electrode 32 Gate electrode 33 Gate insulating film 34a Depletion layer insulating films 35, 36, 37 Depletion Conductor layer for layer

Claims (5)

複数の絶縁ゲート型トランジスタのセルの集合から成る絶縁ゲート型トランジスタであって、前記複数のセルのための複数のセル部分（１９）を有する半導体基板（２０）と、第１及び第２の主電極（２９、３１）と、ゲート電極（３１）と、ゲート絶縁膜（３３）と、空乏層用絶縁膜（３４）と、空乏層用導体層（３５）と、電圧印加手段とを備え、
前記複数のセル部分（１９）を互いに分離するように前記半導体基板に溝（２７）が形成され、
前記溝（２７）は前記半導体基板の一方の主面に入口を有するように形成され、
前記半導体基板の各セル部分（１９）は、前記溝の壁面に露出する表面を有するように配置された第１導電形の第１の半導体領域（２２）と、前記半導体基板の一方の主面と前記第１の半導体領域（２２）との間に配置され且つ前記一方の主面に露出する表面を有している第２導電形の第２の半導体領域（２３）と、前記一方の主面と前記第２の半導体領域（２３）との間に配置され且つ前記一方の主面に露出する表面を有している第１導電形の第３の半導体領域（２４）とをそれぞれ備えており、
前記第２の半導体領域（２３）は前記第１の半導体領域（２２）と前記第３の半導体領域（２４）との間において露出するチャネル用表面を有し、
前記第１の主電極（２９）は前記半導体基板（２０）の前記一方の主面に配置され且つ各セル部分の前記第２及び第３の半導体領域（２３、２４）にそれぞれ接続され、
前記第２の主電極（３１）は前記第１の半導体領域（２２）に直接に又は別の半導体領域を介して接続され、
前記ゲート絶縁膜（３３）は前記第２の半導体領域（２３）の前記チャネル用表面を覆うように配置され、
前記ゲート電極（３１）は前記ゲート絶縁膜（３３）に隣接配置され、
前記空乏層用絶縁膜（３４）は前記溝の壁面に露出する前記第１の半導体領域（２２）に隣接配置され、
前記空乏層用導体層（３５）は前記溝の中に配置され且つ前記空乏層用絶縁膜（３４）に隣接配置され、
前記電圧印加手段は、前記第１及び第２の半導体領域（２２、２３）間のＰＮ接合に逆方向電圧が印加され且つ前記第２の半導体領域にチャネルが形成されていない状態において前記第１の半導体領域（２２）に空乏層を形成するための電圧を前記空乏層用導体層（３５）に供給するものであって、前記ゲート電極（３２）と前記空乏層用導体層（３５）との間に接続された第１の定電圧素子と、前記空乏層用導体層（３５）と前記第２の主電極（３１）との間に接続された第２の定電圧素子とから成ることを特徴とする絶縁ゲート型トランジスタ。An insulated gate transistor comprising a set of cells of a plurality of insulated gate transistors, comprising a semiconductor substrate (20) having a plurality of cell portions (19) for the plurality of cells, a first and a second main An electrode (29, 31), a gate electrode (31), a gate insulating film (33), a depletion layer insulating film (34), a depletion layer conductor layer (35), and a voltage applying means,
A groove (27) is formed in the semiconductor substrate to separate the plurality of cell portions (19) from each other;
The groove (27) is formed to have an entrance on one main surface of the semiconductor substrate,
Each cell portion (19) of the semiconductor substrate has a first semiconductor region (22) of the first conductivity type disposed so as to have a surface exposed to the wall surface of the groove, and one main surface of the semiconductor substrate. And the first semiconductor region (22) and a second semiconductor region (23) of the second conductivity type having a surface exposed to the one main surface, and the one main region And a third semiconductor region (24) of the first conductivity type disposed between the surface and the second semiconductor region (23) and having a surface exposed to the one main surface. And
The second semiconductor region (23) has a channel surface exposed between the first semiconductor region (22) and the third semiconductor region (24);
The first main electrode (29) is disposed on the one main surface of the semiconductor substrate (20) and connected to the second and third semiconductor regions (23, 24) of each cell part,
The second main electrode (31) is connected to the first semiconductor region (22) directly or via another semiconductor region;
The gate insulating film (33) is disposed so as to cover the channel surface of the second semiconductor region (23),
The gate electrode (31) is disposed adjacent to the gate insulating film (33),
The depletion layer insulating film (34) is disposed adjacent to the first semiconductor region (22) exposed on the wall surface of the groove,
The depletion layer conductor layer (35) is disposed in the groove and adjacent to the depletion layer insulating film (34),
The voltage application means applies the reverse voltage to the PN junction between the first and second semiconductor regions (22, 23) and does not form a channel in the second semiconductor region. A voltage for forming a depletion layer in the semiconductor region (22) is supplied to the depletion layer conductor layer (35), the gate electrode (32), the depletion layer conductor layer (35), And a second constant voltage element connected between the depletion layer conductor layer (35) and the second main electrode (31). An insulated gate transistor characterized by the above. 更に、前記第１の半導体領域（２２）と前記第２の主電極（３１）との間に配置され且つ前記第１の半導体領域（２２）の第１導電形不純物の濃度よりも高い第１導電形不純物の濃度を有している第４の半導体領域（２１）を備え、前記第２の主電極（３１）が前記第４の半導体領域（２１）に接続されていることを特徴とする請求項１記載の絶縁ゲート型トランジスタ。Furthermore, the first semiconductor region (22) and the second main electrode (31) are disposed between the first semiconductor region (22) , and the first semiconductor region (22) has a first conductivity type impurity concentration higher than the first conductivity type impurity . fourth comprising a semiconductor region (21) of which have a concentration of conductivity type impurity, and said second main electrode (31) is connected to said fourth semiconductor region (21) The insulated gate transistor according to claim 1. 更に、前記第１の半導体領域（２２）の前記半導体基板（２０）側の主面に隣接配置され且つ前記第１の半導体領域（２２）の第１導電形不純物の濃度よりも高い第１導電形不純物の濃度を有している第４の半導体領域（２１ａ）と、前記第４の半導体領域（２１ａ）と前記第２の主電極（３１）との間に配置され且つ第２の導電形を有している第５の半導体領域（２１ｂ）とを備え、
前記第２の主電極（３１ａ）は前記第５の半導体領域（２１ｂ）に接続されていることを特徴とする請求項１記載の絶縁ゲート型トランジスタ。Furthermore, the semiconductor substrate (20) side is arranged adjacent to the main surface and a first conductivity higher than the concentration of the first conductivity type impurity in said first semiconductor region (22) of said first semiconductor region (22) a fourth semiconductor region that have a concentration in the form impurity (21a), the fourth is the disposed between the semiconductor region (21a) and said second main electrode (31) and the second conductivity type and a fifth semiconductor region having a (21b),
The insulated gate transistor according to claim 1, wherein the second main electrode (31a) is connected to the fifth semiconductor region (21b). 前記第２の半導体領域（２３）の前記チャネル用表面は前記溝の中に露出していることを特徴とする請求項１又は２又は３記載の絶縁ゲート型トランジスタ。Claim 1 or 2 or 3 insulated gate transistor according possible and said exposed in said channel for surface the grooves of the second semiconductor region (23). 前記第２の半導体領域（２３）の前記チャネル用表面は前記半導体基板（２０）の一方の主面に露出していることを特徴とする請求項１又は２又は３記載の絶縁ゲート型トランジスタ。The insulated gate transistor according to claim 1 or 2, wherein said channel for surface and wherein the exposed on one main surface of said semiconductor substrate (20) of the second semiconductor region (23).
JP2002042990A 2002-02-20 2002-02-20 Insulated gate transistor Expired - Fee Related JP4009825B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002042990A JP4009825B2 (en) 2002-02-20 2002-02-20 Insulated gate transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002042990A JP4009825B2 (en) 2002-02-20 2002-02-20 Insulated gate transistor

Publications (2)

Publication Number Publication Date
JP2003243655A JP2003243655A (en) 2003-08-29
JP4009825B2 true JP4009825B2 (en) 2007-11-21

Family

ID=27782917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002042990A Expired - Fee Related JP4009825B2 (en) 2002-02-20 2002-02-20 Insulated gate transistor

Country Status (1)

Country Link
JP (1) JP4009825B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180057063A (en) * 2016-11-21 2018-05-30 현대오트론 주식회사 Power semiconductor device and method for working thereof

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4202149B2 (en) * 2003-01-28 2008-12-24 ローム株式会社 Semiconductor device and manufacturing method thereof
CN103199017B (en) * 2003-12-30 2016-08-03 飞兆半导体公司 Form buried conductive layer method, material thickness control methods, form transistor method
JP5183857B2 (en) * 2004-03-29 2013-04-17 古河電気工業株式会社 Field effect transistor and manufacturing method
DE102004021050A1 (en) * 2004-04-29 2005-11-24 Infineon Technologies Ag Field effect semiconductor device, e.g. depletion trench gate FET, has p-type region embedded in n-type semiconductor body near insulating layer and connected to gate electrode
DE102004029435B4 (en) 2004-06-18 2017-02-16 Infineon Technologies Ag Field plate trench transistor
DE102005041322B4 (en) * 2005-08-31 2017-03-16 Infineon Technologies Ag Trench transistor structure with field electrode assembly and manufacturing method thereof
US7521773B2 (en) * 2006-03-31 2009-04-21 Fairchild Semiconductor Corporation Power device with improved edge termination
US8093621B2 (en) 2008-12-23 2012-01-10 Power Integrations, Inc. VTS insulated gate bipolar transistor
US7871882B2 (en) 2008-12-20 2011-01-18 Power Integrations, Inc. Method of fabricating a deep trench insulated gate bipolar transistor
US8362550B2 (en) * 2011-01-20 2013-01-29 Fairchild Semiconductor Corporation Trench power MOSFET with reduced on-resistance
CN106935645B (en) * 2015-12-30 2020-07-07 节能元件控股有限公司 MOSFET power device with bottom gate
EP3624201B1 (en) * 2018-09-17 2022-11-02 Infineon Technologies Austria AG Transistor device
TW202215662A (en) * 2020-10-05 2022-04-16 美商電源整合公司 Vertical field effect transistor, field effect transistor, and cascode device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180057063A (en) * 2016-11-21 2018-05-30 현대오트론 주식회사 Power semiconductor device and method for working thereof
KR101870822B1 (en) * 2016-11-21 2018-07-20 현대오트론 주식회사 Power semiconductor device and method for working thereof

Also Published As

Publication number Publication date
JP2003243655A (en) 2003-08-29

Similar Documents

Publication Publication Date Title
CN107112358B (en) Semiconductor device and method for manufacturing semiconductor device
KR100967883B1 (en) Trench dmos device with improved drain contact
JP3356162B2 (en) Semiconductor device and manufacturing method thereof
US7714383B2 (en) Semiconductor device
JP5089284B2 (en) Semiconductor device having a space-saving edge structure
JP4932088B2 (en) Insulated gate type semiconductor device manufacturing method
KR101404906B1 (en) Lateral power devices with self-biasing electrodes
US7109110B2 (en) Method of manufacturing a superjunction device
EP3815131A1 (en) Shielded trench devices
JP4865166B2 (en) Transistor manufacturing method, diode manufacturing method
JP6668798B2 (en) Semiconductor device
US11393736B2 (en) Method of manufacturing a semiconductor device having an integrated pn diode temperature sensor
JP4009825B2 (en) Insulated gate transistor
CN110620152A (en) Trench type metal oxide semiconductor field effect transistor
JP2004064063A (en) High voltage vertical type dmos transistor, and method for producing the same
US11955540B2 (en) Semiconductor device and production method
TW202006956A (en) Power MOSFET with an integrated pseudo-Schottky diode in source contact trench
JP2011124464A (en) Semiconductor device and method for manufacturing the same
US6534830B2 (en) Low impedance VDMOS semiconductor component
CN111200008A (en) Super junction device and manufacturing method thereof
US20040108551A1 (en) Semiconductor device
JPH0548936B2 (en)
JP2004039655A (en) Semiconductor device
US11705506B2 (en) Lateral trench transistor device
EP4336561A1 (en) Insulated gate bipolar transistor with super junction structure, and preparation method therefor

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050204

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070514

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070516

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070713

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070808

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070821

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100914

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees