CN101180737B - Power semiconductor devices and methods of manufacture - Google Patents

Power semiconductor devices and methods of manufacture Download PDF

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Publication number
CN101180737B
CN101180737B CN2004800421611A CN200480042161A CN101180737B CN 101180737 B CN101180737 B CN 101180737B CN 2004800421611 A CN2004800421611 A CN 2004800421611A CN 200480042161 A CN200480042161 A CN 200480042161A CN 101180737 B CN101180737 B CN 101180737B
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China
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groove
semiconductor device
electric charge
grid
layer
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CN101180737A (en
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阿肖克·沙拉
艾伦·埃尔班霍威
克里斯托弗·B·科康
史蒂文·P·萨普
彼得·H·威尔逊
巴巴克·S·萨尼
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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Abstract

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Description

Power semiconductor and manufacture method
The cross reference of related application
The application requires the priority of the U.S. Patent application of following interim submission:
People's titles such as submission on December 30 in 2003, Challa are " PowerSemiconductor Devices and Methods of Manufacture " the 60/533rd, No. 790;
The application is the part continuity of the U.S. Patent application of following common transfer:
People's titles such as submission on August 14 in 2003, Kocon are " Improved MOSGating Method for Reduced Miller Capacitance and Switching Losses " the 10/640th, No. 742;
Submission on May 20th, 2003, Herrick title are " Structure and Method forForming a Trench MOSFET Having Self-Aigned Features " the 10/442nd, No. 670.
The application is relevant with the U.S. Patent application of following common transfer:
People's titles such as submission on May 24 in 2002, MO are " Field Effect Transistorand Methods of its Manufacture " the 10/155th, No. 554;
Submission on July 30th, 2002, Sapp title are the No.10 of " Dual Trench PowerMOSFET ", 209, No. 110;
Submission on October 17 calendar year 2001, Kocon title are " Semiconductor Structurewith Improved Smaller Forward Loss and Higher Blocking Capability " the 09/981st, No. 583;
Submission on January 30 calendar year 2001, Marchant title are " Field Effect TransistorHaving a Lateral Depletion Structure " the 09/774th, No. 780;
People's titles such as submission on July 18 in 2002, Sapp are " Vertical ChangeControl Semiconductor Device with Low Output Capacitance " the 10/200th, No. 056;
People's titles such as submission on November 5 in 2002, Kocon are " Drift Region HigherBlocking Lower Forward Voltage Drop Semiconductor Structure " the 10/288th, No. 982;
Submission on December 10th, 2002, Yedinak title are " Method of Isolating theCurrent Sense on Planar or Trench Stripe Power Devices whileMaintaining a Continuous Stripe Cell " the 10/315th, No. 719;
Submission on August 16th, 2002, Elbanhawy title are " Methods and Circuitfor Reducing Losses in DC-DC Converters " the 10/222nd, No. 481;
Submission on September 4th, 2002, Joshi title are " Unmolded Package for aSemiconductor device " the 10/235th, No. 249; And
People's titles such as submission on June 27 in 2003, Joshi are " Flip Chip in LeadedMolded Package and Method of Manufacture Thereof " the 10/607th, No. 633.
The full content of above-mentioned application is hereby expressly incorporated by reference.
Technical field
On the whole, the present invention relates to semiconductor device, specifically, relate to, comprise the various embodiment that encapsulate and be combined with the circuit of power semiconductor about improved power semiconductor (for example, transistor and diode) and manufacture method thereof.
Background technology
Critical component in the power semiconductor is solid-state switch (solid state switch).To the IGNITION CONTROL of battery-operated consumer electronic devices, the power transfer in the commercial Application all needs to satisfy most the power switch of application-specific needs from automatic application.Sustainable development comprises that the solid state switch such as power metal oxide semiconductor field-effect transistor (power MOSFET), insulated gate bipolar transistor (IGBT) and various types of thyratrons addresses that need.For example, under the situation of power MOSFET, in many other technologies, developed have lateral channel double diffusion structure (DMOS) (for example, people's such as Blanchard the United States Patent (USP) the 4th, 682 of (lateral channel), No. 405), structure (for example for trench gate (trenched gate), No. the 6th, 429,481, people's such as Mo United States Patent (USP)), and the various technology that are used for transistor drift district charge balance (for example, the United States Patent (USP) the 4th of Temple, 941, No. 026, the 5th, 216 of Chen, No. 275, and Neilson the 6th, 081, No. 009), to satisfy different and often to serve as the demand of competition performance.
Some performance characteristics that is used to define power switch is its conducting resistance, puncture voltage and switching speed.According to the requirement of special applications, different emphasis are placed on each of these performance standards.For example, for the power application greater than about 300-400 volt, IGBT compares with power MOSFET and demonstrates intrinsic lower conducting resistance, but because its slower turn-off characteristic makes its switching speed lower.Therefore, for the low switching frequency with requirement low on-resistance greater than 400 volts application, IGBT is preferred switch, and power MOSFET often is to be used for the selected device of higher relatively frequency application.If the frequency requirement of given application is specified employed switchtype, voltage request is determined the composition structure of concrete switch so.For example, under the situation of power MOSFET, because the conducting resistance R of drain electrode-source electrode DSonAnd the proportionate relationship between the puncture voltage, make to have caused when improving the transistor voltage performance, to keep low R DSonDifficulty.The various charge balance structure of having developed in the transistor drift district solve this difficulty, and obtain success in various degree.
The device performance parameter also can be subjected to the influence of manufacturing process and tube core (die) encapsulation.Various effort have been made to solve some problem in these problems by developing various improved technologies and encapsulation technology.
No matter be in super portable consumer electronic devices or in router in communication system and the hub, various application sustainable growth of power switch along with the expansion of electronics industry.Therefore, power switch is the semiconductor device with high development potentiality.
Summary of the invention
The invention provides power device and manufacture method, encapsulation that is used for various power electronics applications and the various embodiment that are combined with the circuit of power device.Briefly, one aspect of the present invention carries out combination with the technology that many charge balance techniques and other are used to reduce parasitic capacitance, with realize having improved voltage performance, than high switching speed and than the various embodiment of the power device of low on-resistance.Another aspect of the present invention provides the improvement terminal structure that is used for low and high tension apparatus (termination structure).According to other aspects of the invention, provide improving one's methods of power device manufacturing.Provide improvement by various embodiment of the present invention, for example, the formation of the formation of the formation of groove, groove inner-dielectric-ayer, mesa structure (mesa structure), be used to reduce the technology of substrate thickness concrete treatment step.According to a further aspect in the invention, the power device of charge balance will be combined on the identical tube core with current sensing elements such as the temperature of diode.Other aspects of the present invention have been improved the equivalent series resistance (ESR) or the resistance of power device, in conjunction with adjunct circuit, and provide improvement to the encapsulation of charge balance power devices on the chip identical with power device.
Below in conjunction with accompanying drawing, describe these and other aspects of the present invention in detail.
Description of drawings
Fig. 1 illustrates the sectional view of the part of exemplary n type groove (trench) power MOSFET;
Fig. 2 A illustrates the exemplary embodiment of two groove power MOSFET;
Fig. 2 B illustrates the exemplary embodiment of planar gate (planar gate) MOSFET with source shield groove structure;
Fig. 3 A illustrates the part of the exemplary embodiment of shielded gate trench power MOSFET;
Fig. 3 B illustrates the optional embodiment in conjunction with the shielded gate trench power MOSFET of the shielded gate structure of two groove structures of Fig. 2 A and Fig. 3 A;
Fig. 4 A is the simplification partial graph of the exemplary embodiment of bigrid groove power MOSFET;
Fig. 4 B illustrates in conjunction with the exemplary power MOSFET of planar double-gated electrode structure with the trench electrode that is used for vertical electric charge control;
Fig. 4 C is illustrated in the identical groove exemplary embodiment with the power MOSFET of bigrid and the combination of dhield grid technology;
Fig. 4 D and Fig. 4 E are the sectional views of optional embodiment with power MOSFET of dark body structure (deep body structure);
Fig. 4 F and Fig. 4 G illustrate the influence of ditch groove depth body structure to distributing near the equipotential line of gate electrode in the power MOSFET;
Fig. 5 A, Fig. 5 B and Fig. 5 C are the sectional views that the part of the exemplary power MOSFET with various vertical electric charge balanced structures is shown;
Fig. 6 illustrates the simplification sectional view in conjunction with the power MOSFET of exemplary vertical electric charge control structure and shielded gate structure;
Fig. 7 illustrates the simplification sectional view in conjunction with another power MOSFET of exemplary vertical electric charge control structure and double-grid structure;
Fig. 8 illustrates an example of the dhield grid power MOSFET with vertical electric charge control structure and integrated schottky diode;
Fig. 9 A, Fig. 9 B and Fig. 9 C illustrate the various exemplary embodiments of the power MOSFET with integrated schottky diode;
The exemplary layout that Fig. 9 D, Fig. 9 E and Fig. 9 F illustrate the Schottky diode unit that intersperses in the active cell array (active cell array) that is used at power MOSFET changes;
Figure 10 illustrates and has the diode of burying the simplification sectional view of the exemplary groove type power MOSFET of (buried diode claims to embed diode again) charge balance structure;
Figure 11 and Figure 12 illustrate respectively dhield grid and double-grid structure and bury the exemplary embodiment of the power MOSFET that diode electric charge junction at equilibrium closes;
Figure 13 is in conjunction with the simplification sectional view of burying the exemplary planar power MOSFET of diode electric charge balancing technique and integrated schottky diode;
Figure 14 illustrates has the alternately simplified embodiment of exemplary accumulation mode (accumulation-mode) power transistor of conduction region that be arranged in parallel with electric current;
Figure 15 is the reduced graph with another accumulation mode device of the trench electrode that is used for the electric charge expansion;
Figure 16 is the reduced graph of exemplary pair of groove accumulation mode device;
Figure 17 and Figure 18 illustrate other simplified embodiments of exemplary accumulation mode device of groove of the filled dielectric material of the outer liner (exterior liner) with opposite polarity;
Figure 19 is to use one or more another simplified embodiments of burying the accumulation mode device of diode;
Figure 20 is the transistorized simplification isometric view of exemplary accumulation mode that comprises heavy doping opposite polarity district along the surface of silicon;
Figure 21 is illustrated in has the alternately simplified example of super junction (super-junction the claims super junction again) power MOSFET in opposite polarity district in the voltage sustaining layer;
Figure 22 is illustrated in the exemplary embodiment that vertical direction in the voltage sustaining layer has the super junction power MOSFET on the opposite polarity island that disunity separates;
Figure 23 and Figure 24 illustrate the exemplary embodiment of the super junction power MOSFET with bigrid and shielded gate structure respectively;
Figure 25 A illustrates the top view of the active of trench transistor and terminal trenches layout;
Figure 25 B to 25F illustrates the simplified layout diagram of the optional embodiment of groove terminal structure;
Figure 26 A to 26C is the sectional view of exemplary groove terminal structure;
Figure 27 illustrates the exemplary means of the terminal trenches with larger radius of curvature;
Figure 28 A to 28D is the sectional view with termination environment of silicon post (silicon pillar) charge balance structure;
Figure 29 A to 29C is to use the sectional view of exemplary embodiment of the superhigh pressure device of super junction technology;
Figure 30 A illustrates the example of the EDGE CONTACT (edge contacting) of trench device;
Figure 30 B to 30F is illustrated in the illustrative processes step of the EDGE CONTACT structure that forms trench device;
Figure 31 A is a plurality of examples of burying active area contact (activearea contact) structure of polysilicon layer (poly layer);
Figure 31 B to 31M illustrates the exemplary process flow of the active area shielding contact structures that are used to form groove;
Figure 31 N is the sectional view of the optional embodiment of active area shielding contact structures;
Figure 32 A and Figure 32 B are the layouts with exemplary trench device of active area shielding contact structures;
Figure 32 C to 32D is used for the feasible simplified layout diagram that touches two embodiment of the groove periphery with the trench device that interrupts groove structure;
Figure 33 A is the optional embodiment that is used to contact the plough groove type shielding polysilicon layer in the active area;
Figure 33 B to 33M illustrates the example of the technological process of the active area shielding construction that is used for type shown in the hookup 33A;
Figure 34 illustrate have separator (spacer) or the buffering (potential barrier) layer to reduce the epitaxial loayer of extension drift region (epi drift region) thickness;
Figure 35 illustrates the optional embodiment of the device with barrier layer;
Figure 36 illustrates in order to minimize the barrier layer of epitaxy layer thickness in dark body-epitaxy junction place use;
Figure 37 is to use the simplified example of the transistorized trap-drift region knot of diffusion barrier layer;
Figure 38 A to 38D illustrates the simplification technology of the example of the self-Aligned Epitaxial-trap trench device with buried electrodes;
Figure 39 A to 39B illustrates the exemplary process flow that the angle trap injects;
Figure 40 A to 40E illustrates the example of self-Aligned Epitaxial trap technology;
Figure 40 R to 40U illustrates the method that reduces substrate thickness;
Figure 41 illustrates and uses the example of chemical technology as the technological process of last attenuate (thinning) step;
Figure 42 A to 42F illustrates the example of improved etch process;
Figure 43 A and Figure 43 B illustrate the embodiment of the groove etching process of eliminating the beak problem;
Figure 44 A and Figure 44 B illustrate optional etch processes;
Figure 45 A to 45C illustrates the technology that forms (inter-poly) dielectric layer between improved polysilicon layer;
Figure 46 A, 46B and 46C illustrate the optional method that forms the IPD layer;
Figure 47 A and Figure 47 B are the sectional views that forms the another kind of method of high-quality polysilicon interlayer dielectric layer;
Figure 48 and Figure 49 A to 49D illustrate other embodiment that are used to form improved IPD layer;
Figure 50 A illustrates the anisotropic plasma etch process that is used for the IPD complanation;
Figure 50 B illustrates the optional IPD method of planarizing that uses chemical machinery technology;
Figure 51 is the flow chart that is used for the illustrative methods of controlled oxidation speed;
Figure 52 illustrates and is used to use low pressure chemical vapor deposition to handle improving one's methods at channel bottom formation thick oxide layer;
Figure 53 is used to use directed tetraethoxysilane (Tetraethoxyorthsilicate) technology to form the exemplary process diagram of thick oxide layer at channel bottom;
Figure 54 and Figure 55 illustrate another embodiment that is used to form thick bottom oxidization layer;
Figure 56 to 59 illustrates another technology that is used for forming at channel bottom thick dielectric layer;
Figure 60 is the reduced graph with MOSFET of induction by current device;
Figure 61 A is the example with charge balance MOSFET of planar gate and separate current induction structure;
Figure 61 B illustrates induction by current device and the integrated example of groove MOSFET;
Figure 62 A to 62C illustrates the optional embodiment of the MOSFET with series connection temperature sense diode;
Figure 63 A and Figure 63 B illustrate the optional embodiment of the MOSFET with esd protection;
Figure 64 A to 64D illustrates the example of esd protection circuit;
Figure 65 illustrates the illustrative processes that is used to form the charge balance power devices with low ESR;
Figure 66 A and Figure 66 B illustrate the topology that reduces ESR;
Figure 67 illustrates the DC-DC converter circuit that uses power switch;
Figure 68 illustrates another DC-DC converter circuit that uses power switch;
Figure 69 illustrates the exemplary driver circuits of bigrid MOSFET;
Figure 70 A illustrates the optional embodiment of the driving gate electrode with separation;
Figure 70 B illustrates the sequential chart of the circuit operation of key diagram 70A;
Figure 71 is the simplification sectional view of molded package; And
Figure 72 is the simplification sectional view of not molded package.
Embodiment
Mains switch can be by any realization the in power MOSFET, IGBT, the various types of thyristors etc.For illustrative purposes, many new technologies of this paper appearance are described under the condition of power MOSFET.Yet, should be appreciated that, various embodiment of the present invention as herein described are not limited to MOSFET, but can be applied to for example comprise the double-pole switch of IGBT, other types, various types of thyristor and diode in the power switch technology of many other types.Further, for illustrative purposes, the of the present invention various embodiment that illustrate comprise concrete p and n type district.Those skilled in the art should understand, and technology herein can be applied in the opposite device of the conductivity in each district equally.
With reference to Fig. 1, show the partial cross section figure of exemplary n type groove power MOSFET 100.Other views should be understood that the relative size of various elements shown in the figure and parts and size directly do not reflect actual size as described herein, only are to be used for illustrative purposes.Groove MOSFET 100 is included in the gate electrode that forms in the groove 102, and wherein, groove 102 begins to pass p type trap or body region (body region) 104 extensions from the upper surface of substrate, terminates in drift of n type or the epitaxial region 106.Along groove 102 thin dielectric layer 108 is set, and groove 102 is filled by electric conducting material 110 (for example, doped polycrystalline silicon) substantially.In the body region 104 that is adjacent to groove 102, form n type source area 112.Form the drain terminal of MOSFET 100 at the substrate rear side that is connected to heavy doping n+ substrate zone 114.On by the common substrate of making such as silicon, repeatedly repeat structure shown in Figure 1, to form transistor array.This array can be configured to various netted (cellular) known in the art or striated structure.When transistor turns, between source area 112 and drift region 106, form conducting channel along gate trench 102 sidewalls.
Because its vertical gate structure, when comparing with the planar gate device, MOSFET 100 can realize high packaging density, and higher packaging density can realize relatively low conducting resistance.In order to improve this transistorized breakdown voltage property, in p-trap 104, form p+ heavy doping body region 118, make formation abrupt junction at the interface between heavily doped body region 118 of p+ and p-trap 104.By control the degree of depth of p+ heavy doping body region 118 with respect to the degree of depth of gash depth and trap, make the electric field that when transistor is applied voltage, produces from groove, disappear.So just increased transistorized avalanche current disposal ability.To the variation of this improvement structure be used to form transistorized technology, especially abrupt junction and describe in detail in No. the 6th, 429,481, United States Patent (USP) that people such as Mo have, its full content is hereby expressly incorporated by reference.
Although vertical trench MOSFET 100 demonstrates the good conducting resistance and the durability of improvement, it has higher relatively input capacitance.The input capacitance of groove MOSFET 100 comprises two parts: the gate-to-source capacitor C GsWith the gate-to-drain capacitor C GdThe gate-to-source capacitor C GsProduce by grid conducting material 110 with near the stack between the source area 112 at groove top.The electric capacity that forms between the reverse raceway groove in grid and the main body can increase C equally Gs, this is because in typical power switch was used, transistorized main body was in the same place with the source electric pole short circuit.The gate-to-drain capacitor C GdProduce by the grid conducting material 110 of each channel bottom and the stack that is connected between the drift region 106 of drain electrode.The gate-to-drain capacitor C Gd, or Miller capacitance restriction rein in transistorized V DSTransit time.Therefore, higher C GsAnd C GdCaused considerable switching loss.These switching losses are along with power management application becomes increasing near higher switching frequency.
Reduce the gate-to-source capacitor C GsA kind of method be to reduce transistorized channel length.Short channel length directly reduces C GsGrid-raceway groove component.Than short channel length also just in time with R DSonProportional, and can have the identical device current amount of acquisition under the situation of less gate trench.So just by reducing gate-to-source and gate-to-drain stack amount has reduced C simultaneously GsAnd C GdYet when being deep into body region owing to back-biased main body-drain junction and forming depletion layer near source area, short channel length makes that device is fragile and causes break-through (punch through).Reduce the doping content of drift region, make and to keep wideer depletion layer and have the transistor conduct resistance of increasing R DSonThe effect of not expecting.
Use improves transistor arrangement with additional " shielding " groove of gate trench lateral separation, has not only reduced channel length, and has solved above-mentioned shortcoming effectively.With reference to Fig. 2 A, show the exemplary embodiment of two groove MOSFETs 200.Term " two groove " is meant the transistor that has with two kinds of total relative dissimilar grooves of similar groove.Except with the common architectural feature of the MOSFET 100 of Fig. 1, two groove MOSFETs 200 comprise the shield trenches 220 that is interposed between the neighboring gates groove 202.In the exemplary embodiment shown in Fig. 2 A, shield trenches 220 is passed p+ district 218 from the surface, body region 204 extends into drift region 206, fully is lower than the degree of depth of gate trench 202.Be provided with dielectric material 222 along groove 220, and with groove 220 basic electric conducting materials 224 of filling such as doped polycrystalline silicon.Metal level 216 is electrically connected to n+ source area 212 and heavy doping p+ body region 218 with the electric conducting material 224 in the groove 220.Therefore, in this embodiment, groove 220 can be called the source shield groove.U.S. Patent application the 10/209th at the common transfer that is entitled as " Dual Trench Power MOSFET " of Steven Sapp, the example, manufacturing process of describing such pair of groove MOSFET in No. 110 in detail with and circuit application, its full content is hereby expressly incorporated by reference.
The influence of darker source shield groove 220 is to make because the depletion layer that back-biased main body-drain junction forms is deep in the drift region 206 more.Therefore, the depletion region of broad can be so that do not increase electric field.This just allows heavy doping drift region more, and don't can reduce puncture voltage.More heavily doped drift region has reduced transistorized conducting resistance.In addition, near the electric field that reduces main body-drain junction makes channel length fully reduce, and further reduces transistorized conducting resistance, and fully reduces the gate-to-source capacitor C GsIn addition, compare with MOSFET among Fig. 1, two groove MOSFETs make it possible to obtain identical transistor current amount under the gate trench situation that has still less.Gate-to-source and gate-to-drain overlap capacitance have been reduced so significantly.Notice that in the exemplary embodiment shown in Fig. 2 A, gate trench conductive layer 210 is buried in the groove of eliminating interlayer dielectric dome (dome) needs, wherein, above the groove 102 of interlayer dielectric dome in MOSFET 100 shown in Figure 1.Equally, the use of source shield groove as an illustration here is not limited to trench gate mosfet, can obtain identical advantage when the source shield groove used in time in the planar MOSFET of level formation grid on the upper surface at substrate.In the exemplary embodiment that has the planar gate MOSFET of source shield groove structure shown in Fig. 2 B.
In order further to reduce input capacitance, can carry out additional structure and improve, focus on reducing the gate-to-drain capacitor C GdAs mentioned above, gate-to-drain capacitor C GdBe to produce by stack between the drain region of grid and channel bottom.A kind of method that reduces this electric capacity is the thickness that increases the gate dielectric of channel bottom.Again with reference to Fig. 2 A, illustrate with the dielectric layer along gate trench sidewalls and compare, gate trench 202 exists the channel bottom of stack to have thicker dielectric layer 226 with drift region 206 (transistor drain terminal).Reduced the gate-to-drain capacitor C like this Gd, but do not reduce transistorized forward conduction.Can be implemented in the gate trench bottom with many methods and generate thicker dielectric layer.Described an illustrative processes that is used to generate thicker dielectric layer in No. the 6th, 437,386, people's such as Hurst the total United States Patent (USP), its full content is hereby expressly incorporated by reference.The back 56 to 59 further describes other technologies that are used for forming at channel bottom thick dielectric layer in conjunction with the accompanying drawings.Reduce second dielectric core (core) of the another kind of method of grid-capacitance of drain for the setting of center in the upwardly extending groove of suprabasil dielectric liner from groove.In one embodiment, second dielectric core can extend upward from all directions, with the dielectric layer above the contact trench electric conducting material 210.The example of this embodiment and its change is described in detail in No. the 6th, 573,560, the total United States Patent (USP) of Shenoy.
Be used to reduce the gate-to-drain capacitor C GdAnother kind of technology relate to and use one or more bias electrodes to come dhield grid.According to this embodiment, in gate trench and below the electric conducting material that forms gate electrode, form one or more electrodes grid and drift region shielding are come, thereby fully reduced the gate-to-drain overlap capacitance.With reference to Fig. 3 A, show the part of the exemplary embodiment of shielded gate trench MOSFET 300A.In this example, the groove 302 among the MOSFET 300A comprises gate electrode 310 and two supplemantary electrode 311a below gate electrode 310 and 311b.Electrode 311a and 311b shield grid electrode 310 make it not have any substantial stack with drift region 306, thereby have almost eliminated the gate-to-drain overlap capacitance.Bucking electrode 311a and 311b can independently setover at best current potential.In one embodiment, can equally with source terminal setover for one of bucking electrode 311a and 311b at the same potential place.Similar with two groove structures, the biasing of bucking electrode can help to widen the depletion region that forms at main body-drain junction place equally, has further reduced C GdShould be understood that can be according to switch application, and especially the voltage request of Ying Yonging changes the number of bucking electrode 311.Similarly, the size of the bucking electrode in given groove also can change.For example, bucking electrode 311a can be greater than bucking electrode 311b.In one embodiment, minimum bucking electrode is near channel bottom, and remaining bucking electrode increases gradually along with moving closer to gate electrode.The electrode of independent biasing can also be used for vertical electric charge control in the groove, to improve less forward voltage loss and higher blocking-up (blocking) ability.With this aspect of the transistor arrangement that further describes in conjunction with high tension apparatus in the back also at the U.S. Patent application the 09/981st of the common transfer that is entitled as " Semiconductor Structure with Improved SmallerForward Loss and Higher Blocking Capability " of Kocon, describe in detail in No. 583, its full content is hereby expressly incorporated by reference.
Fig. 3 B illustrates the optional embodiment with the shielded gate trench MOSFET 300B of the shielded gate structure combination of the two groove structures among Fig. 2 A and Fig. 3 A.In the exemplary embodiment shown in Fig. 3 B, similar with the groove 302 of MOSFET 300A, gate trench 301 comprises the gate electrode 310 above the bucking electrode 311.Yet for the purpose of vertical electric charge control, MOSFET 300B comprises the non-gate trench 301 that can be deeper than gate trench 302.Shown in Fig. 2 A, when electric charge control groove 301 can have electric conducting material (for example, the polysilicon) individual layer that connects source metal at the groove top, the embodiment among Fig. 3 B used a plurality of polysilicon electrodes that can independently setover 313 that pile up.The number of the electrode 313 that piles up in groove can change according to application need, also can be the size of the electrode 313 shown in Fig. 3 B.Electrode can independently setover or be electrically connected to together.The number of the electric charge control groove in the device depends on this application equally.
The another technology that is used to improve power mosfet switch speed reduces the gate-to-drain capacitor C by using double-grid structure GdAccording to this embodiment, the grid structure separated into two parts in the groove: first is used to carry out traditional gate electrode function of receiving key signal, and second portion comes first grid part and the shielding of drift (drain electrode) district, and can independently setover.So just reduced the gate-to-drain electric capacity of MOSFET significantly.Fig. 4 A is the simplification partial graph of the exemplary embodiment of bigrid groove MOSFET 400A.Shown in Fig. 4 A, the grid of MOSFET 400A has two part G1 and G2.Be different from the bucking electrode (311a and 311b) among the MOSFET 300A of Fig. 3 A, the electric conducting material that forms G2 among the MOSFET 400A has the district 401 with the ditch trace-stacking, therefore as gate terminal.Yet this time gate terminal G2 is independent of main grid gate terminal G1 biasing, and does not receive the transistorized same signal of driving switch.On the contrary, in an embodiment example, G2 only greater than the constant potential upper offset of MOSFET threshold voltage, with the raceway groove in the counter-rotating stack district 401.To guarantee like this when when inferior grid G 2 is transformed into main grid utmost point G1, forming continuous raceway groove.In addition, because the current potential at G2 place is higher than source potential, reduced C Gd, and the electric charge transfer from the drift region to inferior grid G 2 also helps to reduce C GdIn another embodiment, replace constant potential, inferior grid G 2 can be biased to the current potential that is higher than threshold voltage only before switch motion.In other embodiments, the current potential at G2 place can change and carry out optimal adjustment, with the gate-to-drain capacitor C GdAny marginal portion minimize.Double-grid structure can use at the MOSFET with planar gate and comprise in the trench-gate power devices of other types of IGBT etc.To the change of bigrid groove MOS gated device be used to make the U.S. Patent application 10/640th of the technology of such device at people's such as Kocon the common transfer that is entitled as " Improved MOS Gating Method for Reduced Miller Capacitance andSwitching Losses ", describe in detail in No. 742, its full content is hereby expressly incorporated by reference.
Another embodiment of improved power MOSFET has been shown in Fig. 4 B, and wherein, exemplary MOSFET 400B combines planar gate and is used for the bucking electrode of vertical electric charge control.Main grid gate terminal G1 and time gate terminal G2 with the similar mode effect of the groove double-grid structure of Fig. 4 A, deep trench 420 is provided with electrode in the drift region, with the expansion electric charge and increase the puncture voltage of device.In the illustrated embodiment, shielding or inferior grid G 2 are superimposed with the top of main grid utmost point G1, and extend on p trap 404 and drift region 406.In optional embodiment, main grid utmost point G1 extends on shielding/time grid G 2.
Can be in conjunction with various technology described so far, for example grid cover and be used for the trench electrode of vertical electric charge control is to obtain for the optimized power device of given performance characteristics (comprising laterally and vertical MOSFET, IGBT, diode etc.).For example, the groove double-grid structure shown in Fig. 4 A can combine with the vertical electric charge control groove structure of type shown in Fig. 3 B or the 4B easily.Such device comprises the active groove with the double-grid structure shown in Fig. 4 A, and the darker electric charge control groove of being filled by electric conducting material individual layer (as the groove among Fig. 4 B) or a plurality of conductive electrode that piles up (as the groove among Fig. 3 B 301) substantially.Transversal device (that is, the electric current lateral flow) on the same similar face that is positioned at substrate with source terminal of drain terminal replaces piling up in vertical trench, and the charge control electrode horizontally set forms field plate (field plate).The direction that electric current flows in the directed general and drift region of charge control electrode is parallel.
In one embodiment, in identical groove in conjunction with bigrid and dhield grid technology, to increase switching speed and blocking voltage.Fig. 4 C illustrates MOSFET 400C, wherein, and the main grid utmost point G1, inferior grid G 2 and the screen 411 that pile up in the single groove shown in groove 402C is included in.It is very dark that groove 402C can do, and can comprise and the as many screen 411 of application requirements.The same trench that use is used for charge balance and bucking electrode can realize higher density, because it has been eliminated the needs of two grooves and they are combined into one.It can also realize more current expansion, and improves the conducting resistance of device.
So far described device uses the combination of dhield grid, bigrid and other technologies to reduce parasitic capacitance.Yet because edge effect, these technology can not be fully with the gate-to-drain capacitor C GdMinimize.With reference to Fig. 4 D, show the partial cross section figure of the exemplary embodiment of the MOSFET400D with dark body design.According to this embodiment, main body (body) structure forms by groove 418, and wherein, groove 418 carries out etching by table top (mesa) center of formation between gate trench 402, and extends to the same with gate trench 402 dark or be deeper than the position of gate trench 402.Source metal shown in main body groove 418 is filled.Source metal can comprise thin refractory metal on metal diffusing boundary face (not shown).In this embodiment, agent structure also comprises basic p+ main body injection knot 419 around main body groove 418.P+ injects knot 419 to make and realizes additional mask, to change in the device especially the Potential distribution near gate electrode.In the optional embodiment shown in Fig. 4 E, for example, main body groove 418 uses for example selective epitaxy growth (SEG) to deposit and fills epitaxial material substantially.Alternatively, the main body groove 418 basic doped polycrystalline silicon of filling.In any one of this two embodiment, replace injecting p+ shielding knot 419, but in Temperature Treatment subsequently with alloy from the main diffusion of filling to silicon, to form p+ shielding knot 419.Described many variation and formation for the groove agent structure in the United States Patent (USP) of the common transfer of Huang the 6th, 437, No. 399 and the 6th, 110, No. 799, its full content is hereby expressly incorporated by reference.
In the embodiment shown in Fig. 4 D and the 4E, the distance L between control gate trench 402 and the main body groove 418 and the relative depth of two grooves are to minimize edge gate-to-drain electric capacity.In the embodiment of the main body groove that uses SEG or filling polysilicon, the outward flange of layer 419 and the interval between the gate trench wall can be regulated by the doping content that changes polysilicons in SEG or the main body groove 418.Fig. 4 F and 4G illustrate the influence of ditch groove depth body to distributing near the equipotential line of gate electrode in the device.For illustrative purposes, Fig. 4 F and 4G use the MOSFET with shielded gate structure.Fig. 4 F illustrates the equipotential line of the back-biased dhield grid MOSFET 400F with ditch groove depth body 418, and Fig. 4 G illustrates the equipotential line of the back-biased dhield grid MOSFET 400G with shallow body structure.When reverse bias (for example, blocking state (blocking off-state)), the contour in each device illustrates the Potential distribution in the device.White line illustrates the trap knot, and has defined the bottom of the raceway groove that is next to gate electrode.As can be seen from the figure, there are lower current potential and lower electric field to be arranged on the raceway groove and around the gate electrode of the ditch groove depth body MOSFET of Fig. 4 F 400F.This current potential that has reduced can reduce channel length, thereby reduces the total gate charge of device.For example, the degree of depth of gate trench 402 can be reduced to less than for example 0.5um, and can accomplish to be shallower than main body groove 418, and spacing L is approximately 0.5um or littler.In one exemplary embodiment, spacing L is less than 0.3um.Other advantages of this embodiment are to have reduced the gate-to-drain charge Q GdWith Miller capacitance C GdThe value of these parameters is low more, and the speed that device can be changed is fast more.Realize these improvement by reducing to appear at the current potential that is next to gate electrode.Improved structure has the very low current potential that will be converted, and the induced electricity capacitive electric current in the grid is very low.Make the faster of gate switch so again.
The ditch groove depth body structure of describing in conjunction with Fig. 4 D and 4E can with other charge balance techniques (for example, dhield grid or double-grid structure) combination, further improve switching speed, conducting resistance and the blocking ability of device.
Produce the reinforcement switch element of the power electronics applications that is used for relatively low voltage by improvement that above-mentioned power device provided and change thereof.Low-voltage used herein for example is meant that about 30 volts-40 volts and following voltage range can be according to specifically being used for changing this scope.The application of requirement blocking voltage on this scope, need be carried out the structural modification of some types to power transistor substantially.In general, keep higher voltage, will reduce the doping content in the power transistor drift region in order during blocking state, to make device.Yet slight drift region of mixing can cause transistor conduct resistance R DSonIncrease.Higher resistivity has directly increased the power loss of switch.Along with the new development that the semiconductor that further reduces the power device packaging density is made, it is more important that power loss just becomes.
Carry out attempting improving the conducting resistance and the power loss of device, kept high blocking voltage simultaneously.Various vertical electric charge control technologys are used in many this trials, with the big plane electric fields of vertical generation in semiconductor device.Many such device architectures have been proposed, be included in the total United States Patent (USP) the 6th that is entitled as " Field Effect Transistor Having a LateralDepletion Structure " of Marchant, 713, the horizontal depleted device that discloses in No. 813, this device is at the total U.S. Patent application the 6th of Kocon, be described in 376, No. 878, its full content is hereby expressly incorporated by reference.
Fig. 5 A illustrates the partial cross section figure of the exemplary power MOSFET 500A with planar gate.MOSFET 500A seems to have the similar structure of plane MOSFET 200B to Fig. 2 B, but different with that device aspect important at two.Replace with electric conducting material filling groove 520, the dielectric material of these trench fill material such as silicon dioxide, this device also comprise the discontinuous p of the floating type district 524 adjacent to the lateral wall separation of groove.As described in conjunction with two groove MOSFETs of Fig. 2 A, the electric conducting material (for example, polysilicon) in the source electrode groove 202 helps improve the unit puncture voltage by making depletion region go deep into the drift region.Removing electric conducting material from these grooves therefore will cause reducing puncture voltage, reduces the additive method of electric field up to use.Floating region 524 is used to reduce electric field.
With reference to the MOSFET 500A shown in Fig. 5 A, because electric field increases when increasing drain voltage, the corresponding current potential that feasible p district 524 acquisitions of floating are determined at space charge region by them.The floating potential in these p districts 524 makes electric field be deep into more in the drift region, causes more uniform field to spread all over the degree of depth of table section between the groove 520.As a result, increased transistorized puncture voltage.The advantage that substitutes the electric conducting material in the groove with insulating material is that the more parts of space charge region stride across insulator and are not possible be the drift region of silicon.Because the dielectric constant of insulator is lower than the dielectric constant such as silicon, and because the depletion region in the groove reduces, so the fan-out capability of device significantly reduces.Further like this strengthened transistorized switching characteristic.The degree of depth of the groove 520 of filled dielectric material depends on voltage request; Groove is dark more, and blocking voltage is high more.More advantages of vertical electric charge control technology are to allow transistor unit at the thermal insulation horizontally set, and do not need to increase electric capacity.In optional embodiment, the p district that replaces floating is provided with p type layer along the lateral wall of the groove of filled dielectric material, to realize similar vertical electric charge balance.At the partial cross section figure of the simplification of this embodiment shown in Fig. 5 B, wherein, the lateral wall of groove 520 is covered by p type layer or lining 526.In the exemplary embodiment, grid has further improved the mutual conductance of device equally by the ditch channelization in Fig. 5 B.Use this changes in technology the improvement power device other embodiment people such as Sapp be entitled as " Vertical Change Control Semiconductor Device with LowOutput Capacitance; " the U.S. Patent application the 10/200th of common transfer, describe in detail in detail in No. 056 (acting on behalf of case 18865-0097/17732-55280), its full content is hereby expressly incorporated by reference.
As mentioned above, the groove MOSFET 500B of Fig. 5 B demonstrates output capacitance and the improved puncture voltage that reduces.Yet, because active groove (gate trench 502) is between the electric charge control groove 520 of filled dielectric material, so the channel width of MOSFET 500B can not be the same wide with the channel width of conventional groove MOSFET structure.May cause higher conducting resistance R like this DSonWith reference to Fig. 5 C, show the optional embodiment of the groove MOSFET 500C with vertical electric charge control of having eliminated inferior electric charge control groove.Groove 502C among the MOSFET 500C comprises gate electrode 510 and deeply extends to the bottom of the filled dielectric material of drift region 506.In one embodiment, groove 502C extends to and is approximately half the degree of depth of drift region 506 degree of depth.As shown in the figure, around P type lining 526C is looped around outer wall along the bottom of each groove.This single groove structure of planting has been eliminated inferior electric charge control groove, is used to increase channel width and reduces R DSonIn order to reduce output capacitance and gate-to-drain electric capacity, the groove outer wall by p type lining 526C around the bottom of darker groove 502C keep the major part of electric field.In optional embodiment, be made into a plurality of locus of discontinuities along side and the bottom p type lining 526C of groove 502C.Can realize other embodiment by plant control of groove electric charge and above-mentioned dhield grid or dual-gate technologies in conjunction with list, further to reduce the parasitic capacitance of device.
With reference to Fig. 6, show and be suitable for the simplification sectional view that high-voltage applications also requires the power MOSFET 600 of very fast switching speed.MOSFET 600 combines the vertical electric charge control technology of improving puncture voltage and the shielded gate structure of improving switching speed.As shown in Figure 6, between the grid conducting material 610 and channel bottom of bucking electrode 611 in gate trench 602.Electrode 611 comes transistorized grid and the shielding of following drain region (drift region 606), makes significantly to have reduced transistorized gate-to-drain electric capacity, has therefore increased its maximum switching frequency.Groove 620 with filled dielectric material of p doping lining 626 helps the vertical big plane electric fields that produces, to improve the puncture voltage of device.When work, the combination and the shielded gate structure of the groove 620 of filled dielectric material and p type lining 626 have reduced parasitic capacitance, and help to exhaust the n drift region, and the electric field that focuses on the gate electrode marginal portion is disperseed.Such device can be used for the RF amplifier or HF switch is used.
Fig. 7 shows the optional embodiment of another power MOSFET that is suitable for high voltage, upper frequency application.In simplified example shown in Figure 7, MOSFET 700 combines the vertical electric charge control technology of improving puncture voltage and the double-grid structure that improves switching speed.Similar with device shown in Figure 6, the groove 720 that has the filled dielectric material of p doping lining 726 by use is realized vertical electric charge control.By using double-grid structure to realize reducing of parasitic capacitance, by time gate electrode G2 main grid electrode G1 and drain electrode (n drift region 706) shielding are come thus.For when the break-over of device, be reversed in raceway groove in the district 701 and guarantee continuous flow through the electric current of continuous raceway groove, inferior gate electrode G2 can continue biasing or only setover before switch motion.
In another embodiment, shielding vertical electric charge control MOSFET has also used the trenched side-wall of the filled dielectric material that mixes to realize integrated Schottky diode.Fig. 8 shows an example according to the dhield grid MOSFET 800 of this embodiment.In this example, the electrode 811 in groove 802 bottoms comes gate electrode 810 and drift region 806 shieldings, to reduce the gate-to-drain parasitic capacitance.The groove 820 that has the filled dielectric material of p doping lining on lateral wall is used for vertical electric charge control.Between two groove 820A of the mesa structure that forms width W and 820B, form Schottky diode 828.This Schottky diode structure spreads all over the groove MOSFET cell array, to strengthen the performance characteristics of switch mosfet.The advantage of the low barrier height by utilizing Schottky junction structure 828 reduces forward voltage drop.In addition, compare with the common PN junction of vertical power mosfet, this diode has the advantage of intrinsic reverse resume speed.By with the wall doping of the groove 820 of filled dielectric material boron for example, eliminated the sidewall leakage passage that produces owing to phosphorous segregation (phosphorus segregation).The performance that can use the characteristics of trench process to come optimization Schottky diode 828.For example, in one embodiment, regulate width W, make by the loss in the drift region of adjacent PN junction influence and control Schottky diode 828, to increase the reversal voltage ability of Schottky diode 828.Can find the example of single chip integrated groove MOSFET and Schottky diode in No. the 6th, 351,018, the United States Patent (USP) of the common transfer of Sapp, its full content is hereby expressly incorporated by reference.
Should be understood that, the Schottky diode that between the groove of filled dielectric material, forms can with various dissimilar MOSFET carry out integrated, comprise MOSFET with planar gate, channel bottom have or do not have thick dielectric without any trench-gate MOSFET of bucking electrode etc.The exemplary embodiment of the bigrid groove MOSFET with integrated schottky diode has been shown in Fig. 9 A.MOSFET 900A comprises gate trench 902, and wherein, main grid utmost point G1 formation on inferior grid G 2 is to reduce parasitic capacitance and to increase switching frequency.MOSFET 900A also comprises the groove 920 of filled dielectric material, and wherein, groove 920 has the p doping lining 926 that is used for vertical electric charge control that forms along its lateral wall, to increase the blocking voltage of device.For above-mentioned many embodiment (for example, Fig. 5 B, 6,7,8 and 9A shown in), a kind of method that forms lining is to use plasma doping technology.As shown in the figure, between the groove 920A of two adjacent filled dielectric materials and 920B, form Schottky diode 928A.In another variation instance, form single chip integrated Schottky diode and groove MOSFET, and do not have the groove of filled dielectric material.Fig. 9 B is the sectional view according to the exemplary means 900B of this embodiment.
MOSFET 900B comprises active groove 902B, and each has the electrode 911 of burying for 910 times at gate electrode.As shown in the figure, between two groove 902L and 902R, form Schottky diode 928B.The charge balance effect of bias electrode 911 makes has increased the doping content of drift region, and does not influence reverse blocking voltage.For this structure, the doping content of higher drift region has reduced forward voltage drop again.The groove MOSFET that has buried electrodes as described above, the degree of depth of each groove and the number of buried electrodes can change.In a variation instance shown in Fig. 9 C, as shown in the figure, groove 902C only has a buried electrodes 911, and the gate electrode 910S among the schottky cell 928C is connected to the source electrode.Alternatively, the grid of Schottky diode can be connected to the gate terminal of MOSFET.Fig. 9 D, 9E and 9F show the change of the exemplary layout of the Schottky diode in the active cell array that is dispersed in MOSFET.Fig. 9 D and 9E show the layout of single table surface Schottky and two table top Schottky respectively, and Fig. 9 F shows the schottky region layout vertical with the MOSFET groove.These and other of integrated schottky diode change (Schottky that comprises optional a plurality of MOSFET district) and can combine with any transistor arrangement as herein described.
In another embodiment, by use one or more series connection, be buried in the groove that is provided with dielectric material and strengthen the voltage blocking ability of power device with the diode structure that electric current in the device drift region be arranged in parallel.Figure 10 provides the simplification sectional view according to the exemplary groove MOSFET 1000 of this embodiment.Diode groove 1020 is arranged on the both sides of gate trench 1002, extends into drift region 1006 from trap.Diode groove 1020 comprises one or more diode structures of being made up of opposite conductivity type district 1023 and 1025, and wherein, conductivity type district 1023 and 1025 has formed one or more PN junctions in groove.In one embodiment, groove 1020 comprises having and opposite polarity single district, drift region, make with the interface of drift region on form single PN junction.P type and n type doped polycrystalline silicon or silicon can be respectively applied for and form district 1023 and 1025.The material of other types (for example, carborundum, GaAs, SiGe etc.) also can be used to form district 1023 and 1025.The thin dielectric layer 1021 that extends along the madial wall of groove is with diode in the groove and drift region 1006 insulation.As shown in the figure, do not have dielectric layer, therefore, allow bottom zone 1027 and following substrate to electrically contact along the bottom of groove 1020.In one embodiment, be applied in the design and formation of dielectric layer 1021 with the similar Consideration of making for those control grid oxic horizon 1008 designs.For example, the thickness of dielectric layer 1021 determines by such factor, that is, the voltage that it need keep and in the drift region induced diode groove internal electric field degree (as, by the degree of dielectric layer coupling).
In when work, as MOSFET 1000 during in its blocking state below-center offset, the peak electric field reverse bias that the PN junction utilization in the diode groove produces at each diode junction place.By dielectric layer 1021, the respective electric field in the electric field induction drift region 1006 in the diode groove.The electric field of sensing occurs in the drift region with the form of rising spike (up-swing spike), and generally increases in the electrical bending of drift region.The increase of this electric field causes the electrical bending in Geng Da district, causes higher puncture voltage again.The change of this embodiment is at the U.S. Patent application the 10/288th of people's such as Kocon the common transfer that is entitled as " Drift Region Higher Blocking Lower ForwardVoltage Drop Semiconductor Structure ", be described in detail in No. 982 (acting on behalf of case 18865-117/17732-66560), its full content is hereby expressly incorporated by reference.
Can have and to be used for the trench diode of charge balance and other embodiment of the power device of technology (for example, dhield grid or the double-grid structure) combination that reduces parasitic capacitance.Figure 11 shows an example according to the MOSFET 1100 of such embodiment.MOSFET 1100 uses the bucking electrode under the gate electrode 1,110 1111 in active groove 1102, to reduce and the transistorized gate-to-drain capacitor C relevant as the MOSFET 300A among Fig. 3 A GdCompare with MOSFET 1000, in MOSFET 1100, used the PN junction of different numbers.Figure 12 is the sectional view that combines the MOSFET 1200 of dual-gate technologies and trench diode structure.Active groove 1202 among the MOSFET 1200 comprises main grid utmost point G1 and time grid G 2, and works in the mode identical with active groove among the bigrid MOSFET that Fig. 4 B describes.Diode groove 1220 provides charge balance, increasing the blocking voltage of device, and bigrid active groove architecture advances the switching speed of device.
Figure 13 shows the another embodiment that in planar gate MOSFET 1300 the trench diode charge balance technique is combined with integrated schottky diode.By integrated schottky diode 1328 with can obtain similar advantage in conjunction with the MOSFET that describes among Fig. 8 and 9.In this embodiment, for illustrative purposes, show planar gate, it is apparent to those skilled in the art that the combination of Schottky diode and trench diode structure can be applied to have among the grid structure of any other type MOSFET of (comprising trench-gate, bigrid and dhield grid).As in conjunction with the MOSFET 400D of Fig. 4 D and Fig. 4 E and the description of 400E, any one synthetic embodiment can also combine with the groove agent technology, further to reduce the edge parasitic capacitance.Other variations also can be arranged and be equal to.For example, the number of the opposite conduction region in the diode groove can change along with the degree of depth of diode groove.The polarity of opposite conduction region can be reversed along with the polarity of MOSFET.In addition, if expectation by for example each district being extended along the third dimension, up to the silicon face that can electrically contact with them, so any PN district (923,925 or 1023,1025 etc.) all can independently setover.Further, the requirement that a plurality of diode grooves can need as the voltage by device size and application, and the interval of diode groove can be realized with various stripeds or mesh design with configuration.
In another embodiment, suppose the various charge balance techniques that are used to reduce the forward voltage loss and improve blocking ability of accumulation mode transistor-like use.Blocking-up is not tied in general accumulation mode transistor, and comes pinch-off current that device is ended by the channel region of the close gate terminal of slight counter-rotating.When by application grid bias turn-on transistor, form accumulation layer rather than inversion layer at channel region.Owing to do not form inversion channel, institute is so that the channel resistance minimum.In addition, in the accumulation mode transistor, do not have the PN body diode, make and use the loss minimum that otherwise produces in (for example, synchronous rectifier) in particular electrical circuit.The shortcoming of tradition accumulation mode device is to have to slightly mix in the drift region, to provide reverse bias during at blocking mode when device.More lightly doped drift region causes higher conducting resistance.The embodiment of Miao Shuing has overcome this restriction by use various charge balance techniques in the accumulation mode device herein.
With reference to Figure 14, show simplified embodiment with the exemplary accumulation mode transistor 1400 that replaces conduction region that be arranged in parallel with electric current.In this embodiment, transistor 1400 is the n channel transistor, comprising: the drift region 1406 and the n type drain region 1414 of gate terminal, the n type channel region 1412 that forms between groove, the column n type that comprises opposite polarity and p type part 1403 and 1405 that form in groove 1402.Be different from enhancement transistor, accumulation mode transistor 1400 does not comprise blocking-up (being the p type in this example) trap or forms the body region of raceway groove within it.On the contrary, when in district 1412, forming accumulation layer, form conducting channel.Transistor 1400 generally according to the doping type of the doping content in district 1412 and gate electrode come conducting or by.When n type district 1412 exhausts fully and slightly reverses, transistor by.Regulate the district 1403 of opposite polarity and 1405 doping content,, can make transistor keep higher voltage with the expansion of maximization electric charge.By not allowing to reduce electric field linearly, utilize the column opposite polarity district parallel to make Electric Field Distribution become mild with electric current away from the knot that forms between the district 1412 and 1406.The electric charge expansion effect of this structure allows to use the more heavily doped drift region that reduces transistor conduct resistance.The doping content in each district can change, and for example, n type district 1412 and 1403 can have identical or different doping content.Those skilled in the art should understand, and the polarity in various districts that can be by the device shown in Figure 14 that reverses obtains improved p channel transistor.The back will be described other changes in the column opposite polarity district in the drift region in conjunction with the superhigh pressure device in detail.
Figure 15 is the reduced graph with another accumulation mode device 1500 of the trench electrode that is used for the electric charge expansion.All districts 1512,1506 and 1514 have identical conduction type (being the n type in this example).For general disconnection device (off device), grid polycrystalline silicon 1510 is made the p type.The doping content of regulatory region 1512 is not there to be to form under the bias condition blocking-up knot that exhausts.In each groove 1502, under gate electrode 1510, form one or more buried electrodes 1511, by dielectric material 1508 around.As described in conjunction with the enhancement mode MOSFET 300A of Fig. 3 A, buried electrodes 1511 is as field plate, and if necessary, can be biased to and make the optimized current potential of its electric charge expanded function.Owing to can control the electric charge expansion by independent biasing buried electrodes 1511, so can increase maximum field significantly.Similar to the buried electrodes of using in MOSFET 300A, difference that can implementation structure changes.For example, can be according to the degree of depth of using change groove 1502 and the size and the number of buried electrodes.In the identical mode of groove structure of the MOSFET 300B shown in Fig. 3 B, the electric charge diffusion electrode can be buried in the groove that separates with the active groove of covering transistor gate electrode.The example of such embodiment has been shown among Figure 16.In example shown in Figure 16, n type district 1612 comprises the heavy doping n+ source area 1603 that can selectivity increases.As shown in the figure, heavy-doped source polar region 1603 can extend along the top edge in n type district 1612, or can form two district's (not shown)s adjacent to trench wall along the top edge in n type district 1612.In certain embodiments, can suitably block in order to ensure transistor, the alloy in n+ district 1603 can be lower than the doping content in n type district 1606 necessarily.This selectively can be used in any one accumulation transistor described herein the heavy-doped source polar region in an identical manner.
Transistorized another embodiment of improved accumulation mode uses the groove of the filled dielectric material with opposite polarity outer liner.Figure 17 is the simplification sectional view according to the accumulation transistor 1700 of this embodiment.The groove 1720 of filled dielectric material extends into drift region 1706 downwards from silicon trap surface.Groove 1720 basic dielectric materials of filling such as silicon dioxide.In this exemplary embodiment, transistor 1700 is the n channel transistors with trench gate structure.As shown in the figure, p type district 1726 is along the outer wall of the groove 1720 of filled dielectric material.Similar with transistor 500A, the 500B and the 500C that combine the enhancement mode that Fig. 5 A, 5B and 5C describe respectively, groove 1720 has reduced transistorized output capacitance, and the charge balance that provides in the drift region of p type lining 1726, to increase transistorized blocking ability.In optional embodiment shown in Figure 180, the lining 1826N of phase contra-doping and 1826P form at the opposite side of the groove 1820 of filled dielectric material.Just, the groove 1820 of filled dielectric material has the p type lining 1826P that extends along the lateral wall of a side, and the n type lining 1826N that extends along the lateral wall of the opposite side of same trench.As description, the various variations of the groove combination with accumulation transistor AND gate filled dielectric material can be arranged also in conjunction with corresponding enhancement transistor.For example, this comprises: the device shown in Fig. 5 A has plane (as relative with groove) grid structure and replaces the accumulation transistor in the p type of the floating district of p type lining 1726; Device shown in Fig. 5 B has the accumulation transistor that only covers lateral wall and do not have covering groove 1726 bottoms; And the device shown in Fig. 5 C, have the accumulation transistor etc. of single groove structure of the p type lining of covering groove bottom.
In another embodiment, the accumulation mode transistor uses one or more diodes that series connection forms in groove that are used for charge balance.Figure 19 shows the simplification sectional view according to the exemplary accumulation mode transistor 1900 of this embodiment.Diode groove 1920 is arranged on each side of gate trench 1902, extends into drift region 1906 from trap.Gate trench 1902 comprises one or more diode structures, and wherein, diode structure is made up of the district 1923 and 1925 of the opposite conductivity type that forms one or more PN junctions in groove.P type and n type doped polycrystalline silicon or silicon can be used to form district 1923 and 1925.The thin dielectric layer 1920 that extends along the inwall of groove makes diode and drift region 1906 insulation in the groove.As shown in the figure, do not have dielectric layer, therefore allow bottom zone 1927 and following substrate to electrically contact along the bottom of groove 1920.As be combined in the description of the corresponding enhancement transistor as shown in Figure 10,11,12 and 13, this other changes that will accumulate transistor and trench diode combination can be arranged.
Above-mentioned any one accumulation mode transistor can use heavy doping reversed polarity district in (source electrode) district at the top.Figure 20 shows this feature and changes the simplification graphics of the exemplary accumulation mode transistor 2000 that combines with other.In this embodiment, the charge balance diode in the accumulation mode transistor 2000 forms in identical groove with grid.Groove 2000 comprises gate electrode 2010, is n type 2023 and p type 2025 silicon or the polysilicon layer that forms PN junction below.Thin dielectric layer 2008 is separated diode structure and gate terminal 2002 and drift region 2006.As shown in the figure, form heavy doping p+ district 2118 in the interval of the table top length that between the groove in source area 2012, forms.Heavy doping p+ district 2118 reduces the area in n-district 2012, and reduces the leakage of device.P+ district 2118 considers that also the hole current that will improve in the snowslide contacts with the p+ that improves the device robustness.Discussed the exemplary vertical mos gate utmost point has been accumulated transistorized change, so that the various feature and advantage of this class device to be described.Those skilled in the art should understand, and these also can be realized in the device of the other types that comprise lateral MOS gridistor, diode, bipolar transistor etc.Can form the electric charge expansion electrode in the groove identical or in the groove that is separating with grid.Above-mentioned various exemplary accumulation mode transistor has the groove that stops in the drift region, but they also can terminate in the heavy doping substrate that is connected to drain electrode.Various transistors can form with striped or the network structure that comprises hexagon or foursquare transistor unit.In conjunction with described other changes of some other embodiment with in conjunction with being possible, further be described in the U.S. Patent application of some of them reference formerly the 60/506th, No. 194 and the 60/588th, No. 845, its full content is hereby expressly incorporated by reference.
Being used for extra-high pressure uses the another kind of device for power switching of (for example, 500V-600V and more than) design and uses p in the epitaxial region between substrate and trap to mix and the n doped silicon replaces vertical component.With reference to Figure 21, show the example of the MOSFET2100 that uses this kinds of structures.In MOSFET 2100, district 2102 is known as voltage sometimes and keeps or block the district, comprises alternating n-type district 2104 and p type district 2106.The effect of this structure is: when device was applied voltage, depletion region flatly was diffused into each side in district 2104 and 2106.The whole vertical thickness of barrier layer 2102 exhausted before the enough high generation avalanche breakdown of horizontal component of electric field, because the electric charge net quantity in each vertical area 2104,2106 is less than producing the required quantity of breakdown electric field.After this district flatly exhausts fully, continue vertically to set up electric field, reach every micron snowslide electric field that is approximately 20 to 30 volts up to it.So significantly strengthened the voltage blocking ability of device, with the voltage range of device expand to 400 volts or more than.The change of the difference of such super junction device is described in detail in the total patent of Nielson the 6th, 081, No. 009 and the 6th, 066, No. 878, and its full content is hereby expressly incorporated by reference.
Change to super junction MOSFET 2100 is used the p type island of floating in n type blocking-up district.The use on the p type of floating island is opposite with column method, reduces R by the thickness that reduces charge balance layers DSonIn one embodiment, replace separating equably p type island, they are by separated from one another, so that keep the electric field near critical electric field.Figure 22 is the simplification sectional view that illustrates according to the MOSFET 2200 of an example of the device of this embodiment.In this example, darker float a p district 2226 and top separate farther.Just, distance L 3 is greater than distance L 2, and distance L 2 is greater than distance L 1.By handling the distance of floating between the knot by this way, minority carrier enters in more short grained mode.The source electrode particle of these carriers is more little, just can realize lower R more DSonHigher puncture voltage.Those skilled in the art should understand, and can make many changes.For example, the number of floating region 2226 in vertical direction is not limited to four shown in the figure, and optimal number can change.In addition, the doping content of each floating region 2226 also can change, and for example, in one embodiment, the doping content of each floating region 2226 is along with the district reduces gradually near the degree of substrate 2114.
Further, as describing in conjunction with low-voltage and middle voltage devices, the many technology that are used for reducing parasitic capacitance and increase switching speed that comprise dhield grid and double-grid structure can combine with Figure 21 and 22 high tension apparatus of describing and its change.Figure 23 is the simplification sectional view that combines the high-voltage MOSFET 2300 of the change of super-junction structures and double-grid structure.MOSFET 2300 has by being similar to for example the gate terminal G1 of the double gate transistor shown in Fig. 4 B and the planar double-gated electrode structure that G2 forms.Opposite polarity (in this example for p type) district 2326 is vertically set in the n type drift region 2306 below the p trap 2308.In this example, the size in p type district 2326 is with at interval different, thereby as shown in the figure, the district 2326 that is provided with near trap 2308 contacts with each other, and setting more by under district 2326 float and size more little.Figure 24 shows the another embodiment that is used for high-voltage MOSFET 2400 of combining super knot technology and shielded gate structure.MOSFET 2400 is the trench-gate device, has the gate electrode 2410 and the bucking electrode 2411 that come with drift region 2406 shieldings, and is for example, similar with the MOSFET 300A among Fig. 3 A.MOSFET 2400 also comprise be arranged in the drift region 2406, the floating region 2426 of the opposite polarity parallel with electric current.Terminal structure
Above-mentioned various types of discrete device has by in the cylinder of the depletion region at die edge place or the puncture voltage of spherical form restriction.Because such cylinder or spherical puncture voltage are general all than the parallel plane puncture voltage BV in device active region PPMuch lower, thus need to stop the edge of device, so that reach the device electric breakdown strength that approaches the active area puncture voltage.Developed different technology and enlarged electric field and the voltage that is unified on the edge termination width, to realize near BV PPPuncture voltage.These technology comprise the different combinations of field plate, a ring, knot termination extension (JTE) and these technology.An example that comprises the field terminal structure with the dark knot (being deeper than trap) that is looped around the superimposed field oxide layer around the active cell array has been described in No. the 6th, 429,481, people's such as Mo total United States Patent (USP).For example, under the situation of n channel transistor, terminal structure comprises the dark p+ district that forms the PN junction with n type drift region.
In optional embodiment, be looped around cell array periphery one or more ring-shaped grooves on every side and be used to weaken electric field and increase avalanche breakdown.Figure 25 shows the groove layout of the common use that is used for trench transistor.Active groove 2502 by annular terminal trenches 2503 around.In this structure, the table top end by the district 2506 shown in the imaginary circle shape than other districts exhaust fast, make the electric field enhancing in this district, make under back-biased condition, to reduce puncture voltage.Therefore, such design be restricted to lower voltage devices (as,＜30V).Figure 25 B illustrates to Figure 25 F has the several optional embodiment that reduces the terminal structure of high electric field region with ditch trench patterns different shown in Figure 25 A.As can be seen from the figure, in these embodiments, some or all active grooves separate with terminal trenches.Gap W between active groove end and the terminal trenches GBe used for reducing in the observed electric field set of structure shown in Figure 25 A effect.In one exemplary embodiment, W GMake half that is approximately mesa width between the groove.For the higher voltage device, can use a plurality of terminal trenches shown in Figure 25 F, further to reduce the puncture voltage of device.The more detailed description some the change among these embodiment in No. the 6th, 683,363, the total United States Patent (USP) that is entitled as " Trench Structure for Semiconductor Devices " of Challa, its full content is incorporated into this.
Figure 26 A shows the sectional view of the exemplary groove terminal structure that is used for the charge balance groove MOSFET to Figure 26 C.In the exemplary embodiment that illustrates, MOSFET2600A uses the shielded gate structure with the polycrystalline electrodes 2611 that is buried in the shielding below the gate electrode 2610 in active groove 2602.In the embodiment shown in Figure 26 A, be provided with thicker dielectric layer (oxide layer) 2605A relatively along terminal trenches 2603A, and terminal trenches 2603A fills the electric conducting material such as electrode 2607A.Interval between the thickness of oxide layer 2605A, the degree of depth of terminal trenches 2603A and terminal trenches and the adjacent active groove (for example, the width of last table top) is determined by device reverse blocking voltage.In the embodiment shown in Figure 26 A, at the groove broad (T groove structure) of surface, metal field plate 2609A is used on the termination environment.In optional embodiment (not shown), can by the electrode 2607A in the terminal trenches 2603A is extended on the surface and the termination environment on (left end of terminal trenches in Figure 26 A) form field plate by polysilicon.Many changes can be arranged.For example, can below metal, increase the p+ district (not shown) that touches silicon and carry out ohmic contact better.P-well region 2604 in last table top of adjacent terminals groove 2603A and the contact separately between them can optionally be removed.The p type of floating district also can be increased to the left side (for example, active area is outer) of terminal trenches 2603A.
In another changes, replace filling terminal trenches 2603 with polysilicon, polysilicon electrode is buried in the groove bottom in the groove of fill oxide.Figure 26 B shows this embodiment, wherein, the only about half of fill oxide 2605B of terminal trenches 2603B, Lower Half has the polysilicon electrode 2607B that is buried in the oxide.Can handle the degree of depth of change groove 2603B and the height of buried electrodes 2607B based on device.In the another embodiment shown in Figure 26 C, terminal trenches 2603C has filled up dielectric material substantially, does not have buried conductive material therein.For three embodiment shown in Figure 26 A, B and the C, the width of last table top that terminal trenches and last active groove are separated can be different with the width of the typical table top that forms between two active grooves, and can regulate the best charge balance of realizing in the termination environment.Above-mentioned all changes in conjunction with structure shown in Figure 26 A can be applied in those structures shown in Figure 26 B and the 26C.Further, those skilled in the art should understand, and when terminal structure described herein was used for the dhield grid device, similarly structure can be to realize for the termination environment of all above-mentioned various devices based on groove.
For lower voltage devices, can not make excessive demands the turning design of groove end ring.Yet,, can expect that the fillet (rounding) at end ring turning has bigger radius of curvature for the higher voltage device.The voltage request of device is high more, and the radius of curvature at terminal trenches turning is just big more.The number of end ring also can increase along with the increase of device voltage.Figure 27 illustrates the exemplary means with two relatively large groove 2703-1 of radius of curvature and 2703-2.Can regulate interval between the groove based on the voltage request of device equally.In this embodiment, be approximately the twice of the distance between the first terminal trenches 2703-1 and the active groove end apart from S1 between terminal trenches 2703-1 and the 2703-2.
Figure 28 A, 28B, 28C and 28D show and are used for various example cross section with termination environment of silicon post charge balance structure.In the embodiment shown in Figure 28 A, each ring of field plate 2809A contact p type post 2803A.So just allow wideer table section, this is because because the lateral loss that field plate produces.Puncture voltage generally depends on the thickness of field oxide, the number of ring and the degree of depth and the interval of terminal pillar 2803A.For such terminal structure many different changes can be arranged.For example, Figure 28 B shows optional embodiment, and wherein, big field plate 2809B-1 covers all the post 2803B except last post that is connected to another field plate 2809B-2.By with big field plate 2809B-1 ground connection, very fast the exhausting of table section between the p type post, and horizontal pressure drop will can be very not remarkable makes the puncture voltage that is lower than the embodiment shown in Figure 28 A.In another embodiment shown in Figure 28 C, terminal structure does not have field plate on the post of centre.Because on the post of centre, do not have field plate, so just had narrower table section to exhaust fully.In one embodiment, reduce mesa width gradually towards outer shroud and produce best performance.Embodiment shown in Figure 28 D by broad is provided well region 2808D and increase interval between the field oxide and help and the contacting of p type post.
State in the use under the situation of superhigh pressure device of various super junction technology of type, puncture voltage is much higher than conventional BV PPFor the super junction device, charge balance or super-junction structures (for example, opposite polarity post or floating region, buried electrodes etc.) also can be used in the termination environment.Also can use standard edge terminal structure in conjunction with charge balance structure, for example, the field plate of device edge place top plan.In certain embodiments, can in the terminal knot, reduce electric charge fast by use and eliminate the standard edge structure at top.For example, can be with along with the few more p type post that forms in the termination environment of distance active area electric charge far away more, wherein, active area is created clean n type balancing charge.
In one embodiment, the distance that moves away from active area along with post changes the interval between the p type post in the termination environment.Figure 29 A shows the sectional view of simplifying according to the height of the exemplary embodiment of the device 2900A of this embodiment.In the active area of device 2900A, for example form under the p type trap 2908A of opposite conductivities post 2926A in n type drift region 2904A that makes by the p type spheroid of a plurality of connections.In the edge of device, below the termination environment, formation p type terminal pillar TP1, TP2 as shown in the figure is to TPn.Substitute have unified interval in active area, terminal pillar TP1 increases along with the increase of the interface distance of mobile post and active area to the interval of the center to center between the TPn.Just, the distance D 1 between TP2 and the TP3 is less than the distance D between TP3 and the TP4 2, and distance D 2 is less than the distance D between TP4 and the TP5 3, and the like.
Can carry out many variations to this super junction terminal structure.For example, substitute in voltage sustaining layer 2904A and form p type terminal pillar TP1 to TPn, but the interval of center to center is consistent, still can change the width of each terminal pillar with different distances.Figure 29 B shows the simplified example according to the terminal structure of this embodiment.In this example, terminal pillar TP1 has the width W 1 greater than the width W 2 of terminal pillar TP2, and W2 is greater than the width W 3 of terminal pillar TP3 successively, and the like.According to the interval between the charge balance district of the opposite polarity in the termination environment, similar among resultative construction among the device 2900B and the device 2900A is although the interval of the center to center between the groove post can be identical in device 2900B.In another exemplary embodiment shown in the simplification sectional view of Figure 29 C, the width of each the opposite polarity post 2926C in the active area reduces from the top plan to the substrate, and the width of terminal pillar TP1 and TP2 is consistent.Utilize less area just to realize the puncture voltage of expectation like this.It should be appreciated by those skilled in the art, above-mentioned various terminal structures combination in any desired way, for example, comprise that the interval of the center to center of the terminal pillar of device 2900C shown in Figure 29 C and/or beam overall can change in conjunction with the embodiment shown in Figure 29 A and the 29B.
Technology
Many different components with a plurality of buried electrodes or transistorized groove structure have so far been described.For these trench electrode of setovering, these devices need electrically contact with each buried regions.Here disclosed groove structure with buried electrodes and the method that is used for contacting of being used to form with the polysilicon layer of burying in the groove.In one embodiment, the edge at tube core contacts with the groove polysilicon layer.Figure 30 A shows an example of the EDGE CONTACT of the trench device 3000 with two polysilicon layers 3010 and 3020.Figure 30 A illustrates along the sectional view of the device of the groove longitudinal axis.According to this embodiment, groove stops in the edge near tube core, for the purpose that contacts, and the surface of polysilicon layer 3010 and 3020 referred substrates.Opening 3012 in dielectric (oxidation) layer 3030 and 3040 and 3022 allows the Metal Contact with polysilicon layer.Figure 30 B shows each treatment step that relates to the EDGE CONTACT structure that forms Figure 30 A to 30F.In Figure 30 B, at the top of epitaxial loayer 3006 one patterned dielectric (for example, silicon dioxide) layer 3001, and the surface that etching substrates exposes is to form groove 3002.Then, shown in Figure 30 C, the upper surface that crosses the substrate that comprises groove forms first oxide layer 3003.Then, shown in Figure 30 D, form first electric conducting material (for example, polysilicon) 3010 at the top of oxide layer 3003.With reference to Figure 30 E, etching polysilicon layer 3010 in groove, and on polysilicon layer 3010, form another oxide layer 3030.Carry out similar step, forming the interlayer of second oxide layer-polysilicon layer-oxide layer shown in Figure 30 F, the top oxide layer 3040 shown in the etching is formed for carrying out with polysilicon layer 3010 and 3020 opening 3012 and 3022 of Metal Contact respectively.Can repeat last step and form additional polysilicon layer, and if desired, can polysilicon layer be connected together by the stack metal level.
In another embodiment, carry out with the contacting in the active area of device of a plurality of polysilicon layers in the given groove, rather than along the edge of tube core.Figure 31 A shows and is used for a plurality of examples of burying the active area contact structures of polysilicon layer.In this example, the sectional view along the groove longitudinal axis shows polysilicon layer 3110 that gate terminal is provided and polysilicon layer 3111a and the 3111b that two screens are provided.When the metal wire 3112,3122 of three separation that illustrate when 3132 contact with polysilicon layer, they can link together and be connected to the source terminal of device, perhaps use the combination of any other contact by the requirement of special applications.Compare with the multilayer EDGE CONTACT structure shown in Figure 30 A, the advantage of this structure is the plane character of contact.
Figure 31 B illustrates an example that is used to the groove with two polysilicon layers to form the technological process of active area shielding contact structures to 31M.Then the etched of groove 3102 among Figure 31 B is the formation of the screen oxide 3108 among Figure 31 C.Then, shown in Figure 31 D, deposition shield polysilicon 3111, and make in its recessed groove.In Figure 31 E, shield position contacting except being desirably in the substrate surface place, bucking electrode 3111 is recessed inwards again.In Figure 31 E, the polysilicon in the middle of mask 3109 protections in the groove is in order to avoid further etched.In one embodiment, this mask is applied in diverse location along different grooves, for example middle groove, and the shielding polysilicon is recessed into other parts of groove at third dimension (not shown).In another embodiment, the shielding polysilicon 3111 in the one or more selection grooves in active area is masked along the total length of groove.Then, shown in Figure 31 F, etch shield oxide layer 3108 then, shown in Figure 31 G, is crossed the thin layer that grid oxic horizon 3108a is formed on the substrate top after removing mask 3109.Then be deposition and recessed (Figure 31 H) of gate electrode, the injection of p trap and driving (drive) (Figure 31 I), and the n+ source electrode injects (Figure 31 J).Figure 31 K, 31L and 31M show the step that BPSG deposition, contact etch and p+ heavy doping main body are injected respectively, are metallization then.Figure 31 N shows the sectional view of the optional embodiment of active area shielding contact structures, wherein, forms the platform of relative broad at the top barrier polysilicon 3111 of screen oxide.Help contacting bucking electrode like this, may make further complicated configuration (topography) of manufacturing process but introduced.
Top-down simplified layout diagram at the exemplary trench device that has active area shielding contact structures shown in Figure 32 A.The mask that limits the bucking electrode groove prevents position 3211C place and shield trenches 3213 peripheral recessed of bucking electrode in active area.The improvement of this technology uses " dog bone (dogbone) " shape to be used to shield polysilicon groove mask, provides wideer district to be used to contact the shielding polysilicon at the intersection with each groove 3202.Make shielding polysilicon in the blasnket area also by recessed like this, but be the initial surface that is recessed into table top, therefore eliminated configuration.At the top-down layout of optional embodiment shown in Figure 32 B, wherein, the active area groove is connected to peripheral groove.In this embodiment, for contacting with the active area shield trenches of source metal, it is recessed along the length of selected groove (this example is depicted as middle groove) that shielding polysilicon groove mask prevents to shield polysilicon.Figure 32 C and 32D illustrate the simplified layout diagram that is used for two different embodiment contacting with peripheral groove in having the trench device that disconnects groove structure.In these figure, for illustrative purposes, active groove 3202 and peripheral groove 3213 are represented by single line.In Figure 32 C, the extension of peripheral gates polysilicon bearing 3210 or finger (finger) are with respect to the cross arrangement of periphery shielding polysilicon finger, so that the periphery contact is separated with peripheral groove.Source electrode with the shielding contact zone 3215 also shown in 3211C place, position contact with active area inner shield polysilicon.Embodiment shown in Figure 32 D has eliminated the side-play amount between active and the peripheral groove, with the possible restriction of avoiding being caused by groove inclination requirement.In this embodiment, aim at the horizontal-extending portion of active groove 3202 and peripheral groove 3213, the window 3217 in the grid polycrystalline silicon bearing 3210 is used for contacting of carrying out with peripheral groove shielding polysilicon on every side.The active area contact is carried out at the 3211C place, position as previous embodiment.
Optional embodiment at the groove shielding polysilicon that is used for contacting active area shown in Figure 33 A.In this embodiment, instead of recesses shielding polysilicon, but vertically it is extended to silicon face above the active groove entity part.With reference to Figure 33 A, grid polycrystalline silicon 3310 is divided into two parts along with shielding the height vertical extent of polysilicon 3311 along groove 3302.Two grid polycrystalline silicon parts correct position in groove is in the third dimension or connects together when they enter groove.The advantage of this embodiment is to utilize the silica space that replaces being used for the contact of groove polysilicon by the district that carries out the contact of source electrode polysilicon in active groove.Figure 33 B shows an example of the technological process of the active shielding contact structures that are used to form Figure 33 A shown type to 33M.In Figure 33 B, etched trench 3302 is the formation of the screen oxide 3308 shown in Figure 33 C afterwards.Then, shown in Figure 33 D, shielding polysilicon 3311 is deposited in the groove.Shown in Figure 33 E, etch shield polysilicon 3311, and make in its recessed groove.Then, shown in Figure 33 F, etch shield oxide skin(coating) 3308 stays the part that the shielding polysilicon 3311 that forms two grooves in groove inner shield polysilicon 3311 sides exposes.Then, shown in Figure 33 G, cross the interior lamellar grid oxic horizon 3308a of flute profile of top, trenched side-wall and groove of substrate.Then be deposition and recessed (Figure 33 H) of grid polycrystalline silicon, the injection of p trap and driving (Figure 33 I), and the n+ source electrode injects (Figure 33 J).Figure 33 K, 33L and 33M illustrate the step that BPSG deposition, contact etch and p+ heavy doping main body are injected respectively, then are metallization.Can change this technological process.For example, by rearranging some processing steps, the processing step that forms grid polycrystalline silicon 3310 can be before the step that forms shielding polysilicon 3311.
It all is well-known being used to carry out the concrete processing method of many steps of above-mentioned technological process and parameter and change thereof.For given application, can well adjust special process method, chemistry and material type, with the manufacturability and the performance of enhance device.Can begin to improve from raw material, just, form the substrate of extension drift region thereon.In most of power application, expectation reduces transistorized conducting resistance R DSonThe desirable conducting resistance of power transistor is the stronger function of critical field (critical field), and wherein, critical field is defined as the maximum field in the device under breakdown condition.Suppose to keep rational mobility,, can reduce transistorized conducting resistance significantly if device is the made that is higher than the critical field of silicon with critical field.Because the characteristic (comprising structure and technology) of many power devices described so far is described in the content of silicon substrate, can use other embodiment of the baseplate material that is different from silicon.According to an embodiment, the power device described herein substrate manufacturing of making by wide bandgap materials (for example comprising carborundum (SiC), gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), diamond etc.).These wide bandgap materials demonstrate the critical field greater than the critical field of silicon, can be used for significantly reducing transistorized conducting resistance.
Another mainly contains what help to reduce transistor conduct resistance is the thickness and the doping content of drift region.The drift region generally is to be formed by epitaxially grown silicon.In order to reduce R DSon, expectation minimizes the thickness of this extension drift region.Partly control the thickness of epitaxial loayer by the type of initial substrate.For example, for discrete-semiconductor device, the substrate of doping red phosphorus is the material of initial substrate general type.Yet the characteristic of phosphorus atoms is their diffusions promptly in silicon.Therefore, determine thickness, to regulate the phosphorus atoms that upwards spreads from following heavy doping substrate in the epitaxial region of substrate top formation.
In order to make the thickness minimum of epitaxial loayer,, on phosphorus substrate 3414, form the extension spacer region or buffering (potential barrier) layer 3415 of alloy (for example, arsenic) with less relatively diffusivity according to an embodiment shown in Figure 34.The substrate of the Doping Phosphorus of combination and the resilient coating of arsenic doped provide the basis for forming extension drift region 3406 subsequently.Require definite layer 3415 arsenic doping concn by the puncture voltage of device, and the thickness of determining arsenic epitaxial loayer 3415 by concrete heat budget (thermal budget).Then, can deposit uniform epitaxial loayer 3406 at the top of arsenic epitaxial loayer, its thickness is determined by requirement on devices.The diffusivity that arsenic is very low allows to reduce the gross thickness of extension drift region, makes to have reduced transistorized conducting resistance.
In optional embodiment,, between two layers, use diffusion barrier layer in order to calculate the upwards diffusion of dopant species from the heavy doping substrate to epitaxial loayer.According to an exemplary embodiment shown in Figure 35, by for example carborundum Si xC 1-xBe deposited on the substrate 3514 of boron or phosphorus to barrier layer 3515 extensions of forming.Then, epitaxial loayer 3506 be deposited on barrier layer 3515 above.Heat budget according to technology can change thickness and carbon compound.Alternatively, the carbon alloy can at first be injected in the substrate 3514, then heat-treats the activation carbon atom, forms Si with the surface at substrate 3514 xC 1-xCompound.
Another aspect that restriction reduces the specific trench transistor technology of epitaxy layer thickness ability is the knot that forms between dark body and epitaxial loayer, is used in active area when this has, and is used in the termination environment sometimes.The formation in this dark tagma relates generally at the early stage implantation step of technology.Because the formation by field oxide and grid oxic horizon requires heat budget subsequently, the knot between dark body and the drift region is divided into big scope.In order to avoid early puncturing at the edge of tube core, need very thick drift region, this has just caused higher conducting resistance.For the thickness with required epitaxial loayer minimizes, the use of diffusion barrier layer also can be used at dark body-epitaxial loayer knot place.According to exemplary embodiment shown in Figure 36,, before carrying out dark body injection, inject the carbon alloy by dark body window.Thermal process subsequently activates carbon atom, forms Si with the border in dark tagma 3630 xC 1-xCompound 3615.Silicon carbide layer 3615 is as the diffusion barrier layer that stops boron diffusion.The final dark body knot that forms is the shallow-layer that allows to reduce epitaxial loayer 3606 thickness.Another knot in benefiting from the typical trench transistor of barrier layer is trap-drift region knot.The simplified example of the embodiment of this barrier layer of use shown in Figure 37.In the exemplary process flow that is used for Figure 31 M structure, between two steps shown in Figure 31 H and the 31I, form the p trap.Before, at first inject carbon at injection trap alloy (this exemplary n raceway groove embodiment is the p type).Thermal process subsequently activates carbon atom, to form Si at p trap epitaxy junction place xC 1-xLayer 3715.Layer 3715 prevents boron diffusion as diffusion barrier layer, the feasible degree of depth that can keep p trap 3704.Help like this to reduce transistorized channel length, and do not increase the break-through current potential.Break-through when arriving source junction, takes place in the increase of loss border along with drain electrode-source voltage of advancing.By being used as diffusion barrier layer, layer 3715 can also prevent break-through.
As mentioned above, expectation reduces transistorized channel length, because it causes reducing of conducting resistance.In another embodiment, make the transistor channel length minimum by using epitaxially grown silicon to form well region.Just, replace before diffusing step, forming conventional method, form well region at the top of extension drift layer about the trap that injects the drift epitaxial loayer.Except obtaining short channel length, also have other advantages from the formation of extension-trap.For example, in the shielded gate trench transistor, the distance that gate electrode extends in the bottom of the trap of contact trench (grid is to the overlapping portion of drain electrode) is for definite gate charge Q GdVery important.Gate charge Q GdDirectly influence transistorized switching speed.Therefore, expectation can accurately minimize and control this distance.Yet, for example, the trap shown in above-mentioned Figure 31 I inject and be diffused into shown in the manufacturing process of epitaxial loayer, be difficult to control this distance.
For the corner's grid that better is controlled at trap arrives the stack that drains, the various methods that are used to form the trench device of the trap with self-aligned have been proposed.In one embodiment, the depositing operation flow process that relates to epitaxial loayer-trap can make the bottom and the gate bottom self-aligned of body junction.To 38D, show the have buried electrodes simplification technological process of an example of extension-trap trench device of self-aligned of (or dhield grid) with reference to Figure 38 A.Groove 3802 etchings are advanced first epitaxial loayer 3806 that forms at the top of substrate 3814.For the n channel transistor, the substrate 3814 and first epitaxial loayer 3806 are n section bar material.
Figure 38 A shows the shield dielectric layer 3808S in the grown on top of the epitaxial loayer 3806 that comprises internal groove 3802.Then, shown in Figure 38 B, deposits conductive material 3811 in groove 3802 (for example, polysilicon), and below the extension table top, carry out dark etching.The additional dielectric material 3809S of deposition shields polysilicon 3811 to cover.Shown in Figure 38 C, after dark etching dielectric layer is cleared up table top, second epitaxial loayer 3804 of optionally growing at the top of first epitaxial loayer 3806.The table top that forms by epitaxial loayer 3804 shown in generation groove top above the original groove 3802.This second epitaxial loayer 3804 has the opposite polarity alloy (for example, p type) with first epitaxial loayer 3806.The doping content of second epitaxial loayer 3804 is set to the aspiration level of transistor well region.After selective epitaxy growth (SEG) step of cambium layer 3804, on end face and along trenched side-wall, form gate dielectric 3808G.Then, shown in Figure 38 D, the deposition grid conducting material, the remainder of filling groove 3802 is carried out complanation then.For example, continue at Figure 31 J to the technological process shown in the 31M, to finish transistor arrangement.
Shown in Figure 38 D, this technology forms the grid polycrystalline silicon 3810 with trap epitaxial loayer 3804 self-aligneds.For the bottom that makes grid polycrystalline silicon 3810 is reduced under the extension trap 3804, can be slightly the upper surface of the polysilicon interlayer dielectric layer 3809S shown in Figure 38 C be etched into desired locations in the groove 3802.Therefore, this technology provides accurate control to the distance between the turning of gate electrode and trap.It should be appreciated by those skilled in the art that the SEG trap forms technology and is not limited to the shielded gate trench transistor, also can use in many other trench-gate transistor arrangements, wherein, manyly be described in this article.The additive method that forms the SEG mesa structure is described in the 6th, 373, No. 098 of people such as the common people's such as Madson that transfer the possession of No. the 6th, 391,699, United States Patent (USP) and Brush, and its full content is hereby expressly incorporated by reference.
The optional method at turning that is used to control the trap of self-aligned does not rely on the formation of SEG trap, relates to the technology that the angle trap injects but replace using.Figure 39 A and 39B illustrate the exemplary process flow of this embodiment.In this embodiment, replacement shown in the trench fill (for example, in Figure 31 H and 31I) grid polycrystalline silicon after form trap, but embed after the shielding polysilicon in the dielectric layer 3908 groove 3902 in, before the remainder of filling groove, carrying out first trap injection 3905 to certain portions.Then, shown in Figure 39 B, the sidewall by groove 3902 carries out second but become the trap at angle to inject.Then, finish drive cycle, arrive the profile of drift epitaxial interface with the trap that obtains expectation at the trench corner place.According to the structural requirement of device, will change the details of injection rate (implant does), energy and drive cycle.This technology can be used in many different type of device.In optional embodiment, regulate that groove tilts and angle is injected, make and inject when spreading when angle that the district of itself and adjacent unit combines and forms continuous trap, has eliminated the needs of first trap injection.
40A describes another embodiment of the extension trap technology of the self-aligned that is used to form trench device to 40E in conjunction with the accompanying drawings.As mentioned above, in order to reduce gate-to-drain electric capacity, some trench gate type transistors use gate dielectrics, and wherein, the bottom thickness of the groove of gate dielectric below grid polycrystalline silicon is greater than the thickness along the dielectric layer of interior vertical sidewall.To the illustrative processes embodiment shown in the 40E, shown in Figure 40 A, at first form dielectric layer 4008B according to Figure 40 A at the top of extension drift layer 4006.Formation has the dielectric layer 4008B of expectation thickness, then, shown in Figure 40 B, the dielectric post of the feasible remaining groove same widths that has and form subsequently of etching dielectric layer 4008B.Next, in Figure 40 C, carry out the selective epitaxial growth step, around dielectric post 4008B, to form the second extension drift layer 4006-1.The second extension drift layer 4006-1 has identical conduction type and can be identical materials with the first extension drift layer 4006.Alternatively, the second extension drift layer 4006-1 also can use the material of other types.In one exemplary embodiment, by using SiGe (Si xGe 1-x) the SEG step of alloy forms the second extension drift layer 4006-1.The SiGe alloy has improved the carrier mobility of the accumulation area of adjacent trenches bottom.So just improve transistorized switching speed, and reduced R DSonAlso can use other compounds, for example, GaAs or GaN.
Shown in Figure 40 D and 40E difference, on upper surface, form and cover extension trap layer 4004, then, etching extension trap layer 4004 forms groove 4002.Then be the formation of grid oxic horizon and the deposition (not shown) of grid polycrystalline silicon.Final structure is the trench-gate with extension trap of self-aligned.Can use traditional treatment technology to finish remaining processing step.It should be appreciated by those skilled in the art that change can be arranged.For example, replace forming covering extension trap layer 4004 etched trench 4002 then, extension trap 4004 can only optionally be grown at the top of the second drift epitaxial loayer 4006-1, along with its growth formation groove 4002.
Above-mentioned various treatment technology is by paying close attention to the formation enhance device performance of well region, to reduce channel length and R DSonBy improving other aspects of technological process, can realize that also similar performance strengthens.For example, by reducing substrate thickness, can further reduce the impedance of device.Therefore in order to reduce the thickness of substrate, generally carry out wafer grinding and handle.Generally carry out wafer grinding by mechanical lapping and tape handling (tape process).Grinding and tape handling are that mechanical force is applied on the wafer, cause the damage of wafer surface, have so just caused a manufacturing difficult problem.
Among the embodiment of Miao Shuing, improved wafer grinding is handled and has been reduced the substrate impedance significantly hereinafter.A kind of method that is used to reduce substrate thickness has been shown in Figure 40 R, Figure 40 S, Figure 40 T and Figure 40 U.Finish on wafer after the making of expectation circuit, the top that makes the wafer of circuit is adhered to carrier provisionally.Figure 40 R illustrates the wafer of finishing 4001 and adheres to carrier 4005 by adhesion material 4003.Then, use the polished backside of the wafer finished to be arrived and expect thickness such as processing such as grindings, chemical etchings.Figure 40 S illustrates and similar sandwich shown in Figure 40 R, has the wafer 4001 of attenuate.After the back side of polished wafer 4001, shown in Figure 40 T, the back side of wafer adheres to Low ESR (for example, metal) wafer 4009.Can use traditional method to finish these steps, for example, the shallow layer of use scolder 4007 adheres to metal wafer 4009 wafer 4001 of attenuate under temperature and pressure.Then, before further handling, remove carrier 4005 and clear up the upper surface of the wafer 4001 of attenuate.The metal substrate 4009 of high conduction helps to dispel the heat, reduce impedance and provides mechanical strength for the wafer of attenuate.
By using chemical treatment to carry out last reduction processing, optional embodiment has realized not having traditional mechanical to handle the thinner wafer of shortcoming.According to this embodiment, on the silicon layer of heavy sheet glass silicon (silicon-on-thick-glass abbreviates SOTG as) substrate, form active device.In the grinding stage, can be by chemically the glass etching of SOTG substrate back being fallen wafer grinding.Figure 41 illustrates the exemplary process flow according to this embodiment.From silicon substrate, at first in step 4110, such as He or H 2Alloy be injected into silicon substrate.Then, 4112, silicon substrate is adhered to glass substrate.Can use different adhesion process.In an example, silicon wafer and chip glass are made sandwich-like, are heated to about 400 ℃ and come bonding two substrates.Glass can be silicon dioxide etc., and can have for example thickness of about 600um.Then, in step 4114, randomly adhesive silicone substrate, and formation heavy sheet glass silicon (siicon-on-thick-glass) SOGT substrate.Avoid stress for protective substrate in processing and processing procedure subsequently, can repeat adhesion process, form SOGT substrate (step 4116) with opposite side at substrate.Next, deposit epitaxial layers (step 4118) on the silicon face of substrate.Except the front side, also can carry out at rear side.Preferably, the doping content of the doping content of epitaxial loayer rear side and rear side silicon is similar, and the front side epitaxial loayer is along with the doped in concentrations profiled of requirement on devices.Then, substrate is used for forming each step of the manufacturing process of active device on the silicon layer of front side.
In one embodiment, in order further to strengthen the intensity of substrate opposing by the stress of front side treatment step introducing, backside substrate can be carried out the reverse geometry that pattern turns to approximate front side tube core framework.By this way, glass substrate etching network access grid is to help the stress in the thin base plate supports wafer.After grinding, at first from rear side silicon layer is removed (step 4120) by traditional grinding technics.Then be another grinding steps 4122, remove the part (for example, half) of glass substrate.Then, handle the part removal that glass substrate is remaining by using as the chemical etching of hydrofluoric acid.Can carry out the etching of rear glass substrate, and active silicon layer not corroded or causes the risk of mechanical damage.So just cancelled the needs of band around (tape) wafer, eliminated band around with again with needs and every technology risk that operation is relevant around (re-tape) equipment.Therefore, such technology makes and further substrate thickness is minimized the enhance device performance.Should be understood that the change that many this improvement wafer grinding technologies can be arranged.For example, according to the expectation thickness of final substrate, the attenuate step can relate to grinding or not relate to grinding, because chemical etching is enough.In addition, improved wafer grinding technology is not limited to the processing of discrete device, also can be applied in the processing of other types device.Other wafer grinding technology is described in the United States Patent (USP) the 6th, 500,764 of the common transfer of Pritchett, and its full content is incorporated into this.
Have other structures of many power transistors and processing aspect and other active devices that can their performance of appreciable impact.The shape of groove is an example.In order to reduce to be easy to potential destructive electric field concentrated around the turning of groove, sharp corners is avoided in expectation, but forms the groove with radiused corners.In order to improve reliability, also expectation realizes having the trenched side-wall of smooth surface.Different etch chemistries provides balance in different result (for example, the selectivity of silicon etch rate, mask layer, etching section (side wall angle), top corner fillet, the degree of roughness of sidewall and the fillet of channel bottom).Fluoride (for example, SF 6) high silicon etch rate (greater than 1.5um/min), the channel bottom of circle and straight side be provided.The fluoride shortcoming is the coarse sidewall and the difficulty (can be recessed) of groove top control.Chloride (for example, Cl 2) more smooth sidewall is provided, and etching section and groove top are better controlled.Muriatic shortcoming is to have lower silicon etch rate (less than 1.0um/min), and the littler fillet of channel bottom.
Additional gas can be added in the etch chemistries, to help passivation sidewall during etching.Side wall passivation is used for side etching is minimized, and etches into the gash depth of expectation.Can use additional treatment step to make trenched side-wall smooth, and the rounding of realizing groove top corner and bottom.The surface quality of trenched side-wall is very important, because it has influence on the quality of the oxide layer that can grow on trenched side-wall.No matter the chemicals that use, the general use penetrates (breakthrough) step before main etching step.The purpose of penetration step is to remove any on the silicon face can shelter the etched native oxide of silicon during main etching step.Typical break-through-etch chemicals are CF 4Or Cl 2
Be used to improve the main silicon trench etching of an embodiment use of etch process shown in Figure 42 A, then be based on the etching step of fluorine based on chlorine.An example of this technology uses Cl 2/ HBr master etching step then is SF 6Etching step.Chlorinating step is used for main line is etched into the part of desired depth.Produce the groove side surface that has tapering to a certain degree and have smooth side wall like this.Fluorination step subsequently is used for residue, the rounding channel bottom of the etched trench degree of depth and the further smoothing that the silicon bond of any suspension that sticks on the trenched side-wall is provided.Preferably, fluoridize that etching step flows at relatively low fluorine, carry out under low pressure and the lower powered condition, with control smoothing and rounding.Difference owing to etch-rate between two kinds of etch chemistries, time that can two steps of balance, have the technology of the reliable more and manufacturability of acceptable total etching period with realization, and keep groove side surface, sidewall roughness and the channel bottom fillet of expectation.
In another embodiment shown in Figure 42 B, be used for etched the improving one's methods of silicon and comprise main etching step based on fluorine, then be based on second etching step of chlorine.An example of this technology uses SF 6/ O 2Main etching step then is Cl 2Etching step.Fluorination step is used for most of degree of depth of etching main line.This step generates the groove of the channel bottom with straight sidewall and rounding.Randomly, oxygen can be added to this step, so that side wall passivation to be provided, and help to keep straight sidewall by reducing side etching.The top corner of follow-up chlorinating step rounding groove also reduces the roughness of sidewall.The high silicon etch rate of fluorination step increases the manufacturability of technology by the throughput that increases etch system.
In the another embodiment shown in Figure 42 C, by argon being added to based on obtaining improved silicon etch process in the chemicals of fluorine.Example according to the chemicals that are used for main etching step of this embodiment is SF 6/ O 2/ Ar.Therefore the argon that is increased to etching step has increased ion bombardment, makes etching physicsization more.Help to control the top of groove like this, and eliminated the recessed again tendency in groove top.Additional argon can also increase the fillet of channel bottom.Additional etch processes can be used for the smoothing of sidewall.
Shown in Figure 42 D, be used for the chemicals of the optional embodiment use of improved silicon etch process based on fluorine, begin to remove oxygen from main etching step.An example of this technology uses SF 6Step then is SF 6/ O 2Step.In the etched phase I, owing to there is not O 2, lack side wall passivation.Such result is the increase of the side etching amount at groove top.Then, second etching step, SF 6/ O 2, continue the remaining gash depth of etching, make to have straight side and circular channel bottom.Cause top broad in groove structure like this, be sometimes referred to as the T groove.The device example that uses the T groove structure Herrick be entitled as " Structureand Method for Forming a Trench MOSFET Having Self-AlignedFeatures; " the U.S. Patent application the 10/442nd of common transfer, be described in detail in No. 670 (acting on behalf of case 18865-131/17732-66850), its full content is hereby expressly incorporated by reference.Can adjust the cycle that is used for two main etching steps, to realize the expectation thickness of the every part of T groove (top T part, the part of bottom smooth side wall).Can use additional treatments to come, and trenched side-wall is polished the top corner cavetto of T groove.These additional treatments can comprise, for example: (1) step when the groove engraving method finishes based on fluorine, perhaps (2) in the release etch system, separate based on the etching of fluoridizing, perhaps (3) sacrifical oxide, or any other combination.Can use chemical-mechanical planarization (CMP) step, with the top of removing groove side surface recessed portion again.Can also use H 2Annealing (anneal) is helped rounding and is formed favourable valley gutter side.
For the darker high-voltage applications of groove trend, has extra consideration.For example, because darker groove, so silicon etch rate is very important for producing the technology that can make.The etch chemistries that is used for this application is generally fluoridizes chemicals, because the reaction of the etching chemistry of chlorination is too slow.Expect that also straight line arrives the ditch grooved profile of taper, has smooth sidewall.Because the degree of depth of groove, etch process also needs to have to the good selectivity of mask layer.If selectivity is very poor, so just need thicker mask layer, will increase total aspect ratio.Side wall passivation also is strict, and need realize balance accurately.Undue side wall passivation will make channel bottom narrow down to the point of its closure, and side wall passivation very little will cause increasing side etching.
In one embodiment, provide the optimally deep trench etch process of all these requirements of balance.According to this embodiment, shown in Figure 42 E, etch process comprises (ramped) O that has gradual change 2, gradual change power and/or gradual change pressure the chemicals based on fluorine.An exemplary embodiment is used SF to keep etching section and the mode that runs through etched silicon etch rate 6/ O 2Etching step.By gradual change O 2, can control the etched side wall passivation amount that runs through, with side etching (under the situation of passivation very little) or the pinch off channel bottom of avoiding increasing (under the situation of excess passivation).Use has the United States Patent (USP) the 6th that is entitled as " Integrated Circuit Trench Etch withIncremental Oxygen Flow " that the etched example based on fluorine of gradual change Oxygen Flow has people such as Grebs, 680, be described in detail in No. 232, it is hereby expressly incorporated by reference.The gradual change of power and pressure helps to control ion current density and keeps silicon etch rate.If along with groove is etched darker and reduce significantly, so total etching period will increase silicon etch rate during etching.The low processing of wafers ability that has so just caused etcher.In addition, gradual change O 2Can help to control selection to mask material.According to this embodiment for being deeper than the O that the exemplary process of the groove of 10um for example can have per minute 3 to 5sccm 2The power level of turnover rate, per minute 10-20 watt and the pressure stage of per minute 2-3mT.
The optional embodiment of deep trench etch process uses stronger (for example, the NF of the chemicals based on fluorine 3).Because for silicon etching, NF 3Compare SF 6Easier reacting used NF 3Technology can realize the silicon etch rate that increases.Need to increase extra gas and be used for side wall passivation and section control.
In another embodiment, NF 3After the etching step is SF 6/ O 2Handle.According to this embodiment, NF 3Step is used for the major part with the high silicon etch rate etched trench degree of depth.Then, SF 6/ O 2Etching step is used for the existing trenched side-wall of passivation, and the remainder of the etched trench degree of depth.In the change of this embodiment shown in Figure 42 F, carry out NF in the mode that replaces 3And SF 6/ O 2Etching step.So just produced and had than direct SF 6/ O 2The technology of the silicon etch rate that technology is higher.So just at fast etch-rate step (NF 3) and generate the step (SF of the side wall passivation be used for section control 6/ O 2) between realized balance.The Balance Control of step the roughness of sidewall.For etched SF 6/ O 2Part also needs gradual change O 2, power and pressure, keeping silicon etch rate, and generate enough side wall passivations and help to control the etching section.It should be appreciated by those skilled in the art, in conjunction with each processing step combination in a different manner of the foregoing description description, to realize best trench etch process.Should be understood that any groove of any power device that these groove etching process can be used for describing in this article, and the groove that uses any other type in the integrated circuit of other types.
Before groove etching process, form the groove etching mask at silicon face, and carry out one patterned to expose the district that will carry out the ditch channelization.Shown in Figure 43 A, in general device, groove is etched in before the etching silicon substrate, and at first nitride layer 4305 and liner (pad) thin oxide layer 4303 are passed in etching.Form during the oxide layer in forming groove after the groove, cushion oxide layer 4303 can also be in edge's growth of the groove that promotes the nitride layer that superposes.So just produced the structure 4307 that is commonly referred to as " beak ", promptly cushion oxide layer is being grown partly near the slot wedge place under the nitride layer 4305.To will near groove, shoal at the source area that the slot wedge place that is adjacent under the cushion oxide layer with beak structure forms subsequently.This is very undesirable.In order to eliminate beak effect, in one embodiment, shown in Figure 43 B, non-oxide material (for example, polysilicon) layer 4309 is clipped between nitride layer 4305 and the cushion oxide layer 4303.Polysilicon layer 4309 protective lining oxide layers 4303 are in case further oxidation of quilt during groove oxidation formation subsequently.In another embodiment, shown in Figure 44 A, after the nitride layer 4405 and cushion oxide layer 4403 that limits groove opening passed in etching, on board structure, form thin layer 4405-1 such as the non-oxide material of nitride.Then, shown in Figure 44 B, remove protective layer 4405-1, be left along the separator of the vertical edge of nitride-cushion oxide layer structure from horizontal surface.Nitride spacer protective lining oxide layer 4403 is in case further oxidation of quilt in step has subsequently reduced beak effect.In optional embodiment,, can be combined in the embodiment shown in Figure 43 B and the 44B in order to reduce the degree that any beak forms.Just, the separator except generating from the technology in conjunction with Figure 44 A and 44B description also can be interposed in polysilicon layer between the nitride layer of cushion oxide layer and stack.Other change can be arranged, for example, increase another layer (for example, oxide layer) at the top of nitride layer, to help the selectivity of nitride when the etching silicon groove.
In conjunction with various transistors with shielded gate structure, dielectric materials layer comes bucking electrode and grid electrode insulating as above-mentioned.Dielectric layer must form in firm and reliable mode between this electrode that is called as polysilicon interlayer dielectric layer or IPD sometimes, makes it can withstand the potential difference that exists between bucking electrode and gate electrode gate electrode.Again with reference to Figure 31 E, 31F and 31G, show the simplification flow process that is used for associated process steps.After the shielding polysilicon 3111 in dark etched trench (Figure 31 E), shield dielectric layer 3108 is etched into and is shielded the same degree (Figure 31 F) of polysilicon 3111 deeply.Then, shown in Figure 31 G, on the upper surface of silicon, form gate dielectric 3108a.It is the step that forms the IPD layer.The vacation of shielding dielectric groove etching similarly is to form shallow slot on the upper surface of the residual shield dielectric layer of the either side of bucking electrode.This is shown in Figure 45 A.The structure that finally has uneven configuration can cause consistency problem, filling step especially subsequently.In order to eliminate such problem, improving one's methods of the various IPD of being used to form proposed.
According to an embodiment, after shielding dielectric groove etching, shown in Figure 45 B, use for example low-pressure chemical vapor phase deposition (LPCVD) processing deposit spathic silicon lining 4508P.Alternatively, polysilicon lining 4508P can only form on shielding polysilicon and shield dielectric layer, by the selection growth process of use polysilicon or the polysilicon sputter of aligning, makes trenched side-wall not have polysilicon substantially.The oxidized subsequently silicon dioxide that is converted to of polysilicon lining 4508P.This can carry out by traditional thermal oxidation.Do not form on trenched side-wall among the embodiment of polysilicon, this oxidation processes also forms gate dielectric 4508G.In addition, shown in Figure 45 C, after trenched side-wall etching oxidation polysilicon, form gate dielectric thin layer 4508G, remaining groove cavity is filled gate electrode 4510.The advantage of this processing is that polysilicon deposits in very conformal mode.Make space and other shortcoming minimums like this, in case and polysilicon in the top of shield dielectric layer and bucking electrode deposition, will form more smooth surface.The result obtains firmer and reliable improvement IPD layer.By along trenched side-wall and adjacent silicon surface region polysilicon being set before oxidation, oxidation step subsequently will make table top loss still less, and the groove that will not expect is widened and minimized.
In optional embodiment, at the sectional view of simplifying shown in Figure 46 A, 46B and the 46C, the cavity that will be produced by shielding polysilicon groove etching in groove is filled dielectric fill material 4608F, and wherein, dielectric fill material 4608F has the etch-rate identical with shield dielectric layer 4608S.Can use any this step of carrying out in high-density plasma (HDP) oxide deposition, chemical vapor deposition (CVD) or spin-coating glass (SOG) processing, then be planarization steps, to obtain the plane at groove top.Then, shown in Figure 46 B, dielectric fill material 4608F and shielding dielectric material 4608S are unified by dark etching, make the insulation material layer with necessary thickness stay on the bucking electrode 4611.Then, shown in Figure 46 C, after trenched side-wall was provided with grid dielectric material, remaining groove cavity was filled gate electrode.The result is an IPD layer of having avoided the inconsistent height of configuration conformal.
Be used to form the exemplary embodiment of the another kind of method of high-quality IPD shown in the simplification sectional view in Figure 47 A and 47B.Shield dielectric layer 4708S in forming groove and with after the shielding polysilicon cavity filling carries out the dark etching step of shielding polysilicon, is recessed at groove so that shield polysilicon.In this embodiment, shielding polysilicon groove etching stays more polysilicon in groove, make the upper surface of recessed shielding polysilicon be higher than the final objective degree of depth.The thickness of the extra polysilicon on shielding polysilicon upper surface is designed to the approximately thickness identical with Target IP D.Then, the top of bucking electrode is by physics or chemically change, with its oxidation rate of further enhancing.Can be by impurity (for example, fluorine or argon ion) ion being injected the method that polysilicon is into carried out chemistry or physically changed electrode, to strengthen the oxidation rate of bucking electrode respectively.Preferably, shown in Figure 47 A, this is infused under the zero degree carries out, just vertical with bucking electrode, so that can physics or chemically change trenched side-wall.Then, etch shield dielectric layer 4708S removes dielectric layer from trenched side-wall.This shielding dielectric groove etching remaining contiguous bucking electrode 4711 shield dielectric layer in produce slight recessed (being similar to shown in Figure 45 A).Then be traditional oxidation step, thereby the top that bucking electrode 4711 changes is oxidized with the speed faster than trenched side-wall.Caused like this on bucking electrode rather than formed fully thick insulating barrier 4708T along the sidewall on groove silicon surface.Thicker insulating barrier 4708T on bucking electrode forms IPD.The polysilicon lateral oxidation that changes compensates some grooves that form owing to shielding dielectric groove etching at the upper surface of shield dielectric layer.Then, carry out traditional step,, generate the structure shown in Figure 47 B in groove, to form gate electrode.In one embodiment, change bucking electrode with the acquisition scope at 2: 1 to 5: 1 the IPD and the thickness ratio of grid oxic horizon.For example, if selected 4: 1 ratio,, form the gate oxide of 500 dusts along the big appointment of trenched side-wall for the IPD of about 2000 dusts that on bucking electrode, form.
In optional embodiment, after shielding dielectric groove etching, carry out physics or chemical modification step.Just, etch shield oxide layer 4708S is to remove oxide from trenched side-wall.The top of above-mentioned bucking electrode and silicon have been disclosed like this by the method for physics or chemical modification.Owing to expose trenched side-wall, be only limited to horizontal surface so change step, just, only be silicon mesa and bucking electrode.Change method (for example, the ion of alloy injects) will be carried out at zero degree (perpendicular to bucking electrode), so that avoid physics or chemically change trenched side-wall.Then, carry out traditional method,, therefore on bucking electrode, produce thicker dielectric layer in groove, to form gate electrode.
Figure 48 illustrates the another method that is used to form improved IPD layer.According to this embodiment, on recessed screen oxide 4808S and bucking electrode 4811, form by the thick dielectric layer 4808T that makes such as oxide.Preferably, the craft of orientated deposition techniques of the plasma chemical vapor deposition (PECVD) of use such as high-density plasma (HDP) deposition or enhancing forms thick dielectric layer 4808T (just, " being inverted filling (bottm up fill) ").As shown in figure 48, orientated deposition makes along horizontal plane (just, on bucking electrode and screen oxide), rather than forms enough thick insulating barrier along vertical plane (just, along trenched side-wall).Then, carry out etching step, getting on except that oxide, and on the shielding polysilicon, stay enough oxides from sidewall.Then, carry out traditional step, in groove, to form gate electrode.Except obtaining conformal IPD, the advantage of this embodiment is to have prevented that table top loss and groove from widening, because IPD forms by deposition processes rather than oxidation processes.Another advantage of this technology turning on groove obtains fillet.
In another embodiment, after shield dielectric layer or shielding polysilicon were recessed, thin oxide layer 4908P was sheltered in growth in groove.Then, shown in Figure 49 A, deposited silicon nitride layer 4903 is to cover oxidation masking layer 4908P.Then, uneven etches both silicon nitride layer 4903 makes its bottom surface from groove (just, on bucking electrode) and does not remove from trenched side-wall.In final structure shown in Figure 49 B.Then, shown in Figure 49 C, wafer is exposed to oxidation environment, makes to form thick oxide layer 4908T on the shielding polysilicon surface.Because nitride layer 4903 can be not oxidized, just significant oxidation growth can not take place along trenched side-wall.Then, by wet etching, use for example strong phosphoric acid to remove nitride layer 4903.Shown in Figure 49 D, follow traditional processing step, to form grid oxic horizon and gate dielectric.
In certain embodiments, the formation of IPD layer relates to etch processes.For example, the embodiment that on configuration, deposits for the IPD film, the at first thick a lot of thin layer of final IPD thickness of deposition rate expectation.Do to obtain the plane thin layer like this, minimize in the groove with groove with initiation layer.Then, etching can the complete filling groove and the thicker thin layer that extends on silicon face, its thickness is reduced to Target IP D layer thickness.According to an embodiment, this IPD etch process is carried out with minimum two etching steps.First step is to silicon face with layer planesization.In this step, etched uniformity is very important.Second step is to make the recessed desired depth of IPD layer (and thickness) in groove.In this second step, the IPD layer is very important to the etching selectivity of silicon.During the groove etching step, expose silicon mesa, and the silicon trench sidewall is the same with the IPD layer is recessed in the groove.Any loss on the table top all can influence actual gash depth, and if comprise the T groove, also can influence the degree of depth of T groove.
In an exemplary embodiment shown in Figure 50 A, anisotropic plasma etch step 5002 is used for the IPD layer planeization up to silicon face.The exemplary etch-rate that is used for plasma etching can be 5000A/min.Then be isotropic wet etch step 5004, with in the recessed groove of IPD.Preferably, the solution that uses controlled silicon to select is carried out dark etching, so that when exposing, can not corrode sidewall silicon, and provide repeatably etching to obtain accurate depth of groove.The exemplary chemical agents that is used for wet etching can be 6: 1 buffer oxide etch (BOE), is approximately the etch-rate of 1100A/min 25 ℃ of generations.Provide in No. the 6th, 465,325, the United States Patent (USP) of the common transfer of Rodney Risley to be used to be suitable for the exemplary plasma of this technology and the details of wet etch process, its full content is hereby expressly incorporated by reference.First plasma etch step that is used for complanation is compared with wet etching, and the IPD layer on the groove has less groove.Second wet etch step that is used for groove etching is compared with plasma etching, produces better silicon selectivity and the infringement littler to silicon.In the optional embodiment shown in Figure 50 B, chemical-mechanical planarization (CMP) is handled and is used for the IPD layer planesization up to silicon face.Then be wet etching, with in the recessed groove of IPD.CMP handles the IPD layer that makes on the groove and produces less groove.The wet etch step that is used for groove etching is compared with CMP, produces better silicon selectivity and the infringement littler to silicon.Other combinations of these processing are possible also.
Except IPD, expectation forms high-quality insulating barrier in structure, comprises groove and plane gate dielectric, interlayer dielectric layer etc.The most generally the dielectric material of Shi Yonging is a silicon dioxide.The parameter that several definition oxide film of high quality are arranged.Mainly be uniform thickness, good integrality (low interface trap density), high electric field breakdown strengths and low leak level.Influence the speed that factor is an oxide growth of the many character in these character.Expectation is the growth rate of controlled oxidation thing accurately.During thermal oxidation, the charged particle on the wafer surface produces gas-phase reaction.In one embodiment, the method that is used for controlled oxidation speed is finished by influencing charged particle, is typically silicon and oxygen, by wafer is applied external voltage, to reduce or to increase oxidation rate.This is different from the plasma enhanced oxidation, does not form plasma (having active component) on wafer.In addition, according to this embodiment, gas does not quicken towards the surface, only is to prevent that itself and surface from reacting.In the exemplary embodiment, reactive ion etch (RIE) chamber with high temperature capabilities can be used to adjust required energy value.The RIE chamber also is not used in etching, controls institute's energy requirement but be used to apply the DC bias voltage, to slow down and to stop oxidation.Figure 51 is for the flow chart according to the illustrative methods of this embodiment.At first, the RIE chamber is used under test environment wafer being applied DC bias voltage (5100).Determining to suppress the required potential energy (5110) of surface reaction afterwards, apply enough big external bias, to prevent oxidation (5120).Then, by control external bias (for example, pulse modulation or additive method), the oxidation rate (5130) in the time of can being controlled at average very high-temperature.This method can obtain the advantage (better oxide flows, lower stress, eliminates the differential growth of various crystal orientations etc.) of high-temperature oxydation, and does not have the shortcoming of quick and non-homogeneous growth.
Although for example above-mentioned those can improve the quality of the oxide layer of generation in conjunction with the technology of Figure 51, especially in trench-gate device, left over the integrity problem of oxide.One of them main deterioration problem is because the high electric field at trench corner place, and wherein, electric field is by producing in the local reduction of the gate oxide at these some places.High grid leakage current and low gate oxide breakdown voltage have been caused like this.This influence reduces conducting resistance along with trench device is further proportional and becomes more violent, and along with the grid voltage requirement that reduces, caused thinner gate oxide.
In one embodiment, the dielectric material that has a dielectric constant (high-k dielectrics) greater than silicon dioxide by use solves the integrity problem of gate oxide.Allow the threshold voltage and the mutual conductance that equate with very thick dielectric like this.According to this embodiment, high-k dielectrics has reduced grid leakage current, and has increased the puncture voltage of gate-dielectric, and can not reduce the conducting resistance or the drain breakdown voltage of device.The hafnium of the interface state density that shows required thermal stability and be fit to (comprises Al 2O 3, HfO 2, Al xHfyO z, TiO 2, ZrO 2Deng) will in trench gate and other power devices, carry out integrated.
As mentioned above, in order to improve the switching speed of groove power MOSFET, expectation is with transistor gate-capacitance of drain C GdMinimize.Compare with trenched side-wall, using thicker dielectric layer at channel bottom is the above-mentioned C that is used to reduce GdOne of SOME METHODS.A kind of method that is used to form thick bottom oxidization layer relates to along the sidewall of groove and bottom and forms the masking oxide thin layer.Then, suppress material (for example, nitride) layer by oxidation and cover thin oxide layer.Then, anisotropically the nitride etching layer makes and remove all nitride from the horizontal bottom of groove, but trenched side-wall keeps the nitride layer that applies.After channel bottom is removed nitride, form oxide layer with expectation thickness in the bottom of groove.After this, after removing nitride layer and masking oxide, trenched side-wall forming thin raceway groove oxide layer.This be used to form the method for thick bottom oxidization layer and be modified in No. the 6th, 437,386, the common United States Patent (USP) of transferring the possession of of people such as Hurst carried out more detailed description, its full content is incorporated into this.Other relates to selective oxidation deposition and is used for being described in No. the 6th, 444,528, the United States Patent (USP) of the common transfer of Murphy in method that channel bottom forms thick oxide layer, and its full content is incorporated into this.
In one embodiment, forming improving one's methods of thick oxide layer at channel bottom uses low pressure chemical vapor deposition (SACVD) to handle.According to this method, exemplary process diagram shown in Figure 52, at etched trench (5210) afterwards, SACVD is used for the conformal oxide layer of height of deposition (5220), for example uses tetraethoxysilane (TEOS) not have the filling groove in space in oxide.Can hold in the palm the low pressure of 700 holder scopes from 100, and carry out the SACVD step under the condition of about 600 ℃ exemplary temperature scope from about 450 ℃.For example, TEOS (is unit with mg/min) and Ozone are (with cm 3/ min is a unit) ratio can be arranged in 2 to 3 the scope, be preferably about 2.4.Use this technology, can form and have thickness in about 2000 dusts to 10, the oxide layer between 000 dust.Should be understood that these data just for illustrative purposes, can change according to concrete technological requirement and other factors (for example, the air pressure in manufacturing equipment place).Can obtain optimum temperature by the quality of oxide layer of balance deposition rate and formation.Under higher temperature, deposition rate slows down, and can reduce the contraction of thin layer.Such thin layer shrinks can be so that form the gap along slight crack in the oxide layer of ditch groove center.
After deposited oxide layer, carry out dark etching from silicon face with in groove, to form relative more flat oxide layer (5240) at channel bottom with expectation thickness.For example use the HF of dilution, can carry out this etching by the combination of wet etching process or wet etching and dry ecthing.Because the oxide that SACVD forms is easy to infiltration, so the moisture around it has absorbed after deposition.In a preferred embodiment, follow dark etching and carry out fine and close step 5250, to improve this effect.For example, can for example carry out fine and close step by Temperature Treatment under 1000 ℃ of about conditions of 20 minutes.
Other advantage of this method is the ability of shield terminal groove (step 5230) during the dark etching step of SACVD oxidation, stays the terminal trenches of fill oxide.Just, for the various embodiment of above-mentioned terminal structure (groove that comprises filled dielectric material), identical SACVD step can be used for the terminal trenches fill oxide.In addition, by shelter a termination environment during dark etching, identical SACVD treatment step can be eliminated required in addition processing step to form the thermal field oxide layer so that form field oxide in the termination environment.In addition, this technology provides other flexibility, because since silicon not by the thermal oxidation loss but between the SAVCD depositional stage, be arranged on two positions and under the too etched situation, it allows terminal dielectric layer and the complete reprocessing of thick bottom oxidization layer.
In another embodiment, be used for using directed TEOS to handle in the another kind of method of channel bottom formation thick oxide layer.According to this embodiment, exemplary process diagram shown in Figure 53, the conformal nature of TEOS combines with the directional characteristic of plasma-reinforced chemical vapor deposition (PECVD), with deposition oxide (5310) optionally.This combination can have the deposition velocity higher than vertical surface at horizontal surface.For example, use the oxide layer of this process deposits can have the thickness of 2500 dusts and the average thickness that on trenched side-wall, has about 800 dusts at channel bottom.Then, isotropically etching oxide until removing all oxides from sidewall, keeps oxide layer at channel bottom.Etch process can comprise dried top oxide etching (dry top oxide etch) step 5320, then is wet buffer oxide etch (BOE) step 5340.For exemplary embodiment as described herein, after etching, have for example oxide layer of 1250 dust thickness in the channel bottom reservation, and remove all side wall oxide.
In a particular embodiment, the upper surface that concentrates on structure uses dried top oxide etching, with the oxide of the speed etching top area quickened, and to reduce the oxide of a lot of speed etched trench bottoms.This etching type that is called " mist etching (fog etch) " herein comprises that balanced etching condition and etch chemistries are to produce the selectivity of expectation carefully.In an example, under relatively low power and pressure, use plasma etcher (for example, LAM 4400) to carry out this etch process with top power supply.The example value of power and pressure is respectively in the scope between 200-500 watt and 250-500 millitorr.Can use different etch chemistries.In one embodiment, the combination fluoride (for example, C2F6) and chlorine, mixes down at for example about 5: 1 best ratio (for example, C2F6 is 190sccm, and Cl is 40sccm), produces the selectivity of expectation.Use chlorine uncommon as the partial oxidation etch chemistries, because chlorine is used more generally to etching metal or polysilicon, and its general etching that suppresses oxide.Yet, for the etched purpose of such selection, this work in combination fine, because the very strong etching of C2F6 is near the oxide of upper surface, higher energy makes C2F6 overcome the influence of chlorine, approaches channel bottom simultaneously, the chlorine etching speed that slowed down.After this main dry etching steps 5320, prior to BOE etching 5340 is to remove etching 5330.Should be understood that according to this embodiment, can realize best selectivity according to pressure, energy and the etch chemistries that plasma etcher changes by regulating minutely.
If expectation obtains to have the bottom oxidization layer of target thickness, can repeat one or many according to the PECVD/ etch process of this embodiment.This technology also makes and form thick oxide layer on the level table between the groove.Can be in groove etched this oxide layer after deposit spathic silicon and the dark from the teeth outwards etching, make the oxide of protection channel bottom avoid the influence of etching step subsequently.
Can be useful on the additive method that forms thick oxide layer in the channel bottom selectivity.Figure 54 illustrates the flow chart of an illustrative methods, uses high-density plasma (HDP) deposition to prevent forming oxide layer (5410) on trenched side-wall.The characteristic of HDP deposition be it along with deposition etch, compare with directed TEOS method, on trenched side-wall, form the oxide less with respect to the oxide of channel bottom.Then, use wet etching (step 5420), removing some from sidewall or to remove oxide, and be retained in the thick oxide layer on the channel bottom.Shown in Figure 55, the advantage of this technology be slope, side 5510 at the groove top away from groove 5500, make to be more prone to realize that the atresia polysilicon fills.Fill (step 5440) before at polysilicon, can use above-mentioned " mist etching " (step 5430) that some oxides are etched away from the top, make that after the polysilicon etching, oxide still less need etch away from the top.The HDP deposition processes also can be used for deposition oxide between two polysilicon layers that have in the groove of buried electrodes (groove MOSFET that for example, has shielded gate structure).
According to the another method shown in Figure 56, the SACVD of selection handles and be used for forming thick oxide layer on channel bottom.This method utilizes SACVD in the lower TEOS:Ozone ratio selective ability that becomes.Oxide has very slow deposition velocity in silicon nitride, but can deposit fast in silicon.The ratio of TEOS and Ozone is low more, and deposition just becomes more selective.According to this method, at etched trench (5610) afterwards, grow liners oxide layer (5620) on the silicon face of groove array.Then, depositing nitride thin layer (5630) on cushion oxide layer.Then be anisotropically etching,, and on trenched side-wall, keep nitride layer (5640) with the denitrify layer that gets on from horizontal plane.Then, for example be approximately under 0.6 TEOS:Ozone ratio, the about 405 ℃ condition, at the SACVD oxide (5650) that is comprising that deposition is selected on the horizontal plane of channel bottom.Then, by Temperature Treatment selectively with SACVD oxide compacting (5660).Then, carry out oxide-nitrogen-oxide etching, to remove nitride and the oxide (5670) on the trenched side-wall.
As mentioned above, comparing using a reason of thicker oxide layer in the gate trench bottom with trenched side-wall is the Q that has reduced to improve switching speed GdOr gate-to-drain electric charge.Identical reason specifies the degree of depth of groove approximately identical with the degree of depth that trap is tied, so that the groove stack is minimized in the drift region.In one embodiment, the method that is used for forming at channel bottom thick dielectric layer extends to channel side with thick dielectric layer.This makes the thickness of bottom oxidization layer and gash depth and trap junction depth have nothing to do, and makes the polysilicon in groove and the groove be deeper than the trap knot, and can not increase Q Gd
Figure 57 illustrates the exemplary embodiment that forms thick bottom dielectric layer according to this method to Figure 59.Figure 57 A is illustrated in after its etched only covering groove sidewall, simplification and partial cross section figure that liner oxidation thin layer 5710 and nitride layer 5720 are provided with along groove.Shown in Figure 57 B, can realize the etching of cushion oxide layer 5710 like this, with the silicon that exposes channel bottom and the upper surface of tube core.Then be expose the anisotropic etching of silicon, the result is the structure shown in Figure 58 A, wherein, the silicon of top silicon and channel bottom all has been removed to the degree of depth of expectation.In optional embodiment, can shelter the silicon of upper surface, make during the silicon etching, only the etched trench bottom.Next, carry out oxidation step, with grow thick oxide layer 5730 on the position that is not covered by nitride layer 5720, the result is the structure shown in Figure 58 B.For example, thickness of oxide layer can for about 1200 dusts to 2000 dusts.Then, remove nitride layer 5720, and etch away cushion oxide layer 5710.The etching of cushion oxide layer will cause some attenuates of thick oxide layer 5730.Remaining technology can be used the flow process of standard, and to form gate electrode, trap and source junction, the result is the exemplary configurations shown in Figure 59.
Shown in Figure 59, final grid oxic horizon comprises along trenched side-wall and extends to bottom thick-layer 5730 on the trap knot of district in 5740.In certain embodiments, wherein, the channel doping in the well region on groove next door has the less doping thing near drain side 5740 places, and this district compares with district near source electrode, generally has lower threshold voltage.The channel side of distinguishing the raceway groove in 5740 along being added to is extended thicker oxide layer will can not increase the threshold voltage of device.Just, this embodiment makes optimization trap junction depth and side wall oxide the best, with Q GdMinimize, and can not influence the conducting resistance of device.It is apparent to those skilled in the art that the method that forms thick oxide layer at channel bottom can be applied in the above-mentioned various device, comprise dhield grid, in conjunction with bigrid and other trench-gate device of various charge balance structure.
Those skilled in the art it is also to be understood that any above-mentioned being used for can use in the technology that is used to form any ditch gate transistor as herein described with the technology that is used for IPD at channel bottom formation thick oxide layer.Can carry out other change to these technologies.For example, as the technology in conjunction with Figure 47 A and Figure 47 B description, the chemistry of silicon or physics change can strengthen its oxidation rate.According to such embodiment, halogen ionic species (for example, fluorine, bromine etc.) is injected in the silicon of channel bottom with zero degree.This injection can occur in about 15KeV or littler example energy, greater than 1E 14(for example, 1E 15To 5E 17) Exemplary amounts and 900 ℃ to 1150 ℃ between exemplary temperature under.In the halogen injection region of channel bottom, oxide layer is to compare the speed growth of acceleration with trenched side-wall.
Above-mentioned a plurality of trench device comprises that for the purpose of charge balance trenched side-wall mixes.For example, Fig. 5 B and Fig. 5 C and Fig. 6 have the trenched side-wall doped structure to all embodiment shown in Fig. 9 A.The wall doping technology exists because the restriction that the vertical sidewall of physical constraint restriction, deep trench and/or groove produces.Source of the gas or angle are injected can be used to form the trenched side-wall doped region.In one embodiment, improved trenched side-wall doping techniques uses plasma doping or pulse plasma doping techniques.This technology utilization is applied to the pulse voltage of the wafer in the plasma that is included in dopant ion.The voltage that applies has been accelerated the speed of ion from cathode sheath injection wafer.The voltage that applies is subjected to impulse action, and continuous action is up to the result who realizes expectation.This technology can make many such trench devices realize conformal doping techniques.In addition, the high-throughput of this technology has reduced the total cost of manufacturing process.
It is to be appreciated that those skilled in the art that plasma doping or pulse plasma doping techniques are not limited to the groove charge balance structure, can also be applied to other structures, comprise that the groove terminal structure is connected with groove drain electrode, source electrode or main body.For example, this method can be used to mix the shield trenches structure (for example, those in conjunction with Fig. 4 D, 4E, 5B, 5C, 6,7,8 and the described structure of 9A) trenched side-wall.In addition, this technology can be used to form the channel region of even doping.Depletion region when the reverse bias power device is controlled by the charge concentration on these knot both sides to the infiltration of channel region (p trap knot).When the doping content of epitaxial loayer is very high, can allow break-through to the infiltration of this knot, the raceway groove of being longer than desired length with restriction puncture voltage or requirement keeps low conducting resistance.For the infiltration with raceway groove minimizes, the channel doping concentration that can have relatively high expectations can be so that reduce threshold value.Because this threshold value is that the Cmax (peak concentration) below source electrode in the groove MOSFET is definite, the uniform doping concentration in the raceway groove can provide better balance between channel length and the puncture voltage.
Can use additive method to obtain to come raceway groove concentration more uniformly, comprise and use epitaxy technique to form channel junction, use multiple energy to inject and other are used to form the technology of projection knot.Another kind of technology is used has the initial wafer of lightly doped protective layer.By this way, compensation is minimized, and upwards diffusion can be used to form more uniform channel doping section.
It is the fact that is provided with by the channel doping concentration along trenched side-wall that trench device can utilize threshold value.Allow high-dopant concentration away from groove, keep the technology of low threshold value can help prevent break-through mechanism simultaneously.Before gate oxidation process, provide the p trap to mix and make that separating trap p type impurity (for example, boron) enters the groove oxide layer,, therefore reduced threshold value to reduce the concentration in the raceway groove.With this technology and above-mentioned technology in conjunction with shorter raceway groove can be provided and can break-through.
Some power application require to measure the magnitude of current that flows through power transistor.Typically by isolating and measure the part of total device current, be used to then infer that the total current that flows through device finishes.Total device current of isolated part flows through induction by current or detection means, generates the signal that size of current is isolated in expression, and it is used for determining total device current then.This set is known mirror current source.The common integral body of current sense transistor is fabricated to two devices and shares the common substrate (drain electrode) and the power device of grid.Figure 60 is the reduced graph with MOSFET 6000 of induction by current device 6002.The electric current that flows through main MOSFET 6000 is divided into active area each other in proportion between main transistor and induction by current portion 6002.Therefore, flow through the electric current of sensing device by measurement, the ratio that then induced current be multiply by active area calculates the electric current that flows through main MOSFET 6000.
Be used for isolating the total U.S. Patent application 10/315th that be entitled as " Method of Isolating the Current Sense on Planar or Trench StripePower Devices while Maintaining a Continuous Stripe Cell " of the whole bag of tricks of induction by current device people such as Yedinak from main device, be described in 719, its full content is hereby expressly incorporated by reference.Below use description to sensing device and the integrated embodiment of various power device are comprised that those have the device of charge balance structure.According to an embodiment, in the power transistor with the integrated induction by current device of charge balance structure and integral body, preferably, the induction by current district forms has identical continuous N OSFET structure and charge balance structure.In charge balance structure, do not keep continuity, will make puncture voltage reduce, cause that voltage provides Qu Buhui to exhaust fully owing to charge mismatch.Figure 61 A illustrates the exemplary embodiment of the charge balance MOSFET 6100 of an induction by current structure 6115 with planar gate and isolation.In this embodiment, charge balance structure is included in opposite conductivities (being the p type in this example) post 6126 that forms in the drift region (n type) 6104.For example, p type post 6126 can form with doped polycrystalline silicon or extension filling groove.Shown in Figure 61 A, charge balance structure keeps continuity 6115 times in the induction by current structure.The induction liner metal 6113 that covers current response device 6115 surface regions is separated with source metal 6116 electronically by dielectric regime 6117.Should be understood that the induction by current device with analog structure can carry out integrated with any any other power device described herein.For example, Figure 61 B shows the induction by current device and how to carry out integrated example with the groove MOSFET with dhield grid, can obtain charge balance by the shielding polysilicon of regulating in gash depth and the biasing groove.
There are many expectations that diode and power transistor are integrated in power application on the same die.Such application comprises temperature sense, Electrostatic Discharge protection, source clamper and voltage division wherein.For example, for temperature sense, one or more diode in series are integrally integrated with power transistor, and the anode of diode and cathode terminal are used to separate bond pad (bond pad) whereby, perhaps use conductive interconnection to be connected to whole control circuit parts.The variation of the forward voltage (Vf) by diode comes temperature sensor.For example, have suitable interconnecting, because the Vf of diode makes that grid voltage is dragged down, to reduce to flow through the electric current of device, until reaching desired temperatures along with temperature reduces with the gate terminal of power transistor.
Figure 62 A illustrates the exemplary embodiment of the MOSFET 6200A with series connection temperature sensing diode.MOSFET 6200A comprises diode structure 6215, wherein, has the alternately temperature sense diode of three series connection of doped polycrystalline silicon formation of conductivity.In this exemplary embodiment, the MOSFET of device 6200A partly uses the charge balance groove of the p type extension filling that forms the opposite conductivities district in n type extension drift region 6204.As shown in the figure, preferably, charge balance structure is the maintenance continuity below temperature sense diode structure 6215.Diode structure is formed on the top of field dielectric (oxidation) layer 6219 on the silicon face top.P type knot isolated area 6221 can be at random in 6219 times diffusions of dielectric layer.At the device 6200B that does not have this p type knot shown in Figure 62 B.In order to confirm to obtain the diode of forward-, series biasing, use short circuit metal 6223 so that back-biased P/N+ is tied short circuit.In one embodiment, pass this knot and carry out p+ injection and diffusion,, wherein, the ohmic contact that p+ is improved occurs 6223 times at the short circuit metal to form the N+/P/P+/N+ structure.For the opposite polarity N+ that also can pass the diffusion of N/P+ knot, to form the P+/N/N+/P+ structure.Equally, it should be appreciated by those skilled in the art that such temperature sense diode can use in any various power devices in conjunction with many other features described herein.For example, Figure 62 C illustrates the MOSFET 6200C with shield trenches grid structure, and wherein, bucking electrode can be used for charge balance.
In another embodiment, by using and similar isolation technology shown in the device 6200 that is used for the temperature sense diode, realized asymmetric esd protection.For the purpose of esd protection, an end of diode structure is electrically connected to source terminal, and the other end is connected to the gate terminal of device.Alternatively, shown in Figure 63 A and 63B, connect the N+/P/N+ knot by any back of the body of not short circuit and obtain symmetrical esd protection.Exemplary MOSFET 6300A shown in Figure 63 A uses planar gate, and is used for the opposite conductivities post of charge balance, and the exemplary MOSFET 6300B shown in Figure 63 B is the trench-gate device with shielded gate structure.In order to prevent inhomogeneous in the charge balance, charge balance structure at grid in conjunction with extension below pad metal and any other control element bond pad.
Figure 64 A shows exemplary esd protection circuit to Figure 64 D, wherein, can be to use the power device any described herein of any charge balance or other technologies by above-mentioned diode structure protection main device, grid.Figure 64 A illustrates the reduced graph of the polysilicon diode esd protection of symmetry isolation, and Figure 64 B shows the polysilicon diode esd protection circuit that the standard back of the body connects isolation.Esd protection circuit shown in Figure 64 C is used for BV CerThe fast NPN transistor of recovering.BV CerIn subscript " cer " represent back-biased collector electrode-emitter bipolar transistor duct ligation, wherein, use resistance to control base current to the connection of base stage.Low ESR makes most of emitter current move by base stage, prevents the EB junction conducting, just, injects minority carrier and returns collector electrode.Can turn-on condition be set by resistance value.When charge carrier is injected into when returning collector electrode, the sustaining voltage between the emitter and collector reduces-is called " the fast recovery " phenomenon.Can be by adjusting base stage-collector resistance R BEValue BV is set CerThe electric current that fast recovery is triggered.Figure 64 D show use thyristor or SCR and shown in the esd protection circuit of diode.By using grid negative electrode short-circuit structure, can control trigger current.The diode breakdown voltage SCR that can be used to setover latchs voltage.The diode structure of above-mentioned integral body can use in these or other any esd protection circuit.
In some power application, the important performance characteristics of device for power switching is the ESR of its equivalent series resistance or measuring switch terminal or grid impedance.For example, in the synchronous buck converter that uses power MOSFET, lower ESR helps to reduce switching loss.Under the situation of trench gate mosfet, its grid ESR is determined by the size of the groove of filling polysilicon to a great extent.For example, the length of gate trench can be passed through packages limits (for example, minimum wire bond bond pad size) and limits.As everyone knows, polysilicon is used silicide film and can reduce resistance.Yet, in groove MOSFET, use silicide film a lot of problems to occur.In the discrete MOS structure in typical plane, after tying the degree of depth that has been injected into and has been driven into separately, grid polycrystalline silicon can be by silication., used silicide and become complicated more by recessed trench-gate device for grid polycrystalline silicon.The use limited maximum temperature of conventional salicide, wafer can stand approximately the quick silicidation less than 900 ℃.When forming diffusion region (for example, source electrode, drain electrode and trap), this is provided with very big restriction to process for making.The most typical metal that is used for silication is a titanium.Other metals such as tungsten, tantalum, cobalt and platinum also can be used for the quick silicidation of higher heat budget, and bigger process range is provided.Can also reduce grid ESR by various designing techniques.
The various embodiment that are used to form the charge balance device for power switching with lower ESR are described below.In an embodiment shown in Figure 65, process 6500 comprises forming to have for shielding and/or charge balance purpose and forms groove (step 6502) than low electrode in the groove bottom.Then be deposition and etching IPD layer (step 6504).Can form the IPD layer by known technology.Alternatively, above-mentioned any technology in conjunction with Figure 45 to 50 can be used to form the IPD layer.Next, in step 6506, use processes well known deposition and etching upper electrode or grid polycrystalline silicon.Then be to inject and driving trap and source area (step 6508).In the step 6510 after the step 6508, silicide is applied to grid polycrystalline silicon.Then, in step 6512, deposition and complanation dielectric layer.In the change of this technology, at first carry out the step 6512 of deposition and complanation dielectric layer, after forming silicide contacts, open contact hole and arrive source/body and grid then.These two embodiment rely on the heavy doping main body injection region of activating by the process annealing that is lower than the silicide film transition point.
In another embodiment, polysilicon gate is replaced by metal gates.According to this embodiment, Ti forms metal gates by using the source electrode of aiming at for example to deposit, to improve the filling capacity in the groove structure.After the applied metal grid, in case injected and drive knot, dielectric is selected to comprise and HDP and TEOS is kept apart so that grid is contacted with source/body.In optional embodiment, ripple and dual damascene method with various metals selections from aluminium to copper are used to form gate terminal.
The layout of grid conductor also can influence the master switch speed of grid ESR and device.In another embodiment shown in Figure 66 A and the 66B, topology is with vertical siliconized surfaces polysilicon rectangular (stripe) and chase groove polysilicon combination reducing grid ESR.With reference to Figure 66 A, the device architecture of highly simplifying 6600 is shown, wherein, the polysilicon lines 6604 that silicide applies extends along the silicon face perpendicular to groove rectangular 6602.Figure 66 B illustrates along the simplification sectional view of the device 6600 of AA ' axle.Silicification polysilicon line 6604 is contacting grid polycrystalline silicon with the infall of groove.A plurality of silication polycrystalline lines 6604 can extend at the end face of silicon face, to reduce the resistivity of gate electrode.For example, make this and other topologies become possibility, can be used for the grid ESR that improves at any trench-gate device described herein by processing with two or more interconnection layers.
Circuit application
For example, owing to significantly reducing of the break-over of device resistance that provides by various devices described herein and technology, can reduce the chip region that takies by power device.As a result, these the whole integrated of high tension apparatus with low voltage logic and control circuit become more feasible.In typical circuit application, can comprise power control, induction, protection and interface circuit with various types of functions that power device is integrated on the same die.In the whole major issue in integrated of power device and other circuit is to be used for the technology of high voltage power device with low voltage logic or the isolation of control circuit electricity.Exist many known method to realize, comprise knot isolation, dielectric isolation, insulator silicon (silicon-on-insulator) etc.
Below, use describing many electric currents that are used for power switch, wherein, various galvanic elements can be integrated on the identical chip.Figure 67 illustrates the synchronous buck converter (DC-DC transducer) that requires lower voltage devices.In this circuit, n channel mosfet Q1 (being commonly called " high-side switch ") is designed to have the low on-resistance of appropriateness but fast switching speed is arranged, with minimum power losses.MOSFET Q2 (being commonly referred to " low side switch ") is designed to have the high switching speed of low-down conducting resistance and appropriateness.Figure 68 illustrates another DC-DC transducer that is more suitable for being used for high tension apparatus.In this circuit, main switching device Qa demonstrates fast switching speed and high blocking voltage.Because this circuit uses transformer,, make it have suitable conducting resistance so less electric current flows through transistor Qa.For synchronous rectifier Qs, can use have low-down conducting resistance, the MOSFET of electric capacity between fast switching speed, low-down QRR and low electrode.Other embodiment and to the improvement of this DC-DC transducer U.S. Patent application the 10/222nd at the common transfer that is entitled as " Methods and Circuit for Reducing Losses in DC-DCConverters " of Elbanhawy, be described in detail in No. 481 (acting on behalf of case 18865-91-1/17732-51430), its full content is hereby expressly incorporated by reference.
Any MOSFET that can be used for the converter circuit of Figure 67 and 68 of above-mentioned various power devices.For example, the bigrid MOSFET type shown in Fig. 4 A is to provide a type of certain benefits when realizing synchronous buck converter when being used in.In one embodiment, special driving is provided with all features that utilization is provided by bigrid MOSFET.The example of this embodiment shown in Figure 69, wherein, the current potential of the first grid terminal G2 of high side MOSFET Q1 is determined by the circuit of being made up of diode D1, resistance R 1 and R2 and capacitor C 1.The fixed potential at the gate terminal G2 place of Q1 can be adjusted to best Q Gd, with optimization transistorized switching time.The second grid terminal G1 of high side MOSFET Q1 receives common gate drive signal from pulse-width modulation (PWM) controller/driver (not shown).As shown in the figure, two of lower switching transistor Q2 gate electrodes are driven similarly.
In optional embodiment, at example shown in Figure 70 A, two gate electrodes of high-side switch are driven respectively, further to make the circuit performance optimum.According to this embodiment, gate terminal G1 and the G2 of different drive waveform high-side switch Q1 are to realize the best conducting resistance of device during switching speed that transition period is best and the rest period.Shown in an example in, carry low-down Q for the grid of high-side switch Q1 at about 5 volts voltage of transition period Gd, cause high switching speed, but before transitional period td1 and td2 and afterwards, R DSonNot at its minimum.Yet, because at transition period R DSonNot significant loss side, so this can't produce adverse influence to the operation of circuit.In order during remaining pulse persistance, to guarantee minimum R DSon, the current potential V at gate terminal G2 place G2Bring up to the second voltage Vb, wherein, at the time t shown in the sequential chart of Figure 70 B pThe second voltage Vb is higher than Va during this time.This driving design has realized optimum efficient.To the U.S. Patent application 10/686th of this driving design change in the common registration that is entitled as " Driver for Dual GateMOSFETs " of Elbanhawy, carried out more detailed description in No. 859 (acting on behalf of case 17732-66930), its full content is hereby expressly incorporated by reference.
Encapsulation technology
Major issue for all power semiconductors is shell or the encapsulation that is used for device is connected to circuit.Semiconductor element generally uses the metallic bond coat (for example, welding) or the epoxy adhesive of filling metal to be connected to metal pad.Lead generally adheres to the top of chip, then, makes that projection by molded main body.Then, this assembling is installed in circuit board.Shell provides electricity and the hot link between semiconductor chip and electronic system and the surrounding environment thereof.Low dead resistance, electric capacity and inductance are the desired electrical characteristics for the shell that can realize better being connected with chip.
The improvement of the encapsulation technology that has proposed mainly concentrates on resistance and the inductance in reducing to encapsulate.In specific encapsulation technology, soldered ball or copper button are distributed in relatively approaching on the metal surface of (for example, 2-5 μ m) of chip.Connect by distribution metal on the large tracts of land of metal surface, it is shorter that the current path in the metal is done, and reduced metallic resistance.Be connected to the copper conductor frame or be connected to copper cash on the printed circuit board as the convex side of fruit chip, compare, reduced the resistance of power device with wire bonding method.
Figure 71 and 72 illustrates the simplification sectional view of molded and non-molded package respectively, uses the soldered ball or the copper button that lead frame are connected to the metal surface of chip.Molded package 7100 shown in Figure 71 comprises lead frame (leadframe) 7106, and it is connected to first side of tube core 7102 by soldered ball or copper button 7104.Second side away from the tube core 7102 of lead frame 7106 is exposed by moulding material.In typical Vertical power transistors, second side of tube core forms drain terminal.Second side of tube core can be formed into the direct electrical connection of pad on circuit board, therefore provide low-impedance heat and power path for tube core.Such encapsulation and change thereof are at the U.S. Patent application the 10/607th of people's such as Joshi the common transfer that is entitled as " Flip Chip in Leaded Molded Package andMethod of Manufacture Thereof ", carried out more detailed description in No. 633 (acting on behalf of case 18865-42-1/17732-1342), its full content is hereby expressly incorporated by reference.
Figure 72 illustrates the non-molded embodiment of encapsulation 7200.In the exemplary embodiment shown in Figure 72, encapsulation 7200 has multilager base plate 7212, and it comprises basic unit 7220 (for example, being made up of metal) and the metal level 7221 that separates by dielectric layer 7222.Welding Structure 7213 (for example, soldered ball) is connected to substrate 7212.Tube core 7211 is connected to substrate 7212, and Welding Structure 7213 is arranged on around the tube core.Tube core 7211 can connect material (for example, scolder 7230) by tube core and be connected to substrate 7212.After encapsulation shown in forming, be squeezed and be installed on circuit board (not shown) or other circuit substrates.In the embodiment that Vertical power transistors is made on tube core 7211, soldered ball 7230 forms drain terminal and connects, and chip surface forms source terminal.Can also realize the counter-rotating connection by counter-rotating tube core 7211 to the connection of substrate 7212.As shown in the figure, encapsulation 7200 is very thin and non-molded, so do not need moulding material.Be used for the U.S. Patent application 10/235th of such non-molded package at the common transfer that is entitled as " Unmolded Package for a Semiconductor device " of Joshi, carried out more detailed description in No. 249 (acting on behalf of case 18865-007110/17732-26390.003), its full content is incorporated into this.
The upper surface that has proposed chip is directly connected to the optional method of copper by scolder or conductive epoxy resin.Because the stress that causes between copper and the silicon is along with chip region increases, so directly method of attachment may be limited, because scolder or epoxy resin interface only can be pressed the sort of degree before destroying.On the other hand, raised pad makes realized more replacements before destroying, and had shown with very large chip and work.
Another important problem is heat radiation in package design.The improvement of power semiconductor performance causes littler chip region usually.Do not increase as the power loss in the fruit chip, the centralized heat energy on smaller area can produce higher temperature and descend reliably so.The method that increases the outer heat transfer ratio of encapsulation comprises the quantity that reduces hot interface, use and have more the material of high-termal conductivity and the thickness that reduces layer (for example, silicon, scolder, tube core are fixed and tube core anchor pad).Rajeev Joshi be entitled as " Semiconductor Die PackageWith Improved Thermal and Electrical Performance; " the United States Patent (USP) the 6th of common transfer, 566, the solution of heat dissipation problem has been discussed, especially about comprising the tube core of the vertical power mosfet that is used for the RF application in No. 749.Be used to improve the United States Patent (USP) 6th of the other technologies of total encapsulation performance at the common transfer of Rajeev Joshi, 133, No. 634 and the 6th, 469, No. 384, and describe in detail in people's such as Joshi the U.S. Patent application the 10/271st, 654 (acting on behalf of case 18865-99-1/17732.53440) that is entitled as " Thin Thermally EnhancedFlip Chip in a Leaded Molded Package " number.Should be understood that any can being contained in any encapsulation described herein or any other the suitable encapsulation in the various power device described herein.
Use the shell areas that are used to dispel the heat also to increase the ability that shell keeps lower temperature more, for example, the hot interface of cover top portion and bottom.The surface area of the increase that combines with these surface air-flows has on every side increased rate of heat dispation.Housing designs can also be connected with external heat sink easily.Because heat conduction and infrared radiation technology are commonsense methods, so alternately the application of cooling means is fine.For example, U.S. Patent application the 10/408th at the common transfer that is entitled as " Power CircuitryWith A Thermionic Cooling System " of Reno Rossetti, being described thermionic emission in 471 (the acting on behalf of case 17732-6672) number is a kind of method that can be used for the heat radiation of cooling power device, and its full content is hereby expressly incorporated by reference.
The integrated other problems that brought that in single encapsulation, comprises the logical circuit of power output and controlled function.One, shell need more pins to be connected with other electric function.Encapsulation should be considered interconnecting of high current power and interconnecting of low current signal in the encapsulation.The various encapsulation technologies that can address these problems comprise: chip is to chip (chip-to-chip) wire bonding, to eliminate special connection pads; Stacked die (chip-on-chip) is to save the space in the shell; And multi-chip module, its permission is attached to different silicon technologies in the single electric function.The various embodiment of multicore sheet encapsulation technology are at the U.S. Patent application the 09/730th of the common transfer that is entitled as " Stacked Package Using Flip in LeadedMolded Package Technology " of Rajeev Joshi, No. 932 (acting on behalf of case 18865-50/17732-19450), and be the 10/330th of being entitled as of RajeevJoshi " Multichip Module Including Substrate with an Array ofInterconnect Structures " equally, be described in No. 741 (acting on behalf of case 18865-121/17732-66650.08), its full content is hereby expressly incorporated by reference.
Though the complete description to the preferred embodiment of the present invention is provided above, many replacements, to revise and be equal to all be feasible.For example, in this article, many charge balance techniques are at MOSFET, especially are described under the situation of groove gate type MOSFET.It is to be appreciated that those skilled in the art that and identical technology can be applied in the device and transversal device of the other types that comprise IGBT, thyristor, diode and plane MOSFET.Therefore, for these and other reasons, more than describing not is to be used to limit the scope of the invention defined by the claims.

Claims (32)

1. semiconductor device comprises:
The drift region of first conduction type;
Well region extends on described drift region, and has second conduction type with described first conductivity type opposite;
Active groove, pass described well region extension and extend into described drift region, sidewall and bottom along described active groove are provided with dielectric material, and described active groove is filled with first screening conductive layer and the grid conducting layer, the described first screening conductive layer is arranged under the described grid conducting layer, and separate with described grid conducting layer by dielectric material between electrode, wherein said grid conducting layer with the stack of described drift region;
Source area has described first conduction type, and it is formed in the described well region adjacent with described active groove; And
Electric charge control groove more in depth extends in the described drift region than described active groove, and is filled with the material that is used in the vertical electric charge control of described drift region.
2. semiconductor device according to claim 1 wherein, along described electric charge control groove dielectric materials layer is set, and described electric charge control trench fill has electric conducting material.
3. semiconductor device according to claim 2, wherein, the source electrode is electrically connected to described source area with the described electric conducting material in the described electric charge control groove.
4. semiconductor device according to claim 1 wherein, is filled in the described electric charge control groove material and is made up of a plurality of conductive layers, and described a plurality of conductive layer vertical stackings are also separated from one another and separate with described trenched side-wall by dielectric material.
5. semiconductor device according to claim 4 wherein, is electrically biased at the described a plurality of conductive layers in the described electric charge control groove, so that the vertical electric charge balance to be provided in described drift region.
6. semiconductor device according to claim 5, wherein, the described a plurality of conductive layers in described electric charge control groove are configured to independent biasing.
7. semiconductor device according to claim 4, wherein, the thickness difference of the described a plurality of conductive layers in described electric charge control groove.
8. semiconductor device according to claim 4, wherein, the thickness of the first more deep conductive layer is less than the thickness that is arranged on second conductive layer on described first conductive layer in described electric charge control groove.
9. semiconductor device according to claim 1, wherein, the described first screening conductive layer in the described active groove is configured to electrical bias to the expectation current potential.
10. semiconductor device according to claim 1, wherein, the described first screening conductive layer is electrically connected to identical current potential with described source area.
11. semiconductor device according to claim 1, wherein, described active groove also comprises the secondary shielding conductive layer that is arranged under the described first screening conductive layer.
12. semiconductor device according to claim 11, wherein, the described first screening conductive layer is different with the thickness of secondary shielding conductive layer.
13. semiconductor device according to claim 11, wherein, described first screening conductive layer and secondary shielding conductive layer are configured to independent biasing.
14. semiconductor device according to claim 1, wherein, described electric charge control trench fill has dielectric material.
15. semiconductor device according to claim 14 also comprises the lining of second electric conducting material that extends along the lateral wall of described electric charge control groove.
16. semiconductor device according to claim 1, table top and the described electric charge control trench isolations of the second adjacent electric charge control groove by being formed with Schottky junction structure on it.
17. a semiconductor device comprises:
The drift region of first conduction type;
Well region extends on described drift region, and has second conduction type with described first conductivity type opposite;
Active groove, pass described well region extension and extend into described drift region, in described active groove, form the main grid utmost point of making by electric conducting material and the inferior grid of making by electric conducting material, and it is separated from one another and separate with described trenched side-wall by dielectric materials layer, the described main grid utmost point is on described grid, described active groove also has first bucking electrode of being made by electric conducting material, and it is arranged under described grid and by dielectric material and separates with described grid; And
Source area has described first conduction type, and it is formed in the described well region adjacent with described active groove, and
The drain region is positioned at described source area opposite, and is under the described drift region.
18. semiconductor device according to claim 17, wherein, the described main grid utmost point and described grid are configured to independent electrical bias.
19. semiconductor device according to claim 18, wherein, described grid is in the constant potential place biasing that is the threshold voltage of described semiconductor device.
20. semiconductor device according to claim 18, wherein, described time grid is being setovered greater than the current potential place that is applied to described source area current potential.
21. semiconductor device according to claim 18, wherein, described grid was connected to the current potential into the described threshold voltage of described semiconductor device before switch motion.
22. semiconductor device according to claim 17, wherein, described first bucking electrode is configured to independently be biased to the expectation current potential.
23. semiconductor device according to claim 17, wherein, described active groove also comprises one or more additional mask electrodes except that described first bucking electrode, and it is stacked under described first bucking electrode.
24. semiconductor device according to claim 23, wherein, described first bucking electrode is different with the size of described one or more additional mask electrodes.
25. semiconductor device according to claim 17 also comprises electric charge control groove, it extends into described drift region and is filled with the material that is used in the vertical electric charge control of described drift region.
26. semiconductor device according to claim 25, wherein, the source electrode is electrically connected to described source area with the electric conducting material in the described electric charge control groove, and wherein, described electric conducting material is the material of filling described electric charge control groove and being used for controlling at the vertical electric charge of described drift region.
27. semiconductor device according to claim 25, wherein, the material that is filled in the described electric charge control groove is made up of a plurality of conductive layers, and described a plurality of conductive layer vertical stackings are separated from one another and separate with described trenched side-wall by dielectric material.
28. semiconductor device according to claim 27, wherein, the described a plurality of conductive layers in the described electric charge control of the electrical bias groove are to provide the vertical electric charge balance in substrate.
29. semiconductor device according to claim 28, wherein, the described a plurality of conductive layers in the described electric charge control groove are configured to independent biasing.
30. semiconductor device according to claim 27, wherein, the size difference of the described a plurality of conductive layers in the described electric charge control groove.
31. semiconductor device according to claim 30, wherein, the size that is deep into the conductive layer in the described electric charge control groove more is less than the size that is arranged on the conductive layer on this conductive layer.
32. semiconductor device according to claim 17 also comprises: second groove is adjacent with described active groove; And Schottky junction structure, be formed between described active groove and described second groove.
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