TWI399855B - Power semiconductor devices and methods of manufacture - Google Patents

Abstract

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Description

Power semiconductor component and method of manufacturing the same (1) Cross-reference to related applications

This application claims the benefit of the following provisional filing of a U.S. Patent Application: No. 60/533,790 (Attorney Docket No. 18865-133/17732-67260) entitled "Power Semiconductor Components and Methods of Making Same", Subsidiary Ashok et al., filed on December 30, 2003; this application is part of the following joint US patent application: No. 10/640,742 (Office Case No. 90065.000241/17732- 66550), entitled "Modified MOS Gateway Method for Reduced Miller Capacitance and Switching Losses", Kocon et al., filed August 14, 2003; No. 10/442,670 (Business Case No. 18865-131/17732-66850, entitled "Structure and Method for Forming a Channel MOSFET with Self-Alignment Characteristics", by Herrick, submitted May 20, 2003 This application is related to the following commonly assigned U.S. Patent Application Serial No. 10/155,554 (Attorney Docket No. 18865-17-2/17732-7226.001), entitled "Field Effect Transistor and Method of Making Same Mo Mo et al., filed May 24, 2002; No. 10/209,110 (Office Case No. 18865-98/17732- 55270), titled "Double-Channel Power MOSFET", Sapp, 2002 Submitted on July 30, 2007; No. 09/981,583 (Office Case No. 18865-90/17732-51620), entitled "Semiconductor Structure with Improved Small Forward Loss and High Resistivity", Kocon, submitted on October 17, 2001; No. 09/774,780 (Office Case No. 18865-69/17732-26400), entitled "Field Effect Transistor with Side-Lowing Structure" , Marchant, submitted on January 30, 2001; No. 10/200,056 (Office Case No. 18865-97/17732-55280), entitled "Vertical Charge Control Semiconductor Components with Low Output Capacitance "Sapp" et al., filed July 18, 2002; No. 10/288,982 (Office Case No. 18865-117/17732-66560), entitled "Drift Zone Higher Resistance to Lower Positive" To the voltage drop semiconductor structure, Kocon et al., filed November 5, 2002; No. 10/315,719 (Office Case No. 90065.051802/17732-56400), entitled "Isolation Planarity Or current sensing on a channel stripe power element while maintaining a continuous stripe unit cell," Yedinak, filed December 10, 2002; No. 10/222,481 The company's case No. 18865-91-1/17732-51430), entitled "Methods and Circuits for Reducing Losses in DC-DC Converters", Elbanhawy, August 16, 2002 Japanese Patent Application No. 10/235,249 (Office Case No. 18865-71-1/17732-26390-3), entitled "Unmolded Package for a Semiconductor Component", Joshi, Submitted on September 4, 2002; and No. 10/607,633 (Office Case No. 18865-42-1/17732-13420), entitled "Flip Chip in Leaded Molded Package and Method of Manufacturing the Same", Joshi et al. Person, filed June 27, 2003; all of the above-identified applications are hereby incorporated by reference in entirety.

Background of the invention

SUMMARY OF THE INVENTION The present invention is generally directed to semiconductor devices, and more particularly to various embodiments and methods of fabricating the same for improved power semiconductor components such as transistors and diodes, and to packages and circuits including such power semiconductor components.

The key components of power electronics applications are solid state switches. From ignition control in automotive applications to battery-operated consumer electronic components, in order to supply power to converters in industrial applications, a power switch that best meets the needs of a particular application is needed. Solid-state relationships, such as power metal oxide semiconductor field effect transistors (power MOSFETs), insulated gate bipolar transistors (IGBTs), and various types of thyristors, are continually evolving to meet this need. In the case of a power MOSFET, for example, a lateral path has been developed (e.g., U.S. Patent No. 4,682,405 to Blanched et al.), and a channel gate structure (U.S. Patent No. 6,429,481, issued to Mo et al.). Double diffused structure (DMOS) and various techniques for balancing charge in the drift region of the transistor (for example, US Patent No. 4,941,026 to Temple, 5,216,275 to Chen, and Neilson) 6,081,009), and has many other techniques to address different and often competing performance requirements.

The definition of the power switch is based on the performance characteristics of its on-resistance, breakdown voltage, and switching speed. Depending on the needs of a particular application, a different emphasis is placed on each of these performance criteria. For example, for power applications greater than about 300-400 volts, the IGBT exhibits a congenitally low on-resistance compared to the power MOSFET, but its switching speed is lower due to the slower turn-off characteristics. Therefore, for applications requiring a low on-resistance with a low switching frequency of greater than 400 volts, IGBTs are preferred switches, while power MOSFETs are often the preferred component for relatively high frequency applications. If the frequency requirement for a given application specifies the type of switch used, the voltage demand determines the structural configuration of the particular switch. For example, in the case of power MOSFETs, improving the voltage performance of the transistor while maintaining a low R _DSon poses a challenge because of the proportional relationship between the _接通-to- source on-resistance R _DSon and the breakdown voltage. Various charge balancing structures in the drift region of the crystal have been developed to address this challenge with varying degrees of effectiveness.

Component performance parameters are also affected by die packaging and processing. Attempts have been made to address some of these challenges by developing a variety of different improved processing and packaging techniques.

Whether in ultra-portable consumer electronic components or routers and hubs for communication systems, the power-on relationship continues to increase with a wide range of applications as the electronics industry expands. Therefore, the power switch is still a semiconductor component with high development potential.

Summary of invention

The present invention provides various embodiments for power components and their manufacture Methods, packages, and circuits comprising such power components for a wide variety of power electronics applications. Broadly speaking, one aspect of the present invention incorporates several charge balancing techniques and other techniques for reducing parasitic capacitance to achieve power components with improved voltage performance, higher switching speeds, and lower on-resistance. Different embodiments. Another aspect of the present invention provides improved termination structures for low, medium and high voltage components. Methods of fabricating improved power components are provided in accordance with other aspects of the present invention. Various embodiments of the present invention provide improvements in specific process steps such as shaping of the trench, formation of a dielectric layer on the inside of the trench, formation of the mesa structure, and reduction of substrate thickness and other program steps. According to another aspect of the invention, the charge balanced power component comprises temperature and current sensing components such as diodes on the same die. Other aspects of the invention are improved for equivalent series resistance (ESR) or gate resistance of a power component, including additional circuitry on the same wafer as the power component and providing improved packaging for the charge balanced power component.

These and other aspects of the invention are described in more detail below in conjunction with the drawings.

Simple illustration

1 shows a cross-sectional view of a portion of an exemplary n-channel power MOSFET; FIG. 2A shows an exemplary embodiment of a dual channel power MOSFET; and FIG. 2B shows a structure with a source shielded trench An exemplary embodiment of a planar gate MOSFET; Figure 3A shows a portion of an exemplary embodiment of a shielded gate channel power MOSFET; Figure 3B shows a dual-channel structure incorporating Figure 2A and a shielded gate structure of Figure 3A for a shielded gate channel An alternative embodiment of a power MOSFET; FIG. 4A is a simplified partial view of an exemplary embodiment of a dual gate channel power MOSFET; FIG. 4B shows a planar dual gate structure and a channel electrode for vertical An exemplary power MOSFET for charge control; Figure 4C shows an exemplary implementation of a power MOSFET incorporating one of the double gate and shielded gate technologies on the same channel; Figures 4D and 4E are for a deep body A cross-sectional view of an alternative embodiment of a structured power MOSFET; Figures 4F and 4G show the effect of the trench-type deep body structure on the potential line distribution inside the power MOSFET near the gate electrode; Figures 5A, 5B, and 5C are A cross-sectional view showing a portion of an exemplary power MOSFET having various vertical charge balancing structures; and FIG. 6 is a simplified cross-sectional view showing a power MOSFET incorporating an exemplary vertical charge control structure and a shielded gate structure Figure 7 shows a simplified cross-sectional view of another power MOSFET incorporating an exemplary vertical charge control structure and a double gate structure; Figure 8 shows a vertical charge control structure and an integrated Schottky diode (Schottky diode) An example of a shielded gate power MOSFET; Figures 9A, 9B, and 9C depict power with integrated Schottky diodes Various exemplary embodiments of MOSFETs; Figures 9D, 9E, and 9F show exemplary layout variations for spreading Schottky diode cells within an active cell array of a power MOSFET; Figure 10 provides a A simplified cross-sectional view of an exemplary channel power MOSFET with a buried diode charge balancing structure; Figures 11 and 12 respectively show a power MOSFET incorporating a shielded gate and dual gate technology with buried diode charge balance. Exemplary Embodiment; Figure 13 is a simplified cross-sectional view of a planar planar power MOSFET incorporating one of the embedded dipole charge balancing techniques and an integrated Schottky diode; Figure 14 shows a flow for current flow A simplified embodiment of an exemplary cumulative mode power transistor in alternating parallel conducting regions; Figure 15 is a simplified diagram of another cumulative mode component having a channel electrode based on charge dispersion use; A simplified diagram of a dual channel accumulative mode component; Figures 17 and 18 show exemplary accumulation mode components for a dielectric filled channel containing an outer pad of opposite polarity. Simplified embodiment; FIG. 19 is another simplified embodiment of an accumulation mode element employing one or more buried diodes; and FIG. 20 is an exemplary diagram including a heavily doped opposite polarity region along the surface of the crucible A simplified isometric view of the cumulative mode transistor; Figure 21 shows an alternating opposite polarity region in the voltage sustaining layer A simplified example of a super junction power MOSFET; FIG. 22 shows an exemplary embodiment of a super junction power MOSFET having islands of opposite polarity distributed in a vertical direction in the voltage sustaining layer; layers 23 and 24 are respectively shown An exemplary embodiment of a super junction power MOSFET having a dual gate and shielded gate structure; Figure 25A shows a top view of the active and termination channel layout for a channel transistor; and Figure 25B-25F shows a trench A simplified layout of an alternative embodiment of a track termination structure; FIGS. 26A-26C are cross-sectional views of an exemplary channel termination structure; and FIG. 27 shows exemplary components of a termination channel having a large radius of curvature; 28A-28D A cross-sectional view of a termination region having a purlin column charge balancing structure; FIGS. 29A-29C are cross-sectional views of an exemplary embodiment of an ultra high voltage component employing a super junction technique; and FIG. 30A is a diagram showing a channel component Examples of edge contact; FIGS. 30B-30F show exemplary procedural steps for an edge contact structure of a channel element; and FIG. 31A is an active area contact structure for a multi-embedded polysilicon layer Example; FIG. 31B-31M show a first for forming a channel for one of the active region masked with a contact structure of the exemplary program flow; one active area shield contact structure of a first alternative graph for 31N A cross-sectional view of an embodiment; FIGS. 32A and 32B are layout views of an exemplary channel element having an active area shield contact structure; and FIGS. 32C-32D are for use in a channel element having a ruptured channel structure A simplified layout of two embodiments in which the peripheral channel is in contact; FIG. 33A is an alternative embodiment for contacting the trench shielding polysilicon layer in the active region; and FIGS. 33B-33M are shown to be in contact with the 33A An example of a program flow of an active area shield structure of the type shown; Figure 34 shows an epitaxial layer having a spacer or buffer (barrier) layer to reduce the thickness of the epitaxial drift region; An alternative embodiment of an element having a barrier layer; Figure 36 shows a barrier layer using a deep body-elongation junction to minimize the thickness of the epitaxial layer; and Figure 37 is a diffusion barrier layer A simplified example of a well-drift junction of a transistor; Figures 38A-38D show a simplified program flow of a self-aligned epitaxial-well channel element with an embedded electrode; 39A-39B The figure shows one for a bevel An exemplary flow of well implants; Figures 40A-40E show an example of a self-aligned epitaxial well program; 40R-40U shows a method for reducing substrate thickness; and Figure 41 shows a use a chemical process as the final thinning step An example of a sequence flow; panels 42A-42F show examples of improved etching procedures; and panels 43A and 43B show an embodiment of a channel etching procedure that eliminates bird's beak problems; 44A and 44B An alternative etch process is shown; Figures 45A-45C show a procedure for forming an improved inter-poly dielectric layer; and Figures 46A, 46B and 46C show an example for forming an IPD layer. Alternative Method; Figures 47A and 47B are cross-sectional views of another method for forming a high quality interstitial polysilicon dielectric layer; and Figs. 48 and 49A-49D show other embodiments for forming a modified IPD layer. Figure 50A shows an anisotropic plasma program for IPD planarization; Figure 50B shows an alternative IPD planarization method using a chemical mechanical program; and Figure 51 shows an exemplary control flow rate. A flow chart of the method; Figure 52 shows an improved method of forming a thick oxide at the bottom of a channel using a primary atmospheric chemical vapor deposition process; and Figure 53 is a process using a directional tetraethyl citrate procedure. At the bottom of a channel An exemplary method of forming the thick oxide flowchart; 54 and FIG. 55 shows another for forming a thick bottom oxide of the embodiment; Figures 56-59 show another procedure for forming a thick dielectric layer at the bottom of a trench; Fig. 60 is a simplified diagram of a MOSFET having a current sensing element; and Fig. 61A shows a plane having a plane An example of a charge balancing MOSFET having a gate structure and an isolated current sensing structure; FIG. 61B shows an example of integrating a current sensing element with a channel MOSFET; and FIGS. 62A-62C are shown for An alternative embodiment of a MOSFET of a series temperature sensing diode; Figures 63A and 63B show an alternative embodiment for a MOSFET with ESD protection; and Figures 64A-64D show an example of an ESD protection circuit; The figure shows an exemplary procedure for forming a charge-balanced power component with a lower ESR; panels 66A and 66B show a layout technique for reducing ESR; and Figure 67 shows a DC-DC converter using power switching. Circuitry; Figure 68 shows another DC-DC converter circuit using power switching; Figure 69 shows an exemplary driver circuit for a dual-gate MOSFET; Figure 70A shows an alternative to a gate electrode that is driven separately Sexual embodiment; Figure 70B A timing diagram illustrating the operation of the circuit of FIG. 70A is shown; and FIG. 71 is a simplified cross-sectional view of a molded package; Figure 72 is a simplified cross-sectional view of an unmolded package.

Detailed description of the preferred embodiment

The power switch can be implemented by power MOSFETs, IGBTs, various types of thyristors, and the like. Many of the novel techniques presented herein are described in terms of power MOSFETs for illustrative purposes. However, it should be understood that the various embodiments of the invention described herein are not limited to power MOSFETs and are applicable to other types of power switching technologies including IGBTs and other types of bipolar switches and various types of thyristors and Many of the polar bodies. Also, various embodiments of the present invention are shown to include specific p and n-type regions based on illustrative uses. Those skilled in the art will appreciate that the teachings herein are equally applicable to elements in which the conductivity of each zone is reversed.

Referring to Figure 1, a cross-sectional view of a portion of an exemplary n-channel power MOSFET 100 is shown. As with all other figures described herein, it is understood that the relative dimensions and dimensions of the various components and components shown in the figures do not accurately reflect the actual dimensions and are merely illustrative. The trench MOSFET 100 includes a gate electrode formed inside the trench 102. The trench 102 extends from a top surface of the substrate through a p-type well or body region 104 and terminates in an n-type drift or epitaxial region 106. . The channel 102 is lined with a thin dielectric layer 108 and is substantially filled with a conductive material 110 such as a doped polysilicon. The N-type source region 112 is formed inside the body region 104 adjacent to the channel 102. A germanium termination for MOSFET 100 is formed on the back side of the substrate that is coupled to a heavily doped n+ substrate region 114. The structure shown in Figure 1 is heavy on a common substrate made of tantalum. Overlay many times to form an array of transistors. This array can be constructed from a variety of different honeycomb or striped structures known in the art. When the transistor is turned on, a conduction path is formed vertically between the source region 112 and the drift region 106 along the wall of the gate channel 102.

Because of its vertical gate structure, MOSFET 100 is capable of having a higher packing density than a planar gate element, and a higher packing density can be converted to a relatively lower on-resistance. To improve the breakdown voltage performance of the transistor, a p+ heavy body region 118 is formed inside the p-well 104 to form a sharp junction at the interface between the p+ heavy body portion 118 and the p-well 104. By controlling the depth of the p+ heavy body portion 118 relative to the channel depth and well depth, the electric field generated when a voltage is applied to the transistor moves away from the channel. This increases the avalanche current handling capability of the transistor. The modified structure and the variation of the procedure for forming the transistor, and in particular the abrupt junction, are described in more detail in commonly-owned U.S. Patent No. 6,429,481, the disclosure of which is incorporated herein by reference. The manner is incorporated herein in its entirety.

Although vertical channel MOSFET 100 exhibits good on-resistance and improved robustness, it has a relatively high input capacitance. The input capacitor for the channel MOSFET 100 has two components: a gate-to-source capacitance Cgs and a gate-to-tantalum capacitance Cgd. The gate-to-source capacitance Cgs is due to the overlap between the source region 112 near the top of the channel and the gate conductive material 110. Because the source and body of the transistor are shorted together in a typical power switching application, the capacitance formed between the gate and the inverted via in the body also contributes to Cgs. The gate-to-tantalum capacitance Cgd is caused by the overlap between the gate conductive material 110 at the bottom of each channel and the drift region 106 connected to the crotch portion. The gate-to-tantalum capacitor Cgd or Miller capacitance limits the PV V _DS turnaround time. Therefore, higher Cgs and Cgd result in appreciable switching losses. As power management applications move to higher switching frequencies, these switching losses become more important.

One way to reduce the gate-to-source capacitance Cgs is to reduce the path length of the transistor. A shorter path length directly reduces the gate-to-channel component of the Cgs. The shorter path length is also directly proportional to R _DSon and can achieve the same component current carrying with fewer gate channels. This reduces both Cgs and Cgd by reducing the gate to source and gate to 汲 overlap. However, the shorter path length will allow the element to be easily penetrated when the depleted layer formed by the reverse biased body-twisting surface is pushed deep into the body region and approaches the source region. By reducing the doping concentration of the drift region to maintain a large number of depletion layers, there is an undesirable effect of increasing the on-resistance R _DSon of the transistor.

An improvement in the transistor structure that reduces the length of the via and is also effective in addressing the above drawbacks is the use of an additional "shield" channel that is laterally separated from the gate channel. Referring to Figure 2A, an exemplary embodiment of a dual channel MOSFET 200 is shown. The term "dual channel" refers to a transistor having two different types of channels rather than a similar total number of channels. In addition to the structural features common to the MOSFET of FIG. 1, the dual channel MOSFET 200 includes a shield channel 220 interposed between adjacent gate channels 202. In the exemplary embodiment illustrated in FIG. 2A, shield channel 220 extends from the surface through p+ region 218, body region 204 into drift region 206 that is substantially below the depth of gate channel 202. The channel 220 is lined with a dielectric material 222 and is substantially filled with a conductive material 224 such as a doped polysilicon. A metal layer 216 is electrically connected to the conductive material 224 inside the trench 220 and the n+ source region 212 and the p+ heavy body region 218. This reality As an example, the channel 220 can therefore be referred to as a source shielded channel. An example of this type of dual channel MOSFET and its fabrication process and circuit application are described in more detail in U.S. Patent Application Serial No. 10, entitled "Double Channel Power MOSFET" by Steven Sapp. In the case of No. 209,110, the entire disclosure of this application is incorporated herein by reference.

The effect of the deeper source shielding channel 220 is to push the depletion layer formed by the reverse biased body-twisting surface further into the drift region 206. Therefore, a wider depletion layer can be caused without increasing the electric field. This allows the drift region to be heavily doped without reducing the breakdown voltage. A highly doped drift region reduces the on-resistance of the transistor. Moreover, the reduced electric field near the body-twisting surface can significantly reduce the length of the via to further reduce the on-resistance of the transistor and significantly reduce the gate-to-source capacitance Cgs. Moreover, compared to the MOSFET of Figure 1, the dual channel MOSFET is capable of achieving the same transistor current carrying capacity with far fewer gate channels. This significantly reduces the gate-to-source and gate-to-汲 overlap capacitance. Note that in the exemplary embodiment shown in FIG. 2A, the gate channel conductive layer 210 is buried inside the channel without requiring a dielectric circle between the top of the channel 102 of the MOSFET 100 in FIG. top. Also, the use of a source shielded channel as taught herein is not limited to a trench gate MOSFET, and a similar approach can be obtained when the source shielded trench is employed in a planar MOSFET that is formed horizontally on the top surface of the substrate. The advantages. An exemplary embodiment for a planar channel MOSFET having a source shielded channel structure is shown in FIG. 2B.

To further reduce the input capacitance, additional structural improvements can be made to reduce the gate-to-source capacitance Cgd. As mentioned above, the gate-to-source capacitance Cgd is defined by the trench The overlap between the drift zone at the bottom of the track and the gate is caused. One method for reducing this capacitance is to increase the thickness of the gate dielectric layer at the bottom of the trench. Referring again to FIG. 2A, the gate trench 202 is depicted as having a dielectric layer 226 that is thicker than the dielectric layer along the sidewalls of the gate trench at the bottom of the trench that overlaps the drift region 206 (the transistor termination). . This reduces the gate to the tantalum capacitor Cgd without degrading the forward conduction of the transistor. A thicker dielectric layer can be created at the bottom of the gate trench in a number of different ways. An exemplary procedure for the generation of a thicker dielectric layer is described in commonly-owned U.S. Patent No. 6,437,386 issued to the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire content Other procedures for forming a thick dielectric layer at the bottom of a trench are further described below with reference to Figures 56 through 59. Another way to minimize the gate-to-tantalum capacitance is to include a centrally disposed second dielectric core including the inside of the channel extending upward from the dielectric liner on the trench floor. In one embodiment, the second dielectric core can extend all the way up to contact the dielectric layer above the channel conductive material 210. An example of this embodiment and its variants are described in more detail in co-owned certification issued to Shenoy, U.S. Patent No. 6,573,560.

Another technique for reducing the gate-to-tantalum capacitance Cgd involves using one or more biased electrodes to shield the gate. According to this embodiment, one or more electrodes are formed under the gate channel and under the conductive material for forming the gate electrode to shield the gate from the drift region, thereby significantly reducing the gate-to-turn overlap capacitance. Referring to Figure 3A, a portion of an exemplary embodiment of a shielded gate trench MOSFET 300A is shown. The channel 302 in the MOSFET 300A includes a gate electrode 310 and two additional electrodes 311a and 311b under the gate electrode 310 in this embodiment. The electrodes 311a and 311b shield the gate electrode 310 It does not have any significant overlap with the drift region 306 and almost eliminates the gate to 汲 overlap capacitance. The shield electrodes 311a and 311b can be independently biased at an optimum potential. In one embodiment, one of the shield electrodes 311a or 311b can be biased at the same potential as the source terminal. Similar to the dual channel structure, the bias of the shield electrode can also help widen the depletion region formed on the body-junction surface to further reduce Cgd. It is understood that the number of shield electrodes 311 can vary depending on the switching application and particularly on the voltage requirements of the application. Likewise, the size of the shield electrode can vary in a given channel. For example, the shield electrode 311a may be larger than the shield electrode 311b. In one embodiment, the smallest shield electrode is closest to the bottom of the channel, while the remaining shield electrodes are gradually increased in size as they approach the gate electrode. The independently biased electrode layers on the inside of the channel can also be used for vertical charge control applications to improve small forward voltage losses and higher rejection. This aspect of the transistor structure, further described below in connection with higher voltage components, is also described in more detail in the co-transfer of Kocon under the name "with improved small forward voltage loss and higher In the U.S. Patent Application Serial No. 09/981,583, the entire disclosure of which is incorporated herein by reference.

Figure 3B shows an alternative embodiment of a shielded gate trench MOSFET 300B for a shielded gate structure incorporating a dual channel structure of Figure 2A and a shielded gate structure of Figure 3A. In the exemplary embodiment illustrated in FIG. 3B, gate channel 301 includes gate polysilicon 310 similar to channel 302 of MOSFET 300A. However, MOSFET 300B includes a non-gate channel 301 that may be deeper than gate channel 302 based on vertical charge control applications. Although the charge control channel 301 can have a single layer of conductive material connected to the source metal at the top of the channel as in FIG. 2A (Example of the polysilicon), the embodiment shown in Fig. 3B uses a polycrystalline germanium electrode 313 which can be independently biased. The number of electrodes 313 stacked in a channel can vary depending on the application requirements, as does the size of electrode 313 shown in Figure 3B. The electrodes can be electrically biased or tied together independently. Also, the number of charge control channels on the inside of an element will depend on the application.

Another technique for improving the switching speed of power MOSFETs uses a dual gate structure to reduce the gate-to-tantalum capacitance Cgd. According to this embodiment, the gate structure inside the channel is divided into two segments: a first segment that performs the conventional gate function for receiving the switching signal; and a second segment that shields the first gate segment. The segments are not subject to drift (汲) regions and can be independently biased. This dramatically reduces the gate-to-source capacitance of the MOSFET. 4A is a simplified partial view of an exemplary embodiment of a dual gate trench MOSFET 400A. As shown in FIG. 4A, the gate of MOSFET 400A has two segments G1 and G2. Unlike the shield electrodes (311a and 311b) in the MOSFET 300A of Fig. 3A, the conductive material for forming G2 in the MOSFET 400A has an overlap region 401 with the via and thus serves as a gate terminal. However, the secondary gate terminal G2 is biased independently of the primary gate terminal G1 and does not receive the same signal for driving the switching transistor. Rather, in one embodiment, G2 is biased at a fixed potential just above the MOSFET low limit voltage to reverse the path in overlap region 401. This will ensure that a continuous path is formed as it transitions from the secondary gate G2 to the primary gate G1. Also, since the potential at G2 is higher than the source electrode, Cgd is lowered, and the charge transfer leaving the drift region into the secondary gate G2 will further contribute to lowering Cgd. In another embodiment, if there is no fixed potential, the secondary gate G2 can be biased to a potential above the low limit voltage just prior to a switching event. In other embodiments, the potential at G2 can be made variable and optimally adjusted to minimize the gate to any marginal portion of the tantalum capacitance Cgd. The dual gate structure can be used in MOSFETs with planar gate structures and other types of channel gate power elements including IGBTs and the like. Variations in such dual-gate channel MOS gate components and the manufacturing procedures for such components are described in more detail in the co-transfer of Kocon et al. entitled "Modified Miller Capacitors for Reduction" U.S. Patent Application Serial No. 10/640,742, the disclosure of which is incorporated herein by reference.

Another embodiment for a modified power MOSFET is depicted in FIG. 4B, in which an exemplary MOSFET 400B incorporates a planar dual gate structure and a trench electrode for vertical charge control. The primary and secondary gate terminals G1 and G2 have a similar operation to the trench double gate structure of Figure 4A, while the deep trench 420 provides an electrode in the drift region to dissipate charge and increase the breakdown voltage of the device. In the illustrated embodiment, the shield or secondary gate G2 overlaps the upper portion of the primary gate G1 and extends above the p-well 404 and drift region 406. In an alternative embodiment, the primary gate G1 extends above the shield/secondary gate G2.

Various techniques, such as gate shields and channel electrodes for vertical charge control, described so far, can be combined to obtain power components, including lateral and vertical MOSFETs, IGBTs, diodes, and the like, and their performance characteristics Optimize for a given application. For example, the trench type double gate structure shown in Fig. 4A can advantageously incorporate a vertical charge control channel structure of the type shown in Fig. 3B or 4B. The device will include an active channel having a dual gate structure as shown in FIG. 4A and substantially filled with a single layer of conductive material (as in channel 420 of FIG. 4B) or filled with multiple stacked conductive electrodes (eg, The deeper charge control channel in channel 301 of Figure 3B). For lateral elements in which the crucible terminal is positioned on the same substrate surface as the source termination (ie, current flows laterally), the charge control electrodes will be laterally configured to form a field plate rather than being stacked in a vertical channel. . The orientation of the charge control electrode is generally parallel to the direction of current flow in the drift region.

In one embodiment, the dual gate and shielded gate technology are combined inside the same channel to provide switching speed and rejection voltage enhancement. 4C shows a MOSFET 400C in which the channel 402C includes one of the main gate G1, the primary gate G2, and a shield layer 411 stacked in a single channel as illustrated. Channel 402C can be made to the depth required for the application and can include the number of shield layers 411 required for the application. For the charge balance and the use of the same channel for the shield electrode, since the two channels are not required and combined into one, it is possible to have a higher density. It can also have a large current dispersion and improve the on-resistance of the component.

The components described so far use a combination of shielded gates, double gates, and other techniques to reduce parasitic capacitance. However, due to fringing effects, these techniques do not completely minimize the gate-to-tantalum capacitance Cgd. Referring to Figure 4D, a partial cross-sectional view of an exemplary embodiment of a MOSFET 400D having a deep body design is shown. According to this embodiment, the body structure is formed by etching a channel 418 through the center of the mesa formed between the gate channels 402 and extending deep to the gate channel 402 or deeper. The body channel 418 is filled with active metal as shown. The source metal layer can include a thin refractory metal on the metal-diffusion boundary (not shown). In this embodiment, the body structure further includes a p+ body implant 419 that substantially surrounds the body channel 418. p+ implant layer 419 It is possible to have an additional shielding to change the potential distribution inside the element and in particular close to the gate electrode. In an alternative embodiment illustrated in FIG. 4E, the body channel 418 is substantially filled with an epitaxial material, such as by selective epitaxial growth (SEG) deposition. Alternatively, body channel 418E is substantially filled with doped polysilicon. In either of these embodiments, if the p+ shield junction 419 is not implanted, subsequent temperature processing will diffuse the dopant from the filled body into the crucible to form the p+ shield junction 419. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; .

In the embodiment illustrated in Figures 4D and 4E, the distance L between the gate channel 402 and the body channel 418, and the relative depth of the two channels are controlled to minimize the marginal gate to the tantalum capacitance. In embodiments using SEG or polysilicon filled body channels, the spacing between the outer edge of layer 419 and the gate channel wall can be adjusted by varying the doping concentration of SEG or polysilicon inside the body channel 418. . Figures 4F and 4G show the effect of the channel-type deep body on the distribution of the potential line inside the element near the gate electrode. For illustrative purposes, the 4F and 4G diagrams use MOSFETs with shielded gate structures. Figure 4F shows a potential line for a reverse biased gate MOSFET 400F having a trench-type deep body portion 418, and Figure 4G shows a reverse biased shielded gate MOSFET 400G for a shallow body structure. The potential line. The outline in each element shows the potential distribution inside the element when reverse biased (i.e., blocked). The white line shows the well junction and also defines the bottom of the pathway next to the gate electrode. It can be seen from the figure that a lower potential and a lower electric field are applied to the trench depth of the 4F map. The path used by the body MOSFET 400F and the surrounding gate electrode. This reduced potential can have a reduced path length to reduce the total gate charge of the component. For example, the depth of the gate channel 402 can be reduced to less than, for example, 0.5 microns, and can be made shallower than the body channel 418 and wherein the spacing L is about 0.5 microns or less. In an exemplary embodiment, the spacing L is less than 0.3 microns. Another advantage of this embodiment is the reduction in gate-to-turn charge Qgd and Miller capacitance Cgd. The lower the value of these parameters, the faster the component can switch. This improvement is achieved by a reduction in the potential appearing next to the gate electrode. The modified structure has a much lower potential to be switched, and the gate has a much lower induced capacitive current. This will enable the gate to switch faster.

The trench-type deep body structure described in conjunction with Figures 4D and 4E may incorporate other charge balancing techniques such as shielded or double gate structures to further improve component switching speed, turn-on resistance, and rejection.

The improvements provided by the above power components and variations thereof have resulted in robust switching components for relatively low voltage power electronics applications. As used herein, low voltage refers to a voltage in the range of, for example, about 30V to 40V and below, although this range may vary depending on the particular application. Applications requiring a blocking voltage that is significantly higher than this range must make some type of structural modification to the power transistor. In general, the doping concentration in the drift region of the power semiconductor is reduced to maintain the component at a higher voltage during the blocking state. However, a slightly doped drift region results in an increase in the transistor on resistance R _DSon . A higher resistivity directly increases the power loss of the switch. With recent advances in semiconductor manufacturing that further increase the packing density of power components, power loss has become more pronounced.

Attempts have been made to improve component turn-on resistance and power loss while maintaining a high resistive voltage. Many of these attempts employ a variety of different vertical charge control techniques to vertically generate a substantially flat electric field in a semiconductor component. A number of component structures of this type have been proposed, including the laterally depleted components disclosed in U.S. Patent No. 6,713,813, the commonly-owned, to the name of the s. And the elements described in U.S. Patent No. 6,376,878, the entire disclosure of which is incorporated herein by reference.

Figure 5A shows a cross-sectional view of a portion of an exemplary power MOSFET 500A having a planar gate structure. The MOSFET 500A exhibits a structure having a planar MOSFET 200B similar to that of FIG. 2B, but differs from the element in two distinct aspects. The conductive material is not used to fill the trenches 520, which are filled with a dielectric material such as hafnium oxide, and the elements further include discontinuous floating P-type regions spaced adjacent the outer sidewalls of the trenches 520. As described for the dual channel MOSFET of Figure 2A, the conductive material (e.g., polysilicon) in the source channel 202 helps to improve the cell collapse voltage by pushing the depletion layer deeper into the drift region. Therefore, the removal of the conductive material from the channel will result in a breakdown voltage reduction unless other means of reducing the electric field is employed. The floating p region 524 has a function of reducing an electric field.

Referring to the MOSFET 500A shown in Fig. 5A, as the electric field increases as the erbium voltage increases, the floating p region 524 obtains a corresponding potential determined by its position in the space charge region. The floating potential of these p regions 524 causes the electric field to disperse deeper into the drift region, resulting in a more uniform field for the depth of the mesa region between the trenches 520 as a whole. As a result, the breakdown voltage of the transistor is increased plus. The advantage of replacing the conductive material in the channel with an insulating material is that a larger portion of the space charge region appears on an insulator rather than a drift region that may be germanium. Since the permittivity of an insulator is lower than that of, for example, 电容, and because the area of the hollow region of the channel is reduced, the output capacitance of the element is significantly reduced. This further enhances the switching characteristics of the transistor. The depth of the channel 520 filled with dielectric is determined by the voltage requirement, and the deeper the channel, the higher the blocking voltage. An additional advantage of the vertical charge control technique is that it allows the transistor cell to be laterally displaced for thermal isolation without appreciable additional capacitance. In an alternative embodiment, instead of a floating p-region, the p-type layer pads the outer sidewalls of the dielectric filled trench to achieve a similar vertical charge balance. A simplified and partial cross-sectional view of this embodiment is shown in Figure 5B, wherein the outer sidewall of the channel 520 is covered by a p-type layer or liner 526. In the exemplary embodiment shown in FIG. 5B, the gate is also channeled, which further improves the transconductance of the component. Other embodiments of the improved power component employing this variation are described in more detail in U.S. Patent Application Serial No. Sapp et al., entitled "Vertical Charge Control Semiconductor Component with Low Output Capacitance". In the case of No. 10/200,056 (Attorney Docket No. 18865-0097/17732-55280), the entire disclosure of which is incorporated herein by reference.

As described above, the channel MOSFET 500B of FIG. 5B exhibits reduced output capacitance and improved breakdown voltage. However, because the active channel (gate channel 502) is positioned between the charge control channels 520 filled with dielectric, the via width of MOSFET 500B is not as large as the conventional channel MOSFET structure. This may result in a higher on-resistance R _DSon . Referring to Figure 5C, an alternate embodiment of a trench MOSFET 500C with vertical charge control that eliminates the secondary charge control channel is shown. Channel 502C in MOSFET 500C includes gate polysilicon 501 and a lower portion filled with dielectric extending into drift region 506. In one embodiment, the channel 502C extends to a depth that is less than about half the depth of the drift region 506. A p-type liner 526C surrounds the outer wall along the lower portion of each channel as shown. This single channel structure eliminates the secondary charge control channel and allows for an increased via width and a lower R _DSon . The lower portion of the deeper channel 502C surrounded by a p-type pad 526C on the outer wall supports a major portion of the electric field to reduce the output capacitance and the gate to the tantalum capacitance. In an alternative embodiment, p-type liner 526C is formed in a plurality of discontinuities along the sides and bottom of channel 502C. Other embodiments may be created by combining a single channel charge control structure with a shielded gate or double gate technique as described above to further reduce component parasitic capacitance.

Referring to Figure 6, a simplified cross-sectional view of a power MOSFET 600 suitable for higher voltage applications that also require faster switching is shown. The MOSFET 600 family incorporates vertical charge control for improved breakdown voltage and shielded gate structure for improved switching speed. As shown in FIG. 6, a shield electrode 611 is positioned within the gate channel 602 between the gate conductive material 610 and the bottom of the trench. The electrode 611 shields the gate of the transistor from the underlying germanium region (drift region 606), thereby significantly reducing the gate-to-tantalum capacitance of the transistor and thereby increasing its maximum switching frequency. A channel 620 filled with a dielectric filled with p-doped pad 626 helps to create a substantially flat electric field vertically to improve the breakdown voltage of the device. In operation, the combination of the dielectric filled trench 620 and the shielded gate structure including the p-type pad 626 reduces parasitic capacitance and helps to make the n drift region empty. Lacking to disperse the electric field concentration on the edge portion of the gate electrode. This type of component can be used in RF amplifier or high frequency switching applications.

Figure 7 depicts an alternate embodiment of another power MOSFET suitable for higher voltage, higher frequency applications. In the simplified example shown in Figure 7, MOSFET 700 combines vertical charge control for improved breakdown voltage with dual gate structure for improved switching speed. Similar to the elements shown in FIG. 6, vertical charge control is performed using a channel 720 filled with a dielectric filled with p-doped pad 726. The reduction in parasitic capacitance is achieved by a double gate structure in which a primary gate electrode G1 is shielded from the crotch portion (n drift region 706) by the primary gate electrode G2. The secondary gate electrode G2 can be continuously biased or biased only prior to a switching event to reverse the path in region 701 to ensure an uninterrupted current flow through a continuous path when the component is turned "on".

In another embodiment, the shielded vertical charge control MOSFET also employs a dielectric filled channel through the doped sidewalls to implement an integrated Schottky diode. Figure 8 shows an example of a shielded gate MOSFET 800 in accordance with this embodiment. In this example, electrode 811 in the lower portion of trench 802 shields gate electrode 810 from drift region 806 to reduce parasitic gate to tantalum capacitance. A channel 820 filled with a p-doped pad filled with a dielectric on the outer sidewall provides vertical charge control. A Schottky diode 828 is formed between the two channels 820A and 820B that are used to form a mesa having a width W. This Schottky diode structure is interspersed on the channel MOSFET cell array to enhance the performance characteristics of the MOSFET switch. The low barrier height of the Schottky structure 828 is utilized to reduce the forward voltage drop. In addition, this diode will have an inherent reverse recovery speed advantage over the normal PN junction of a vertical power MOSFET. For example by Boron is doped to the sidewalls of the dielectric filled trench 820 to eliminate sidewall leakage paths due to phosphorus isolation. The characteristics of the channel program can be utilized to optimize the performance of the Schottky diode 828. For example, in one embodiment, the width W is adjusted such that the depletion in the drift region of the Schottky structure 828 is affected and controlled by the adjacent PN junction to increase the reverse voltage capability of the Schottky diode 828. An example of a monotonically integrated channel MOSFET and a Schottky diode can be found in U.S. Patent No. 6,351,018, the entire disclosure of which is incorporated herein by reference.

It is understood that a Schottky diode system formed between channels filled with dielectric can be integrated with a variety of different types of MOSFETs, including MOSFETs with a planar gate structure, without any shield electrodes and in trenches. Channel gate MOSFETs with or without thick dielectric on the bottom of the track. An exemplary embodiment of a dual gate trench MOSFET with integrated Schottky diodes is shown in Figure 9A. The MOSFET 900A includes a gate channel 902 in which a main gate G1 is formed over the primary gate G2 to reduce parasitic capacitance and increase the switching frequency. MOSFET 900A also includes a dielectric filled channel 920 including a p-doped pad 926 along its outer sidewall for vertical charge control to enhance the device blocking voltage. One of the many embodiments described above for forming a liner (such as those shown in Figures 5B, 6, 7, 8 and 9A) uses a plasma doping procedure. The Schottky diode 928A is formed between two adjacent dielectric filled trenches 920A and 920B as shown. In another variation, a monotonically integrated Schottky diode and channel MOSFET are formed without a channel filled with dielectric. Figure 9B is a cross-sectional view of an exemplary element 900B in accordance with one such embodiment. MOSFET 900B includes active The trenches 902B each have an electrode 911 buried under a gate electrode 910. A Schottky diode 928B is formed between the two channels 902L and 902R as shown. The charge balance effect of the biased electrode 911 is such that the doping concentration of the drift region is increased without sacrificing the reverse blocking voltage. The higher doping concentration in the drift region in turn reduces the forward voltage drop of the structure. As in the aforementioned channel MOSFET having a buried electrode, the depth of each channel and the number of buried electrodes may vary. In a variation shown in Fig. 9C, the channel 902C has only one buried electrode 911 and the gate electrode 910S in the Schottky cell 928C is connected to the source electrode as shown. The Schottky diode gate can be alternatively connected to the gate terminal of the MOSFET. Figures 9D, 9E, and 9F show exemplary layout variations of Schottky diodes interspersed within the active cell array of the MOSFET. Figures 9D and 9E show a single mesa Schottky and a double mesa Schottky layout, respectively, while the 9F shows a layout that makes the Schottky zone perpendicular to the MOSFET channel. These and other variations of the Schottky diodes, including alternating Schottky-to-MOSFET regions, can be combined with any of the transistor structures described herein.

In another embodiment, a power component is enhanced by one or more diode structures embedded in a matrix lined with a dielectric and parallel to the current flow in the drift region of the component. The ability to resist voltage. Figure 10 provides a simplified cross-sectional view of an exemplary channel MOSFET 1000 in accordance with one such embodiment. The diode channel 1020 is disposed on either side of a gate channel 1002 and extends deep into the drift region 1006. The diode channel 1020 includes one or more diodes formed by opposite conductivity type regions 1023 and 1025 for forming one or more PN junctions on the inside of the channel. structure. In one embodiment, the channel 1020 includes a single region of opposite polarity to the drift region such that a single PN junction is formed on the interface with the drift region. The regions 1023 and 1025 can be formed using P-type and n-type doped polysilicon or germanium, respectively. Other types of materials such as tantalum carbide, gallium arsenide, antimony telluride, etc. may also be utilized to form regions 1023 and 1025. A thin dielectric layer 1021 extending along the inner sidewall of the trench insulates the diode in the trench from the drift region 1006. As shown, there is no dielectric layer along the bottom of the channel 1020, thus allowing the bottom region 1027 to be in electrical contact with the underlying substrate. In one embodiment, considerations similar to those used to determine the design and fabrication of gate oxide 1008 are applicable to the design and formation of dielectric layer 1021. For example, the thickness of the dielectric layer 1021 depends on factors such as the voltage required to maintain it and the range of electric fields in the diode channel induced in the drift region (ie, the range of the dielectric layer).

In operation, when the MOSFET 1000 is biased in its blocking state, the PN junction in the diode channel 1020 is reverse biased and the peak electric field occurs at the junction of the diodes. Via the dielectric layer 1021, the electric field in the diode channel induces a corresponding electric field in the drift region 1006. The induced electric field is clearly shown in the drift region as a generalized increase in the upper electric field curve in the upper pendulum and the drift region. This increase in electric field results in a larger area at the bottom of the electric field curve, which in turn results in a higher breakdown voltage. The variation of this embodiment is described in more detail in U.S. Patent Application Serial No. 10/288,982, the entire disclosure of which is assigned to the benefit of the benefit of the benefit of the co-transfer of Kocon et al. In case number No. 18865-117/17732-65560), the case is incorporated by reference in its entirety. In this article.

There may be other embodiments of power elements incorporating a trench diode for charge balancing and a technique such as a shielded gate or double gate structure to reduce parasitic capacitance. Figure 11 shows an example of a MOSFET 1100 in accordance with this embodiment. The MOSFET 1100 uses a shield electrode 1111 inside the active channel 1102 under the gate electrode 1110 to reduce the gate-to-tantalum capacitance Cgd for the transistor as described above for the MOSFET 300A of FIG. 3A. The MOSFET 1100 uses a different number of PN junctions than the MOSFET 1000. Figure 12 is a cross-sectional view of a MOSFET 1200 incorporating a dual gate technique and a trench diode structure. Active channel 1202 in MOSFET 1200 includes a primary gate G1 and a primary gate G2 and operates in the same manner as the active channel in the dual gate MOSFET described in FIG. 4B. The diode channel 1220 provides charge balancing to increase the component rejection voltage, and the dual gate active channel structure improves the component switching speed.

Another embodiment incorporates a trench diode charge balancing technique and an integrated Schottky diode in a planar MOSFET 1300 as shown in FIG. Similar advantages can be obtained by integrating the Schottky diode 1328 and the MOSFET as described in the eighth and ninth embodiments. In this embodiment, a planar gate structure is shown for illustrative purposes, and those skilled in the art will appreciate that an integrated Schottky can be employed in a MOSFET having any other type of gate structure including a gate gate, a double gate, and a shield gate. A combination of a diode and a trench diode structure. Any of the resulting embodiments can also be combined with trench body technology to further minimize marginal parasitic capacitance, as described for MOSFET 400D or 400E of Figures 4D and 4E. May also have other changes Different from equals. For example, the number of regions of opposite conductivity inside the diode channel may change, as does the depth of the diode channel. The polarity of the region with opposite conductivity can be reversed, as is the polarity of the MOSFET. Also, any PN region (923, 925 or 1023, 1025, etc.) can be independently biased by extending the respective regions along the third dimension and then to the surface of the crucible in which they are in electrical contact. Also, multiple diode channels can be used as needed for component size and application voltage requirements, and the spacing and alignment of the diode channels can be performed in a variety of different stripes or honeycomb designs.

In another embodiment, a graded accumulation mode transistor is provided that employs a variety of different charge balancing techniques to have less forward voltage loss and higher rejection. In a typical accumulation mode transistor, there is no blocking junction and the component is turned off by clamping the path region next to the gate terminal slightly to reverse the current flow. When the transistor is turned on by applying a gate bias, an accumulation layer is formed in the via region instead of an inversion layer. Since the reverse path is not formed, the path resistance is minimized. In addition, there is no PN body diode in an accumulation mode transistor, which minimizes losses that would otherwise occur in a particular circuit application such as a synchronous rectifier. A drawback of the conventional accumulation mode component is that the drift region must be lightly doped to support a reverse bias voltage when the component is in the blocking mode. A lightly doped drift zone represents a higher on-resistance. The embodiments described herein overcome this limitation by utilizing various different charge balancing techniques in a cumulative mode component.

Referring to Figure 14, a simplified implementation of an exemplary cumulative mode transistor 1400 having alternating conductive regions arranged in parallel with current flow is shown. example. In this example, the transistor 1400 is an n-channel transistor and has a gate terminal formed inside the channel 1402, an n-type via region 1412 formed between the channels, and a columnar n having opposite polarities. The drift region 1406 of the type and p-type segments 1403 and 1405, and an n-type germanium region 1414. Unlike the enhanced mode transistor, the cumulative mode transistor 1400 does not include a well or a body region that is internally formed with a via (in this example, a p-type). Rather, a conductive path is formed as a cumulative layer is formed in region 1412. Depending on the doping concentration of region 1412 and the doping type of the gate electrode, transistor 1400 is typically turned "on" or "off". When the n-type region 1412 is completely depleted and slightly inverted, it is turned off. The doping concentrations in the opposite polarity regions 1403 and 1405 are adjusted to maximize charge dispersion, thereby enabling the transistor to support higher voltages. The electric field distribution is smoothed by a columnar opposite polarity region parallel to the current flow by not allowing it to linearly decrease from the junction formed between the regions 1412 and 1406. The charge dispersion effect of this structure allows for the use of a highly doped drift region to reduce the on-resistance of the transistor. The doping concentration of the various zones may vary; for example, n-type regions 1412 and 1413 may have the same or different doping concentrations. Those skilled in the art will appreciate that an improved p-channel transistor can be obtained by reversing the polarity of the various regions of the elements shown in Figure 14. Other variations of the columnar opposite polarity regions on the inside of the drift region are described in more detail along with the ultra high voltage components described further below.

Figure 15 is a simplified diagram of another accumulation mode element 1500 having a channel electrode for charge dispersion purposes. All zones 1512, 1506 and 1504 belong to the same conductivity type, in this example n-type. For a component that is normally turned off, the gate polysilicon 1510 is made p-type. The doping concentration of zone 1512 is regulated In order to form a depleted junction at an unbiased condition. Inside one of the channels 1502, one or more buried electrodes 1511 are formed under the gate electrode 1510, and are surrounded by a dielectric material 1508. As described in conjunction with the enhanced mode MOSFET 300A of Figure 3A, the buried electrode 1511 acts as a field plate and can be biased as needed to a potential that optimizes its charge dispersion function. Since the charge dispersion can be controlled by independently biasing the buried electrode 1511, the maximum electric field can be significantly increased. Similar to the buried electrodes used in MOSFET 300A, this structure may have different variations. For example, the depth of the channel 1502 and the size and number of the buried electrodes 1511 can vary depending on the application. The charge-distributing electrode can be buried inside the channel separated from the active channel for accommodating the transistor gate electrode by a manner similar to that shown in the channel structure of the MOSFET 300B in FIG. 3B. An example of this embodiment is shown in Figure 16. In the example shown in FIG. 16, n-type region 1612 includes a relatively heavily doped n+ source region 1603 that can be selectively added. The heavily doped source region 1603 may extend along the top edge of the n-type region 1612 as illustrated or may be formed as two regions adjacent the channel wall along the top edge of the n-type region 1612 (not shown). In some embodiments, it may be necessary to reduce the doping concentration of the n-type region 1606 by including the n+ region 1603 to ensure that the transistor can be properly turned off. This selectively heavily doped source region can be used in the same manner as any of the accumulated transistors described herein.

Another embodiment of a modified accumulation mode transistor employs a dielectric filled channel comprising an outer pad of opposite polarity. Figure 17 is a simplified cross-sectional view of a cumulative transistor 1700 in accordance with this embodiment. A dielectric filled channel 1720 extends downwardly from the surface of the crucible into the drift region 1706. Channel The 1720 is substantially filled with a dielectric material such as cerium oxide. In this exemplary embodiment, the transistor 1700 is an n-channel transistor having a trench gate structure. A p-type region 1726 is patterned as a spacer on the outer wall of the dielectric filled channel 1720. Similar to the enhanced mode transistors 500A, 500B, and 500C described in conjunction with FIGS. 5A, 5B, and 5C, respectively, the channel 1720 reduces the output capacitance of the transistor, while the p-type pad 1726 provides charge balancing in the drift region to increase the charge. The ability of the crystal to block. In an alternative embodiment illustrated in FIG. 18, the oppositely doped pads 1826N and 1826P are formed adjacent the opposite side of a dielectric filled channel 1820. That is, a dielectric filled channel 1820 has a p-type pad 1826P extending along an outer sidewall on one side and an n-type extending along an outer sidewall on the other side of the same channel. Pad 1826N. Other variations of this combination of cumulative transistor and dielectric filled channel may be as described in conjunction with the corresponding enhancement mode transistor. These variations include, for example, a cumulative transistor having a planar (rather than trench) gate structure and a floating p-type region rather than a p-type pad 1726 in the device shown in Figure 5A; a crystal having a p-type liner covering the outer sidewall instead of the bottom of the channel 1726 in the component shown in FIG. 5B; and a cumulative transistor having a cover member as shown in FIG. 5C The single channel structure of the p-type pad in the lower part of the channel, and others.

In another embodiment, an accumulation mode electro-crystal system is formed in tandem on one or more diodes inside a channel based on charge balancing purposes. A simplified cross-sectional view of an exemplary cumulative mode transistor 1900 in accordance with one of the embodiments is shown in FIG. The diode channel 1920 is disposed on either side of a gate channel 1902 and extends deep into the drift region 1906. Diode channel The 1920 series includes one or more diode structures formed by opposite conductivity type regions 1923 and 1925 for forming one or more PN junctions on the inside of the channel. Regions 1923 and 1925 can be formed using P-type and n-type doped polysilicon or germanium. A thin dielectric layer 1921 extending along the inner sidewall of the trench insulates the diode in the trench from the drift region 1906. As shown, there is no dielectric layer along the bottom of the channel 1920, thus allowing the bottom region 1927 to electrically contact the underlying substrate. Other variants of this combination of cumulative transistor and channel diode may be as described for the corresponding enhancement mode transistors and their variations shown in Figures 10, 11, 12 and 13.

Any of the above cumulative mode transistors may employ a heavily doped opposite polarity region in one of the top (source) regions. Figure 20 is a simplified perspective view of an exemplary cumulative mode transistor 2000 showing this characteristic combined with other variations. In this embodiment, the charge balancing dipole system in the accumulation mode transistor 2000 is formed inside the same channel as the gate. The trench 2002 includes a gate electrode 2010 and has an n-type 2023 and a p-type 2025 germanium or polysilicon layer underneath to form a PN junction. A thin dielectric layer 2008 separates the diode structure from the gate terminal 2002 and the drift region 2006. The heavily doped p+ regions 2118 are formed with a spacing along the length of the mesas between the channels in the source region 2012 as illustrated. The heavily doped p+ region 2118 reduces the area of the n-region 2012 and reduces leakage of components. The P+ region 2118 may also allow for p+ contacts that will improve the flow of the hole in the avalanche and improve the robustness of the component. Variations of an exemplary vertical MOS gate cumulative transistor have been discussed to illustrate the various different features and advantages of such a stage component. Those skilled in the art will appreciate that other types of components, including lateral MOS gate transistors, diodes, bipolar transistors, and the like, can be implemented. Charge fraction The diffused electrode system may be formed inside the same channel as the gate or may be formed inside the separated channel. The various exemplary cumulative mode electro-optic systems described above have channels that terminate in the drift region, but they can also terminate in the heavily doped substrate that is coupled to the crotch portion. A variety of different transistors can be formed from stripe or honeycomb structures including hexagonal or square transistor cells. There may be other variations and combinations of some of the other embodiments, and many of which are further described in the previously cited U.S. Patent Application Serial Nos. 60/506,194, the entire disclosure of each of .

Another level of power switching element designed to be used in very high voltage applications (eg, 500V-600V and above) is the use of alternating vertical segments of p-doped and n-type in the epitaxial region between the substrate and the well. Doped with antimony. Referring to Fig. 21, an example of a MOSFET 2100 of this type is shown. In the MOSFET 2100, a region 2102, sometimes referred to as a voltage sustaining region or a blocking region, includes an alternating n-type segment 2104 and a p-type segment 2106. The effect of this configuration is that when a voltage is applied to the component, the depletion region is horizontally dispersed into each of the sides 2104 and 2106. Since the amount of net charge in each of the vertical segments 2104, 2106 is less than that required to create a crash site, the overall vertical thickness of the barrier layer 2102 is depleted before the horizontal field is high enough to cause an avalanche collapse. After this area is completely horizontally depleted, the field continues to accumulate vertically until it reaches an avalanche field of approximately 20 to 30 volts per micrometer. This greatly enhances the voltage blocking capability of the component and extends the voltage range of the component to 400 volts and above. The different variants of this type of super-junction element are described in more detail in the commonly-owned Nielson Patent Nos. 6,081, 009 and 6, 066, 878, the entireties of each of which are incorporated herein by reference.

A variation of the super-junction MOSFET 2100 uses a floating p-type island in the n-type barrier region. Using the floating island portion rather than p-type bars embodiment, the thickness of the charge-balancing layer can be reduced and thereby reducing the R _DSon. In one embodiment, the p-type islands are not evenly separated, but are separated to maintain the electric field close to the critical electric field. Figure 22 is a simplified cross-sectional view of a MOSFET 2200 showing an example of an element in accordance with this embodiment. In this example, the deeper floating p-zone 2226 is separated from the upper one. That is, the distance L3 is greater than the distance L2, and the distance L2 is greater than the distance L1. By manipulating the distance between the floating faces in this way, a small number of carriers are introduced in a relatively granular manner. The more granular the source of these carriers, the lower the R _DSon and the higher the breakdown voltage. Those skilled in the art understand that there may be many variations. For example, the number of floating zones 2226 in the vertical direction is not limited to four as shown, and the optimum number may vary. Also, the doping concentration in each floating zone 2226 may vary; for example, in one embodiment, the doping concentration in each floating zone 2226 decreases as the zone approaches the substrate 2114.

Also, as described in conjunction with low voltage and medium voltage components, many techniques for reducing parasitic capacitance to enhance switching speed and including shielded gate and double gate structures can be combined with the high voltage components described in FIGS. 21 and 22 and The mutations are combined. Figure 23 is a simplified cross-sectional view of a high voltage MOSFET 2300 incorporating a variation of a super junction architecture and a dual gate structure. The MOSFET 2300 has a planar double gate structure formed by the gate terminals G1 and G2 similarly to the double gate transistor as shown in FIG. 4B above. The opposite polarity (p-type in this example) region 2326 is disposed vertically in the n-type drift region 2306 below the p-well 2308. The size and spacing of the p-type region 2326 will vary in this example, where This causes the closerly disposed regions 2326 closer to the p-well 2308 to make contact with each other and the region 2326 that is further disposed below floats and has a smaller size as illustrated. Figure 24 depicts another embodiment of a high voltage MOSFET 2400 incorporating a super junction technique and a shielded gate structure. The MOSFET is a channel gate element having a gate electrode 2410, and is shielded by a shield electrode 2411 such as one of the MOSFETs 300A similar to FIG. 3A. MOSFET 2400 also includes an opposite polarity floating gate 2426 that is disposed in drift region 2406 in parallel with the flow of current.

Termination structure

The various types of discrete elements described above have a breakdown voltage that is limited by the cylindrical or spherical shape of the depletion region on the edge of the grain. Since the cylindrical or spherical breakdown voltage is generally much lower than the parallel plane breakdown voltage BVpp in the active region of the component, the edge of the component needs to be terminated so that the component reaches a breakdown voltage close to the active region breakdown voltage. Different techniques have been developed to evenly spread the field and voltage over the edge termination width to achieve a near-BVpp breakdown voltage. It includes field plates, field loops, junction termination extensions (JTE) and different combinations of these techniques. U.S. Patent No. 6,429,481, the disclosure of which is incorporated herein by reference in its entirety in its entire entire entire entire entire entire entire entire entire entire content An example of the termination structure of the field. In the case of an n-channel transistor, for example, the termination structure includes a deep p+ region for forming a PN junction with the n-type germanium region.

In an alternative embodiment, one or more of the annular channel systems surrounding the perimeter of the unit cell array have the effect of slowing the electric field and increasing avalanche collapse. Figure 25A shows a common trench layout for a channel transistor. The active channel 2502 is surrounded by a toroidal termination channel 2503. In this configuration, the region 2506, represented by a point circle on the end of the mesa, is more depleted than the other regions, causing an increased field in this region thus reducing the breakdown voltage under reverse bias conditions. Therefore, this type of layout is limited to lower voltage components (such as <30V). Figures 25B through 25F show several alternative embodiments for termination structures having different channel layouts to reduce the high electric field regions shown in Figure 25A. As shown, in these embodiments, some or all of the active channel is disconnected from the termination channel. The gap W _G between the termination channel and the end of the active channel has the function of reducing the electric field crowding effect observed in the structure shown in Fig. 25A. In an exemplary embodiment, W _{G is} made to be approximately half the width of the mesa between the channels. For higher voltage components, a multiple termination channel as shown in Figure 25F can be employed to further increase the breakdown voltage of the component. The variation of certain such embodiments is described in more detail in U.S. Patent No. 6,683,363, the entire disclosure of which is incorporated herein by reference in its entirety in its entirety in its entirety in the the the the the the the the the

26A-26C depict cross-sectional views of various exemplary channel termination structures for charge balanced channel MOSFETs. In the exemplary embodiment shown, MOSFET 2600A uses a shielded gate structure that embeds a shielded polysilicon electrode 2611 under gate polysilicon 2610 inside active channel 2602. In the embodiment illustrated in Figure 26A, the termination channel 2603A is lined with a relatively thick layer of dielectric (oxide) 2605A and filled with a conductive material such as polysilicon 2607A. The thickness of the oxide layer 2605A, the depth of the termination channel 2603A, and the spacing between the termination channel and the adjacent active channel (that is, the width of the final mesa) depends on the component's reverse blocking voltage. In the embodiment shown in Fig. 26A, the channel is wider on the surface (T-channel structure) and a metal field plate 2609A is used over the termination region. In an alternative embodiment (not shown), the polysilicon 2607A can be formed by using polysilicon by extending the inside of the termination channel 2603A over the surface and over the termination region (the left side of the termination channel in FIG. 26A). Field board. There may be many variations. For example, in order to have a better ohmic contact, a p+ region (not shown) underneath the metal contact portion of the crucible can be added. The p-well 2604 and its respective contacts in the last mesa adjacent to the termination channel 2603A can be selectively removed. Also, a floating p-type region can be added to the left of the termination channel 2603A (ie, outside the active region).

In another variation, the termination channel 2603 is not filled with polysilicon, and a polysilicon electrode is buried in the lower portion of the channel inside a channel filled with oxide. This embodiment is shown in Figure 26B, in which approximately half of the termination channel 2603B is filled with oxide 2605B and the lower half of a polysilicon electrode 2607B is buried inside the oxide. The depth of the trench 2603B and the height of the buried polysilicon 2607B may vary based on component processing. In another embodiment, illustrated in FIG. 26C, a termination channel 2603C is substantially filled with a dielectric and in which a conductive material is not embedded. For all three embodiments shown in Figures 26A, B and C, the width of the last mesa used to separate the termination channel from the last active channel may be different from a typical mesa formed between the two active channels. Width, and can be adjusted to achieve optimal charge balance in the termination zone. All of the above variations of the structure shown in Fig. 26A are applicable to those shown in Figs. 26B and 26C. Moreover, those skilled in the art understand that although the termination structure has been described herein for a shielded gate element, all of the above may not be Similar structures are implemented as termination regions with channel-based components.

For lower voltage components, the corner design of the channel termination ring may not be important. However, for higher voltage components, corner arcing of the termination ring with a larger radius of curvature may be required. The higher the component voltage requirement, the greater the radius of curvature at the end of the channel corner. Also, the number of termination loops may increase as the component voltage increases. Figure 27 shows an exemplary component having two termination channels 2703-1 and 2703-2 that exhibit a relatively large radius of curvature. The spacing between the channels can also be adjusted based on the component voltage requirements. In this embodiment, the distance S1 between the termination channels 2703-1 and 2703-2 is approximately twice the distance between the first termination channel 2703-1 and the active channel end point.

Figures 28A, 28B, 28C, and 28D show exemplary cross-sectional views for various termination regions having a purlin column charge balancing structure. In the embodiment shown in Fig. 28A, the field plate 2809A contacts each of the p-type bars 2803A. This allows for a wider mesa area due to lateral depletion caused by the field plates. The breakdown voltage is generally determined by the field oxide thickness, the number of rings, and the depth and spacing of the termination bar 2803A. This type of termination structure may have many different variations. For example, Figure 28B shows an alternative embodiment of having all of the bars 2803-1 covering the last bar except for the last plate 2809-1, which is connected to the other field plate 2809-2. By grounding the large field plate 2809-1, the mesa regions between the p-type bars are rapidly depleted and the horizontal voltage drop will be less pronounced, resulting in a lower breakdown voltage than the embodiment shown in Figure 28A. In another embodiment, illustrated in Figure 28C, the termination structure does not have a field plate on the center post. Because the middle column does not have a field plate, it has a narrower mesa area to be properly empty. Lacky. In one embodiment, a mesa width that tapers toward the outer ring produces optimum performance. The embodiment shown in Fig. 28D facilitates contact with the p-type bar by providing a wider well region 2808D and increasing the spacing between the field oxide layers.

In the case of ultra-high voltage components using various types of super-junction techniques of the type described above, the breakdown voltage is much higher than the conventional BVpp. For a super junction component, a charge balancing or super junction structure (e.g., opposite polarity bars or floats, buried electrodes, etc.) is also used in the termination region. Standard edge termination structures combined with charge balancing structures such as field plates on the top surface at the edge of the component can also be used. In some embodiments, a rapidly decreasing charge in the termination junction can be utilized to eliminate the standard edge structure on the top. For example, a p-type strip in the termination region can form a reduced charge while moving away from the active region to generate a net n-type equilibrium charge.

In a preferred embodiment, the spacing between the p-type bars in the termination zone is a function of the movement of the bars away from the active zone. A highly simplified cross-sectional view of an exemplary embodiment of an element 2900A in accordance with this embodiment is shown in Figure 29A. In the active region of element 2900A, an opposite conductive strip 2926A, such as made up of multiple connected p-type spheres, is formed under p-well 2908A in n-type drift region 2904A. At the edge of the element, under the termination zone, p-type termination bars TP1, TP2 to TPn are formed as shown. Rather than having a uniform spacing in the active region, the center-to-center spacing between the terminating bars TP1 through TPn increases as the bar moves away from the interface with the active region. That is, the distance D1 between TP2 and TP3 is smaller than the distance D2 between TP3 and TP4, and the distance D2 is smaller than the distance D3 between TP4 and TP5, and so on.

This type of superjunction termination structure may have several variations. For example, the p-type terminating bars TP1-TPn are not formed inside the voltage maintaining layer 2904A with a varying distance, and the center-to-center spacing can be kept uniform but the width of each terminal bar can be varied. Figure 29B shows a simplified example of a termination structure in accordance with one of the embodiments. In this example, the terminating bar TP1 has a width W1 greater than the width W2 of the terminating bar TP2, while W2 is made larger than the width W3 of the terminating bar TP3, and so on. With respect to the spacing between opposite polarity charge balance regions in the termination region, even though the center-to-center spacing between the channel strips in element 2900B may be the same, the structure produced in element 2900B is similar to that in element 2900A. In another exemplary embodiment illustrated in the simplified cross-sectional view of FIG. 29C, the width of each of the opposite polarity bars 2926C in the active region is reduced from the top surface to the substrate, while the widths of the terminating bars TP1 and TP2 are maintained. Roughly the same. This achieves the required breakdown voltage while utilizing a smaller area. Those skilled in the art will appreciate that the various termination structures described above can be combined in any desired manner, including, for example, the center-to-center spacing and/or overall width of the terminating bars in element 2900C shown in Figure 29C can be as described in conjunction with section 29A. And the description of the embodiment shown in Fig. 29B is changed as usual.

Processing technology

Several different components of a channel structure having multiple buried electrodes have been described to date. To bias these channel electrodes, these elements may allow electrical contact to be made to each buried layer. Several methods for forming a channel structure having buried electrodes and contacting the buried polysilicon layer on the inside of the channel are disclosed herein. In one embodiment, contact to the trench polysilicon layer is created on the edge of the die. Figure 30A shows a channel element 3000 and two more An example of edge contact of wafer layers 3010 and 3020. Figure 30A depicts a cross-sectional view of the component along the longitudinal axis of a channel. According to this embodiment, which terminates the channel near the edge of the die, polysilicon layers 3010 and 3020 are brought to the surface of the substrate for contact. Openings 3012 and 3022 in dielectric (or oxide) layers 3030 and 3040 are in metal contact with the polysilicon layer. Figures 30B through 30F show various processing steps for forming the edge contact structure of Figure 30A. In FIG. 30B, a dielectric (e.g., hafnium oxide) layer 3001 is patterned on top of the epitaxial layer 3006, and the exposed surface of the substrate is etched to form the trench 3002. A first oxide layer 3003 is then formed across the top surface of the substrate and includes a channel as shown in Figure 30C. A first layer of conductive material (e.g., polysilicon) 3010 is then formed on top of the oxide layer 3003 as shown in Figure 30D. Referring to FIG. 30E, the polysilicon layer 3010 is etched away inside the trench and another oxide layer 3030 is formed over the polysilicon 3010. A similar step is performed to form a second oxide-polysilicon-oxide embedded portion as shown in FIG. 30F, wherein the top oxide layer 3040 is shown as being etched to form a metal contact layer for the polysilicon layers 3010 and 3020, respectively. Openings 3012 and 3022 are used. The final step can be repeated for additional polysilicon layers, and the polysilicon can be bound together by the laid metal layer as desired.

In another embodiment, contact is made for multiple polysilicon layers in a given channel in the active region of the device rather than along the edge of the die. Figure 31A depicts an example of an active area contact structure for a multiple buried polysilicon layer. In this example, a cross-sectional view along the longitudinal axis of the channel shows a polysilicon layer 3110, and it supplies gate terminals and polysilicon layers 3111a and 3111b for providing two shield layers. Although three separate metal wires 3112, 3122 And 3132 are shown as making contact for the shielded polysilicon layer, which are tied together and connected to the source termination of the component, or any other combination of contacts can be used as needed for a particular application. An advantage of this configuration is that the contact system has a planar nature compared to the multilayer edge contact structure shown in Figure 30A.

Figures 31B through 31M show an example of a program flow for forming an active area shield contact structure for a channel of two polysilicon layers. The etching of the trench 3102 in Fig. 31B is followed by the formation of the shield oxide 3108 in Fig. 31C. The shielded polysilicon 3111 is then deposited and recessed inside the trench as shown in Figure 31D. The shielded polysilicon 3111 is more recessed in Figure 31E, except where the shielded contact of the substrate surface is required. In Fig. 31E, a mask 3109 protects the polysilicon inside the middle channel from further etching. In one embodiment, the mask is applied to different locations along different channels, so for example, for a mid-channel, the shielded polysilicon is recessed into other portions of the trench in a third dimension (not shown). In another embodiment, the shielded polysilicon 3111 inside one or more of the active channels in the active region is shielded along the entire length of the channel. The shield oxide 3108 is then etched as shown in FIG. 31F, and after the mask 3109 is removed, a thin layer of gate oxide 3108a is formed across the top of the substrate as shown in FIG. This is followed by gate polysilicon deposition and recession (Fig. 31H), p well implant and drive (Fig. 31I), and n+ source implantation (Fig. 31J). Sections 31K, 31L, and 31M depict steps of BPSG deposition, contact etching, and p+ heavy body implantation, followed by metallization, respectively. Figure 31N shows a cross-sectional view of an alternative embodiment of an active area shield contact structure in which a shielded polysilicon 3111 forms a relatively wide platform on top of the shield oxide. This will facilitate contact with the shielded polysilicon, but introduce a topological structure that may further complicate the process.

A simplified top view layout of an exemplary channel element having an active area shield contact structure is shown in Figure 32A. A mask for defining the recess of the polysilicon prevents the shielded polysilicon from being recessed into the active region and the perimeter shield channel 3213 at location 3211C. A modification of this technique uses a similar "dog bone" shape for the shielded polycrystalline recessed mask, which provides a wider area at the intersection with each channel 3202 to contact the shielded polysilicon. This allows the shielded polysilicon in the masked area to be recessed but the original surface of the mesa is excluded, thus eliminating the topography. A top plan view of an alternative embodiment is shown in Figure 32B, wherein the active region channel is connected to the peripheral channel. In this embodiment, the shielded polysilicon recessed mask is prevented from being recessed in the shielded polysilicon along a selected channel (the middle channel in the illustrated example) to allow the active region shield channel to contact the source metal. 32C and 32D are simplified layout diagrams showing two different embodiments for making contact with a peripheral channel in a channel element having a ruptured channel structure. In these figures, active channel 3202 and peripheral channel 3213 are depicted by a single line for illustrative purposes. In Fig. 32C, the extensions or fingers from the peripheral gate polysilicon channel 3210 are staggered relative to the perimeter shield polysilicon fingers to separate the perimeter contacts from the perimeter channels. The source and shield contact regions 3215 also make contact with the shielded polysilicon in the active region at location 3211C as shown. The embodiment shown in Fig. 32D eliminates the offset between the active and peripheral channels to avoid possible limitations due to channel spacing requirements. In this embodiment, the active channel 3202 and the horizontal extension from the peripheral channel 3213 are aligned, and the gate polysilicon channel 3210 The window 3217 in the middle allows for contact with the shielded polysilicon around the perimeter. As in the previous embodiment, active area contact is created in position 3211C.

An alternative embodiment for contacting a trench shielded polysilicon layer in the active region is shown in Figure 33A. In this embodiment, the shield polysilicon is not recessed, but extends vertically over a significant portion of the active channel until the surface of the germanium. Referring to Fig. 33A, the shield polysilicon 3311 splits the gate polysilicon 3310 into two when it extends vertically along the height of the channel 3302. The two gate polysilicon segments are connected at a suitable location inside the channel or in a third dimension as they exit the channel. An advantage of this embodiment is the area saved by creating a source polysilicon contact inside the active channel rather than using a trench-type polysilicon contact dedicated germanium space. Figures 33B through 33M show an example of a program flow for forming an active area shield contact structure of the type 33A. The etching of the channel 3302 in Fig. 33B is followed by the formation of the shield oxide 3308 shown in Fig. 33C. The shielded polysilicon 3311 is then deposited on the inside of the trench as shown in Figure 33D. The shield polysilicon 3311 is etched and recessed inside the trench as shown in Fig. 33E. Shield oxide 3308 is then etched as shown in Figure 33F, leaving an exposed portion of shielded polysilicon 3311 for forming two trenches on its sides on the inside of the trench. A thin layer of gate oxide 3308a then forms a trench across the top of the substrate, the sidewalls of the trench, and the inside of the trench as shown in Figure 33G. This is followed by gate polysilicon deposition and recession (Fig. 33H), p well implant and drive (Fig. 33I), and n+ source implantation (Fig. 33J). Figures 33K, 33L, and 33M depict steps of BPSG deposition, contact etching, and p+ heavy body implantation, followed by metallization, respectively. This program flow may have variations. For example, by rearranging the order of some of the program steps, a mask can be formed The step of forming the gate polysilicon 3310 is performed before the step of the polysilicon 3311.

Specific program recipes and parameters and variations thereof for performing many of the steps in the above described program flow are well known. For a given application, specific program recipes, chemistries, and material types can be fine-tuned to enhance the manufacturability and performance of the component. The improvement can be made from the starting material - that is, the substrate on top of which the epitaxial drift region can be formed. In most power applications, it is desirable to reduce the transistor on-resistance R _DSon . The ideal on-resistance of a power transistor is a strong function of the critical field, where the critical field is defined as the maximum electric field in the component under collapse conditions. If the component is fabricated from a material having a higher critical field than 矽, the specific on-resistance of the transistor can be significantly reduced under the constraints of maintaining reasonable mobility. While a number of power component characteristics, including structures and procedures, described so far have been described using a single substrate as a background, other embodiments of substrate materials other than tantalum may be used. According to an embodiment, the power components described herein are fabricated by, for example, including tantalum carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), diamonds, and the like. In a substrate made of a wide band gap material such as a material. These wide bandgap materials exhibit a higher critical field than the critical field of germanium and can have a significant reduction in transistor on-resistance.

Another major contributor to transistor on-resistance is the thickness and doping concentration from the drift region. The drift region is generally formed by epitaxially grown germanium. In order to reduce R _DSon , it is necessary to minimize the thickness of this epitaxial drift region. The thickness of the epitaxial layer depends in part on the type of starting substrate. For example, a red phosphorus doped substrate is a starting substrate material commonly used for one of the discrete semiconductor components. However, the nature of the phosphorus atom is such that it can diffuse rapidly in the crucible. Therefore, the thickness of the epitaxial region formed on the top of the substrate is determined to accommodate the upward diffusion of phosphorus atoms from the underlying heavily doped substrate.

In order to minimize the thickness of the epitaxial layer, according to an embodiment shown in FIG. 34, an epitaxial spacer or buffer (or barrier) layer 3415 of a dopant having a relatively small diffusivity such as arsenic is formed. Above the phosphorous substrate 3414. The combined phosphorus-doped substrate and the arsenic-doped buffer layer provide the basis for subsequent formation of the epitaxial drift region 3406. The concentration of arsenic dopant in layer 3415 is dependent on the breakdown voltage requirement of the component, while the thickness of arsenic epitaxial layer 3415 depends on the particular thermal budget. Subsequently, a conventional epitaxial layer 3406 can be deposited on top of the arsenic epitaxial layer, the thickness of which is determined by the component requirements. The fact that arsenic is far lower diffuse allows the overall thickness of the epitaxial drift region to decrease, resulting in a decrease in the on-resistance of the transistor.

In an alternative embodiment, a diffusion barrier is employed between the two layers in order not to diffuse the dopant species from the heavily doped substrate up to the epitaxial layer. According to an exemplary embodiment shown in Fig. 35, a barrier layer 3515 composed of, for example, tantalum carbide Si _x C _1-X is epitaxially deposited on a boron or phosphor substrate 3514. Epitaxial layer 3506 is then deposited atop barrier layer 3515. Thickness and carbon composition may vary depending on the thermal budget of the processing technology. Alternatively, the carbon dopant may be implanted in the substrate 3514 first, and then activated to heat the carbon atoms on the surface of the substrate 3514 to form a compound of Si _x C _1-x.

Another aspect of a particular channel transistor technique used to limit the ability to reduce epitaxial thickness is that it is sometimes used in the active region and sometimes between the deep body and the epitaxial layer in the termination region. The junction. The formation of this deep body region typically involves an implantation step at an early stage of the procedure. Due to the large subsequent thermal budget required for the formation of field oxides and gate oxides, the junctions in the deep body region and the drift region are rated to have a wide range. In order to avoid early collapse at the edge of the grain, a much thicker drift region is required resulting in a higher on-resistance. A diffusion barrier layer can also be used on the deep body-epitaxial junction to minimize the required epitaxial thickness. According to an exemplary embodiment illustrated in Fig. 36, the carbon dopant is implanted through the deep body window prior to the deep body implantation. The subsequent thermal process activates the carbon atoms to form a layer of Si _x C _1-x compound 3615 at the boundary of the deep body region 3630. The tantalum carbide layer 3615 acts as a diffusion barrier against boron diffusion. The resulting deep body junction is shallower to reduce the thickness of the epitaxial layer 3606. One of the other junctions in a typical channel transistor that can benefit from a diffusion barrier is a well-drift junction. A simplified example of an embodiment employing this barrier layer is shown in Figure 37. In the exemplary program flow of the structure of Fig. 31M, a p well is formed between the two steps shown in Figs. 31H and 31I. Carbon is implanted prior to implantation of the well dopant (p-type in this exemplary n-channel embodiment). Subsequent thermal procedures activate the carbon atoms to form a layer of 3715Si _x C _1-x on the epitaxial junction of the p-well. Layer 3715 acts as a diffusion barrier to prevent boron diffusion thereby preserving the depth of p-well 3704. This helps to reduce the length of the transistor via without increasing the potential for reach-through. At the edge of the current vacant boundary, a breakdown occurs as the 汲-source voltage increases and the source junction is touched. Layer 3715 also prevents contact through by acting as a diffusion barrier.

As mentioned above, it is desirable to reduce the transistor path length as this will result in a reduction in the on-resistance. In another embodiment, the epitaxially grown germanium is used to form the well region to minimize the transistor path length. That is, do not use inclusion Into the drift epitaxial layer, followed by a conventional method for forming a well in a diffusion step, the well region is formed on top of the epitaxial drift layer. The advantage of a shorter length of the passage can be obtained by using an epitaxial well forming system. In the shielded gate channel transistor, for example, for determining the gate charge Qgd, the gate electrode extends below the bottom of the well and the distance to the channel (gate to 汲 overlap) is of critical importance. The gate charge Qgd directly affects the switching speed of the transistor. Therefore, it is necessary to be able to accurately reduce and control this distance as much as possible. However, in the process in which the well as shown is implanted and diffused into the epitaxial crystal, as in the above-mentioned 31st I, it will be difficult to control this distance.

In order to better control the gate-to-汲 overlap on the well profile, various methods for forming a channel element having a self-aligned well are proposed. In one embodiment, a program flow system comprising depositing an epitaxial well enables self-alignment of the bottom of the body junction to the bottom of the gate. Referring to Figures 38A-38D, an exemplary simplified program flow of a self-aligned epitaxial well channel element having an embedded electrode (or shielded gate) is shown. A channel 3802 is etched into a first epitaxial layer 3806 formed on top of the substrate 3814. For an n-channel transistor, the substrate 3814 and the first epitaxial layer 3806 are of an n-type material.

Figure 38A shows a layer of shielding dielectric 3808A grown on the top surface of epitaxial layer 3806 included on the inside of trench 3802. Conductive material 3811, such as polysilicon, is then deposited inside channel 3802 and etched back below the epitaxial mesa, as shown in FIG. 38B. An additional dielectric material 3809S is deposited to cover the shielded polysilicon 3811. After the dielectric etch back to remove the mesa, as shown in FIG. 38C, a second epitaxial 3804 is selectively grown atop the first epitaxial layer 3806. The mesa formed by the epitaxial layer 3804 is as shown in the original channel An upper channel portion is generated above 3802. The second epitaxial layer 3804 has a dopant of opposite polarity (eg, p-type) to the first epitaxial layer 3806. The dopant concentration in the second epitaxial layer 3804 is set to the desired level of the transistor well region. After the step of forming a selective epitaxial growth (SEG) of layer 3804, a layer of gate dielectric 3808G is formed on the top surface and formed along the sidewalls of the channel. The gate conductive material (polysilicon) is then deposited to fill the remainder of the trench 3802 and then planarized as shown in Figure 38D. This procedure is continued, for example, in the program flow shown in Figures 31J through 31M to complete the transistor structure.

As shown in Fig. 38D, this procedure results in a gate polysilicon 3810 that is self-aligned with well epitaxy 3804. To lower the bottom of the gate polysilicon 3810 below the epitaxial well 3804, as shown in FIG. 38C, the top surface of the interstitial polysilicon dielectric layer 3809A can be slightly etched to the desired location inside the trench 3802. Therefore, this procedure provides precise control of the distance between the bottom of the gate electrode and the well profile. It is understood by those skilled in the art that the SEG well forming procedure is not limited to a shielded gate channel transistor and can be used in many other trench gate transistor structures and many of which have been described herein. Other methods for forming the SEG platform structure are described in U.S. Patent No. 6,391,699 to Madson et al., and Bruker et al. 6,373,098, each of which is incorporated by reference in its entirety. Incorporated herein.

An alternative approach to controlling the corners of a well based on self-aligned use does not rely on SEG well information, but rather a procedure involving the implantation of a beveled well. Figures 39A and 39B show an exemplary program flow of this embodiment. It is not the case that the well is formed after the channel is filled with the gate polysilicon as shown in FIGS. 31H and 31I. In this embodiment, the dielectric of the shield polysilicon is embedded inside the channel 3902. A first well implant 3905 at a given portion of the dose is performed after layer 3908 and before the remainder of the channel is filled. A second, but beveled, well implant is then performed through the sidewalls of the channel 3902 as shown in FIG. 39B. The drive cycle is then completed to obtain the desired profile for the well to drift epitaxial interface on the corners of the channel. The specific details of the implant dose, energy, and drive cycle will vary depending on the structural requirements of the component. This technique can be used in several different component types. In an alternative embodiment, the channel spacing and angle implant system is adjusted such that when the angle implant is diffused, it merges regions from an adjacent unit cell to form a continuous well without the need for a first well In.

Another embodiment of a self-aligned epitaxial well procedure for forming a channel element is described in conjunction with Figures 40A through 40E. As described above, in order to reduce the gate-to-tantalum capacitance, the partial channel gate transistor system employs a gate dielectric layer that is thicker at the bottom of the channel below the gate polysilicon than the dielectric layer along the inner vertical sidewall. According to the exemplary program embodiment shown in FIGS. 40A through 40E, a dielectric layer 4008B is first formed on top of an epitaxial drift layer 4006, as shown in FIG. 40A. Dielectric layer 4208B forms the desired thickness of the bottom of the trench and is subsequently etched to leave a dielectric post having the same width as the subsequently formed trench as shown in FIG. 40B. Next, in FIG. 40C, a selective epitaxial growth step is performed to form a second epitaxial drift layer 4006-1 around the dielectric pillar 4008B. The second drift epitaxial layer 4006-1 has the same conductivity type as the first epitaxial drift layer 4006 and may be made of the same material. Alternatively, other types of materials may be used for the second epitaxial drift layer 4006-1. In an exemplary embodiment, the second drift epitaxial layer 4006-1 is formed by a SEG step that is subjected to a germanium telluride (Si _x Ge _1-x ) alloy. The SiGe alloy system improves carrier mobility near the accumulation region at the bottom of the channel. This improves the switching speed of the transistor and reduces R _DSon . Other compounds such as GaAs or GaN may also be used.

A blanket epitaxial layer 4004 is then formed on the top surface and then etched to form the trench 4002 as shown in Figures 40D and 40E, respectively. This is followed by gate oxide formation and gate polysilicon deposition (not shown). The resulting structure is a channel gate with a self-aligned epitaxial well. The remaining processing steps can be accomplished using conventional processing techniques. Those skilled in the art understand that there may be variations. For example, instead of forming a blanket epitaxial well layer 4004 and subsequently etching the trench 4002, the epitaxial well 4002 can selectively grow only on top of the second drift epitaxial layer 4006-1 to form the trench 4002 as it grows.

The various processing techniques described above focus on the formation of the well region to reduce the path length and R _{DSon to} enhance component performance. Similar enhancements can be achieved by improving the pattern of program flow. For example, the element resistance can be further reduced by reducing the thickness of the substrate. Therefore, a wafer thinning process is usually performed to reduce the thickness of the substrate. Wafer thinning is generally performed by mechanical polishing and tape winding procedures. The grinding and tape-drawing process applies mechanical force to the wafer which can cause damage to the wafer surface, causing manufacturing problems.

In one embodiment described below, an improved wafer thinning process significantly reduces substrate resistance. A method for reducing the thickness of a substrate is shown in Figures 40R, 40S, 40T and 40U. After the required circuitry is fabricated on a wafer, the top of the wafer that can be used to fabricate the circuit is temporarily bonded to a carrier. Figure 40R shows once wafer 4001 is completed and bonded to a carrier 4005 by a bonding material 4003. After the completion of the back side of the wafer, a A program such as grinding, chemical etching or the like is polished to the desired thickness. Fig. 40S shows that the wafer 4001 that has been thinned has the same inlay as the 40R. After the back side of the wafer 4001 is polished, the backside of the wafer is bonded to a low resistance (e.g., metal) wafer 4009 as shown in FIG. 40T. This effect can be achieved by, for example, bonding a metal wafer 4009 to a thinned wafer 4001 using a thin coating of solder 4007 under temperature and pressure. The carrier 4005 is then removed and the top surface of the wafer 4001 is cleaned prior to further processing by thinning. The highly conductive metal substrate 4009 facilitates heat dissipation, reduces electrical resistance, and provides mechanical strength to the thinned wafer.

An alternative embodiment utilizes a chemical process to perform the final thinning step to achieve a thinner wafer without the drawbacks of conventional mechanical procedures. According to this embodiment, the active component is formed in a layer of a SOG (silicon-on-thick-glass) substrate. In the grinding stage, the wafer can be thinned by chemically etching the glass on the back side of the SOTG substrate. Figure 41 depicts an exemplary program flow in accordance with one such embodiment. Starting from a silicon substrate, first in step 4110, such as a He, H _2, based dopant implanted into the silicon substrate. Then, at 4112, the tantalum substrate is bonded to a glass substrate. Different combination procedures can be used. In one example, a stack of wafers and a glass wafer are clamped and heated to about 400 ° C to bond the two substrates. The glass can be, for example, cerium oxide and the like, and can have a thickness of, for example, about 600 microns. This is followed by a selective wall cut of the tantalum substrate in 4114 and formation of the SOTG substrate. To protect the substrate from stress during handling and subsequent processing, the bonding process can be repeated to form a SOTG layer on the other side of the substrate (step 4116). An epitaxial layer is then deposited on the surface of the substrate (step 4118). This effect can be performed on the back side except for the front side. The doping level of the dorsal epitaxial layer is preferably similar to that of the dorsal side, but the front side epitaxial system is doped as required by the element. The substrate is then subjected to a variety of different steps in the process for forming the active component on the front side layer.

In one embodiment, to further enhance the strength of the substrate to withstand the stress introduced by the front side processing step, the backside substrate can be patterned to approximate an inverted structure of the front side grain frame. In this manner, the glass substrate is etched into a grid to help the thin substrate maintain stress in the wafer. When grinding, first, the ruthenium layer from the back side is removed by a conventional grinding procedure (step 4120). This is followed by another grinding step 4122 for removing a portion of the glass, such as half. The remainder of the glass is then removed by a chemical etching procedure such as the use of hydrofluoric acid. The etching of the backside glass can be performed without the risk of invasive or mechanical damage to the active layer. This eliminates the need to reel the wafer, thereby eliminating the risk of tape and rewinding equipment and the procedural processes associated with each of these operations. To this end, this procedure allows for further reduction in substrate thickness to enhance component performance. Please understand that this improved wafer thinning process can have many variations. For example, depending on the desired thickness of the final substrate, the thinning step may or may not include grinding and chemical etching may be sufficient. Moreover, the improved wafer thinning process is not limited to the processing of discrete components and can be used in the processing of other types of components. Other wafer thinning procedures are described in U.S. Patent No. 6,500,764, the entire disclosure of which is incorporated herein by reference.

There are several other structural and processing aspects of power transistors and other power components that can significantly affect performance. The shape of the channel is an example. In order to reduce potentially damaging electric fields that tend to concentrate around the corners of the channel, it is necessary to avoid sharp corners but to form channels with rounded corners. In order to improve reliability, it is also desirable to have a channel sidewall that presents a flat surface. Different etch chemistries provide trade-offs between several such responses: 矽 etch rate, sensitivity to mask layer, etch profile (sidewall angle), top corner rounding, sidewall roughness, and channel The bottom is rounded. A fluorochemical system such as SF ₆ provides a high enthalpy etch rate (greater than 1.5 microns/min), a smooth channel bottom, and a linear profile. Fluorine-containing chemical defects are rough sidewalls and it is difficult to control the top of the channel (which can be a cavity). A chlorine-containing chemistry such as Cl ₂ provides better control of the flatter sidewalls, and the top of the trench and the etch profile. The trade-off relationship between chlorine-containing chemistry is a lower ruthenium etch rate (less than 1.0 micron/min) and a smaller channel bottom rounding effect.

Additional gas can be added to each chemistry to help passivate the sidewalls during etching. Sidewall passivation is utilized to minimize lateral etching while etching to the desired channel depth. Additional processing steps can be utilized to smooth the channel sidewalls and achieve rounding of the bottom and top corners of the trench. The surface quality of the trench sidewalls is important because it affects the quality of an oxide layer that can grow on the sidewalls of the trench. Regardless of the chemistry used, a breakthrough step is typically used prior to the main etch step. The purpose of the breakthrough step is to remove any native oxide on the etched surface of the etch that may be exposed during the main etch step. A typical breakthrough etch chemistry consists of CF ₄ or Cl ₂ .

One embodiment of an improved etch process illustrated in Figure 42A employs a chlorine-based main channel etching followed by a fluorine-based etching step. An example of this procedure is the Cl ₂ /HBr main etch step followed by an SF ₆ etch step. A chlorine containing step is used to etch the main trench to a portion of the desired depth. This defines a channel profile with a partial degree of push and a flat sidewall. The subsequent fluorine-containing step is used to etch the remainder of the channel depth to round the bottom of the trench and further smooth any hanging ruthenium bonds on the sidewalls of the trench. The fluorine-containing etching step is preferably performed at a relatively low fluorine flow rate, low pressure, and low power to control smoothing and smoothing. Due to the difference in etch rate between the two etch chemistries, the two-step time can be balanced to achieve a more reliable and manufacturable process with an acceptable overall etch time while maintaining the desired channel profile, sidewall roughness And the bottom of the channel is rounded.

In another embodiment, illustrated in Figure 42B, a modified method for ruthenium etching includes a fluorine-based main etch step followed by a chloro-based second etch step. An example of this procedure uses an SF ₆ /O ₂ main etch followed by a Cl ₂ step. A fluorine step is used to etch most of the depth of the main channel. This step produces a channel having linear sidewalls and a rounded channel bottom. Oxygen can be selectively added to this step to provide sidewall passivation and help maintain a linear sidewall by reducing lateral etching. The subsequent step of monochlorination smoothes the top corner of the channel and reduces the roughness of the sidewall. The high etch rate of the fluorine step increases the manufacturability of the process by increasing the output of the etch system.

As shown in Fig. 42C, in another embodiment, an improved ruthenium etch process is obtained by adding argon to a fluoro group chemistry. An example of one of the chemistries used in the main etching step according to this embodiment is SF ₆ /O ₂ /Ar. By adding argon to the etching step, ion bombardment can be increased and thus the etching is made more specific. This helps control the top of the channel and relieves the top of the channel from becoming a cavity. The addition of argon also increases the rounding of the bottom of the channel. An additional etching procedure may be required for sidewall smoothing.

An alternative embodiment for an improved ruthenium etch process uses a fluoro-based chemistry and the beginning of its autonomous etch step begins to remove oxygen, as shown in Figure 42D. An example of this procedure uses an SF ₆ step followed by an SF ₆ /O ₂ step. In the first stage of etching, sidewall passivation is lacking due to the absence of O ₂ . This results in an increase in the amount of lateral etching of the top of the channel. Then, a second etching step, SF ₆ /O ₂ , continues to etch the remainder of the channel depth in a straight line profile with a rounded channel bottom. This results in a wider channel structure at the top, sometimes referred to as a T-channel. An example of a component employing a T-channel structure is described in detail in the US patent entitled "Structure and Method for Forming a Channel MOSFET with Self-Aligned Characteristics" by Robert Herrick. Application No. 10/442,670 (office number 18865-131/17732-66850), which is incorporated herein in its entirety by reference. The length of time of the two main etching steps can be adjusted to achieve the desired depth for each portion of the T-channel (top T portion, bottom straight sidewall portion). Additional processing can be utilized to round the top corners of the T-channel and smooth the channel sidewalls. These additional methods may include, for example: (1) a fluorine-based step of the channel etch recipe endpoint, or (2) a separate fluorine-based etch on a separate etch system, or (3) a sacrificial oxide , or any other combination. A chemical mechanical planarization (CMP) step can be used to remove the top cavity portion of the channel profile. An H ₂ anneal can also be used to help the channel profile become rounded and produce a favorable slope.

For high voltage applications that tend to have deeper channels, there are additional considerations. For example, due to the deeper channel, for the process of producing manufacturability It is said that the etch rate is very important. Because the chlorination etch chemistry is too slow, the etch chemistry of this application is typically a fluorochemical. Also, a channel profile that is linear to push-out is required and has a flat sidewall. Due to the depth of the channel, the etching process also requires excellent sensitivity to the mask layer. If the sensitivity is poor, a thicker mask layer is needed, and the overall size ratio of the characteristics is increased. Side passivation is also critical; a delicate balance is required. Excessive sidewall passivation will cause the bottom of the trench to narrow to the extent of closure; too small sidewall passivation will result in increased lateral etching.

In one embodiment, a deep trench etch process that optimally balances all of these requirements is provided. As shown in FIG. 42E, in accordance with this embodiment, the etching process includes a fluorine-based chemistry having ramped O ₂ , ramping power, and/or ramping pressure. An exemplary embodiment uses an etch step in a manner that maintains an etch profile and a ruthenium etch rate during the overall etch. By ramping O ₂ , the amount of sidewall passivation can be controlled in the overall etch to avoid increased lateral etch (in the case of too little passivation) or to clamp the bottom of the trench (in the case of too much passivation). An example of the use of a fluorine-based etch with a ramp-enhanced oxygen stream is described in detail in commonly-owned U.S. Patent No. 6,680,232, entitled "Integrated Circuit Channel Etching with Incremental Oxygen Flow," which is incorporated by reference. Into this article. The ramping in power and pressure will help control ion flux density and contribute to the etch rate. If the erbium etch rate is significantly reduced during etching as the channel etches deeper, the total etch time will increase. This will result in low wafer yield for the process on the etch machine. Also, the ramp up of O ₂ may help control the sensitivity to the mask material. An exemplary procedure according to this embodiment for a channel deeper than 10 microns can have 3 to 5 sccm per minute at a power level of 10-20 watts per minute and a pressure level of 2-3 mT per minute. O ₂ flow rate.

An alternative a deep trench etch process using an embodiment of the system, such as a fluorine-based NF ₃ chemistry more aggressive. Since NF ₃ is more reactive than SF ₆ for germanium etching, an increased germanium etch rate can be achieved by the NF ₃ procedure. Additional gas may need to be added for sidewall passivation and contour control.

In another embodiment, an NF ₃ etching step is followed by an SF ₆ /O ₂ procedure. According to this embodiment, most of the channel depth is etched at a high erbium etch rate using the NF ₃ step. The SF ₆ /O ₂ etch step is then used to passivate the existing trench sidewalls and etch the rest of the trench depth. In a variation of this embodiment illustrated in Figure 42F, the NF ₃ and SF ₆ /O ₂ etching steps are performed in an alternating manner. This produces a program that has a higher etch rate than the linear SF ₆ /O ₂ program. It strikes a balance between a fast etch rate step (NF ₃ ) and a step for contour control to create sidewall passivation (SF ₆ /O ₂ ). The balance of the steps controls the roughness of the sidewalls. It may also be desirable to ramp the pressure, power, and O _{2 of the} etched SF ₆ /O ₂ portion to maintain the erbium etch rate and create sufficient sidewall passivation to help control the etch profile. Those skilled in the art will appreciate that the various steps described in connection with the above embodiments can be combined in different ways to achieve an optimal channel etch process. It is also understood that these channel etch procedures can be used for any of the power devices described herein, as well as for any other type of channel used in other types of integrated circuits.

Prior to the trench etch process, a trench etch mask is formed on the surface of the crucible and patterned to expose the areas to be channelized. As shown in Fig. 43A, in a typical device, the trench etch is first etched before etching the germanium substrate. Pass a layer of oxide 4305 and another thin layer of pad oxide 4303. After the oxide layer is formed in the trench, after the trench is formed, the pad oxide 4303 may also grow on the edge of the trench to lift the deposited nitride layer. The pad oxide locally grows near the edge of the channel under the oxide layer 4305, which results in a structure 4307 commonly referred to as "guanine." Subsequent to the guanine structure, the source region formed beside the edge of the channel under the pad oxide is shallower near the channel. This is a very bad effect. In order to eliminate the guanine effect, in one embodiment, as shown in Fig. 43B, a layer of non-oxidizing material such as polysilicon 4309 is sandwiched between oxide 4305 and pad oxide 4303. The polysilicon layer 4309 prevents pad oxide 4303 from further oxidizing during subsequent channel oxide formation. In another embodiment, as shown in FIG. 44A, after etching the nitride layer 4405 and the pad oxide 4403 to define the channel opening, a thin layer of non-oxidizing material 4405-1 such as nitride is formed on the surface. Structurally. The protective layer 4405-1 is then removed from the horizontal surface leaving a spacer along the vertical edge of the nitride-pad oxide structure, as shown in FIG. 44B. The oxide spacer is the protective pad oxide 4403 which is not subject to further oxidation during subsequent steps to reduce the guanine effect. In an alternative embodiment, to reduce the extent of any guanine formation, both embodiments of Figures 43B and 44B may be combined. That is, in addition to the spacers resulting from the procedures described in Figures 44A and 44B, a layer of polycrystalline germanium may be sandwiched between the pad oxide and the overlying oxide. There may be other variations, such as the addition of another layer (such as an oxide) on top of the nitride to help etch the nitride selectivity of the germanium channel.

As described above in connection with various different transistors having a shielded gate structure, a layer of dielectric material isolates the shield electrode from the gate electrode. Sometimes called The inter-electrode dielectric layer of the interstitial polysilicon dielectric or IPD must be formed in a strong and reliable manner to withstand potential differences that may exist between the shield electrode and the gate electrode. Referring again to Figures 31E, 31F and 31G, a simplified flow of the relevant program steps is shown. After the shield polysilicon 3111 on the inner side of the trench is dispersed (FIG. 31E), the shield dielectric layer 3108 is etched back to the same level as the shield polysilicon 3111 (FIG. 31F). The gate dielectric layer 3108a is then formed on the top surface of the crucible as shown in Fig. 31G. It is this step that forms the IPD layer. The artifact of shielding dielectric recess etching is that shallow trenches are formed on the top surface of the shield dielectric that remains on either side of the shield electrode. This is shown in Figure 45A. The resulting structure with an uneven topology may pose a problem of conformality, particularly for subsequent filling steps. In order to eliminate such problems, various improved methods for forming IPDs have been proposed.

According to an embodiment, after the dielectric recess etch is masked, a polysilicon liner 4508P is deposited, for example, using a low pressure chemical vapor deposition (LPCVD) process as shown in FIG. 45B. Alternatively, a selective growth process of the polysilicon or a collimated sputtering of the polysilicon can be used to form the polysilicon liner 4508P only over the shielded polysilicon and the shield dielectric such that the sidewalls of the trench are substantially free of polysilicon. The polysilicon liner 4508P is subsequently oxidized to convert to cerium oxide. This effect can be carried out by a conventional thermal oxidation procedure. In embodiments where no polysilicon is formed on the sidewalls of the trench, this oxidation process also forms the gate dielectric layer 4508G. Otherwise, after etching the oxidized polysilicon layer from the sidewall of the trench, a thin layer of gate dielectric 4508G is formed and the remaining trench cavity is filled with gate electrode 4510 as shown in FIG. 45C. One advantage of this procedure is that the polycrystalline lanthanide is deposited in a highly conformal manner. Once the polysilicon is deposited on the shield dielectric On top of the quality and shielding electrodes, this minimizes voids and other defects and creates a flatter surface. The result is a stronger and more reliable modified IPD layer. By padging the trench sidewalls and adjacent germanium surface regions with polysilicon prior to oxidation, a subsequent oxidation step results in less mesa consumption and minimizes poor channel widening.

In an alternative embodiment, in the simplified cross-sectional view shown in Figures 46A, 46B, and 46C, the cavity inside the trench caused by the masked polysilicon recessed etch is filled with a similar etch rate to the shield dielectric 4608S. Dielectric filling material 4608F. This step can be performed using either high density plasma (HDP) oxide deposition, chemical vapor deposition (CVD), or spin on glass (SOG) procedures, followed by a planarization step to obtain at the top of the trench. A planar surface. Dielectric fill material 4608F and shield dielectric material 4608S are then uniformly etched back to leave a layer of insulating material having the desired thickness over shield electrode 4611, as shown in FIG. 46B. The channel sidewalls are then lined with a gate dielectric and the remaining channel cavity is filled with gate electrodes as shown in Figure 46C. The result is a highly orthotropic IPD layer without topological inhomogeneities.

Another exemplary embodiment of another method for forming a high quality IPD is shown in the simplified cross-sectional views of Figures 47A and 47B. After the shield dielectric layer 4708S is formed on the inside of the trench and the cavity is filled with the shield polysilicon 4711, a masked polysilicon etch back step is performed to recess the shield polysilicon into the inside of the trench. In this embodiment, the shield polysilicon recessed etch system leaves more polysilicon in the trench such that the top surface of the recessed shielded polysilicon is higher than the final target depth. The thickness of the excess polysilicon on the surface of the shielded polycrystalline dome is designed to be approximately the same as the thickness of the target IPD. This upper portion of the shield electrode is then subjected to crop rational or chemical changes to further enhance its rate of oxidation. A method for chemically or physically changing the electrode can be performed by implanting impurity ions such as fluorine or argon ions into the polycrystalline silicon, respectively, to enhance the oxidation rate of the shield electrode. Preferably, implantation is performed at zero degrees, i.e., perpendicular to the shield electrode, as shown in Fig. 47A, so that the channel sidewalls are not physically or chemically altered. Next, the shield dielectric 4708S is etched to remove the dielectric from the sidewalls of the trench. This shielded dielectric recessed etch system causes a slight recess in the remaining shield dielectric adjacent to shield electrode 4711 (similar to that shown in Figure 45A). This is followed by a conventional oxidation step in which the top of the shielded polysilicon 4711 is thus oxidized at a faster rate than the sidewalls of the channel. This results in an insulator 4708T that is significantly thicker than the sidewalls along the surface of the trench, formed over the shield electrode. The thicker insulator 4708T above the shield electrode forms an IPD. The modified polycrystalline lanthanum is oxidized in the lateral direction and also compensates for the formation of the grooves in the top surface of the dielectric dielectric due to the shielding of the dielectric dielectric recess. A conventional step is then performed to form a gate electrode in the channel resulting from the structure shown in Figure 47B. In one embodiment, the shield electrode is modified to obtain a ratio of IPD in the range of 2:1 to 5:1 for gate oxide thickness. In one example, about 2000 formed over the shield electrode IPD, if a 4:1 ratio is selected, approximately 500 is formed along the sidewall of the channel The gate oxide.

In an alternative embodiment, the physical or chemical alteration step is performed after a shield dielectric recess etch. That is, the shield oxide 4708S is etched to remove oxide from the sidewalls of the trench. This exposes the upper portion of the crucible and the shield electrode to a physical or chemical modification as described above. Due to the channel wall The side is exposed and the changing step is limited to the horizontal surface, ie only the countertop and the shield electrode. Altering methods such as ion implantation of dopants will be performed at zero degrees (perpendicular to the shield electrode) so that the channel sidewalls are not physically or chemically altered. A conventional step is then performed to form a gate electrode in the channel to cause a thicker dielectric over the shield electrode.

Another embodiment for forming a modified IPD layer is shown in Figure 48. In accordance with this embodiment, a thick insulator layer 4808T, such as an oxide, is formed over the recessed shield oxide 4808S and shield electrode 4811. The thick insulator 4808T is preferentially formed (i.e., "filled from the bottom up") using directional deposition techniques such as high density plasma (HDP) deposition or plasma enhanced chemical vapor deposition (PECVD). The directional deposition results in a significantly thicker insulator along the vertical surface (ie, along the sidewall of the trench) along the horizontal surface (ie, over the shield electrode and the shield oxide), as shown in FIG. . An etch step is then performed to remove oxide from the sidewall while leaving sufficient oxide above the shielded polysilicon. A conventional step is then performed to form the gate electrode in the channel. One advantage of this embodiment in addition to obtaining a positive-form IPD is that tabletop consumption and channel widening can be prevented because IPD is formed via a deposition process rather than an oxidation process. Another benefit of this technology is the rounding effect at the top corner of the channel.

In another embodiment, after the dielectric and shielding polysilicon are recessed, a thin layer of screen oxide 4908P grows inside the channel. A layer of tantalum nitride 4903 is then deposited to cover the screen oxide 4908P as shown in Figure 49A. The tantalum nitride layer 4903 is then anisotropically etched such that it is removed from the bottom surface of the trench (i.e., over the shielded polysilicon) but not from the sidewall of the trench. Resulting knot The structure is shown in Figure 49B. The wafer is then exposed to an oxidizing environment, causing a thick oxide 4908T to be formed on the surface of the shielded polysilicon as shown in Figure 49C. Since the nitride layer 4903 is resistant to oxidation, significant oxide growth does not occur along the sidewalls of the channel. The oxide layer 4903 is then removed, for example, by wet etching using hot phosphoric acid. This is followed by conventional procedural steps to form gate oxide and gate dielectric as shown in Figure 49D.

In some embodiments, the forming of the IPD layer includes an etching process. For example, for embodiments in which an IPD film is deposited over a topography, it is possible to first deposit a film layer that is much thicker than the final IPD thickness required. The purpose of accomplishing this is to obtain a planar film layer to minimize the dishing of the starting layer into the channel. The thicker film, which may completely fill the trench and extend over the surface of the crucible, is then etched to reduce its thickness to the target IPD layer thickness. According to an embodiment, the IPD etch process is performed in at least two etching steps. The first step is intended to planarize the film back to the surface of the crucible. Etching uniformity is important in this step. The second step is intended to recess the IPD layer to the desired depth (and thickness) within the channel. In this second step, the IPD film is important for the etch selectivity of the ruthenium. During the recess etch step, the mesas are exposed and the trench sidewalls and IPD layers are also recessed into the trench. Any loss of helium on the mesa will affect the actual channel depth, and if a T-channel is included, the depth of T is also affected.

In an exemplary embodiment illustrated in FIG. 50A, an anisotropic plasma etch step 5002 is utilized to planarize the IPE film down to the ruthenium surface. An exemplary etch rate for plasma etching may be 5000 A/min. This is followed by an isotropic wet etch 5004 to recess the IPD into the channel. Better use of a pair of cookware The selectively controlled solution is wet etched so as not to attack the sidewalls of the crucible when exposed and provide a reproducible etch to achieve a particular recess depth. An exemplary chemistry for wet etching may be a 6: 1 buffered oxide etch (BOE), which produces an etch rate of about 1100 A/min at 25C. U.S. Patent No. 6,465,325 to Rodney Ridley, which is incorporated herein by reference in its entirety, in its entirety, is incorporated herein by reference. The first plasma etch step for planarization results in the IPD layer above the channel having a smaller dishing than the wet etch. The second wet etch step of the recess etch results in better selectivity to ruthenium and less damage than occurs with plasma etch. In an alternative embodiment shown in FIG. 50B, a chemical mechanical planarization (CMP) is utilized to planarize the IPD film down to the crucible surface. This is followed by a wet etch to recess the IPD into the channel. The CMP process results in a smaller discoid depression of the IPD layer above the channel. The wet etching step of the recessed embodiment results in better selectivity to ruthenium and less damage to ruthenium than CMP. These programs may also have other combinations.

In a structure other than an IPD including a channel and a planar gate dielectric, an interlayer dielectric, and the like, it is necessary to form a high quality insulating layer. The most commonly used dielectric material is cerium oxide. There are several parameters for defining a high quality oxide film. The main properties are uniform thickness, good integrity (low interface trap density), high electric field collapse strength, and low leakage levels and other properties. One of the factors that affect many of these properties is the rate of growth of the oxide. It is necessary to be able to precisely control the growth rate of the oxide. During thermal oxidation, there is a gas phase reaction with charged particles on the surface of the wafer. In one embodiment, an external potential is applied to the wafer to affect the charge, typically helium and oxygen. The particles increase or decrease the rate of oxidation to effect a method for controlling the rate of oxidation. This differs from plasma enhanced oxidation in that no plasma (with reactive species) is formed above the wafer. Also, according to this embodiment, the gas is not accelerated toward the surface; it is only prevented from reacting with the surface. In an exemplary embodiment, a high temperature capable reactive ion etching (RIE) chamber can be used to adjust the required energy level. The RIE chamber is used not only for etching but also for applying a DC bias to control the energy required to slow down and stop oxidation. Figure 51 is a flow chart of an exemplary method in accordance with one of the embodiments. Initially, the RIE chamber was used to apply a DC bias to the wafer (5100) in a test environment. After determining the potential energy required to suppress the surface reaction (5200), apply an external bias (5120) large enough to prevent oxidation. The rate of oxidation at a more extreme temperature (5130) can then be controlled by manipulating the external bias, such as by pulsing or other means. This method can attain the benefits of high temperature oxidation (better oxide flow, lower stress, elimination of differential growth of various crystal orientations, etc.) without the drawback of rapid and uneven growth.

While techniques such as those described above in connection with Figure 51 can improve the quality of the resulting oxide layer, especially for trench gate components, oxide reliability remains a concern. One major degradation mechanism is due to the high electric field at the corners of the channel, which is due to local thinning of the gate oxide at these points. This results in high gate leakage current and low gate oxide breakdown voltage. This effect is expected to become more severe as the channel element is further shrunk to lower the on-resistance and will result in a thinner gate oxide due to reduced gate voltage requirements.

In one embodiment, the use of a dielectric material (high-k dielectric) having a higher dielectric constant than cerium oxide mitigates the concern of gate oxide reliability. This allows for a lower, lower limit voltage and mutual conductance with a much thicker dielectric. According to this embodiment, the high K dielectric system reduces gate leakage and increases the gate dielectric breakdown voltage without degrading the on-resistance or the smash breakdown voltage of the element. High-k materials that can exhibit the required thermal stability and appropriate interface state density for integration in trench gates and other power components include Al ₂ O ₃ , HfO ₂ , Al _x HfyO _Z , TiO ₂ , ZrO ₂ And similar.

As described above, in order to improve the switching speed of the trench gate power MOSFET, it is necessary to reduce the transistor gate to the tantalum capacitor Cgd as much as possible. The use of a dielectric layer thicker than the channel sidewalls on the bottom of the trench is one of several methods described above for reducing Cgd. A method for forming a thick-bottom oxide layer includes forming a thin layer of mesh oxide along the sidewalls and the bottom of the trench. The thin oxide layer is then covered by a layer of oxidation inhibiting material such as nitride. The nitride layer is then anisotropically etched such that all of the nitride is removed from the horizontal bottom surface of the channel but the channel sidewall remains as coated by the nitride layer. After the nitride is removed from the bottom of the trench, an oxide layer having the desired thickness is formed on the bottom of the trench. Thereafter, the nitride and the screen oxide are removed from the trench sidewalls to form a thinner via oxide layer. The method for forming a thick bottom oxide and its variants are described in more detail in U.S. Patent No. 6,437,386, the entire disclosure of which is incorporated herein by reference. Other methods for the formation of thick oxides on the bottom of the channel, including selective oxide deposition, are described in commonly-owned Murphy, U.S. Patent No. 6,444,528, which is incorporated herein in entirety by reference.

In one embodiment, a modified method for forming a thick oxide on the bottom of a trench uses a sub-atmospheric chemical vapor deposition (SACVD) process. According to this method, an exemplary flow chart thereof is shown in Fig. 52, after channel etching (5210), a highly normal oxide film (5220) is deposited using SACVD, such as by filling the channel in an oxide. Tetraethyl thioacetate (TEOS) without voids. The SACVD step can be carried out at sub-atmospheric pressures ranging from 100 Torr to 700 Torr and exemplary temperatures ranging from about 450 °C to about 600 °C. The ratio of TEOS (in milligrams per minute) to ozone (in cubic centimeters per minute) can be set between, for example, 2 to 3 and preferably about 2.4. Using this program, one can form one with a location of about 2000 To 10,000 An oxide film of any value or greater in thickness. Please understand that these figures are for demonstration purposes only and may vary depending on specific program requirements and other factors such as atmospheric pressure at the location of the manufacturing facility. An optimum temperature can be obtained by balancing the deposition rate with the quality of the resulting oxide layer. At higher temperatures, the deposition rate slows down and may reduce film shrinkage. This film shrinkage causes a gate to be formed in the oxide film along the seam at the center of the channel.

After deposition of the oxide film, it etches back from the tantalum surface and the inside of the trench to leave a relatively flat layer of oxide (5240) of the desired thickness at the bottom of the trench. This etching can be performed, for example, by a wet etch process or a combination of wet and dry etch procedures using diluted HF. Since the oxide formed by SACVD tends to be porous, it will absorb ambient moisture after deposition. In a preferred embodiment, a densification step 5250 is performed after the etch back step to improve this effect. Densification can be carried out by, for example, 1000 ° C and a temperature treatment of about 20 minutes.

An additional benefit of this method is the ability to cover a terminal channel during the etch back step of the SACVD oxide (step 5230), leaving a termination channel filled with oxide. That is, for various embodiments of the termination structure described above including a channel filled with a dielectric, the same SACVD can be used to terminate the channel with an oxide fill. Also, by masking the field termination region during etchback, the same SACVD process step can result in the formation of field oxides in the termination region, eliminating the procedural steps that would otherwise be required to form the thermal field oxide. Moreover, since germanium is not consumed by the thermal oxidation process during SACVD deposition but is disposed in two locations, the process can be completely reprocessed by terminating the dielectric layer and thick oxide which are etched too far. Extra flexibility.

In another embodiment, another method for forming a thick oxide at the bottom of the trench uses a directional TEOS procedure. According to this embodiment, an exemplary flow chart thereof is shown in Fig. 53, and the conformal nature of TEOS is combined with the directional nature of plasma enhanced chemical vapor deposition (PECVD) to selectively deposit oxides (5310). . This combination is capable of having a higher deposition rate on a horizontal surface than a vertical surface. For example, an oxide film deposited using this procedure can have about 2500 at the bottom of the channel. Thickness and about 800 on the sidewall of the channel The average thickness. The oxide is then isotropically etched until all of the oxide from the sidewall is removed, leaving a layer of oxide at the bottom of the trench. The etch process can include a dry top oxide etch step 5320 followed by a wet buffer oxide etch (BOE) step 5340. For the exemplary embodiment described herein, a layer is left at the bottom of the trench after etching, such as 1250 The oxide of thickness, and all sidewall oxides are removed.

In a particular embodiment, a dry top oxide etch that focuses on the top surface of the structure is used to etch away oxide at the top region at an accelerated rate while etching the oxide in the bottom of the trench at a much lower rate. This type of etching, referred to herein as "fog etch," involves balancing the etching conditions with the etch chemistry to produce the desired selectivity. In one example, the etching is performed at a relatively low power and low pressure using a plasma etcher having a top power source such as LAM 4400. Exemplary values for power and pressure may be any of the range of 200-500 watts and 250-500 millitorr, respectively. Different etching chemistries can be used. In one embodiment, a combination of oxidative effects such as C2F6 and an oxygen system at an optimum ratio of, for example, about 5:1 (e.g., 190 sccm for C2F6, 40 sccm for Cl) produces the desired selectivity. Since chlorine is more commonly used to etch metal or polysilicon and generally inhibits the etching of oxides, chlorine is not commonly used as part of the oxide etch chemistry. However, based on the use of this type of selective etching, because C2F6 is aggressively etching oxides near the top surface and where higher energy allows C2F6 to overcome the effects of chlorine and chlorine will slow the etch rate closer to the bottom of the channel, Therefore, the combination works well. This primary dry etch step 5320 may be followed by a etch etch 5330 prior to BOE immersion 5340. It will be appreciated that in accordance with this embodiment, optimum selectivity is achieved by finely adjusting the pressure, energy, and etch chemistry that may be varied depending on the plasma etcher.

The PECVD/etching process according to this embodiment can be repeated one or more times as needed to obtain a bottom oxide having a target thickness. This procedure also results in thick oxide formation on the water landing surface between the channels. This oxide can be etched after the polysilicon is deposited in the channel and etched back on the surface. The underlying oxide is not subjected to subsequent etching steps.

There may be other methods for selectively forming thick oxides at the bottom of the channel. Figure 54 shows a flow diagram of an exemplary method for depositing high density plasma (HDP) such that oxide does not accumulate on the sidewalls of the trench (5410). One property of HDP deposition is that it creates an etch at the time of deposition, resulting in less oxide accumulation on the sidewalls of the channel relative to the oxide at the bottom of the channel than the directional TEOS method. A wet etch (step 5420) can then be used to remove a portion of the oxide or remove oxide from the sidewall while leaving a thick oxide on the bottom of the trench. An advantage of this procedure is that the profile at the top of the channel exits (5510) obliquely from the channel (5500), as shown in Figure 55, making it easier to achieve void-free polysilicon filling. A portion of the oxide may be etched away from the top prior to polysilicon filling (step 5430), as described above for "fog etching" (step 5430), so less oxide is etched from the top after the polysilicon etch. The HDP deposition process can also be used to deposit oxide between two polysilicon layers in a trench having buried electrodes (e.g., channel MOSFETs with shielded gate structures).

According to another method shown in Fig. 56, a selective SACVD is used to form a thick oxide on the bottom of the trench. This method utilizes SACVD to become selective at a lower TEOS:Ozone ratio. Oxides have a very slow deposition rate on tantalum nitride but are easily deposited on tantalum. TEOS: The lower the ratio of ozone, the more selective the deposition becomes. According to this method, after channel etching (5610), the pad oxide grows on the surface of the trench of the channel array (5620). A thin layer of nitride is then deposited on the pad oxide (5630). Followed by an anisotropic etch to remove nitride from the horizontal surface, while in the channel Nitride (5640) is left on the sidewalls. The selective SACVD oxide is then deposited, for example, at a temperature of about 405 ° C at a TEOS:ozone ratio of about 0.6 (5650) on a horizontal surface including the bottom of the channel. The SACVD oxide is then selectively densified by temperature treatment (5660). An oxide-nitride-oxide (ONO) etch is then performed to remove nitrides and oxides (5670) on the sidewalls of the trench.

As mentioned above, one reason for using an oxide layer thicker than the sidewalls at the bottom of the gate channel is that Qgd or gate-to-deuterium charge can be lowered to improve the switching speed. The same reason determines that the channel depth should be about the same as the well junction depth to minimize channel overlap in the drift region. In one embodiment, a method for forming a thicker dielectric layer at the bottom of the trench is such that a thicker dielectric layer extends upwardly on the side of the trench. This allows the thickness of the bottom oxide to be independent of the channel depth and the depth of the well junction, and allows the polycrystalline germanium inside the trench and trench to be deeper than the well junction without appreciable increased Qgd.

An exemplary embodiment of a method for forming a thick-bottom dielectric layer in accordance with one of the methods is shown in Figures 57-59. Figure 57A shows a simplified cross-sectional view of a pad having a thin layer of pad oxide 5710 and a channel of nitride layer 5720 that has been etched to cover only the sidewalls of the channel. This allows the etch of pad oxide 5710 to expose the germanium of the trench bottom and the top surface of the die, as shown in Figure 57B. This is followed by an anisotropic etch of the exposed germanium, resulting in a structure as shown in Figure 58A, in which the top and bottom of the trench have been removed to the desired depth. In an alternative embodiment, the turns on the top cymbal may be shielded by the mask to allow only the bottom of the trench to be etched during the ruthenium etch. Next, an oxidation step is performed to grow the thick oxide 5730 in a position not covered by the nitride layer 5720, resulting in the structure shown in Fig. 58B. The oxide thickness may be approximately 1200 To 2000 . Oxide layer 5720 is then removed and pad oxide 5710 is etched away. Etching of the pad oxide will result in partial thinning of the thick oxide 5730. The remainder of this procedure can be used to form gate polysilicon and well and source junctions, resulting in the exemplary structure shown in Figure 59.

As shown in FIG. 59, the resulting gate oxide includes a bottom thick layer 5730 and extends along the sidewalls of the trench to cover the well junction in the recess 5740. In some embodiments, wherein the via doping in the well region beside the channel is rated to be slightly doped near the radon side 5740, this region will typically have a lower lower limit than the region near the source portion. Voltage. By extending the thicker oxide along the sides of the channel to overlap into the vias in region 5740, the lower limit voltage of the device will not be increased. That is, this embodiment optimizes well junction depth and sidewall oxide to minimize Qgd without negatively affecting the on-resistance of the component. Those skilled in the art understand that this method for forming thick oxides at the bottom of the trench can be applied to a variety of different components as described above, including shielded gates, dual gates incorporating various charge balancing structures, and any other gate gates. element.

Those skilled in the art will also appreciate that any of the above described procedures for forming thick oxides at the bottom of the trench and for IPD can be used in the process for forming any of the trench gate transistors described herein. These programs may have other variations. For example, in the case of the procedure described in Figures 47A and 47B, chemical or physical changes in the ruthenium enhance the rate of oxidation. According to one such exemplary embodiment, a halogen ion species such as fluorine, bromine, etc. is implanted into the crucible at a zero angle at the bottom of the channel. Implantation can occur with exemplary doses greater than 1E ¹⁴ (eg, 1E ¹⁵ to 5E ¹⁷ ), exemplary temperatures between 900 ° C and 1150 ° C, and exemplary energies of about 15 仟 electron volts (KeV) or less. In the region implanted by the halogen, the oxide at the bottom of the channel grows at an accelerated rate compared to the sidewall of the channel.

Several of the above described channel elements include channel sidewall doping based on charge balancing purposes. For example, all of the embodiments shown in Figures 5B and 5C and Figures 6 through 9A have some type of channel sidewall doping structure. The sidewall doping technique is somewhat limited due to the physical limitations of the narrow, deep trenches and/or vertical sidewalls of the trench. A channel source doped region can be formed using a gaseous source or a beveled implant. In one embodiment, an improved trench sidewall doping technique uses plasma doping or pulsed plasma doping techniques. This technique uses a pulsed voltage applied to a wafer enclosed in a plasma of dopant ions. The applied voltage accelerates ions from a cathode cover toward the wafer and into the wafer. The applied voltage is pulsed and its time course continues until the desired dose is reached. This technique is capable of implementing many of these channel elements in a positive doping technique. In addition, the high output of this program reduces the overall cost of the process.

Those skilled in the art understand that the use of plasma doping or pulsed plasma doping techniques is not limited to channel charge balancing structures, but can be applied to other structures as well as trench termination structures and trench structures. Source or body connection. For example, this method can be used to dope the channel sidewalls of the shielded channel structure, such as those described in conjunction with Figures 4D, 4E, 5B, 5C, 6, 7, 8 and 9A. Additionally, this technique can be used to generate a uniformly doped via region. When the power components are reverse biased, the penetration of the depletion region into the via region is controlled by the concentration of charge on both sides of the junction (p-well junction). Highly doped in the epitaxial layer The impurity concentration, by depletion into the junction, will allow penetration to limit the breakdown voltage or require a longer path length than is required to maintain a low on-resistance. In order to minimize depletion into the via, higher channel doping concentrations may be required resulting in lower limit values. Because the low limit depends on the peak concentration below the source in the MOSFET, the uniform doping concentration in the via provides a good trade-off between path length and breakdown.

Other methods that can be used to achieve a more uniform channel concentration include the use of an epitaxial process to form via junctions, the use of multiple energy implants, and other techniques for creating a sudden junction. Another technique employs a starting wafer having a lightly doped cap layer. In this way, the compensation is minimized and can be spread up to generate a more uniform path doping profile.

The channel element can utilize the fact that the low concentration is set by the doping concentration along the channel sidewalls. A program that can have a high doping concentration away from the channel while maintaining a low low limit helps to prevent the penetrating mechanism. By providing a p-well doping prior to the gate oxidation process, well p-type impurities such as boron, such as boron, can be isolated into the channel oxide, thereby lowering the low limit. By combining it with the above techniques, a shorter path length without penetration can be provided.

Part of the power application requires measuring the amount of current flowing through the power transistor. This is typically achieved by isolating and measuring a portion of the total component current and subsequently using it to extrapolate the total current flowing through the component. The isolated portion of the total component current flows through a current sensing or detecting component and produces a signal indicative of the magnitude of the isolated current and which is then used to determine the total component current. This configuration is known as a current monitor. Current sensing transistors are typically monotonically provided with power components and two of the components share a common substrate (ankle) and brake. Figure 60 is a simplified diagram of a MOSFET 6000 having a current sensing component 6002. The current flowing through the main MOSFET 6000 is split between the main transistor and the current sensing portion 6002 in proportion to each active region. Therefore, the current flowing through the main MOSFET is calculated by measuring the current through the sensing element and then multiplying it by the ratio of the active regions.

A variety of different methods for isolating the current sensing element from the main element are described in the commonly owned Yedinak et al. entitled "Current sensing for isolating power components while maintaining a continuous strip. U.S. Patent Application Serial No. 10/315,719, the entire disclosure of which is incorporated herein by reference. Embodiments for integrating sensing elements with a variety of different power components, including those having a charge balancing structure, are described below. According to an embodiment, in a power transistor having a charge balancing structure and a monotonically integrated current sensing element, the current sensing region is preferably formed with the same continuous MOSFET structure and charge balance structure. If the continuity in the charge balancing structure is not maintained, the component breakdown voltage will deteriorate due to the charge mismatch caused by the voltage support region not being completely depleted. Figure 61A shows an exemplary embodiment of a charge balancing MOSFET 6100 having a planar gate structure and isolated current sensing structure 6115. In this embodiment, the charge balancing structure includes opposite conductivity (p-type in this example) stripes 6126 formed inside the drift region 6104 (n-type). The P-type strips 6126 can be formed, for example, as doped polysilicon or epitaxial filled channels. As depicted in FIG. 61A, the charge balancing structure maintains continuity under the current sensing structure 6115. The sensing pad metal 6113 covering the surface area of the current sensing element 6115 is electrically separated from the source metal 6116 by the dielectric region 6117. Please understand the current sensing element with similar structure The components can be integrated with any of the other power components described herein. For example, Figure 61B shows an example of how a current sensing element can be integrated with a shielded gated MOSFET, where charge balancing can be achieved by adjusting the channel depth and biasing the shield polysilicon inside the channel. .

There are several power applications that require the diode to be integrated on the same die as the power transistor. These applications include temperature sensing, electrostatic discharge (ESD) protection, active clamping, and voltage splitting with other applications. For example, for temperature sensing, one or more series connected bipolar systems are monotonically integrated with the power transistor, wherein the anode and cathode of the lead are terminated to separate the bond pads, or connected by conductive interconnects. To monotonic control circuit components. The temperature is sensed by a change in forward voltage (Vf) of one or more diodes. For example, by proper interconnection of the gate terminals of the power transistors, as the diode Vf drops with temperature, the gate voltage is pulled low and the current flowing through the components is lowered until the desired temperature is reached.

Figure 62A shows an exemplary embodiment of a MOSFET 6200A having a series temperature sensing diode. The MOSFET 6200A includes a diode structure 6215 in which the doped polysilicon system having alternating conductivity forms three series temperature sensing diodes. In this exemplary embodiment, the MOSFET portion of element 6200A forms a reverse conductivity region inside the n-type epitaxial drift region 6204 using a p-type epitaxial filled charge balancing channel. As depicted, the charge balancing structure preferably maintains continuity under the temperature sensing diode structure 6215. A diode structure is formed on top of a field dielectric (oxide) layer 6219 on the surface of the crucible. A p-type junction isolation region 6221 is selectively diffused under the dielectric layer 6219. a component that does not have this p-type junction 6200B is shown in Figure 62B. In order to ensure that a series forward biased diode can be obtained, a shorted metal 6223 is used to short the reverse biased P/N+ junction. In one embodiment, the p+ is implanted and diffused across the junction to form an N+/P/P+/N+ structure, wherein p+ occurs under the short metal 6223 to obtain an ohmic contact. For the opposite polarity, N+ can also diffuse across the N/P+ junction to form a P+/N/N+/P+ structure. Moreover, those skilled in the art will appreciate that this type of temperature sensing diode structure can be used in any of a variety of different power components in combination with many of the other features described herein. For example, Figure 62C depicts a MOSFET 6200C having a shielded trench gate structure in which a shielded polysilicon can be used for charge balancing.

In another embodiment, asymmetric ESD protection can be performed using similar isolation techniques as shown in element 6200 for temperature sensing diodes. Based on ESD protection, one end of the diode structure is electrically connected to the source terminal and the other end is connected to the gate terminal of the component. Alternatively, symmetric ESD protection can be obtained by shorting any back-to-back N+/P/N+ junctions as shown in Figures 63A and 63B. The exemplary MOSFET 6300A shown in FIG. 63A employs a planar gate structure and uses opposite conductive stripes for charge balancing, while the exemplary MOSFET 6300B shown in FIG. 63B is a shielded gate structure. Channel gate element. In order to prevent uneven charge balance, the charge balancing structure is continuous under the bond pad metal and any other control component bonding pads.

An exemplary ESD protection circuit is shown in Figures 64A through 64D, wherein the main component of the gate that is protected by the diode structure described above can be any of the power balancing or other techniques described herein. element. Figure 64A shows a simplified diagram of an asymmetrically isolated polysilicon diode ESD protection, while Figure 64B depicts a standard back-to-back isolated polysilicon diode ESD protection circuit. The ESD protection circuit shown in Fig. 64C uses an NPN transistor for BV _cer snap-back. The subscript "cer" in BV _cer refers to a reverse biased collector-emitter bipolar transistor junction in which a resistor is used to control the base current for a connection of the base. The low resistance causes most of the emitter current to be removed via the base to prevent the emitter-base junction from being turned on, that is, a small number of carriers are injected back into the collector. The on condition can be set by the resistor value. When the carrier is injected back into the collector, the sustain voltage between the emitter and the collector is reduced - a phenomenon known as "bounce back". The current that causes the BV _{cer to} bounce back can be set by adjusting the value of the base-emitter resistor R _BE . Figure 64D shows an ESD protection circuit using a controlled rectifier or SCR and diode as shown. The trigger current can be controlled by a gate short circuit structure. The diode breakdown voltage can be utilized to offset the voltage that causes the SCR to latch. A monotonic diode structure as described above can be used in any of these and other ESD protection circuits.

In some power applications, one of the important performance characteristics of a power switching component is its equivalent series resistance or ESR, and this is a measure of the impedance of the switching terminal or gate. For example, in synchronous buck converters that use power MOSFETs, a lower ESR helps to reduce switching losses. In the case of a trench gate MOSFET, most of its gate ESR is dependent on the size of the channel filled with polysilicon. For example, the length of the gate channel may be limited by package constraints such as minimum wire bond pad size. It is known to reduce the gate by applying a vapor film to the polysilicon. resistance. However, implementing a deuterated polysilicon in a trench MOSFET would pose several challenges. In a typical planar discrete MOS structure, the gate polysilicon can be deuterated after the junction has been implanted and driven to its respective depth. For trench gate elements in which the gate polysilicon is recessed, the application of germanide becomes more complicated. The maximum temperature limit at which wafers can withstand post-deuteration treatment is approximately less than 900 °C using conventional telluride systems. This constitutes a significant constraint on the stage of the process when forming diffusion regions such as sources, helium and wells. The most commonly used metal for telluride is titanium. Other metals such as tungsten, tantalum, cobalt, and platinum may also be used to allow for a higher thermal budget post-halide treatment to provide greater processing. The gate ESR can also be reduced by a variety of different layout techniques.

Various different embodiments for forming a charge balanced power balancing component with a lower ESR are described below. In an embodiment illustrated in FIG. 65, a process 6500 includes forming a channel having a lower electrode formed at a lower portion of the trench based on shielding and/or charge balancing purposes (step 6502). This is followed by deposition and etching of an IPD layer (step 6504). The IPD layer can be formed by known procedures. Alternatively, the IPD layer can be formed using any of the procedures described above in connection with Figures 45 through 50. Next, a known procedure is used to deposit and etch an upper electrode or gate polysilicon in step 6505. The well and source regions are then implanted and driven (step 6508). After step 6508, the telluride is applied to the gate polysilicon in step 6510. This is followed by deposition and planarization of a dielectric in step 6512. In a variation of this procedure, a step 6512 of depositing and planarizing the dielectric field is first performed, and then the contact hole is opened to touch the source/body and the gate, and then the germanide contact is formed. The two embodiments rely on a bismuth film transformation The lower part of the implantation site is activated by a lower temperature annealing.

In another embodiment, the polysilicon gate system is replaced by a metal gate. According to this embodiment, a metal gate is formed by, for example, depositing Ti by a collimated source to improve the filling ability in a channel structure. After the metal gate is applied and once the junction has been implanted and driven, the dielectric options include HDP and TEOS to isolate the gate from the source/body contacts. In an alternative embodiment, a gate terminal is formed using a damascene or dual damascene approach having various different metal options, from aluminum to copper top metal.

The layout of the gate conductor also affects the overall switching speed of the gate ESR and components. In another embodiment, illustrated in Figures 66A and 66B, a layout technique incorporates vertical germanium-surfaced polysilicon stripes and recessed-channel polysilicon to reduce gate ESR. Referring to Figure 66A, a highly simplified element structure 6600 is shown and one of the germanide-coated polysilicon lines 6604 extends perpendicular to the channel strips 6602 along the telluride surface. Figure 66B shows a simplified cross-sectional view of element 6600 along the AA' axis. The deuterated polysilicon line 6604 is in contact with the channel polysilicon at the intersection with the channel. The multi-twisted polysilicon line 6604 can extend over the top surface of the germanium surface to reduce the resistivity of the gate electrode. This layout technique and other layout techniques can be used to improve the gate ESR in any of the channel gate elements described herein, for example, by having a program with two or more interconnects.

Circuit application

For example, by the substantial reduction in component on-resistance provided by the various components and programming techniques described herein, the area of the wafer occupied by the power components can be reduced. As a result, monotonic integration of these high voltage components with low voltage logic and control circuitry will become feasible. Typical circuit applications can be integrated The functional types on the same die as the power transistors include power control, sensing, protection, and interface circuitry. One of the important considerations for the monotonic integration of power components with other circuits is the technique used to electrically isolate high voltage power components from low voltage logic or control circuits. There are several known ways to achieve this, including junction isolation, dielectric isolation, twinned insulators, and the like.

In the following, several circuit applications for power switching will be described in which various different circuit components can be integrated on the same wafer to varying degrees. Figure 67 depicts a synchronous male converter (DC-DC converter) that requires a lower voltage component. In this circuit, the n-channel MOSFET Q1, often referred to as the "high-side switch", is designed to have a moderately low on-resistance but exhibits fast switching speeds to minimize power loss. The MOSFET Q2, often referred to as the low side switch, is designed to have a very low on-resistance and a moderately high switching speed. Figure 68 depicts another DC-DC converter that is more suitable for medium to high voltage components. In this circuit, the main switching element Qa exhibits a fast switching speed and a high blocking voltage. Since this circuit uses a transformer, a low current flows through the transistor Qa to have a medium to low on-resistance. For the synchronous rectifier Qs, a MOSFET having a low to very low on-resistance, a fast switching speed, a very low reverse recovery charge, and a low interelectrode capacitance can be used. Other embodiments and improvements of such DC-DC converters are described in more detail in the name "Electrical Method and Circuit for Reducing Losses in DC-DC Converters" by the common transfer of Elbanhawy. U.S. Patent Application Serial No. 10/222,481, the entire disclosure of which is incorporated herein by reference.

The MOSFETs in the converter circuits of Figures 67 and 68 can be implemented using any of the various different power device configurations described above. A dual gate MOSFET of the type shown in Figure 4A is a type of component that provides a particular advantage when used to implement a synchronous male converter. In one embodiment, a particular drive scheme utilizes the advantages of all of the features provided by the dual gate MOSFET. An example of this embodiment is shown in Fig. 69, in which a first gate terminal G2 of the high-side MOSFET Q1 is determined by a circuit composed of a diode D1, resistors R1 and R2, and a capacitor C1. The fixed potential on the gate electrode G2 of Q1 can be adjusted to accommodate the best Qgd, so that the switching time of the transistor is optimized. The second gate terminal G1 of the high side switching transistor Q1 receives a normal gate driving signal from a pulse width modulation (PWM) controller/driver (not shown). The two gate electrodes of the low side switching transistor Q2 are similarly driven as shown.

In an alternative embodiment, an example of which is shown in Figure 70A, the two gate electrodes of the high side switch are driven separately to further optimize the performance of the circuit. According to this embodiment, the different waveforms drive the gate terminals G1 and G2 of the high side switch Q1 to achieve the best switching speed during the transition and achieve the best on-resistance RD _Son during the remainder of the cycle. In the illustrated example, a voltage Va of about 5 volts during the switching period delivers a very low Qgd to the gate of the high-side switch Q1 resulting in a high switching speed, but the RD _Son before and after the transition to td1 and td2 is not at its lowest. value. However, since RD _Son is not a significant loss contributor during the handover, this does not negatively affect the operation of the circuit. In order to ensure that the rest of the pulse duration has the lowest RD _Son , the potential V _g2 at the gate terminal G2 is driven to a second higher than Va during the time period tp as shown in the timing diagram of FIG. 70B. Voltage Vb. This drive scheme results in optimum efficiency. The variants of these drive schemes are described in more detail in U.S. Patent Application Serial No. 10/686,859, to the name of the "Essence of the Double Gate MOSFET" by Elbanhawy. No. 17732-66930), which is incorporated herein in its entirety by reference.

Packaging technology

An important consideration for all power semiconductor components is the housing or package used to connect the components to the circuit. Semiconductor dies are typically attached to a metal pad using a metal bond layer such as solder or a metal-filled epoxy adhesive. The wires are typically bonded to the top surface of the wafer and subsequently bonded to the leads that protrude through the molded body. This assembly is then mounted to a board. The housing provides an electrical and thermal connection between the semiconductor wafer and the electronic system and its environment. Low parasitic resistance, capacitance, and inductance are desirable electrical characteristics of the housing, thereby enabling a better interface to the wafer.

Improvements in packaging techniques that focus on reducing resistance and inductance in the package have been provided. In a particular packaging technique, a solder ball or copper stud is distributed over a relatively thin (e.g., 2-5 micron) metal surface of the wafer. By routing the metal connections over a large area of the metal surface, the current path in the metal is made shorter and the metal resistance is reduced. If the bump side of the wafer is connected to a copper leadframe or to a copper trace on a printed circuit board, the resistance of the power component is reduced compared to the wire bond solution.

Figures 71 and 72 show simplified cross-sectional views of the molded and unmolded package, respectively, and using solder balls or copper posts that connect the leadframe to the metal surface of the wafer. The molded package 7100 as shown in Fig. 71 includes A lead frame 7106 is connected to a first side of a die 7102 via solder balls or copper post segments 7104. The second side of the die 7102 facing away from the leadframe 7106 is exposed through a molding material 7108. In a typical vertical power transistor, the second side of the die forms a germanium termination. The second side of the die can form a direct electrical connection to a pad on the board, thus providing a low resistance thermal and electrical path to the die. This type of package and its variants are described in more detail in U.S. Patent Application No. entitled "Flip Chip in Leaded Molded Package and Method of Making Same" by Joshi et al. .10/607,633 (Office No. 18865-42-1/17732-1342), which is incorporated herein in its entirety by reference.

Figure 72 shows an unmolded embodiment of a package 7200. In the exemplary embodiment shown in FIG. 72, the package 7200 has a multilayer substrate 7212 including a base layer 7220 containing a metal and a metal layer separated by an insulating layer 7222. 7221. A solder structure 7213, such as a solder ball, is attached to the substrate 7212. A die 7211 is attached to the substrate 7212 with the solder structure 7213 disposed about the die. The die 7211 can be coupled to the substrate 7212 by a die attach material such as solder 7230. When the illustrated package is formed, it is flipped over and mounted on a circuit board (not shown) or other circuit substrate. In an embodiment in which a vertical power transistor is fabricated on die 7211, solder balls 7230 form a tantalum termination and the wafer surface forms a source termination. It is also possible to create a reverse connection by reversing the connection of the die 7211 to the substrate 7212. As shown, the package 7200 is thin and unmolded since no molding material is required. Various embodiments of an unmolded package of this type are described in more detail in the name of Joshi, a common transfer. U.S. Patent Application Serial No. 10/235,249, the entire disclosure of which is incorporated herein by reference.

Alternative methods of directly bonding the top surface of the wafer to copper by solder or conductive epoxy have been proposed. Because the stress induced between the copper and germanium wafers increases with wafer area, the direct bonding method may be limited because the solder or epoxy interface can only be subjected to stress levels prior to failure. On the other hand, the bumps can be more displaced before breaking and have been shown to work with very large wafers.

Another important consideration in package design is heat dissipation. Improvements in power semiconductor performance often result in smaller wafer areas. If the power dissipation in the wafer does not decrease, the thermal energy is concentrated in a small area which results in higher temperature and reliability of degradation. Means for increasing the heat transfer rate away from the package include: reducing the number of thermal interfaces, using materials having higher thermal conductivity, and reducing such as germanium, solder, die attach and die attach pads, etc. The thickness of the layer. U.S. Patent No. 6,566,749, to the name of "Semiconductor die package with improved thermal and electrical performance" by Rajeev Joshi, which is incorporated herein by reference in its entirety, for the purpose of heat dissipation. The solution, especially for dies including vertical power MOSFETs for RF applications. Other techniques for improving the overall package performance are described in more detail in the commonly assigned U.S. Patent Nos. 6,133,634 and 6,469,384, to Rajeev Joshi, and Joshi et al. U.S. Patent Application Serial No. 10/271,654, in the form of a thin, heat-enhanced flip-chip in a lead-molded package. No.18865-99-1/17732.53440). It is understood that any of the various power components described herein can be accommodated in any of the packages described herein or any other suitable package.

For heat removal utilizing the larger surface of the housing, the ability to maintain a housing such as a thermal interface on the top and bottom of the housing at a lower temperature can also be enhanced. The increased surface area associated with the airflow around these surfaces increases the rate of heat removal. The housing design can also easily form an interface with an external heat sink. Although heat transfer and infrared radiation techniques are common methods, other cooling methods may be applied. For example, Reno Rossetti, as incorporated herein by reference, is entitled "Power Circuits with Thermal Ion Cooling Systems" US Patent Application No. 10/408,471 (Company Case) The thermionic emission system described in No. 17732-66720) is a heat removal method that can be used to cool power components.

Integrating other logic circuits including power delivery and control functions into a single package poses additional challenges. For example, the housing requires more pins to form an interface with other electronic functions. The package should allow for high current power interconnects and low current signal interconnects in the package. Various packaging technologies that address these challenges include chip-to-chip wire bonding to eliminate special interface pads, chip-on-chips to save space in the housing, and Multi-chip modules are designed to allow different technologies to be combined within a single electronic function. Various embodiments of the multi-chip package technology are described in U.S. Patent Application Serial No. 5, the entire disclosure of which is incorporated herein by reference. .09/730,932 (office case number No. 18865-50/17732-19450), and also No. 10/330, 741 (in the case of a multi-chip module including a substrate including an array of interconnect structures) by Rajeev Joshi No. 18865-121/17732-66650.08), both of which are incorporated herein by reference in their entirety.

Although the preferred embodiment of the invention has been described above in detail, many alternatives, modifications, and equivalents are possible. For example, many charge balancing techniques are described herein as a MOSFET and particularly as a trench gate MOSFET. Those skilled in the art understand that the same techniques are applicable to other types of components, including IGBTs, thyristors, diodes, and planar MOSFETs, as well as lateral components. Therefore, the above description should not be taken as limiting the scope of the invention as defined by the scope of the claims.

100‧‧‧n-channel power MOSFET (vertical channel MOSFET)

102, 202, 302, 402, 502, 602, 902, 1002, 1902 ‧ ‧ gate channel

104‧‧‧p-type well or body area

106‧‧‧n type drift or epitaxial region

108, 1021, 1921, 2008‧‧‧ Thin dielectric layer

110,224,3811‧‧‧Transmission materials

112‧‧‧N-type source area

114‧‧‧ heavily doped n+ substrate area

118,218‧‧‧p+heavy body area

200B, 1300B‧‧‧ planar MOSFET

204‧‧‧ Body District

206,306,506,606,806,1006,1406,1706,1906,2006,2406,6104‧‧‧ drift zone

210‧‧‧gate channel conduction layer

212‧‧‧n+ source area

216,7221‧‧‧metal layer

220‧‧‧Shielded channel

222,1508,3809S‧‧‧ dielectric materials

226, 3908, 4208B‧‧‧ dielectric layer

300A‧‧‧Shielded Gate Channel MOSFET (Enhanced Mode MOSFET)

300B‧‧‧Shielded Gate Channel MOSFET

301,520‧‧‧charge control channel

310,810,910,910S,1110,1510,2010,2410,4510‧‧‧ gate electrode

311,611,1111,2411,4811‧‧‧Shield electrode

311a, 311b, 811, 911 ‧ ‧ electrodes

313‧‧‧Multiple stacking polycrystalline germanium electrodes

400A‧‧‧Double Gate Channel MOSFET...

400B, 6300A, 6300B‧‧‧ exemplary MOSFET

400D‧‧‧ MOSFET with deep body design

400F‧‧‧Reversely biased gate MOSFET with trench deep body 418

400G‧‧‧Reversely biased shielded gate MOSFET with a shallow body structure

401‧‧‧Overlapping area

402C, 502C, 802, 820A, 820B, 902C, 902L, 902R, 1402, 1502, 2002, 3002, 3102, 3202, 3302, 3802, 4002‧ ‧ channel

404, 2308, 3704‧‧‧p well

406‧‧‧ drift zone

411‧‧‧Shield

418,418E‧‧‧ body channel

419‧‧‧p+ shield joint (p+ body implant)

420‧‧‧deep channel

500A‧‧‧Exemplary power MOSFET with planar gate structure (enhanced mode transistor)

500B‧‧‧Channel MOSFET (Enhanced Mode Transistor)

500C‧‧‧Channel with vertical charge control (secondary charge control channel) with vertical charge control (enhanced mode transistor)

501, 2610, 3310, 3810‧‧ ‧ gate polysilicon

524‧‧‧Float p area

526‧‧‧p-type layer or liner

526C, 626, 1826P‧‧‧p type liner

600‧‧‧ Suitable for power MOSFETs for higher voltage applications that also require faster switching

610‧‧‧ brake conductive materials

620, 720, 820, 920, 920A, 920B, 1720, 1820 ‧ ‧ filled with dielectric channels

701, 1506, 1504, 1512, 2506, 5740‧‧‧

706‧‧‧n drift zone

726, 926‧‧‧p-doped gasket

800‧‧‧Shielded gate MOSFET

828, 928A, 928B, 1328‧‧‧ Schottky diode

902B, 1102, 1202, 2502, 2602, 3202‧‧‧ active channel

923, 925, 1023, 1025‧‧ PN area

928C‧‧‧Schottky Cell

1000‧‧‧ exemplary channel MOSFET

1008, 3108a, 3308a‧‧‧ gate oxide

1020, 1220, 1920‧‧ ‧ diode channel

1027, 1927‧‧‧ bottom area

1200‧‧‧ MOSFET with dual gate technology and trench diode structure...

1400‧‧‧Exemplary cumulative mode transistor with alternating conductivity regions arranged in parallel with current flow

1403, 1405‧‧‧ Columnar n-type and p-type segments of opposite polarity

1412‧‧‧n type access area

1413, 1606, 1612‧‧‧n type area

1414‧‧‧n type

1500‧‧‧ cumulative mode components

1511‧‧‧ embedded electrode

1603‧‧‧heavily doped n+ source region

1700‧‧‧Accumulated transistor

1726‧‧‧p-type area (p-type liner)

1826N‧‧n type liner

1900, 2000‧‧‧ exemplary cumulative mode transistor

1923, 1925‧‧‧ opposite conductivity type zone

2002‧‧‧ gate terminal

2012‧‧‧ source area

2023‧‧‧n type tantalum or polysilicon layer

2025‧‧‧p-type or polycrystalline layer

2100‧‧‧Super Junction MOSFET

2102‧‧‧Voltage maintenance zone or resistance zone

2104‧‧‧n section

2106‧‧‧p-type segment

2118‧‧‧ heavily doped p+

2226‧‧‧ floating area

2300‧‧‧High-voltage MOSFETs incorporating a variation of the super-junction architecture and a double-gate structure

2306, 2904A‧‧‧n type drift zone

2326‧‧‧P type area

2400‧‧‧High voltage MOSFET with super junction technology and shielded gate structure

2426‧‧‧ opposite polarity floating gate

2503‧‧‧Circular termination channel

2603, 2603A, 2603B, 2603C‧‧‧ Termination channel

2604‧‧‧p-well area

2605A‧‧‧Dielectric (oxide)

2605B‧‧‧Oxide

2607A, 4309‧‧‧ Polysilicon

2607B‧‧‧Polysilicon electrode

2609A‧‧‧Metal field plate

2611‧‧‧Shielded polysilicon electrode

2703-1, 2703-2‧‧‧ Termination channel with relatively large radius of curvature

2803A‧‧‧p-type bar (stop bar)

2803B‧‧‧ Column

2808D‧‧‧wider area

2809-1‧‧‧ Large field plate

2809-2, 2809A‧‧‧ Field Board

2900A, 2900B, 6200‧‧‧ components

2904A‧‧‧Voltage maintenance layer

2908A‧‧‧p well

2926A‧‧‧ opposite conductive strip

2926C‧‧‧The opposite polarity column

3000‧‧‧Channel components

3001, 3030, 3040‧‧‧ dielectric (or oxide) layer

3003‧‧‧First oxide layer

3006, 3406, 3506, 3606‧‧‧ epitaxial layer

3010, 3020, 3110‧‧‧ polycrystalline layer

3012, 3022‧‧‧ openings

3030‧‧‧Oxide layer

3040‧‧‧Top oxide layer

3108, 4708S‧‧‧Shielded dielectric layer

3108a, 4508G‧‧‧ gate dielectric layer

3109‧‧‧ Cover

3111,3311,4711‧‧‧Shielded polysilicon

3111a, 3111b‧‧ ‧ gate terminal and polysilicon layer

3112, 3122, 3132‧‧‧ separate metal wires

3210‧‧‧ Peripheral gate polysilicon channel

3211C‧‧‧Location

3213‧‧‧ perimeter shielded channel

3215‧‧‧Source and shield contact areas

3217‧‧‧Window

3308, 4808S‧‧‧ Shield Oxide

3414‧‧‧phosphorus substrate

3415‧‧‧Elevation spacer or buffer (or barrier) layer

3514‧‧‧Born or phosphorus substrate

3515‧‧ ‧ barrier layer

3615‧‧‧Si _x C _1-x compound (carbonized layer)

3630‧‧‧Deep Body District

3715‧‧‧Si _x C _1-x (layer)

3804‧‧‧ well epitaxial (extortion well, second epitaxy)

3806‧‧‧First epitaxial layer

3808A, 4608S‧‧‧Shielding dielectric

3808G‧‧‧ thyristor

3809A‧‧‧Interstitial polysilicon dielectric layer

3814‧‧‧Substrate

3902‧‧‧Shielded polysilicon embedded in the channel

3905‧‧‧First well implant

4001‧‧‧Finished wafer

4003‧‧‧Combined materials

4004‧‧‧ blanket overlaying well layer

4005‧‧‧ Carrier

4006‧‧‧First epitaxial drift layer

4006-1‧‧‧Second epitaxial drift layer

4008B‧‧‧ dielectric column

4009‧‧‧Low-resistance (such as metal) wafers

4110‧‧‧ implant He or H2 into a heavily doped ruthenium substrate

4112‧‧‧Combining tantalum substrate to glass substrate

4114‧‧‧ Cut the substrate and form SOTG

4116‧‧‧Repeat the above procedure to form SOTG on the other side of the substrate

4118‧‧‧ depositing epitaxial deposits on the surface of the crucible

4120‧‧‧Removing the enamel layer from the back side by grinding during the grinding stage

4122‧‧‧ Grinding thick glass substrates to, for example, 300 microns

4124‧‧‧Removing the remaining glass by chemical etching

4303,4403,5710‧‧‧Mat oxide

4305‧‧‧Nitride

4307‧‧‧"Bird" structure

4405, 5720‧‧‧ nitride layer

4405-1‧‧‧Non-oxidizing materials (protective layer)

4508P‧‧‧Polysilicon liner

4608F‧‧‧ dielectric filling material

4708T‧‧‧ thicker insulator

4808T‧‧‧ Thick insulator layer

4903‧‧‧Nitride

4908P‧‧‧Screen oxide

4908T, 5730‧‧‧ thick oxide

5002‧‧‧ Plasma etching to planarize IPD film

5003‧‧‧CMP to planarize IPD film

5004‧‧‧ Wet etch to make the IPD concave to the target depth

5005‧‧‧ Wet etching to recess IPD to target depth

5100‧‧‧ Apply DC bias to the wafer in the test environment

5110‧‧‧Determining the energy level that can suppress oxidation

5120‧‧‧ Apply external bias to the wafer during oxidation

5130‧‧‧Manipulate external bias to control oxidation rate

5210‧‧‧Channel etching (active and terminated)

5220‧‧‧Deposition of oxides by SACVD

5230‧‧‧ Covering the termination channel (optional)

5240‧‧‧Required thickness of oxide back to the inside of the channel

5250‧‧‧ Temperature treatment for densification (selective)

5310‧‧‧Deposition of oxides by PECVD

5320‧‧‧Dry top oxide etch ("fog etch")

5330‧‧‧Selective cut

5340‧‧‧ Wet BOE etching

5350‧‧ Is the bottom oxide equal to the required thickness?

5360‧‧‧Complete

5410‧‧‧Deposition of oxides by HDE deposition

5420‧‧‧ Wet etching to remove sidewall oxide

5430‧‧‧Selective "fog etching"

5440‧‧‧Polysilicon filling

5500‧‧‧Channel

5510‧‧‧Slanted leave

5610‧‧‧Channel etching

5620‧‧‧ Forming a pad oxide on the surface

5630‧‧‧ Forming a thin layer of nitride on the pad oxide

5640‧‧‧ Anisotropic etching to remove nitride from horizontal surfaces

5650‧‧‧ Depositing oxides on horizontal surfaces by selective SACVD

5660‧‧‧ Densified SACVD oxide (optional)

5670‧‧‧ONO etching of trench sidewalls

6000‧‧‧ MOSFET with a current sensing element 6002

6002‧‧‧ Current sensing components

6100‧‧• Charge-balanced MOSFET with a planar gate structure and isolated current sensing structure 6115

6113‧‧‧Sense pad metal

6115‧‧‧Isolated current sensing structure

6116‧‧‧ source metal

6117‧‧‧Dielectric zone

6126‧‧‧p-type column

6200A‧‧‧MOSFET with series temperature sensing diode...

6200B‧‧‧ Components without p-junction

6200C‧‧‧ MOSFET with a shielded gate structure...

6215‧‧‧Temperature sensing diode structure

6219‧‧‧Field dielectric (oxide) layer

6221‧‧‧p type junction isolation area

6223‧‧‧Short-circuit metal

6500‧‧‧Program

6502‧‧‧ Forming a channel with a shield and/or charge balance structure

6504‧‧‧Deposition and etching IPD

6506‧‧‧Deposition and etching gate polysilicon

6508‧‧‧ implanted and driven wells and source areas

6510‧‧‧ Applying telluride to the gate polysilicon

6512‧‧‧Deposition and planarization dielectric film

6600‧‧‧Highly simplified component structure

6602‧‧‧Channel stripe

6604‧‧‧Typified polycrystalline germanium wire

7100‧‧‧Molded package

7102,7211‧‧‧ grain

7104‧‧‧Ball or copper column

7106‧‧‧ lead frame

7108‧‧‧Molded materials

7200‧‧‧Package

7212‧‧‧Multilayer substrate

7213‧‧‧ solder structure

7220‧‧‧ Metal-containing base

7222‧‧‧Insulation

7230‧‧‧ Solder (solder ball)

C1‧‧‧ capacitor

Cgd‧‧‧ gate to tantalum capacitor

Cgs‧‧‧ gate to source capacitor

D1‧‧‧ diode

Distance between D1‧‧‧TP2 and TP3

Distance between D2‧‧‧TP3 and TP4

D3‧‧‧Distance between TP4 and TP5

G1‧‧‧ main gate

G2‧‧‧ secondary gate

IPD‧‧‧Interstitial polycrystalline germanium dielectric

The distance between the L‧‧ ‧ gate channel 402 and the body channel 418

L1, L2, L3‧‧‧ distance

200‧‧‧Double-Channel MOSFET

300A, 400C, 400D, 400E, 700, 900A, 900B, 1100, 2200, 2600A‧ ‧ MOSFET

Q1‧‧‧High Side Switch (n-Channel MOSFET)...

Q2‧‧‧Low Side Switch (MOSFET)

Qa‧‧‧ main switching element

Qs‧‧‧Synchronous Rectifier

R1, R2‧‧‧ resistors

R _DSon ‧‧‧汲 to source on resistance

Td1, td2‧‧‧ transformation

TP1-TPn‧‧‧p type termination bar

Va‧‧‧ voltage

Vb‧‧‧second voltage

V _DS ‧‧‧O crystal

Vpp‧‧‧ parallel plane collapse voltage

W‧‧‧Width

W1‧‧‧End bar TP1 width

W2‧‧‧End bar TP2 width

W3‧‧‧End bar TP3 width

W _G ‧‧‧Through the gap between the end of the channel and the active channel

1 shows a cross-sectional view of a portion of an exemplary n-channel power MOSFET; FIG. 2A shows an exemplary embodiment of a dual channel power MOSFET; and FIG. 2B shows a structure with a source shielded trench An exemplary embodiment of a planar gate MOSFET; FIG. 3A shows a portion of an exemplary embodiment of a shielded gate channel power MOSFET; and FIG. 3B shows a combination of a dual channel structure of FIG. 2A and a third channel of FIG. An alternative embodiment of a shielded gate structure for a shielded gate channel power MOSFET; FIG. 4A is an exemplary embodiment of a dual gate channel power MOSFET Simplified partial diagram; Figure 4B shows an exemplary power MOSFET incorporating a planar dual gate structure and channel electrode for vertical charge control; Figure 4C shows the combination of double gate and shielded gate technology on the same channel inside An exemplary implementation of one of the power MOSFETs; FIGS. 4D and 4E are cross-sectional views of an alternative embodiment of a power MOSFET having a deep body structure; and FIGS. 4F and 4G are diagrams showing a deep body structure of the channel 5A, 5B, and 5C are cross-sectional views showing portions of an exemplary power MOSFET having various vertical charge balancing structures; FIG. 6 shows a merged one A simplified cross-sectional view of an exemplary vertical charge control structure and a power MOSFET of a shielded gate structure; FIG. 7 shows a simplified cross-sectional view of another power MOSFET incorporating an exemplary vertical charge control structure and a double gate structure; An example of a shielded gate power MOSFET having a vertical charge control structure and an integrated Schottky diode; Figures 9A, 9B, and 9C depicting Various exemplary embodiments of power MOSFETs incorporating Schottky diodes; Figures 9D, 9E and 9F show demonstrations for dispersing Schottky diode cells in an active cell array of a power MOSFET Sexual layout variation; Figure 10 provides a simplified cross-sectional view of an exemplary channel power MOSFET with a buried diode charge balancing structure; Figures 11 and 12 show merged with buried diode charge flats, respectively An exemplary embodiment of a power MOSFET with a shielded gate and dual gate technology; Figure 13 is a schematic diagram of a planar power MOSFET that incorporates a buried dipole charge balancing technique and an integrated Schottky diode. Simplified cross-sectional view; Figure 14 shows a simplified embodiment of an exemplary cumulative mode power transistor with alternating conduction regions arranged in parallel for current flow; and Figure 15 is another embodiment with channel electrodes based on charge dispersion applications. A simplified diagram of the cumulative mode component; Figure 16 is a simplified diagram of an exemplary dual channel accumulation mode component; and FIGS. 17 and 18 show an exemplary cavity for a dielectric filled trench exhibiting an opposite polarity external pad. Other simplified embodiments of the accumulation mode element; Figure 19 is another simplified embodiment of an accumulation mode element employing one or more buried diodes; and Figure 20 is a heavily doped surface along the surface of the crucible A simplified isometric view of an exemplary cumulative mode transistor of the opposite polarity region; Figure 21 shows a simplified example of a super-junction power MOSFET with alternating opposite polarity regions in the voltage sustaining layer; An exemplary embodiment of a super junction power MOSFET having islands of opposite polarity distributed in a vertical direction in a voltage sustaining layer is shown; layers 23 and 24 respectively show super junction power with double gate and shielded gate structures An exemplary embodiment of a MOSFET; Figure 25A shows active and termination trenches for a channel transistor A top view of the office; 25B-25F shows a simplified layout for an alternative embodiment of the channel termination structure; 26A-26C is a cross-sectional view of an exemplary channel termination structure; and FIG. 27 shows a radius of curvature with a large radius of curvature Exemplary elements for terminating the channel; FIGS. 28A-28D are cross-sectional views of the termination region having the charge column charge balance structure; and FIGS. 29A-29C are exemplary embodiments of the ultra high voltage device using the super junction technique Cross-sectional view; Figure 30A shows an example of edge contact for a channel element; Figure 30B-30F shows an exemplary procedural step for an edge contact structure of a channel element; Figure 31A is for multiple passes An example of an active area contact structure in which a polysilicon layer is buried; 31B-31M shows an exemplary program flow for forming an active area shield contact structure for a channel; FIG. 31N is for an active area A cross-sectional view of an alternative embodiment of a shield contact structure; FIGS. 32A and 32B are layout views of an exemplary channel element having an active area shield contact structure; and FIGS. 32C-32D are for a Rupture outside the channel element in the channel structure of the contact channel to produce two embodiments of a simplified layout diagram; 33A graph of the shield for contacting the polysilicon in the trench in the active region An alternative embodiment of the layer; Figure 33B-33M shows an example of a program flow for contacting an active area shield structure of the type shown in Figure 33A; Figure 34 shows a spacer or buffer (barrier) a layer to reduce one of the thicknesses of the epitaxial drift region; FIG. 35 shows an alternative embodiment for an element having a barrier layer; and FIG. 36 shows a deep body-elevation junction A barrier layer to minimize the thickness of the epitaxial layer; FIG. 37 is a simplified example of a well-drift junction of a transistor using a diffusion barrier layer; and FIGS. 38A-38D show a self-alignment with an embedded electrode An exemplary flow of a quasi-epitaxial-well channel element; a 39A-39B diagram showing an exemplary program flow for a beveled well implant; and a 40A-40E plot showing self-aligned epitaxy An example of a well program; Figure 40R-40U shows a method for reducing the thickness of a substrate; Figure 41 shows an example of a program flow using a chemical procedure as the final thinning step; Figure 42A-42F shows the Examples of improved etching procedures; Figures 43A and 43B It illustrates an embodiment may eliminate the bird's beak (bird's beak) of the channel-etched according to procedures; of FIG. 44A and 44B show an alternative etch process; of FIG. 45A-45C show a modified warp for forming a polysilicon Inter The procedure of the inter-poly dielectric layer; the 46A, 46B and 46C diagrams show an alternative method for forming an IPD layer; and the 47A and 47B diagrams are another for forming a high quality interstitial polysilicon. Cross-sectional view of the method of dielectric layer; panels 48 and 49A-49D show other embodiments for forming a modified IPD layer; Figure 50A shows an anisotropic plasma procedure for IPD planarization; The figure shows an alternative IPD planarization method using a chemical mechanical program; Figure 51 is a flow chart of an exemplary method for controlling the oxidation rate; and Figure 52 shows an improved one-time atmospheric chemical vapor deposition procedure. A method for forming a thick oxide at the bottom of a channel; and FIG. 53 is an exemplary flow chart of a method for forming a thick oxide at the bottom of a channel using a directional tetraethyl citrate procedure; 54 and 55 The figure shows another embodiment for forming a thick bottom oxide; Figures 56-59 show another procedure for forming a thick dielectric layer at the bottom of a trench; Figure 60 shows a current sensing A simplified diagram of the MOSFET of the component; Figure 61A shows An example of a charge balancing MOSFET having a planar gate structure and an isolated current sensing structure; Figure 61B shows an example of integrating a current sensing element with a channel MOSFET; Figures 62A-62C show an alternative embodiment for a MOSFET with a series temperature sensing diode; Figure 63B shows an alternative embodiment for a MOSFET with ESD protection; Figures 64A-64D show an example of an ESD protection circuit; Figure 65 shows an exemplary for forming a charge-balanced power component with a lower ESR Programs; Figures 66A and 66B show a layout technique for reducing ESR; Figure 67 shows a DC-DC converter circuit using power switching; and Figure 68 shows another DC-DC converter circuit using power switching; Figure 69 shows an exemplary driver circuit for a dual gate MOSFET; Figure 70A shows an alternative embodiment with a separately driven gate electrode; and Figure 70B shows a timing diagram illustrating the operation of the circuit of Figure 70A. Figure 71 is a simplified cross-sectional view of a molded package; and Figure 72 is a simplified cross-sectional view of an unmolded package.

100‧‧‧n-channel power MOSFET (vertical channel MOSFET)

104‧‧‧p-type well or body area

106‧‧‧n type drift or epitaxial region

112‧‧‧N-type source area

114‧‧‧ heavily doped n+ substrate area

118‧‧‧p+heavy body area

Claims (21)

A semiconductor device comprising: a plurality of active channels defining an active region; and an edge region located outside the active region, each active channel of the plurality of active channels including a lower shield a polysilicon layer, an upper gate polysilicon, a first oxide layer and a second oxide layer, the first oxide layer isolating the lower shielding polysilicon and the upper gate polysilicon and the second oxide layer covers the upper gate polysilicon; The lower shielding polysilicon, the upper gate polysilicon, the first oxide layer and the second oxide layer conform to the shape of the active channel and extend from the active channel to a surface of the edge region, the edge region includes a first An opening and a second opening extending through the first oxide layer to the lower shielding polysilicon, the second opening extending through the second oxide layer to the upper gate polysilicon, the first opening An opening includes a conductive material in electrical contact with the underlying shielding polysilicon, and the second opening includes a conductive material in electrical contact with the upper gate polysilicon; The polysilicon lines with a shield below the electrically insulating substrate. The semiconductor device of claim 1, wherein the second oxide layer is directly above the upper gate polysilicon, the upper gate polysilicon is directly above the first oxide layer, and the first oxide The layer is directly above the polysilicon layer under the shield. The semiconductor component of claim 1, wherein the first opening is lower than the second opening. The semiconductor device of claim 1, wherein the plurality of active channel lines extend in parallel in a longitudinal direction, and the semiconductor element comprises a peripheral channel having an extension in a longitudinal direction, the relative The plurality of active channels are staggered such that there is an offset between the peripheral channel and the extension of the plurality of active channels. The semiconductor device of claim 1, wherein the plurality of active channel lines extend in parallel in a longitudinal direction, and the semiconductor element comprises a peripheral channel having an extension in a longitudinal direction, the relative Aligned with the plurality of active channels such that there is substantially no offset between the peripheral channel and the plurality of active channels. The semiconductor device of claim 1, wherein the second oxide layer covers a top portion of the plurality of active channels, and the top portion of the at least one active channel of the plurality of active channels is substantially The upper portion of the active channel is wider than the plurality of active channels. The semiconductor device of claim 1, further comprising a body region formed between the plurality of active channels, the body region having a contact etched region on a top surface of the body region A metal layer extends over the second oxide layer and is in electrical contact with the body region via the contact etch region. A semiconductor component comprising: a plurality of active channels defining an active region; An edge region is located outside the active region, and each of the active channels of the plurality of active channels includes a lower shield polysilicon, an upper gate polysilicon, a first oxide layer and a second oxide layer. The first oxide layer isolates the lower shield polysilicon from the upper gate polysilicon and the second oxide layer covers the upper gate polysilicon, the lower shield polysilicon, the upper gate polysilicon, the first oxide layer and the second oxide The layer of material conforms to the shape of the active channel and extends from the active channel to a surface of the edge region; the edge region includes a first opening and a second opening, the first opening extending through the first oxide a layer to the lower shielding polysilicon, the second opening extending through the second oxide layer to the upper gate polysilicon, the first opening comprising a conductive material in electrical contact with the underlying shielding polysilicon, and the second The opening system includes a conductive material in electrical contact with the upper gate polysilicon, the lower shield polysilicon system being electrically insulated from a substrate, the second oxide layer being directly Above the square gate polysilicon, the upper gate polysilicon is directly above the first oxide layer, and the first oxide layer is directly above the lower shielding polysilicon, and the first opening is lower than the second Opening. The semiconductor device of claim 8, wherein the plurality of active channel lines extend in parallel in a longitudinal direction, and the semiconductor element The device includes a peripheral channel having an extension in a longitudinal direction that is staggered relative to the plurality of active channels such that there is a bias between the peripheral channel and the extension of the plurality of active channels shift. The semiconductor device of claim 8, wherein the plurality of active channel lines extend in parallel in a longitudinal direction, and the semiconductor element comprises a peripheral channel having an extension in a longitudinal direction, the relative Aligned with the active channels such that there is substantially no offset between the peripheral channel and the plurality of active channels. The semiconductor device of claim 8, wherein the second oxide layer covers a top portion of the plurality of active channels, and the top portion of the at least one active channel of the plurality of active channels is substantially The upper portion of the active channel is wider than the plurality of active channels. The semiconductor device of claim 8 further comprising a body region formed between the plurality of active channels, the body region having a contact etched region on a top surface of the body region A metal layer extends over the second oxide layer and is in electrical contact with the body region via the contact etch region. A method of fabricating a semiconductor device, comprising: forming an epitaxial layer over a substrate; forming a dielectric layer over the epitaxial layer and patterning the dielectric layer; etching the patterned dielectric layer to Forming an active channel on the dielectric layer to form a portion having no dielectric layer; Forming a first oxide layer across a top surface of the substrate including the active channel; forming a first conductive layer on top of one of the first oxide layers; etching away the active channel Forming a second oxide layer over the first conductive layer; forming a second conductive layer on top of the second oxide layer, wherein the first one of the active channel is first In the region, the second conductive layer does not completely extend over the first conductive layer; a third oxide layer is formed over the second conductive layer; and a first opening is formed through the third oxide layer Exposing the second conductive layer outside the active channel; etching a second opening through the second oxide layer outside the active channel in the first region to expose the first conductive layer Not the second conductive layer; and filling the first opening and the second opening with a conductive material. The method of claim 13, further comprising forming the plurality of active channels in a longitudinal direction, and forming a peripheral channel having a plurality of extensions in the longitudinal direction, the plurality of extensions Interleaving is performed with respect to the plurality of active channels such that there is an offset between the plurality of extensions of the peripheral channel and the plurality of active channels. The method of claim 13, further comprising forming a plurality of active channels in the longitudinal direction and forming in the longitudinal direction a peripheral channel having a plurality of extensions aligned with respect to the plurality of active channels such that a plurality of extensions of the peripheral channel are between the plurality of active channels There is no offset. The method of claim 13, further comprising forming a third conductive layer over the third oxide layer, and contacting the first opening with the conductive material in the second opening to electrically connect the conductive layer a first conductive layer and the second conductive layer. The method of claim 13, further comprising electrically connecting the first opening to a first metal contact and electrically connecting the second opening to a second metal contact. The method of claim 13, wherein forming the dielectric layer comprises depositing a layer of cerium oxide. The method of claim 13, wherein the first conductive layer and the second conductive layer are polycrystalline germanium. The method of claim 13, wherein the first conductive layer is directly formed over the first oxide layer, and the second oxide layer is directly formed over the first conductive layer, the second The conductive layer is formed directly over the second oxide layer, and the third oxide layer is formed directly over the second conductive layer. The method of claim 13, wherein the first conductive layer and The second conductive layer is formed to be substantially the same thickness.