CN105448893B - ESD-protection structure and semiconductor devices in a kind of semiconductor devices - Google Patents
ESD-protection structure and semiconductor devices in a kind of semiconductor devices Download PDFInfo
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- CN105448893B CN105448893B CN201410307952.8A CN201410307952A CN105448893B CN 105448893 B CN105448893 B CN 105448893B CN 201410307952 A CN201410307952 A CN 201410307952A CN 105448893 B CN105448893 B CN 105448893B
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Abstract
The ESD-protection structure and semiconductor devices of a kind of semiconductor devices; the ESD-protection structure has a pair of back-to-back diodes; the top in a diode interface is provided with the field plate being grounded all the time wherein; utilize the internal electric field between field plate and N-type channel area; so that the depletion layer increase in interface; to reach the size of increase breakdown voltage; simultaneously because the presence without field oxide; so conducting resistance Rdson reduces; so that the value of tolerance electric current also increases, the effective contradictory problems for solving breakdown voltage and being resistant between electric current.
Description
Technical field
The invention belongs to semiconductor devices to manufacture field, more particularly to a kind of partly leading with electrostatic preventing structure
Body device.
Background technology
Electrostatic all exists at the nature moment, when the electrostatic charge that the external environment condition or chip internal of chip are accumulated, passes through
When the pin of chip flows in or out chip internal, electric current caused by moment (peak value is up to several amperes) or voltage, it will damage
Integrated circuit, chip functions are made to fail.With the development of semicon industry, characteristic size further reduces, and component density is more next
Bigger, electronic component is increasing by the possibility of electrostatic damage, and industrialization electronic device must design qualified electrostatic
Protection.
In power amplifying device, the high power device such as VDMOS, LDMOS, IGBT can bear high voltage, and its electrostatic is protected
The maintenance voltage of shield design requirement also accordingly increases.Meanwhile as LDMOS is widely used in high frequency wireless transmission field again, its is quiet
The minimum parasitic capacitance of electric protection design requirement is opened and noise coupling with avoiding opening by mistake.
In Publication No. US2008093624 U.S. Patent application, a kind of act in LDMOS device is disclosed
Static discharge (hereinafter referred to as ESD) protection structure.As shown in figure 1, the esd protection structure includes P type substrate 110, lining is arranged on
N-type epitaxy layer 120 on bottom 110, the field oxide 130 for being arranged on the top of N-type epitaxy layer 120, are isolated by the field oxide 130
Two P type trap zones 150,160, and the p-type weight being switched to respectively by 150,160 on the external devices grid of substrate 110 and one
Mix area 180,140.The operation principle of the esd protection structure as shown in Fig. 2 P type trap zone 150,160 respectively at N-type external delays 120
Form two back-to-back PN junction diodes 210,220, in its equivalent circuit, the two back-to-back diodes 210,220
One end is connected on the grid of external devices, other end ground connection, if the breakdown voltage of each diode is 13V, then when grid electricity
When the amplitude of pressure is less than ± 13V, one of diode is necessarily in cut-off state, now grid normal work；When grid electricity
When pressure is more than ± 13V, one conducting of the two diodes, one breakdown so that the branch road where the two diodes is in lead
Logical state, electric current export via the two diodes, cause to damage so as to avoid the too high voltage of grid loading, reach guarantor
Protect the effect of device.
Generally, in LDMOS or some other high-power component, the voltage request that gate operational voltages need to carry can not
More than 15V, therefore the protection voltage for ESD sets and is often slightly less than the voltage, such as 13V.Out of this esd protection structure
Portion is seen, when the voltage that outside applies is more than the breakdown voltage of one of PN junction, one is formed between equivalent to two P type trap zones
The passage of individual carrier, electronics can be moved to the other end from one end, and field oxide 130 is produced on two P with LOCOS techniques
Among type well region, play a part of isolation, while after carrier pathway foundation, add electronics and go to the other end from one end
Distance, that is, add conducting resistance Rdson.Under normal circumstances, the breakdown voltage BV of the esd protection structure turns on this
Resistance Rdson resistance is directly proportional, therefore can increase the value of breakdown voltage using above-mentioned field oxide.But this pass through increasing
Conducting resistance Rdson is added but to produce the problem of following to lift the mode of breakdown voltage：
When PN junction is operated under breakdown mode, its maximum Imax of resistance to electric current and the conducting resistance Rdson resistance are inversely proportional,
Increase conducting resistance Rdson is also implied that, its electric current that can bear will reduce.For esd protection structure, electric current
An often amount than voltage with greater need for consideration, especially the moment in static discharge, its immediate current can reach tens
Individual ampere.If the maximum Imax of the resistance to electric current very littles of pipe, then the protection structure is also easily burned out.
Therefore, in the prior art, breakdown voltage and tolerance electric current become a pair of implacable amounts.
The content of the invention
In view of this, it is an object of the invention to solve to propose a kind of new ESD-protection structure, the static discharge
Protection structure can take into account breakdown voltage and be resistant to the characteristic of electric current, while the breakdown voltage of esd protection structure is not influenceed,
Reduce the conducting resistance at both ends, so that the tolerance electric current of pipe increases, improve the performance of the esd protection structure.
ESD-protection structure in a kind of semiconductor devices proposed according to the purpose of the present invention, including the first conduction
The substrate of type, epitaxial layer over the substrate is set, first well region on the epitaxial layer with the second conductivity type, to first trap
The part surface in area carries out the first conductivity type and gently mixes the second well region and the 3rd well region to be formed, respectively in the second well region and the 3rd trap
The 4th well region, the 5th well region of the heavily doped formation of the first conductivity type are carried out in area, is provided between second well region and the 3rd well region
One section being formed and expose the channel region in epi-layer surface by the first well region, second well region, the 3rd well region and the first well region
Intersection formed two back-to-back PN junctions, the top of wherein at least one PN junction is provided with one block of field plate being grounded all the time.
Preferably, the part of the 3rd well region falls outside the first well region, the 5th well region formed in the 3rd well region
It is electrically connected with through epitaxial layer and the substrate, and the field plate is electrical connected with the 5th well region.
Preferably, the 5th well region is realized and the substrate by the decanting zone of heavily doped first conductivity type in the epitaxial layer
It is electrically connected with.
Preferably, the 5th well region is electrically connected with by opening up the realization of metal hole post in the epitaxial layer with the substrate,
Wherein the metal hole post is through to the surface or inside of the substrate.
Preferably, the field plate is located above the PN junction formed by the 3rd well region and the first well region, and wherein the field plate is located at
Part above first well region is less than the length of the channel region.
Preferably, in the range of the area of second well region entirely falls in the first well region, formed in second well region
The 4th well region be electrically connected in an external devices.
Preferably, the length of the channel region is 3-15um.
Preferably, first conductivity type is p-type, and second conductivity type is N-type.
Simultaneously the invention also provides a kind of semiconductor devices, including grid, source electrode and drain electrode, the semiconductor devices is also
Including ESD-protection structure as described above, wherein the grid is electrically connected with the ESD-protection structure.
Preferably, more metal layers are provided with the semiconductor devices, wherein constituting this positioned at outermost metal level
Gate pads, source pad and the drain pad of semiconductor devices, the ESD-protection structure are located at the gate pads
Lower section, and the 4th well region of the ESD-protection structure is electrically connected with by metal hole post technique and the multiple layer metal.
Preferably, the field plate in the ESD-protection structure is electrically connected with by the first metal layer positioned at innermost layer
To the 5th well region.
Preferably, between the field plate and the first metal layer, and the 5th well region and the first metal layer
Between be provided with metal hole post.
Compared with prior art, esd protection structure of the invention, one piece is set above at least one of which PN junction all the time
The field plate of ground connection replaces field oxide of the prior art, constructs a virtual interface in channel region, by the interior electricity in interface
Field is dispersed into two, the high peaks of single internal electric field originally is substituted by the lower peak value of two internal electric fields, so that PN junction
Reverse voltage endurance capability enhancing, has reached the purpose of increase breakdown voltage, simultaneously because without the presence of field oxide, so conducting
Resistance Rdson reduces so that being resistant to the value of electric current also increases, and effectively solves the problems of the prior art.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is esd protection structure schematic diagram of the prior art.
Fig. 2 is the equivalent circuit diagram in Fig. 1.
Fig. 3 is the esd protection structure schematic diagram under first embodiment of the invention.
Fig. 4 is the esd protection structure schematic diagram under second embodiment of the invention.
Fig. 5 is the complete diagram of esd protection structure of the present invention.
Fig. 6 is the top plan view of semiconductor devices of the present invention.
Embodiment
As described in the background art, existing a kind of semiconductor devices esd protection structure, leaned against by setting a pair
What the diode of the back of the body was realized.This esd protection structure, its operation principle are when the voltage of external load is more than one of them two pole
During the breakdown voltage of pipe, the esd protection structure is operated in conduction mode, by the branch where external voltage from esd protection structure
Road exports.In this case, the conducting resistance Rdson when breakdown voltage of each diode turns on to structure is directly proportional.For
Reach the protection voltage needed for device, in the prior art by making the field oxide of a thickness between two p-well regions, with
Increase Rdson resistance, so as to improve the purpose of breakdown voltage.But the way of this increase conducting resistance, EDS can be caused again
The tolerance electric current of protection structure reduces, and causes the esd protection structure to be easily burned out in the moment of static discharge.Therefore how to solve
The certainly contradiction between breakdown voltage and tolerance electric current, turns into difficult point of the prior art.
For the present invention in order to solve the above problems, creative proposes a kind of new esd protection structure.Its technical scheme
Main thought is：Based on two back-to-back diode structures in the prior art, cast out the field oxidation between two p-well regions
Layer, one block of field plate being grounded all the time is set above a PN junction wherein.The physical principle of this structure is as follows：On the one hand, by
There is no the presence of field oxide between two p-well regions, when working in the conduction mode, carrier channels are formed directly into N
The surface of well region, when being moved equivalent to electronics between two p-well regions, carried out along straight line, greatly reduce electron motion
Path, so as to reduce conducting resistance Rdson.On the other hand, due to being provided with one piece of field being grounded above a PN junction area
Plate, can now form a built in field in the N-type region domain that field plate covers, and the internal electric field has disperseed the single internal electric field of script
Backward voltage when peak value, improving the reverse voltage endurance capability of PN junction, thus puncturing on PN junction also increases, and so ensure that breakdown
The size of voltage.Therefore ESD protective device proposed by the present invention, the size of breakdown voltage is not only increased, simultaneously because conducting
Resistance Rdson reduces so that being resistant to the value of electric current also increases, and perfectly solves the problems of the prior art.
Technical scheme will be described in detail below.
Fig. 3 is referred to, Fig. 3 is the esd protection structure schematic diagram under first embodiment of the invention.As illustrated, the ESD
Protection mechanism includes the substrate 100 of the first conductivity type, the epitaxial layer of setting over the substrate, has the second conduction on the epitaxial layer
First well region 110 of type, the first conductivity type is carried out to the part surface of first well region and gently mixes the second well region 120 to be formed and the
Three well regions 130, the 4th well region of the heavily doped formation of the first conductivity type is carried out in the second well region 120 and the 3rd well region 130 respectively
140th, the 5th well region 150, be provided between the well region 130 of the second well region 120 and the 3rd one section it is being formed by the first well region 110 and
Expose the channel region in epi-layer surface, the intersection of second well region 120, the 3rd well region 130 and the first well region 110 forms two
Individual back-to-back PN junction, the two PN junctions are equivalent into if circuit, PN diodes 112,113 back-to-back equivalent to two.Its
In be provided with one block of field plate 180 being grounded all the time above the PN junction where diode 113.In actual use, it is contemplated that at present partly
Semiconductor process is currently preferred to define the first conductivity type for P, the maturity of n-type doping technique and device effect
For p-type, the second conductivity type is defined as N-type (hereafter same).Certainly well known to a person skilled in the art under technical conditions, this two
Individual conduction type can also be exchanged mutually.
Wherein, substrate 100 is preferably silicon substrate, and the backing material that certainly some other suitable semiconductor devices makes also may be used
Using silicon (SOI), carborundum or some organic semiconductor materials in the alternative as substrate in the present invention 100, such as insulation bottom
Material etc..Substrate 100 does the heavily doped processing of p-type so that the substrate 100 has good electric conductivity, in actual use, due to substrate
100 substrates also as semiconductor devices, therefore the substrate 100 can be allowed to be grounded according to use occasion simultaneously.
Epitaxial layer makes on the substrate 100, and the epitaxial layer is similarly P-type semiconductor, esd protection structure of the invention and
Semiconductor devices is actually all produced in the epitaxial layer.
Implement a n-type doping technique on the selection area of the epitaxial layer, form the first well region 110.First well region 110
Doping area visual organ part to the requirement of esd protection structure depending on.Such as in some large-size devices, it is allowed to ESD protection knots
Structure has slightly larger area, can make first well region 110 larger, conversely in some small size devices, then needs
Control the doping area of first well region 110.Its shape can be square, circular or Else Rule, irregular geometric figures.
The position of making may be selected in the place of neighbouring semiconductor devices, away from semiconductor devices, but it must be ensured that with half
The grid of conductor device does effective electric connection.Extended meeting introduction afterwards, as a preferred mode, it is desirable to welded in grid
The place that metallic region where disk covers.
Second well region 120 and the 3rd well region 130 are produced on the part surface of the first well region 110, second well region
120 and the 3rd the distance between well region 130 form the length of channel region.For in general esd protection structure, the raceway groove
On the one hand the length in area determines the size of total, on the other hand also determine the voltage that esd protection structure can bear
Size, in actual applications, the length of the channel region is about between 3-15um.
In the mode of diagram, the second well region 120 is fallen completely within the first well region 110, and the 3rd well region 130 is then partly fallen into
In first well region 110, another part is then arranged on the outside of the first well region 110, and the two P type trap zones can be with the first well region
110 form a pair of back-to-back PN junctions 112,113.This distribution mode can effectively improve the face of whole esd protection structure
The complexity of product utilization rate and reduction when making these well regions：As shown in figure 5, the second well region 120 is produced on first
The centre of well region 110, only need to be with form design the first well region 110, the second well region 120, Yi Ji of centrosymmetric geometric figure
Three well regions 130, you can obtain this distribution mode.Certainly, if the position of the second well region 120 or the 3rd well region 130 carried out
It is mobile, for example the second well region 120 is not to fall in the centre position of the first well region 110, or the 3rd well region 130 is entirely fallen in the
One well region 110, and feasible design, for those skilled in the art, the two well regions how are designed with respect to
A kind of position of one well region, simply simple change, in the case where meeting to form a pair of back-to-back PN junctions, can do any
Selection.
4th well region 140 and the 5th well region 150 are used as heavily doped p type island region domain, not only increase the electric conductivity of well region, simultaneously
4th well region 140 plays the connection function with external devices, and the 5th well region 150 plays the connection function with substrate.Such as institute in Fig. 3
Show, being made on the surface of the 4th well region 140 has conductive plate, and the conductive plate and the 4th well region 140 keep Ohmic contact, simultaneously
By the metal layer process in semiconductor devices manufacturing process, one or more layers metal is made in the top of the 4th well region 140
190, then it is electrically connected with by metallic conduction post 191, it is final that 4th well region 140 and the electrode of an external devices are welded
Disk connects.
Obstructed with connecting up for the 4th well region 140, the 5th well region 150 is by the way of connecting downwards, through epitaxial layer
It is electrically connected with substrate 100.In first embodiment as shown in Figure 3, this connection downwards is by epitaxial layer
Heavily doped p-type sedimentation (sink) area 160 is made in correspondence position to realize and substrate electric connection.Second embodiment party as shown in Figure 4
In formula, this connection downwards is then by opening up the realization of metal hole post 170 and the connection of substrate 100, these metal apertures in epitaxial layer
Post 170 is through epitaxial layer until the surface or inside of substrate 100.
As mentioned above it is possible, the inventive point of the present invention is, set one piece in the top of at least one PN junction is grounded all the time
Field plate 180.In embodiment as shown in Figure 3, the field plate 180 is arranged on to be formed by the 3rd well region 130 and the first well region 110
PN junction above, in some other embodiment, the field plate can also be arranged on same above another PN junction or two PN junctions
When set, different positions, for the field plate for the modulating action of electric field, be it is the same, those skilled in the art according to
The embodiment that diagram provides can simply obtain the field plate method to set up under other embodiment.
Referring again to Fig. 3, a part for field plate 180 is located at the top of the 3rd well region 130, and another part is located at the first well region
110 top.The field plate 180 utilizes metal level 181 and gold again by the metal layer process in semiconductor devices manufacturing process
Category conductive pole 182 is electrically connected with the 5th well region 150, and is finally electrically connected on substrate 100 so that the field plate 180
Remain in zero potential.It should be noted that the part that wherein field plate 180 is located above the first well region 110 should be less than
The length of the channel region.
The effect to the field plate 180 makes a brief description below：Due to the zero potential that field plate 180 maintains all the time, in the field plate
Electronics in the N-type region domain of 180 lower sections, is repelled downwards, so that the region forms a reversion close to the place on surface
Layer, i.e., the region becomes a positively charged region, so, in the N-type channel area, region below field plate with
Its adjacent region forms a virtual PN junction again, originally single internal electric field is dispersed into the smaller interior electricity of two peak values
, when whole pipe is by reversal connection, the internal electric field peak value ability to bear of script PN junction area strengthens the electricity, it is necessary to when being reversed breakdown
Pressure also increases.On the other hand, when the PN junction just connects conducting, i.e., after forming raceway groove on channel region surface, the motion of electronics need not
As being transmitted in the prior art around field oxide, therefore its conducting resistance Rdson reduces on the contrary.It thus form electric conduction
Hinder the physical effect that Rdson reduces, breakdown voltage increases so that the ESD protective device improves while breakdown voltage is ensured
To the tolerance of reverse current.It is possible to further set another block of field plate above another PN junction, connect on the field plate
The voltage entered is identical with the access voltage of whole ESD structures, when pipe forward conduction, its operation principle as field plate 180,
Reduce conducting resistance.And when pipe reversal connection, equivalent to the direction of low potential, it is acted on and ground connection in the direction residing for the field plate
Field plate 180 is identical, adds the breakdown reverse voltage in the PN junction.
Referring again to Fig. 5, Fig. 5 show the schematic diagram of complete esd protection structure, i.e. Fig. 3 or Fig. 4 to be come with respect to the Fig. 5
Say, merely illustrate an ESD half structure.
In Figure 5, interconnected between a PN junction of esd protection structure and the semiconductor devices of outside by metal level.Gold
Belong to layer the number of plies depending on specific device technology, as shown in 4 layers of metal level, naturally it is also possible to be the metal of other quantity
Layer.Connected between every layer of metal level by least one conductive metal hole post technique.
Please in conjunction with Fig. 5 referring to Fig. 6, Fig. 6 is a kind of top plan view of metal-oxide-semiconductor.As described in Figure, the MOS transistor device bag
Grid, source electrode and drain electrode are included, the gate pads 101 that wherein grid is drawn and the drawn drain pad 102 that drains are for defeated
Enter and/or export electric signal, the active area of whole device is then between gate pads 101 and drain pad 102.Specific
In manufacture craft, these gate pads can be produced using etching technics in the outermost metal 194 of multiple layer metal technique
101 and drain pad 102.Be typically due to the relative device of gate pads 101 has larger size in itself, therefore can be by above
In ESD protection mechanisms design below the gate pads 101, position as shown in dotted outline in FIG..Correspond in Fig. 5, should
Metal level where gate pads was that is, outermost metal 194, so can both realize and connect with the grid of semiconductor devices
Effect is connect, and can makes full use of the space of semiconductor devices in itself so that esd protection structure is almost not take up the area outside device
Domain, so that the size of device is unaffected.Specifically, the 4th well region 140 in esd protection structure passes through metal hole post
Technique interconnects with the multiple layer metal in semiconductor device fabrication process, until being connected to the metal where outermost gate pads
Untill layer.And the metal level 181 of the well region 150 of field plate 180 and the 5th is connected then equivalent to the first metal layer of innermost layer, and
Between field plate 180 and the first metal layer 181, and metal aperture is provided between the 5th well region 150 and the first metal layer 181
Post, so as to realize interconnection.
In summary, esd protection structure of the invention, one block of field plate being grounded all the time is set above a PN junction wherein
To replace field oxide of the prior art, it can not only increase the size of breakdown voltage, simultaneously because conducting resistance Rdson subtracts
It is small so that being resistant to the value of electric current also increases, and perfectly solves the problems of the prior art.
The foregoing description of the disclosed embodiments, professional and technical personnel in the field are enable to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
Embodiment illustrated herein is not intended to be limited to, and is to fit to consistent with principles disclosed herein and features of novelty
Most wide scope.
Claims (12)
- A kind of 1. ESD-protection structure in semiconductor devices, it is characterised in that：Substrate including the first conductivity type, set Epitaxial layer over the substrate, there is the first well region of the second conductivity type, to the part surface of first well region on the epitaxial layer Carry out the first conductivity type and gently mix the second well region and the 3rd well region to be formed, carry out first in the second well region and the 3rd well region respectively The 4th well region, the 5th well region of the heavily doped formation of conductivity type, one section is provided between second well region and the 3rd well region by the first trap Area formed and expose the channel region in epi-layer surface, the intersection of second well region, the 3rd well region and the first well region is formed Two back-to-back PN junctions, the top of wherein at least one PN junction are provided with one block of field plate being grounded all the time.
- 2. ESD-protection structure as claimed in claim 1, it is characterised in that：The part of 3rd well region falls first Outside well region, the 5th well region formed in the 3rd well region is electrically connected with through epitaxial layer and the substrate, and the field plate It is electrical connected with the 5th well region.
- 3. ESD-protection structure as claimed in claim 2, it is characterised in that：5th well region passes through in the epitaxial layer The decanting zone of heavily doped first conductivity type is realized to be electrically connected with the substrate.
- 4. ESD-protection structure as claimed in claim 2, it is characterised in that：5th well region passes through in the epitaxial layer Open up the realization of metal hole post to be electrically connected with the substrate, wherein the metal hole post is through to the surface or inside of the substrate.
- 5. ESD-protection structure as claimed in claim 2, it is characterised in that：The field plate is located at by the 3rd well region and the Above the PN junction that one well region is formed, the part that wherein field plate is located above the first well region is less than the length of the channel region.
- 6. ESD-protection structure as claimed in claim 1, it is characterised in that：The area of second well region is entirely fallen in In the range of first well region, the 4th well region formed in second well region is electrically connected in an external devices.
- 7. ESD-protection structure as claimed in any one of claims 1 to 6, it is characterised in that：The length of the channel region For 3-15um.
- 8. ESD-protection structure as claimed in any one of claims 1 to 6, it is characterised in that：First conductivity type is P-type, second conductivity type are N-type.
- 9. a kind of semiconductor devices, including grid, source electrode and drain electrode, it is characterised in that：The semiconductor devices is also included as weighed Profit requires the ESD-protection structure described in 1-8 any one, wherein the grid and ESD-protection structure electricity Property connection.
- 10. semiconductor devices as claimed in claim 9, it is characterised in that：More metal layers are provided with the semiconductor devices, The gate pads, source pad and drain pad of the semiconductor devices are wherein constituted positioned at outermost metal level, it is described quiet Discharge of electricity protection structure is located at the lower section of the gate pads, and the 4th well region of the ESD-protection structure passes through metal aperture Post technique is electrically connected with the multiple layer metal.
- 11. semiconductor devices as claimed in claim 10, it is characterised in that：Field plate in the ESD-protection structure leads to The first metal layer crossed positioned at innermost layer is electrically connected to the 5th well region.
- 12. semiconductor devices as claimed in claim 11, it is characterised in that：Between the field plate and the first metal layer, And metal hole post is provided between the 5th well region and the first metal layer.
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| CN201410307952.8A CN105448893B (en) | 2014-06-30 | 2014-06-30 | ESD-protection structure and semiconductor devices in a kind of semiconductor devices |
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| CN101540320A (en) * | 2009-04-21 | 2009-09-23 | 上海宏力半导体制造有限公司 | Static discharge protection diode |
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