CN105448893A - Electrostatic discharge protection structure in semiconductor device, and semiconductor device - Google Patents

Abstract

The invention discloses an electrostatic discharge protection structure in a semiconductor device, and the semiconductor device. The structure is provided with a pair of opposite diodes. A field plate which is always grounded is disposed above the node region of one diode. A depletion layer of the node region is increased through an internal electric field between the field plate and an N-type trench region, so as to improve the breakdown voltage. Because there is no oxidation layer, a conduction resistance Rdson is reduced, thereby enabling a withstand current value to be increased, and effectively solving a problem of conflict between the breakdown voltage and the withstand current.

Description

ESD-protection structure in a kind of semiconductor device and semiconductor device

Technical field

The invention belongs to semiconductor device and manufacture field, particularly relate to a kind of semiconductor device with electrostatic preventing structure.

Background technology

Electrostatic all existed in the nature moment, when the external environment condition of chip or the electrostatic charge of chip internal accumulation, when flowing into by the pin of chip or flow out chip internal, the electric current (peak value can reach several amperes) produced instantaneously or voltage, will integrated circuit be damaged, chip functions was lost efficacy.Along with the development of semicon industry, characteristic size reduces further, and component density is increasing, and electronic devices and components suffer the possibility of electrostatic damage increasing, and industrialization electronic device must design qualified electrostatic protection.

In power amplifying device, the high power devices such as VDMOS, LDMOS, IGBT can bear high voltage, and the ME for maintenance of its electrostatic protection design requirement is also corresponding to be increased.Meanwhile, as LDMOS is widely used in again high frequency wireless transmission field, the minimum parasitic capacitance of its electrostatic protection designing requirement opens and noise coupling to avoid opening by mistake.

Be in the U.S. Patent application of US2008093624 at publication number, disclose a kind of static discharge (hereinafter referred to as ESD) operator guards acted in LDMOS device.As shown in Figure 1; this esd protection structure comprises P type substrate 110; N-type epitaxy layer 120 is on a substrate 110 set, is arranged on the field oxide 130 at N-type epitaxy layer 120 top; by two P type trap zone 150,160 that this field oxide 130 is isolated, and be switched to the heavily doped district 180,140 of P type on substrate 110 and an external devices grid respectively by 150,160.The operation principle of this esd protection structure as shown in Figure 2, P type trap zone 150,160 forms two back-to-back PN junction diode 210,220 respectively at N-type external delays 120, in the circuit of its equivalence, these two back-to-back diode 210,220 1 ends are connected on the grid of external devices, other end ground connection, if the puncture voltage of each diode is 13V, then when the amplitude of grid voltage be less than ± 13V time, one of them diode must be in cut-off state, and now grid normally works; When grid voltage be greater than ± 13V time, the conducting of these two diodes, one breakdown; the branch road at these two diode places is made to be conducting state; electric current is derived via these two diodes, thus avoids grid and load too high voltage and cause damaging, and reaches the effect of protection device.

Usually, in LDMOS or some other high-power component, the voltage request of gate operational voltages needs carrying can not more than 15V, and the protection voltage setting therefore for ESD is often slightly less than this voltage, such as 13V.From the inside of this esd protection structure; when the voltage applied when outside is greater than the puncture voltage of one of them PN junction; be equivalent to the passage forming a charge carrier between two P type trap zone; electronics can move to the other end from one end; and field oxide 130 is produced in the middle of two P type trap zone with LOCOS technique, play the effect of isolation, simultaneously after carrier pathway is set up; add electronics goes to other end distance from one end, namely add conducting resistance Rdson.Under normal circumstances, the puncture voltage BV of this esd protection structure is directly proportional to the resistance of this conducting resistance Rdson, therefore uses above-mentioned field oxide can increase the value of puncture voltage.But this mode promoting puncture voltage by increasing conducting resistance Rdson but can produce following problem:

When PN junction is operated under breakdown mode, its maximum max of resistance to electric current I is inversely proportional to the resistance of this conducting resistance Rdson, and also just mean and increase this conducting resistance Rdson, its electric current that can bear will reduce.For esd protection structure, electric current more needs the amount considered often than voltage, especially in the moment of static discharge, its immediate current can reach tens amperes.If the maximum max of resistance to electric current I of pipe is very little, so this operator guards is also easily burnt.

Therefore, in the prior art, puncture voltage and withstand current become a pair implacable amount.

Summary of the invention

In view of this; the object of the invention is to solve and propose a kind of new ESD-protection structure; this ESD-protection structure can take into account the characteristic of puncture voltage and withstand current; while the puncture voltage not affecting esd protection structure; reduce the conducting resistance at two ends; thus the withstand current of pipe is increased, improve the performance of this esd protection structure.

ESD-protection structure in a kind of semiconductor device that object according to the present invention proposes, comprise the substrate of the first conductivity type, epitaxial loayer is over the substrate set, this epitaxial loayer has the first well region of the second conductivity type, the second well region and the 3rd well region that formation gently mixed by first conductivity type is carried out to the part surface of this first well region, the 4th well region of the heavily doped formation of the first conductivity type is carried out respectively in the second well region and the 3rd well region, 5th well region, be provided with between described second well region and the 3rd well region one section by the first well region formed and the channel region of exposing in epi-layer surface, this second well region, the intersection of the 3rd well region and the first well region forms two back-to-back PN junctions, wherein the top of at least one PN junction is provided with the field plate of one piece of ground connection all the time.

Preferably, the part of described 3rd well region drops on outside the first well region, and the 5th well region formed in the 3rd well region is electrically connected through epitaxial loayer and described substrate, and described field plate and described 5th well region are electrical connected.

Preferably, described 5th well region realizes being electrically connected with described substrate by the decanting zone of heavily doped first conductivity type in epitaxial loayer.

Preferably, described 5th well region realizes being electrically connected with described substrate by offering metal aperture post in epitaxial loayer, and wherein this metal aperture post is through to surface or the inside of described substrate.

Preferably, described field plate is positioned at above the PN junction that formed by the 3rd well region and the first well region, and wherein this field plate part be positioned at above the first well region is less than the length of described channel region.

Preferably, the area of described second well region all falls in the scope of the first well region, and the 4th well region be formed in this second well region is electrically connected in an external devices.

Preferably, the length of described channel region is 3-15um.

Preferably, described first conductivity type is P type, and described second conductivity type is N-type.

The invention allows for a kind of semiconductor device simultaneously, comprise grid, source electrode and drain electrode, described semiconductor device also comprises ESD-protection structure as above, and wherein said grid and described ESD-protection structure are electrically connected.

Preferably; more metal layers is provided with in described semiconductor device; wherein be positioned at outermost metal level and constitute the gate pads of this semiconductor device, source pad and drain pad; described ESD-protection structure is positioned at the below of this gate pads, and the 4th well region of this ESD-protection structure is electrically connected by metal aperture post technique and this multiple layer metal.

Preferably, the field plate in described ESD-protection structure is electrically connected to described 5th well region by the first metal layer being positioned at innermost layer.

Preferably, between described field plate and described the first metal layer, and be provided with metal aperture post between described 5th well region and described the first metal layer.

Compared with prior art, esd protection structure of the present invention, the field plate of one piece of ground connection is all the time set above one of them PN junction to replace field oxide of the prior art, a virtual interface is constructed in channel region, the internal electric field in interface is dispersed into two, the high peaks of single internal electric field is originally replaced by the lower peak value of two internal electric fields, thus the reverse voltage endurance capability of PN junction is strengthened, reach the object increasing puncture voltage, simultaneously owing to there is no field oxide, so conducting resistance Rdson reduces, the value of withstand current is also increased, effectively solve the problems of the prior art.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is esd protection structure schematic diagram of the prior art.

Fig. 2 is the equivalent circuit diagram in Fig. 1.

Fig. 3 is the esd protection structure schematic diagram under first embodiment of the invention.

Fig. 4 is the esd protection structure schematic diagram under second embodiment of the invention.

Fig. 5 is the complete diagram of esd protection structure of the present invention.

Fig. 6 is the top plan view of semiconductor device of the present invention.

Embodiment

As described in the background art, existing a kind of semiconductor device esd protection structure, realizes by arranging a pair back-to-back diode.This esd protection structure, its operation principle is that namely this esd protection structure is operated in conduction mode when the voltage of external load is greater than the puncture voltage of one of them diode, is derived by the branch road of external voltage from esd protection structure place.In this case, the puncture voltage of each diode is directly proportional to conducting resistance Rdson during structure conducting.In order to reach the protection voltage needed for device, by making the field oxide of thick layer between two P well regions in prior art, to increase the resistance of Rdson, thus improve the object of puncture voltage.But the way of this increase conducting resistance, the withstand current of EDS operator guards can be made again to reduce, cause this esd protection structure easily to be burnt in the moment of static discharge.Therefore how to solve the contradiction between puncture voltage and withstand current, become difficult point of the prior art.

The present invention, in order to solve the problem, creationaryly proposes a kind of new esd protection structure.The main thought of its technical scheme is: in prior art based on two back-to-back diode structures, cast out the field oxide between two P well regions, arranges the field plate of one piece of ground connection all the time wherein above a PN junction.The physical principle of this structure is as follows: on the one hand, owing to there is no field oxide between two P well regions, when working in the conduction mode, carrier channels is formed directly into the surface of N well region, be equivalent to electronics when moving between two P well regions, carry out along straight line, greatly reduce the path of electron motion, thus decrease conducting resistance Rdson.On the other hand, owing to being provided with the field plate of one piece of ground connection above a PN junction area, the N-type region territory now covered at field plate can form an internal electric field, this internal electric field has disperseed the peak value of single internal electric field originally, improve the voltage endurance capability that PN junction is reverse, reverse voltage when thus PN junction puncturing also increases, and so ensure that the size of puncture voltage.Therefore the ESD protective device of the present invention's proposition, not only increases the size of puncture voltage, simultaneously because conducting resistance Rdson reduces, the value of withstand current is also increased, perfectly solves the problems of the prior art.

To be described in detail technical scheme of the present invention below.

Refer to Fig. 3, Fig. 3 is the esd protection structure schematic diagram under first embodiment of the invention.As shown in the figure, this esd protection mechanism comprises the substrate 100 of the first conductivity type, epitaxial loayer is over the substrate set, this epitaxial loayer has the first well region 110 of the second conductivity type, the second well region 120 and the 3rd well region 130 that formation gently mixed by first conductivity type is carried out to the part surface of this first well region, the 4th well region 140 of the heavily doped formation of the first conductivity type is carried out respectively in the second well region 120 and the 3rd well region 130, 5th well region 150, be provided with between described second well region 120 and the 3rd well region 130 one section by the first well region 110 formed and the channel region of exposing in epi-layer surface, this second well region 120, the intersection of the 3rd well region 130 and the first well region 110 forms two back-to-back PN junctions, these two PN junction equivalences become the words of circuit, be equivalent to two back-to-back PN diodes 112, 113.Above the PN junction at diode 113 place, be wherein provided with the field plate 180 of one piece of ground connection all the time.Actual to use, consider that current semiconductor technology is for the maturity of P, N-type doping process and device effect, the first conductivity type is preferably defined as P type by the present invention, the second conductivity type is defined as N-type (Hereinafter the same).Certainly well known to a person skilled in the art under technical conditions, these two conduction types also can be exchanged mutually.

Wherein, substrate 100 is preferably silicon substrate, the backing material that certain some other applicable semiconductor device makes also can as the alternative of substrate in the present invention 100, silicon (SOI) at the end of such as insulating, carborundum or some organic semiconducting materials etc.Substrate 100 does the heavily doped process of P type, makes this substrate 100 have good electric conductivity, actual to use, and because substrate 100 is simultaneously also as the substrate of semiconductor device, therefore can allow this substrate 100 ground connection according to use occasion.

Epitaxial loayer makes on the substrate 100, and this epitaxial loayer is similarly P type semiconductor, and esd protection structure of the present invention and semiconductor device reality are all produced in this epitaxial loayer.

The selection area of this epitaxial loayer is implemented a N-type doping process, forms the first well region 110.The doping area visual organ part of this first well region 110 is determined the requirement of esd protection structure.Such as in some large-size devices, allow esd protection structure to have slightly large-area, what this first well region 110 can be made is larger, on the contrary in some small size devices, then needs the doping area controlling this first well region 110.Its shape can be square, circular or Else Rule, irregular geometric figures.The position made may be selected in the place of contiguous semiconductor device, also can away from semiconductor device, but must ensure to do effective electric connection with the grid of semiconductor device.Rear extended meeting introduction, as the preferred mode of one, the place that preferably can cover in the metallic region at gate pads place.

Second well region 120 and the 3rd well region 130 are produced on the part surface of the first well region 110, and the distance between this second well region 120 and the 3rd well region 130 defines the length of channel region.For general esd protection structure, the length of this channel region determines the size of total on the one hand, and also determine the voltage swing that esd protection structure can bear on the other hand, in actual applications, the length of this channel region is greatly between 3-15um.

In illustrated mode, second well region 120 falls in the first well region 110 completely, 3rd well region 130 part falls in the first well region 110, and another part is then arranged on the outside of the first well region 110, and these two P type trap zone can form a pair back-to-back PN junction 112,113 with the first well region 110.The area utilization that this distribution mode effectively can improve whole esd protection structure and the complexity reduced when making these well regions: as shown in Figure 5; second well region 120 is produced on the centre of the first well region 110; only with centrosymmetric geometric form design first well region 110, second well region 120 and the 3rd well region 130, need can obtain this distribution mode.Certainly, if the position of the second well region 120 or the 3rd well region 130 is moved, such as the second well region 120 not drops on the centre position of the first well region 110, or the 3rd well region 130 is all fallen into the first well region 110, is also feasible design, as those skilled in the art, how to design the position of relative first well region of these two well regions, just a simple change, when satisfied formation a pair back-to-back PN junction, can do arbitrary selection.

4th well region 140 and the 5th well region 150, as territory, heavily doped p type island region, not only increase the electric conductivity of well region, and the 4th well region 140 plays the connection function with external devices simultaneously, and the 5th well region 150 plays the connection function with substrate.As shown in Figure 3, conductive plate is manufactured with on the surface of the 4th well region 140, this conductive plate and the 4th well region 140 keep ohmic contact, simultaneously by the metal layer process in semiconductor device manufacturing process, one or more layers metal 190 is made above the 4th well region 140, then be electrically connected by metallic conduction post 191, finally make the 4th well region 140 be connected with the electrode pad of an external devices.

Obstructed with being upwards connected of the 4th well region 140, the 5th well region 150 adopts the mode connected downwards, is electrically connected through epitaxial loayer and substrate 100.In the first execution mode as shown in Figure 3, this downward connection realizes being electrically connected with substrate by making heavily doped P type sedimentation (sink) district 160 in the correspondence position of epitaxial loayer.In the second execution mode as shown in Figure 4, this downward connection then realizes and the connection of substrate 100 by offering metal aperture post 170 in epitaxial loayer, and these metal aperture posts 170 run through epitaxial loayer until the surface of substrate 100 or inside.

As noted before, inventive point of the present invention is, arranges the field plate 180 of one piece of ground connection all the time above at least one PN junction.In execution mode as shown in Figure 3, this field plate 180 is arranged on above the PN junction that formed by the 3rd well region 130 and the first well region 110, in some other execution mode, this field plate also can be arranged on above another PN junction or two PN junctions and arrange simultaneously, different positions, for the modulating action of this field plate for electric field, be the same, those skilled in the art simply can obtain the field plate method to set up under other execution modes according to the execution mode that diagram provides.

Please again see Fig. 3, a part for field plate 180 is positioned at the top of the 3rd well region 130, and another part is positioned at the top of the first well region 110.This field plate 180 is equally by the metal layer process in semiconductor device manufacturing process, metal level 181 and metallic conduction post 182 and the 5th well region 150 is utilized to be electrically connected, and be finally electrically connected on substrate 100, this field plate 180 is remained in zero potential.It should be noted that wherein this field plate 180 part be positioned at above the first well region 110 should be less than the length of described channel region.

Below the effect of this field plate 180 is made a brief description: the zero potential maintained all the time due to field plate 180, electronics in N-type region territory below this field plate 180, repelled downwards, thus make this region form an inversion layer near the place on surface, namely this region becomes a positively charged region, so, in this N-type channel region, be positioned at the region adjacent with it, region below field plate and define again a virtual PN junction, single internal electric field is originally made to be dispersed into the less internal electric field of two peak values, when whole pipe is by reversal connection, originally the internal electric field peak value ability to bear of PN junction area is strengthened, the voltage be reversed when puncturing is needed also to increase.On the other hand, when this PN junction is just connecing conducting, namely after surface, channel region forms raceway groove, the motion of electronics need not as transmitting around field oxide in the prior art, and therefore its conducting resistance Rdson reduces on the contrary.Thus form the physical effect that conducting resistance Rdson reduces, puncture voltage increases, make this ESD protective device while guarantee puncture voltage, improve the tolerance to reverse current.Further, can arrange another block field plate above another PN junction, the voltage that this field plate accesses is identical with the access voltage of whole ESD structure, and when pipe forward conduction, its operation principle is the same with field plate 180, reduces conducting resistance.And when pipe reversal connection, the direction residing for this field plate is equivalent to the direction of electronegative potential, its effect is identical with the field plate 180 of ground connection, adds the reverse breakdown voltage in this PN junction.

Please again see Fig. 5, Figure 5 shows that the schematic diagram of complete esd protection structure, namely Fig. 3 or Fig. 4 this Fig. 5 relatively, merely illustrates a half structure of ESD.

In Figure 5, one of esd protection structure is passed through metal layer interconnect between PN junction and the semiconductor device of outside.The number of plies of metal level, depending on concrete device technology, as 4 layers of metal level in diagram, can certainly be the metal level of other quantity.Connected by the metal aperture post technique of at least one conduction between every layer of metal level.

Please composition graphs 5 is a kind of top plan view of metal-oxide-semiconductor see Fig. 6, Fig. 6 again.As described in Figure, this MOS transistor device comprises grid, source electrode and drain electrode, the gate pads 101 that wherein grid is drawn is used for inputting and/or exporting the signal of telecommunication with the drain pad 102 of drawing that drains, and the active area of whole device is then between gate pads 101 and drain pad 102.In concrete manufacture craft, can, in the outermost metal 194 of multiple layer metal technique, etching technics be utilized to produce these gate pads 101 and drain pad 102.Usually because gate pads 101 relative device itself has larger size, therefore can by esd protection mechanism design above below this gate pads 101, position as shown in dotted outline in FIG..Correspond in Fig. 5; namely the metal level at this gate pads place is equivalent to outermost metal 194; so both can realize the grid connection function with semiconductor device; the space of semiconductor device itself can be made full use of again; make esd protection structure take region outside device hardly, thus make the size of device unaffected.Particularly, the 4th well region 140 in esd protection structure is interconnected by the multiple layer metal in metal aperture post technique and semiconductor device fabrication process, till the metal level being connected to outermost gate pads place.The metal level 181 connecting field plate 180 and the 5th well region 150 is then equivalent to the first metal layer of innermost layer, and between field plate 180 and this first metal layer 181, and the 5th is provided with metal aperture post between well region 150 and this first metal layer 181, thus realize interconnection.

In sum; esd protection structure of the present invention; the field plate of one piece of ground connection is all the time set above a PN junction wherein to replace field oxide of the prior art; not only can increase the size of puncture voltage; simultaneously because conducting resistance Rdson reduces; the value of withstand current is also increased, perfectly solves the problems of the prior art.

To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to embodiment illustrated herein, but will meet the widest scope consistent with principle disclosed herein and features of novelty.

Claims (12)

1. the ESD-protection structure in a semiconductor device, it is characterized in that: the substrate comprising the first conductivity type, epitaxial loayer is over the substrate set, this epitaxial loayer has the first well region of the second conductivity type, the second well region and the 3rd well region that formation gently mixed by first conductivity type is carried out to the part surface of this first well region, the 4th well region of the heavily doped formation of the first conductivity type is carried out respectively in the second well region and the 3rd well region, 5th well region, be provided with between described second well region and the 3rd well region one section by the first well region formed and the channel region of exposing in epi-layer surface, this second well region, the intersection of the 3rd well region and the first well region forms two back-to-back PN junctions, wherein the top of at least one PN junction is provided with the field plate of one piece of ground connection all the time.

2. ESD-protection structure as claimed in claim 1; it is characterized in that: the part of described 3rd well region drops on outside the first well region; the 5th well region formed in the 3rd well region is electrically connected through epitaxial loayer and described substrate, and described field plate and described 5th well region are electrical connected.

3. ESD-protection structure as claimed in claim 2, is characterized in that: described 5th well region realizes being electrically connected with described substrate by the decanting zone of heavily doped first conductivity type in epitaxial loayer.

4. ESD-protection structure as claimed in claim 2, is characterized in that: described 5th well region realizes being electrically connected with described substrate by offering metal aperture post in epitaxial loayer, and wherein this metal aperture post is through to surface or the inside of described substrate.

5. ESD-protection structure as claimed in claim 2, is characterized in that: described field plate is positioned at above the PN junction that formed by the 3rd well region and the first well region, and wherein this field plate part be positioned at above the first well region is less than the length of described channel region.

6. ESD-protection structure as claimed in claim 1, it is characterized in that: the area of described second well region all falls in the scope of the first well region, the 4th well region be formed in this second well region is electrically connected in an external devices.

7. the ESD-protection structure as described in claim 1-6 any one, is characterized in that: the length of described channel region is 3-15um.

8. the ESD-protection structure as described in claim 1-6 any one, is characterized in that: described first conductivity type is P type, and described second conductivity type is N-type.

9. a semiconductor device, comprises grid, source electrode and drain electrode, it is characterized in that: described semiconductor device also comprises the ESD-protection structure as described in claim 1-8 any one, and wherein said grid and described ESD-protection structure are electrically connected.

10. semiconductor device as claimed in claim 9; it is characterized in that: in described semiconductor device, be provided with more metal layers; wherein be positioned at outermost metal level and constitute the gate pads of this semiconductor device, source pad and drain pad; described ESD-protection structure is positioned at the below of this gate pads, and the 4th well region of this ESD-protection structure is electrically connected by metal aperture post technique and this multiple layer metal.

11. semiconductor device as claimed in claim 10, is characterized in that: the field plate in described ESD-protection structure is electrically connected to described 5th well region by the first metal layer being positioned at innermost layer.

12. semiconductor device as claimed in claim 12, is characterized in that: between described field plate and described the first metal layer, and are provided with metal aperture post between described 5th well region and described the first metal layer.