KR20210042246A - Electrostatic discharge handling for sense igbt using zener diode - Google Patents

Abstract

Provided is a semiconductor transistor device which comprises: a main insulated gate bipolar transistor (IGBT); a sense IGBT; a sense resistor connected between a sense emitter of the sense IGBT and a main emitter of the main IGBT; and a back-to-back Zener diode connected between a sense gate and the sense emitter of the sense IGBT and configured to clamp a voltage between the sense gate and the sense emitter during an electrostatic discharge (ESD) event. Therefore, ESD protection against both forward and reverse currents between the gate and the sense emitter can be provided.

Description

Electrostatic Discharge Treatment for Sensing IGBTs Using Zener Diodes {ELECTROSTATIC DISCHARGE HANDLING FOR SENSE IGBT USING ZENER DIODE}

This description relates to the treatment of electrostatic discharge for insulated gate bipolar transistor (IGBT) devices.

Electrostatic discharge (ESD) is a common difficulty in the manufacture and use of semiconductor transistors and related devices. ESD can occur, for example, due to electrostatic charges provided by a person or tool inadvertently making contact with a conductive portion of a transistor. Such ESD has the potential to damage or destroy the affected transistor and interfere with the operations of connected circuits and devices.

In particular, transistors that are ultra-high voltage (UHV) devices are susceptible to ESD damage. Existing models or standards for testing against device failure due to ESD, such as Human Body Mode (HBM), show that traditional ESD protection schemes provide protection up to about 1.5 kilovolts (kV). This is likely to be insufficient in many cases for UHV devices.

For example, insulated gate bipolar transistor (IGBT) devices can be used in such high power UHV scenarios while providing advantages such as high speed switching and high efficiency. IGBT devices may be configured in different ways (eg, planar or trench gates), and may be configured with different types of layouts on the underlying substrate. ESD protection schemes have been developed for many scenarios requiring IGBT devices, but such ESD protection schemes may not be sufficient to provide ESD protection in all IGBT use cases.

According to one general aspect, a semiconductor transistor device comprises a main insulated gate bipolar transistor (IGBT) having a main gate, a main collector, and a main emitter. The semiconductor transistor device may include a sense gate, a sense collector, and a sense IGBT having a sense emitter, the sense gate is electrically connected to the main gate, the sense collector is electrically connected to the main collector, and the sense resistor senses It is connected between the emitter and the main emitter. Back-to-back Zener diodes are connected between the sense gate and the sense emitter and can be configured to clamp the voltage between the sense gate and the sense emitter during an electrostatic discharge (ESD) event.

According to another general aspect, a semiconductor transistor device may include a substrate and an epitaxial layer formed on the substrate. The semiconductor transistor device may include a main emitter region formed in the epitaxial layer and isolated by at least a first junction termination extension (JTE), the main emitter region of the main insulated gate bipolar transistor (IGBT). To form. The semiconductor transistor device may include a first plurality of gate trenches formed in the main emitter region and forming a main gate of the main IGBT, and a sensing emitter region formed in the epitaxial layer and isolated by at least a second JTE, , The sensing emitter area forms the sensing emitter of the sensing IGBT. The semiconductor transistor device may include a second plurality of gate trenches formed in the sensing emitter region, forming a sensing gate of the sensing IGBT, and electrically connected to the main gate of the main IGBT. The semiconductor transistor device forms back-to-back Zener diodes, and has an alternating n-doped region and a p-doped region connected between the gate contact common to the main gate and the sense gate and the sense emitter contact of the sense emitter. It may include a silicon layer.

According to another general aspect, a method of manufacturing a semiconductor transistor device may include forming a substrate, and forming an epitaxial layer on the substrate. The method comprises forming a main emitter region formed in the epitaxial layer and isolated by at least a first junction termination extension (JTE)-the main emitter region forming the main emitter of the main insulated gate bipolar transistor (IGBT). -, and forming a first plurality of gate trenches formed in the main emitter region and forming a main gate of the main IGBT. The method comprises forming a sensing emitter region formed in the epitaxial layer and isolated by at least a second JTE, the sensing emitter region forming a sensing emitter of the sensing IGBT, and forming and sensing in the sensing emitter region. Forming a sensing gate of the IGBT, and forming a second plurality of gate trenches electrically connected to the main gate of the main IGBT. The method comprises forming back-to-back Zener diodes and a polysilicon layer having alternating n-doped and p-doped regions connected between the gate contact common to the main gate and the sense gate and the sense emitter contact of the sense emitter. It may include the step of forming.

Details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.

1 is a circuit diagram illustrating ESD protection for a sensing IGBT using at least one Zener diode.
2A is a first plan view of an exemplary implementation of the circuit of FIG. 1.
FIG. 2B is a second plan view of the circuit of FIG. 1, illustrating an embodiment of the at least one Zener diode of FIG. 1.
3 is a flow diagram illustrating exemplary operations for a method for forming a transistor structure according to FIGS. 1, 2A and 2B.
4 is a first cross-sectional side view illustrating exemplary implementations of the process steps of the flow chart of FIG. 3.
5 is a second cross-sectional side view illustrating example implementations of the process steps of the flow chart of FIG. 3.
6 is a third cross-sectional side view illustrating exemplary implementations of the process steps of the flow chart of FIG. 3.
7 is a fourth cross-sectional side view illustrating exemplary implementations of the process steps of the flow chart of FIG. 4.
8 is a graph of the HBM performance provided by back-to-back Zener diodes between the gate and the sense emitter as described in connection with FIGS. 1-7.
9 is a circuit diagram illustrating an example use case for the implementations of FIGS. 1-7.

The transistor devices described herein are used to sense the current flow in the primary or main IGBT device, even when the sense IGBT has isolated junction voltages with respect to the main IGBT device. Zener diode protection schemes for ESD protection against current flow may be included. Moreover, by providing back-to-back Zener diodes, it is possible to provide bidirectional ESD protection, ie ESD protection for both forward and reverse currents between the gate and the sense emitter. In addition, the relevant processing steps for manufacturing a sensing IGBT with Zener diode(s) for ESD protection between the gate of the sensing IGBT and the sensing emitter can be performed inexpensively and with minimal modifications compared to conventional processes. have.

In more detailed examples, some circuits using the sense IGBT and the main IGBT, as described above, use an isolation region to isolate the sense IGBT from the main IGBT. In particular, for example, such isolation may be necessary or useful when a sense resistor for current sensing is added between the sense emitter and the main emitter. For example, such isolation schemes can be used in industrial motor drive applications.

In such a case, a current division can be implemented between the sense current and the main current. Also, since the sense IGBT is much smaller than the main IGBT, the sense IGBT can be much more sensitive to the need for ESD protection. However, in the types of use cases described above, such as industrial motor drive applications, an ESD performance of HBM> 2000V may be required. By adding Zener diode(s) between the gate of the sense IGBT and the sense emitter as described herein, the ESD performance of the described circuits can be improved.

While many of the examples herein are discussed with respect to a particular conductivity type (eg, p-type conductivity, n-type conductivity) by way of example, the conductivity types may, in some implementations, be inverted.

In the example of FIG. 1, the main IGBT 102 represents a number of IGBT devices used for primary purposes, such as industrial motor drive applications, for example. In general, and as discussed in detail below, main IGBT 102 represents a relatively large number of IGBT devices (e.g., approximately thousands of IGBT devices, formed on a lower substrate), each of which is an example. For example, it has a main gate implemented as a gate trench and connected to a common gate contact illustrated as gate 104 in FIG. 1. Similarly, a common collector contact can be electrically connected to the main collector regions of the main IGBT 102, illustrated as collector 106 in FIG. 1. A common main emitter contact may be connected to a plurality of main emitter regions (which may be collectively referred to herein as main emitter regions), illustrated as main emitter 108 in FIG. 1.

Also in FIG. 1, sense IGBT 110 represents a much smaller number of IGBT devices, which are used to monitor and sense the current through main IGBT 102. In more detail, the implementation of the circuit of FIG. 1 may have a ratio defined between the number of sensing IGBT devices 110 and the number of main IGBT devices 102. Then, the sense current flow through the sense IGBT devices 110 will generally be proportional to the main current flow through the main IGBT devices 102, so the sense of the sense current provides useful information about the main current.

1 is a simplified circuit diagram illustrating electrical connections between main IGBT 102 and sensing IGBT 110, as implemented using corresponding electrical contacts. For example, the gate 104 of FIG. 1, when referred to as such, may be understood to represent a common gate contact connecting the main gate of the main IGBT 102 and the sense gate of the sensing IGBT 110. . Similar comments apply to the collector 106 of FIG. 1, when referred to as such in connection with FIG. 1, indicating a sense collector and a common collector contact connected to the main collector. In addition, in FIG. 1, the term'sense emitter 112' collectively refers to the sense emitter area and the sense emitter contact, while the term'main emitter 108' collectively refers to the main emitter area and Refers to the main emitter contact.

Main IGBT 102 may be susceptible to various overcurrent conditions during its normal operations, which may damage main IGBT 102 and/or related circuits. The sensing IGBT 110 may be designed to enable fast and accurate current sensing for the main current so that appropriate actions can be taken. For example, in order to minimize or eliminate the types of damage described above, the main current can be quickly turned off in response to a detected overcurrent condition.

As mentioned, for example, a current sense resistor 113 (which is further illustrated in FIGS. 7 and 9) is connected between the sense emitter 112 and the main emitter 108 of the sense IGBT 110. And thus, as will be described later in connection with FIG. 9, the sense current can be measured through such a sense resistor 113. As described above, and as described and illustrated in more detail below in connection with FIGS. 7 and 9, having an isolation region between the sense emitter 112 and the main emitter 108 is from the collector 106. Current division of the current flowing through the sensing IGBT 110 and the main IGBT 102 may be caused.

Also, as described above, the circuit of FIG. 1 may be susceptible to various types of ESD-related damage. Since ESD is a known problem, a number of different types of ESD protection schemes have been implemented for IGBT devices. Many such ESD protection schemes are limited to providing ESD protection at levels, for example HBM <2000V, which may be insufficient for UHV applications. Moreover, such ESD protection schemes are generally configured for the main IGBT 102.

However, when the circuit of FIG. 1 is used in certain applications, such as industrial motor drive applications, the underlying device structure of the circuit of FIG. 1 may include the types of isolation structures described above, which Along with the inclusion, it may cause current division between the IGBTs 102 and 110. Since the sense IGBT 110 is much smaller than the main IGBT 102, the sense IGBT 110 is also more sensitive to the need for ESD protection in such scenarios. Moreover, any ESD protection that may be provided for the main IGBT 102 will not be able to provide ESD protection for the sensing IGBT 110.

Consequently, as shown in FIG. 1, at least one gate-sensing Zener diode(s) 114, implemented as back-to-back Zener diodes connected between the gate 104 and the sensing emitter 112 in FIG. 1 Is illustrated. As described and illustrated herein, back-to-back Zener diodes 114 are connected between the gate and the sense emitter and are configured to clamp the gate-sensing emitter voltage during an electrostatic discharge (ESD) event. The back-to-back gate-sensing Zener diodes 114 thus provide a high level of ESD protection for the circuit of FIG. 1, even when there are isolated junction voltages between the sense emitter 112 and the emitter 108. Moreover, by providing back-to-back Zener diodes 114 as illustrated, ESD protection is provided for both forward and reverse current flow between gate 104 and sense emitter 112.

In the simplified example of FIG. 1, a main insulated gate bipolar transistor (IGBT) 102 has a main gate, a main collector, and a main emitter, and the sense IGBT 110 has a sense gate, a sense collector, and a sense emitter. In this case, the sensing gate is electrically connected to the main gate by the common gate contact 104, and the sensing collector is electrically connected to the main collector by the common collector contact 106. The sense resistor 113 is connected between the sense emitter and the main emitter, the back-to-back zener diodes 114 are connected between the sense gate and the sense emitter, and the sense gate and sense emitter during an electrostatic discharge (ESD) event. It is configured to clamp the voltage between.

2A is a plan view of an exemplary implementation of the circuit of FIG. 1. In the example of FIG. 2A, the emitter region 202 of the main IGBT (such as the main IGBT 102 of FIG. 1) is illustrated and corresponds to the emitter 108 of FIG. 1. The main emitter region 202 is illustrated as having a gate pad 204, which is gate lines or gate trenches (not shown in Fig. 2A, but not shown in Fig. 3 and crossing the main emitter region 202). 7 to 9) may be electrically connected. Also in FIG. 2A, the sensing cell 206 corresponds to the sensing IGBT 110.

2B is a second plan view of an exemplary implementation of the circuit of FIG. 1. In the example of FIG. 2B, sense cell 206 is enlarged to better illustrate sense emitter 208 and sense pad 210. The gate-sensing Zener diode 212 is a Zener diode(s) 212 (FIG. 1) with a gate contact 216 and a sensing contact 218 formed therebetween, as illustrated in the enlarged view of the portion 214. It is formed to have a similar Zener diodes 114). Specifically, Zener diode(s) 212 is formed using alternating n/p portions of a doped semiconductor material, for example illustrated as n/p/n/p/n structure 220 in FIG. 2B. Can be. As can be appreciated from the following discussion of Figures 3-7, such a Zener diode(s) structure 220 can be easily and/or incorporated in a manufacturing process for manufacturing the circuit of Figure 1 without incurring too much cost. have.

For example, FIG. 3 is a flow diagram 300 illustrating an exemplary manufacturing process for manufacturing the circuit of FIG. 1. As described and illustrated below, FIGS. 4-7 are cross-sectional views of FIG. 2B taken along line B-B'. 4-6 illustrate example implementations of the corresponding processing steps 302-310 of the example of FIG. 3. In particular, FIG. 4 generally corresponds to blocks 302-306 of FIG. 3. FIG. 5 generally corresponds to operation 308 of FIG. 3. 6 generally corresponds to operation 310 of FIG. 3. FIG. 6 as well as FIG. 7 illustrate further exemplary aspects resulting from additional exemplary processing operations for forming desired electrical contacts and other features not explicitly included in the exemplary flow chart of FIG. 3.

As shown in FIG. 4, an epitaxial layer 406, including a buffer layer 404, is formed on the substrate 402 (corresponding method steps shown at block 302 in FIG. 3). In some implementations, the buffer layer can be excluded.

Then, doped junctions 408, 410, 412 (e.g., p-doped junctions) as shown in Figures 4-7 can be formed as junction termination extension (JTE) regions, for example. There is (corresponding method step shown at block 304 in FIG. 3). As described below, the JTE regions 408, 410, 412 define emitter regions. More specifically, such JTEs 408, 410, 412 are used, for example, to reduce surface field strengths, and to surround and protect active device regions (including shielding from external fields). In some implementations, the top view of FIGS. 2A and 2B shows that the JTEs 408, 410 are the sensing emitter region 208 (not shown in FIG. 4, but in the examples of FIGS. 6 and 7 ). 608)).

As shown in FIG. 4, a polysilicon layer 416 may then be deposited on the insulating layer 414 (the corresponding method step shown at block 306 in FIG. 3 ). As will be discussed below, the polysilicon layer 416 can be used for the formation of back-to-back Zener diodes.

As shown in Figure 5, implantation of a first conductivity type (e.g., P+ implantation) in the polysilicon layer 416 to form the polysilicon layer 502 can be performed (block ( 308), which provides the anode region of the back-to-back Zener diodes as described herein.

Implantation of a second conductivity type may be performed into the doped polysilicon layer 502 of FIG. 5 to form back-to-back Zener diodes 611 (corresponding method step shown at block 310 in FIG. 3). . As shown, the back-to-back Zener diodes 611 are formed on the insulating layer 414 on at least a portion of the lower JTE 412, alternating n regions 612 (forming a cathode) and an anode (forming an anode). Are) defined by p regions 614.

As also shown in FIG. 6, p-wells may be included to form the emitter region 606 as well as the sense emitter region 608. Gate trenches 603 may be formed, and corresponding gate oxides 604 and gate polysilicon 602 may be formed therein. As also illustrated in FIG. 6, thus an isolation region 610 is defined between JTE 408 and JTE 410, which isolates main emitter region 606 from sense emitter region 608. That is, as shown, the term'main emitter region' refers to various p- While referring to wells 606, the term'sensing emitter region' refers to p-wells interspersed with sensing gates 602/604 in trenches 603 on the sensing emitter side of the isolation region 610. Refer to (608).

In FIG. 7, the formation of the contact region may include forming the BPSG layers 710 and 712 by including a borophosphosilicate glass (BPSG) layer 710 on the isolation region 610. In some implementations, layers 710 and 712 can be different types of insulating or dielectric material. Gate contacts 706 and emitter contacts 702 and 704 may also be included.

Also in FIG. 7 is shown an exemplary electrical connection between the sensing emitter (contact) 704 and the main emitter (contact) 702, for example, of the current (sensing) detection described above with respect to FIG. An external sense resistor 714 enabling type is illustrated. As described above, in order to be able to add the sense resistor 714 in the types of high voltage (e.g., motor drive) applications described herein, the sense emitter and main image using the isolation region 610. It is desirable to separate or isolate the territories.

8 is a graph illustrating exemplary overvoltage protection provided by the back-to-back Zener diode protection scheme described herein. As shown in Figure 8, the gate-sensing overvoltage condition covers a wide range of voltages, including, for example, about 8 kV, without allowing unwanted and damaging gate-sensing current flow. Can occur across.

9 is a circuit diagram illustrating an example use case for the implementations of FIGS. 1-7. In FIG. 9, the control chip 902 includes a plurality of input/control voltage pins 903 (e.g., inputs IN1, IN2, IN3, rail voltages VDD and VSS) not described in detail herein. ), as well as three output pins 904. Further, pin 906 is an overcurrent detection and shutdown pin that can be used to stop operations of chip 902 upon detection of an overcurrent condition, as described below.

In FIG. 9, transistor 908 is connected to shunt resistor 910, illustrating an example of the implementation of FIG. 1, as also described in more detail below. Transistor 912 is similarly connected to shunt resistor 914 and transistor 916 is similarly connected to shunt resistor 918. The circuit of FIG. 9 may be used for three-phase current sensing, but the further discussion of FIG. 9 is limited to single-phase current sensing, which may occur using transistor 908 and shunt resistor 910. That is, it is assumed that transistor 908 is on while transistors 912 and 914 are off, so a voltage drop occurs across shunt resistor 910 and sense resistor 920, where sense resistor 920 is It corresponds to the sense resistor 113 of FIG. 1 and the sense resistor 714 of FIG. 7.

In transistor 908, sense emitter 922 is connected to gate 924 by a back-to-back Zener diode 923. As shown, the sense resistor 920 is thus connected between the sense emitter 922 and the main emitter 925, as described above with respect to FIGS. 1 and 7. As further illustrated, both the shunt resistor 910 and the sense resistor 920 are connected to the ground terminal 926.

Thus, the sense current through sense resistor 920, as detected at CIN pin 906 using RC (resistor-capacitor) filter 928, can be used to detect an overcurrent condition, and thus all transistors (908, 912, 916) can be shut down. In other words, the voltage drop across sense resistor 920 is delivered to CIN 906 using RC filter circuit 928.

In various example implementations, a semiconductor transistor device may include a main insulated gate bipolar transistor (IGBT) having a main gate, a main collector, and a main emitter. The semiconductor transistor device may include a sense gate, a sense collector, and a sense IGBT having a sense emitter, the sense gate is electrically connected to the main gate, the sense collector is electrically connected to the main collector, and the sense resistor senses It is connected between the emitter and the main emitter. The semiconductor transistor device may include back-to-back Zener diodes connected between the sense gate and the sense emitter and configured to clamp a voltage between the sense gate and the sense emitter during an electrostatic discharge (ESD) event.

Back-to-back Zener diodes can be formed using alternating n-doped and p-doped regions connected between the gate contact of the sense gate and the sense emitter contact of the sense emitter. The alternating n-doped regions and p-doped regions may include at least two n-doped regions and at least two p-doped regions. The sense current through the sense resistor can be proportional to the main current through the main emitter.

The main emitter may include a main emitter region formed in an epitaxial layer formed on the substrate and isolated by at least a first junction termination extension (JTE). The first plurality of gate trenches may be formed in the main emitter region, and at least part of the main gate may be formed. A sensing emitter region may be formed in the epitaxial layer and isolated by at least a second JTE, and the epitaxial layer may comprise an electrically isolated region between at least two JTEs.

The second JTE may be formed by forming a ring surrounding the sensing emitter region. Back-to-back Zener diodes may be formed in a polysilicon layer formed on an insulating layer over at least a portion of the second JTE. The second plurality of gate trenches may be formed in the sensing emitter region and may form at least a part of the sensing gate.

In various additional or alternative implementations, a semiconductor transistor device comprises a substrate, an epitaxial layer formed on the substrate, and a main emitter region formed in the epitaxial layer and isolated by at least a first junction termination extension (JTE). The main emitter region forms a main emitter of the main insulated gate bipolar transistor (IGBT). The semiconductor transistor device further comprises a first plurality of gate trenches formed in the main emitter region and forming a main gate of the main IGBT, and a sensing emitter region formed in the epitaxial layer and isolated by at least a second JTE. And the sensing emitter region forms a sensing emitter of the sensing IGBT. The semiconductor transistor device is formed in the sensing emitter region, forms a sensing gate of the sensing IGBT, forms a second plurality of gate trenches electrically connected to the main gate of the main IGBT, and back-to-back Zener diodes, and is common to the main gate and sensing gate. It may further comprise a polysilicon layer having alternating n-doped and p-doped regions connected between the in-gate contact and the sense emitter contact of the sense emitter.

The sensing IGBT can be configured to provide current sensing of the current flow through the main IGBT. Current sensing can be provided using a sense resistor connected between the main emitter and the sense emitter. At least the second JTE may be formed in a ring configuration surrounding the sensing emitter region.

The alternating n-doped regions and p-doped regions may include at least two n-doped regions and at least two p-doped regions. The epitaxial layer may include an electrically isolated region between at least the first JTE and at least the second JTE. Back-to-back Zener diodes may be formed on an insulating layer over at least a portion of at least the second JTE.

In the above description, when an element such as a layer, region, substrate, or component is referred to as being on, connected to, electrically connected to, connected to, or electrically connected to another element, it is directly It will be appreciated that there may be one or more intervening elements on, connected to or connected to an element. In contrast, when an element is referred to as being directly above, directly connected to, or directly connected to another element or layer, there are no intervening elements or layers. The terms'directly above','directly connected', or'directly connected' may not be used throughout the detailed description, but are depicted as being directly above, directly connected, or directly connected. Elements can be referred to as such. If any, the claims of this application may be amended to enumerate exemplary relationships described in the specification or shown in the drawings.

As used in the specification and claims, the singular form may include the plural form unless a specific case is clearly indicated in terms of context. Spatially relative terms (eg, above, above, above, below, below, below, below, etc.) are intended to include different orientations of the device in use or in operation in addition to the orientation shown in the figure. In some implementations, the relative terms'above' and'bottom' may include'vertically above' and'vertically below', respectively. In some implementations, the term'adjacent' may include'laterally adjacent' or'horizontally adjacent'.

Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations employ various types of semiconductor processing techniques related to semiconductor substrates, including, but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and the like. It can be implemented using.

While certain features of the described embodiments have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now arise to those skilled in the art. Accordingly, it is to be understood that the appended claims are intended to cover all such modifications and variations falling within the scope of implementations. It is presented by way of example only, not limitation, and it should be understood that various changes in form and detail may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except for combinations that are mutually exclusive. The implementations described herein may include various combinations and/or sub-combinations of the functions, components and/or features of the different implementations described.

Claims (7)

As a semiconductor transistor device,
A main insulated gate bipolar transistor (IGBT) having a main gate, a main collector, and a main emitter;
A sensing IGBT having a sensing gate, a sensing collector, and a sensing emitter, wherein the sensing gate is electrically connected to the main gate, and the sensing collector is electrically connected to the main collector;
A sense resistor connected between the sense emitter and the main emitter; And
And back-to-back Zener diodes connected between the sense gate and the sense emitter and configured to clamp a voltage between the sense gate and the sense emitter during an electrostatic discharge (ESD) event. The method of claim 1,
The main emitter formed in the epitaxial layer formed on the substrate and including a main emitter region isolated by at least a first junction termination extension (JTE);
A first plurality of gate trenches formed in the main emitter region and forming at least a portion of the main gate; And
A sensing emitter region formed in the epitaxial layer and isolated by at least a second JTE, the epitaxial layer comprising an electrically isolated region between the at least two JTEs. device. As a semiconductor transistor device,
Board;
An epitaxial layer formed on the substrate;
A main emitter region formed in the epitaxial layer and isolated by at least a first junction termination extension (JTE), the main emitter region forming a main emitter of a main insulated gate bipolar transistor (IGBT);
A first plurality of gate trenches formed in the main emitter region and forming a main gate of the main IGBT;
A sensing emitter region formed in the epitaxial layer and isolated by at least a second JTE, the sensing emitter region forming a sensing emitter of a sensing IGBT;
A second plurality of gate trenches formed in the sensing emitter region, forming a sensing gate of the sensing IGBT, and electrically connected to the main gate of the main IGBT; And
Forming back-to-back Zener diodes, polysilicon having alternating n-doped regions and p-doped regions connected between a gate contact common to the main gate and the sensing gate and a sensing emitter contact of the sensing emitter A semiconductor transistor device comprising a layer. 4. The semiconductor transistor device of claim 3, wherein the epitaxial layer comprises an electrically isolated region between at least the first JTE and at least the second JTE. As a method of manufacturing a semiconductor transistor device,
Forming a substrate;
Forming an epitaxial layer on the substrate;
Forming a main emitter region formed on the epitaxial layer and isolated by at least a first junction termination extension (JTE)-the main emitter region forms a main emitter of a main insulated gate bipolar transistor (IGBT) -;
Forming a first plurality of gate trenches formed in the main emitter region and forming a main gate of the main IGBT;
Forming a sensing emitter region formed in the epitaxial layer and isolated by at least a second JTE, the sensing emitter region forming a sensing emitter of a sensing IGBT;
Forming a second plurality of gate trenches formed in the sensing emitter region, forming a sensing gate of the sensing IGBT, and electrically connected to the main gate of the main IGBT; And
Forming back-to-back Zener diodes, polysilicon having alternating n-doped regions and p-doped regions connected between a gate contact common to the main gate and the sensing gate and a sensing emitter contact of the sensing emitter Forming a layer. 6. The method of claim 5, wherein at least the second JTE is formed in a ring configuration surrounding the sense emitter region. 6. The method of claim 5, comprising forming the back-to-back Zener diodes on the polysilicon layer and on an insulating layer over at least a portion of the second JTE.

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