WO2022162894A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2022162894A1
WO2022162894A1 PCT/JP2021/003344 JP2021003344W WO2022162894A1 WO 2022162894 A1 WO2022162894 A1 WO 2022162894A1 JP 2021003344 W JP2021003344 W JP 2021003344W WO 2022162894 A1 WO2022162894 A1 WO 2022162894A1
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WO
WIPO (PCT)
Prior art keywords
trench
semiconductor device
layer
deep
gate electrode
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PCT/JP2021/003344
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French (fr)
Japanese (ja)
Inventor
太郎 近藤
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サンケン電気株式会社
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Priority to PCT/JP2021/003344 priority Critical patent/WO2022162894A1/en
Publication of WO2022162894A1 publication Critical patent/WO2022162894A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a semiconductor device with a vertical trench gate MOS structure with improved withstand voltage at device termination.
  • the present invention relates to a structure of a semiconductor device having a vertical trench MOS structure, which solves the above problems and can secure a sufficient breakdown resistance.
  • a termination trench having a single field plate inside the trench and an active trench adjacent to the termination trench and having a gate electrode inside the trench and a field plate below the gate electrode.
  • a deep P layer is formed in between, and the position of the deep P layer is between the gate electrode of the adjacent active trench and the field plate under the gate electrode.
  • FIG. 1 shows a termination structure of a semiconductor device having a conventional vertical trench gate MOS structure.
  • 1 is a termination structure of a semiconductor device having a vertical trench gate MOS structure according to Example 1 of the present invention.
  • FIG. 10 is a termination structure of a semiconductor device having a vertical trench gate MOS structure according to a second embodiment of the present invention;
  • FIG. 10 is a termination structure of a semiconductor device having a vertical trench gate MOS structure according to a third embodiment of the present invention;
  • FIG. 1 shows a conventional semiconductor device having a vertical trench gate MOS structure
  • FIG. 2 shows a structure relating to Example 1 of the semiconductor device having a vertical trench gate MOS structure according to the present invention
  • 3 shows the structure of the second embodiment of the semiconductor device having the vertical trench gate MOS structure of the present invention
  • FIG. 4 shows the overall structure of the third embodiment of the semiconductor device having the vertical trench gate MOS structure of the present invention. Show structure.
  • FIG. 1 shows a conventional semiconductor device having a vertical trench gate MOS structure
  • FIG. 2 shows a structure relating to Example 1 of the semiconductor device having a vertical trench gate MOS structure according to the present invention
  • 3 shows the structure of the second embodiment of the semiconductor device having the vertical trench gate MOS structure of the present invention
  • FIG. 4 shows the overall structure of the third embodiment of the semiconductor device having the vertical trench gate MOS structure of the present invention. Show structure.
  • FIG. 1 shows a conventional semiconductor device having a vertical trench gate MOS structure
  • FIG. 2 shows a structure relating to Example 1
  • a deep P layer is formed between
  • the voltage at the end portion of the semiconductor device could not be sufficiently relieved, and a sufficient withstand voltage could not be obtained.
  • a deep P layer is formed between the gate electrode and field plate of adjacent active trenches in the depth direction.
  • FIG. 3 shows a structure relating to Example 2 of a semiconductor device having a vertical trench gate MOS structure according to the present invention.
  • the deep P layer is in contact with neither the active trench nor the termination trench.
  • FIG. 4 shows a structure according to a third embodiment of a semiconductor device having a vertical trench gate MOS structure according to the present invention.
  • Example 3 when the width of the upper portion of the deep P layer is a and the width of the lower portion is b, there is a relationship of a>b.
  • a/b is 1.2 or more in order to secure the fracture resistance.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)

Abstract

[Problem] To provide a semiconductor device of a vertical trench gate MOS structure having high breakage resistance at a terminal portion. [Solution] A semiconductor device of a vertical trench gate MOS structure, wherein: a deep P layer is formed between a termination trench which has a single field plate inside the trench and an active trench which is adjacent to the termination trench and which has a gate electrode inside the trench and a field plate below the gate electrode; and the deep P layer is positioned between the field plate and the gate electrode of the adjacent active part trench.

Description

半導体装置semiconductor equipment
　本発明はデバイス終端における耐量の向上した縦型トレンチゲートMOS構造の半導体装置に関する。 The present invention relates to a semiconductor device with a vertical trench gate MOS structure with improved withstand voltage at device termination.
 縦型トレンチゲートMOS構造の半導体装置において、デバイス終端において、電圧の勾配が強くなり、破壊に至る現象が発生する問題がある。このため、破壊耐量を向上させる構造として、終端トレンチと、終端トレンチに隣接する活性トレンチの間に、深いP層を設ける構造が示されている。
In a semiconductor device having a vertical trench gate MOS structure, there is a problem that a voltage gradient becomes strong at the end of the device and a phenomenon leading to breakdown occurs. For this reason, a structure in which a deep P layer is provided between a terminal trench and an active trench adjacent to the terminal trench is shown as a structure for improving breakdown resistance.
ＵＳ２０２０／０２１２２１８号公報US2020/0212218
しかしながら、先行技術の構造では、十分な破壊耐量を確保することが困難であった。 However, it was difficult to ensure sufficient resistance to breakage in the structure of the prior art.
本発明は、上記問題点を解決し、さらに十分な破壊耐量を確保し得る、縦型トレンチMOS構造の半導体装置の構造に関する。
The present invention relates to a structure of a semiconductor device having a vertical trench MOS structure, which solves the above problems and can secure a sufficient breakdown resistance.
　
縦型トレンチゲートMOS構造の半導体装置において、トレンチ内部に単一のフィールドプレートを有する終端トレンチと、終端トレンチに隣接し、トレンチ内部にゲート電極と、ゲート電極下のフィールドプレートを有する活性トレンチとの間に、深いP層を形成し、深いP層の位置は、隣接する活性トレンチのゲート電極と、ゲート電極下のフィールドプレートの間の位置とする。
In a semiconductor device having a vertical trench gate MOS structure, a termination trench having a single field plate inside the trench and an active trench adjacent to the termination trench and having a gate electrode inside the trench and a field plate below the gate electrode. A deep P layer is formed in between, and the position of the deep P layer is between the gate electrode of the adjacent active trench and the field plate under the gate electrode.
　　　本発明によれば、終端部において高い耐量を有する縦型トレンチゲートMOS構造の半導体装置を製造できる。
According to the present invention, it is possible to manufacture a semiconductor device having a vertical trench gate MOS structure having a high withstand voltage at the terminal portion.
従来の縦型トレンチゲートＭＯＳ構造の半導体装置の終端部構造である。1 shows a termination structure of a semiconductor device having a conventional vertical trench gate MOS structure. 本発明の実施例１に係わる縦型トレンチゲートＭＯＳ構造の半導体装置の終端部構造である。1 is a termination structure of a semiconductor device having a vertical trench gate MOS structure according to Example 1 of the present invention. 本発明の実施例２に係わる縦型トレンチゲートＭＯＳ構造の半導体装置の終端部構造である。FIG. 10 is a termination structure of a semiconductor device having a vertical trench gate MOS structure according to a second embodiment of the present invention; FIG. 本発明の実施例３に係わる縦型トレンチゲートＭＯＳ構造の半導体装置の終端部構造である。FIG. 10 is a termination structure of a semiconductor device having a vertical trench gate MOS structure according to a third embodiment of the present invention; FIG.
以下、本発明の実施の形態となる構造について説明する。
Structures according to embodiments of the present invention will be described below.
図1に、従来の、縦型トレンチゲートＭＯＳ構造の半導体装置を、図２に本発明の縦型トレンチゲートＭＯＳ構造の半導体装置の実施例１に係わる構造を示す。また、図３には本発明の縦型トレンチゲートＭＯＳ構造の半導体装置の実施例２に係わる構造を、図４には本発明の縦型トレンチゲートＭＯＳ構造の半導体装置の実施例３に係わる全体構造を示す。図１に示すように、従来構造では、トレンチ内部に単一のフィールドプレートを有する終端トレンチと、前記終端トレンチに隣接し、トレンチ内部にゲート電極と、ゲート電極下のフィールドプレートを有する活性トレンチとの間に、深いP層が形成されている。しかしこの構造では、半導体装置の終端部において十分、電圧を緩和できず、十分な耐量を得ることができなかった。
本発明においては、図２に示すよう、深いP層を、深さ方向において、隣接する活性トレンチの、ゲート電極と、フィールドプレートとの間に位置するように形成する。この位置に深いP層を形成することで、終端部における電圧を緩和でき、その結果、破壊耐量を向上できる。
FIG. 1 shows a conventional semiconductor device having a vertical trench gate MOS structure, and FIG. 2 shows a structure relating to Example 1 of the semiconductor device having a vertical trench gate MOS structure according to the present invention. 3 shows the structure of the second embodiment of the semiconductor device having the vertical trench gate MOS structure of the present invention, and FIG. 4 shows the overall structure of the third embodiment of the semiconductor device having the vertical trench gate MOS structure of the present invention. Show structure. As shown in FIG. 1, in a conventional structure, a termination trench with a single field plate inside the trench and an active trench adjacent to said termination trench with a gate electrode inside the trench and a field plate below the gate electrode. A deep P layer is formed between However, in this structure, the voltage at the end portion of the semiconductor device could not be sufficiently relieved, and a sufficient withstand voltage could not be obtained.
In the present invention, as shown in FIG. 2, a deep P layer is formed between the gate electrode and field plate of adjacent active trenches in the depth direction. By forming a deep P layer at this position, the voltage at the end portion can be relaxed, and as a result, the breakdown resistance can be improved.
図３に本発明の縦型トレンチゲートＭＯＳ構造の半導体装置の実施例２に係わる構造を示す。実施例２においては、深いP層が、活性部トレンチ、終端トレンチのいずれとも接していない。このような構造で、空乏層を伸ばす領域を確保することができ、さらに終端部における電圧を緩和することができ、半導体装置の破壊耐量を向上することができる。
FIG. 3 shows a structure relating to Example 2 of a semiconductor device having a vertical trench gate MOS structure according to the present invention. In Example 2, the deep P layer is in contact with neither the active trench nor the termination trench. With such a structure, a region for extending the depletion layer can be secured, the voltage at the terminal portion can be relaxed, and the breakdown resistance of the semiconductor device can be improved.
図４に本発明の縦型トレンチゲートＭＯＳ構造の半導体装置の実施例３に係わる構造を示す。実施例３においては、深いP層の上部の幅をa、下部の幅をbとした場合、a＞ｂの関係にある。このような形状で深いP層を形成することで、空乏層の広がりを確保でき、さらに終端部における電圧を緩和することができる。また、これによって半導体装置の破壊耐量を向上することができる。数値的にはa/bは1.2以上であることが破壊耐量を確保するのに望ましい。
FIG. 4 shows a structure according to a third embodiment of a semiconductor device having a vertical trench gate MOS structure according to the present invention. In Example 3, when the width of the upper portion of the deep P layer is a and the width of the lower portion is b, there is a relationship of a>b. By forming a deep P layer with such a shape, it is possible to secure the spread of the depletion layer and further relax the voltage at the end portion. In addition, this can improve the breakdown resistance of the semiconductor device. Numerically, it is desirable that a/b is 1.2 or more in order to secure the fracture resistance.
１、メタル
２、メタル
３、絶縁膜
４、Ｐベース層
５、ソース
６、Pベース層
７、深いP層
８、N-層
９、N+ドレイン層
１０、フィールドプレート
１１、酸化膜
１２、終端トレンチ
１３、ゲート電極
１４、酸化膜
１５、フィールドプレート
１６、活性トレンチ
１７、終端領域
１８、活性領域
１９、活性トレンチ 1, metal 2, metal 3, insulating film 4, P base layer 5, source 6, P base layer 7, deep P layer 8, N- layer 9, N+ drain layer 10, field plate 11, oxide film 12, termination trench 13, gate electrode 14, oxide film 15, field plate 16, active trench 17, termination region 18, active region 19, active trench

Claims (3)

  1. トレンチ内部に単一のフィールドプレートを有する終端トレンチと、前記終端トレンチに隣接し、トレンチ内部にゲート電極と、ゲート電極下のフィールドプレートを有する活性トレンチとの間に深いP層を有し、前記深いP層の位置は、隣接する前記活性トレンチの前記ゲート電極と、前記ゲート電極下のフィールドプレートの間の位置にあることを特徴とする、縦型トレンチゲート型MOS構造の半導体装置。
    a deep P layer between a termination trench having a single field plate within the trench and an active trench adjacent to the termination trench and having a gate electrode within the trench and a field plate below the gate electrode; A semiconductor device having a vertical trench gate type MOS structure, wherein the position of the deep P layer is between the gate electrode of the adjacent active trench and the field plate under the gate electrode.
  2. 前記深いP層が、前記活性トレンチ、前記終端トレンチのいずれとも接していないことを特徴とする請求項１に記載の半導体装置。
    2. The semiconductor device according to claim 1, wherein said deep P layer is in contact with neither said active trench nor said termination trench.
  3. 前記深いP層の,上部の幅をa、下部の幅をbとした場合、a＞ｂの関係にあることを特徴とする請求項２に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein the deep P layer has a relationship of a>b, where a is the width of the upper portion and b is the width of the lower portion.
PCT/JP2021/003344 2021-01-29 2021-01-29 Semiconductor device WO2022162894A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007529115A (en) * 2003-12-30 2007-10-18 フェアチャイルド・セミコンダクター・コーポレーション Power semiconductor device and manufacturing method thereof
US20130153999A1 (en) * 2011-12-20 2013-06-20 Lei Zhang Trench gate mosfet device
JP2017038016A (en) * 2015-08-12 2017-02-16 サンケン電気株式会社 Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007529115A (en) * 2003-12-30 2007-10-18 フェアチャイルド・セミコンダクター・コーポレーション Power semiconductor device and manufacturing method thereof
US20130153999A1 (en) * 2011-12-20 2013-06-20 Lei Zhang Trench gate mosfet device
JP2017038016A (en) * 2015-08-12 2017-02-16 サンケン電気株式会社 Semiconductor device

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