JP2017038016A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2017038016A
JP2017038016A JP2015159734A JP2015159734A JP2017038016A JP 2017038016 A JP2017038016 A JP 2017038016A JP 2015159734 A JP2015159734 A JP 2015159734A JP 2015159734 A JP2015159734 A JP 2015159734A JP 2017038016 A JP2017038016 A JP 2017038016A
Authority
JP
Japan
Prior art keywords
region
trench
electrode
semiconductor device
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015159734A
Other languages
Japanese (ja)
Other versions
JP6573107B2 (en
Inventor
俊介 福永
Shunsuke Fukunaga
俊介 福永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP2015159734A priority Critical patent/JP6573107B2/en
Publication of JP2017038016A publication Critical patent/JP2017038016A/en
Application granted granted Critical
Publication of JP6573107B2 publication Critical patent/JP6573107B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which expansion of a depletion layer from a pn interface with a p-type floating region and an outer peripheral trench to a drift region side is improved and a high breakdown voltage outer peripheral structure can be achieved.SOLUTION: A semiconductor device includes a first conductivity type semiconductor substrate including an active region 200 and an outer peripheral region 300 which surrounds the active region 200. The outer peripheral region 300 includes: an outside trench 110; an outside electrode 120 which is arranged in the outside trench 110 and electrically insulated from the semiconductor substrate; and a second conductivity type floating region 140 formed next to lateral faces of the outside trench 110.SELECTED DRAWING: Figure 1

Description

本発明は、スイッチング動作を行う半導体装置の構造に関する。   The present invention relates to a structure of a semiconductor device that performs a switching operation.

大電流のスイッチング動作を行うスイッチング素子（パワー半導体素子）として、トレンチゲート型のパワーＭＯＳＦＥＴが広く用いられている。   As a switching element (power semiconductor element) that performs a switching operation with a large current, a trench gate type power MOSFET is widely used.

トレンチゲート型のパワーＭＯＳＦＥＴは、一般的に第1導電型のドレイン領域と、第1導電型のドレイン領域の上に形成された第1導電型のドリフト領域と、第1導電型のドリフト領域上に選択的に形成された第２導電型のベース領域と、第２導電型のベース領域上に選択的に形成された第１導電型のソース領域と、ソース領域からベース領域を貫通してドリフト領域に達する溝と、ベース領域と対向する溝の側壁に絶縁膜を介して形成されたゲート電極と、ソース領域と電気的に接続したソース電極と、ドレイン領域と電気的に接続したドレイン電極とを備える。しかし、このようなトレンチゲート型のパワーＭＯＳＦＥＴにおいて、ゲート電極がドリフト領域と対向する面積が広いため、ゲート−ドレイン間の容量が大きくなる。これにより、オン／オフ時のミラー充電期間が長くなり、高速なスイッチング特性が得られないという問題がある。そこで、ゲート−ドレイン間容量を低減するため、溝内のゲート電極の一部をゲート電極と絶縁したソース電位の補助電極に置き換え、ドリフト領域と制御電極との対向する面積を小さくした例が特許文献１に開示されている。また、トレンチゲート型のパワーＭＯＳＦＥＴを取り囲む外周領域として、特許文献２のようにトレンチゲート型のパワーＭＯＳＦＥＴの活性領域を取り囲み、ベース領域を貫通してドリフト領域に達する外側トレンチと、外側トレンチの内側にドリフト領域と絶縁された電極と、外側トレンチの底部を中心としたドリフト領域内にドレイン電極又はソース電極又はゲート電極と電気的に接続されていない第２導電型のＰ型フローティング領域を備える。特許文献２の構造を図３で示す。   A trench gate type power MOSFET generally includes a first conductivity type drain region, a first conductivity type drift region formed on the first conductivity type drain region, and a first conductivity type drift region. A second conductive type base region selectively formed on the first conductive type, a first conductive type source region selectively formed on the second conductive type base region, and drift from the source region through the base region A trench reaching the region, a gate electrode formed on the sidewall of the trench facing the base region via an insulating film, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region Is provided. However, in such a trench gate type power MOSFET, since the area where the gate electrode faces the drift region is wide, the capacitance between the gate and the drain increases. As a result, there is a problem that the mirror charging period at the on / off time becomes long, and high-speed switching characteristics cannot be obtained. Thus, in order to reduce the gate-drain capacitance, an example in which a part of the gate electrode in the trench is replaced with an auxiliary electrode having a source potential insulated from the gate electrode, and the area where the drift region and the control electrode face each other is reduced is patented. It is disclosed in Document 1. Further, as an outer peripheral region surrounding the trench gate type power MOSFET, an outer trench that surrounds the active region of the trench gate type power MOSFET and reaches the drift region through the base region as in Patent Document 2, and an inner side of the outer trench And a second conductivity type P-type floating region that is not electrically connected to the drain electrode, the source electrode, or the gate electrode in the drift region centering on the bottom of the outer trench. The structure of Patent Document 2 is shown in FIG.

特許文献２に開示された構造によれば、ベース領域とドリフト領域とのｐｎ接合から拡がった空乏層と、Ｐ型フローティング領域から拡がった空乏層と、を確実に繋げることができる。さらに外側トレンチの底部に配置されたＰ型フローティング領域から拡がる空乏層と、隣の外側トレンチの底部に配置されたＰ型フローティング領域から拡がる空乏層を確実に繋げる事ができる。よって、半導体素子の耐圧を確保することができる。   According to the structure disclosed in Patent Document 2, it is possible to reliably connect the depletion layer extending from the pn junction between the base region and the drift region and the depletion layer extending from the P-type floating region. Furthermore, the depletion layer extending from the P-type floating region disposed at the bottom of the outer trench can be reliably connected to the depletion layer extending from the P-type floating region disposed at the bottom of the adjacent outer trench. Therefore, the breakdown voltage of the semiconductor element can be ensured.

特開２００２−０８３９６３号公報JP 2002-083963 A 特開２００６−１２８５０７号公報JP 2006-128507 A

特許文献２の半導体装置は、外側トレンチの底部を中心にイオン注入で形成したｐ型フローティング領域であるため、隣り合うｐ型フローティング領域から広がる空乏層同士を確実に繋げるためには、外側トレンチの間隔及びｐ型フローティング領域の大きさは制限されるという問題がある。特に、半導体装置のオン抵抗を低減するために、ドリフト領域の不純物濃度を高めた場合、ｐ型フローティング領域からドリフト領域側への空乏層及び外側トレンチからドリフト領域側への空乏層が広がりにくくなるため、上記制限を考慮すると、外周領域の耐圧が十分に得られないという問題があった。   Since the semiconductor device of Patent Document 2 is a p-type floating region formed by ion implantation around the bottom of the outer trench, in order to reliably connect depletion layers extending from adjacent p-type floating regions, There is a problem that the distance and the size of the p-type floating region are limited. In particular, when the impurity concentration of the drift region is increased in order to reduce the on-resistance of the semiconductor device, the depletion layer from the p-type floating region to the drift region side and the depletion layer from the outer trench to the drift region side are difficult to spread. For this reason, in consideration of the above limitation, there has been a problem that the withstand voltage in the outer peripheral region cannot be obtained sufficiently.

本発明は、かかる問題点に鑑みてなされたものであり、上記問題点を解決する発明を提供することを目的とする。   The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

本発明は、上記課題を解決すべく、以下に掲げる構成とした。
本発明の半導体装置は、第1導電型の半導体基板に活性領域と活性領域を囲む外周領域とを含み、外周領域内には、外側トレンチと、外側トレンチ内に配置され、半導体基板と電気的に絶縁された外側電極と、外側トレンチの側面に隣接して形成された第2導電型のフローティング領域とを備えることを特徴とする。 In order to solve the above problems, the present invention has the following configurations.
The semiconductor device of the present invention includes an active region and an outer peripheral region surrounding the active region in a semiconductor substrate of the first conductivity type. The outer region is disposed in the outer trench and in the outer trench, and is electrically connected to the semiconductor substrate. And a second conductivity type floating region formed adjacent to the side surface of the outer trench.

本発明は以上のように構成されているので、外側トレンチ内に配置された外側電極によって外周領域の深さ方向に空乏層を伸ばしつつ、外側トレンチの側面に隣接して形成された第2導電型のフローティング領域によって外周領域の横方向に空乏層を伸ばすことができる。これにより、外側トレンチの間隔及びｐ型フローティング領域の大きさによる制限を解消し、ｐ型フローティング領域とのｐｎ界面及び外側トレンチからドリフト領域側への空乏層の広がりを改善することができ、半導体装置の耐圧を高めることができる。   Since the present invention is configured as described above, the second conductive material formed adjacent to the side surface of the outer trench while extending the depletion layer in the depth direction of the outer peripheral region by the outer electrode disposed in the outer trench. The depletion layer can be extended in the lateral direction of the outer peripheral region by the floating region of the mold. As a result, the limitation due to the interval between the outer trenches and the size of the p-type floating region can be eliminated, and the spread of the depletion layer from the outer trench to the drift region can be improved. The breakdown voltage of the device can be increased.

半導体装置１の断面図である。1 is a cross-sectional view of a semiconductor device 1. FIG. 半導体装置１に所定の電位を印加した場合の電気力線図である。FIG. 3 is an electric force diagram when a predetermined potential is applied to the semiconductor device 1. 従来の半導体装置の断面図である。It is sectional drawing of the conventional semiconductor device.

以下、本発明の実施の形態となる半導体装置について説明する。   Hereinafter, a semiconductor device according to an embodiment of the present invention will be described.

半導体装置１の断面図を図１で示す。この半導体装置１は、シリコンで構成された半導体基板２に形成されたトレンチゲート型の素子部（活性領域）２００を含む。この半導体基板２においては、ドレイン領域となるN＋層１０の上に、ドリフト領域となるｎ−層２０、ベース領域となるｐ−層３０が順次形成されている。半導体基板２の表面側には、ｐ−層３０を貫通する溝（トレンチ）１００が形成されている。溝１００は、図１における紙面と垂直方向に延伸して並行に複数形成されており、図１には半導体装置１の一部の断面のみが示されている。   A cross-sectional view of the semiconductor device 1 is shown in FIG. The semiconductor device 1 includes a trench gate type element (active region) 200 formed in a semiconductor substrate 2 made of silicon. In this semiconductor substrate 2, an n− layer 20 serving as a drift region and a p− layer 30 serving as a base region are sequentially formed on an N + layer 10 serving as a drain region. On the surface side of the semiconductor substrate 2, a groove (trench) 100 penetrating the p− layer 30 is formed. A plurality of grooves 100 are formed in parallel to extend in the direction perpendicular to the paper surface in FIG. 1, and FIG. 1 shows only a partial cross section of the semiconductor device 1.

半導体基板２の表面側の溝１００の両側に、ソース領域となるｎ＋層４０が形成されている。溝１００の内面（側面及び底面）には絶縁膜７１が形成されている。   On both sides of the groove 100 on the surface side of the semiconductor substrate 2, n + layers 40 serving as source regions are formed. An insulating film 71 is formed on the inner surface (side surface and bottom surface) of the groove 100.

まず、ゲート電極６０は、ｐ−層３０と対向するように設けられている。ゲート電極６０は、例えば高濃度にドープされた導電性の多結晶シリコンで構成される。ゲート電極６０は図１のように溝１００内に１つずつ配置しても良い。また、溝１００の左右の側壁部に左右のゲート電極６０が設けても良い。この場合、溝１００の左右の側壁部に設けられた左右のゲート電極６０は、図示しないゲートバスライン等を介して電気的に接続されている。
First, the gate electrode 60 is provided so as to face the p− layer 30. The gate electrode 60 is made of, for example, conductive polycrystalline silicon doped at a high concentration. The gate electrodes 60 may be arranged one by one in the trench 100 as shown in FIG. The left and right gate electrodes 60 may be provided on the left and right side wall portions of the trench 100. In this case, the left and right gate electrodes 60 provided on the left and right side wall portions of the trench 100 are electrically connected via a gate bus line or the like (not shown).

ゲート電極６０の下にはゲート電極６０と分離（絶縁）された補助電極５０が形成されている。溝１００の底面においても絶縁膜７０が形成されているため、補助電極５０はその下のｎ−層２０とも絶縁される。補助電極５０とゲート電極６０間には、絶縁膜７０が形成され、補助電極５０とゲート電極６０とは絶縁されている。   Under the gate electrode 60, an auxiliary electrode 50 separated (insulated) from the gate electrode 60 is formed. Since the insulating film 70 is also formed on the bottom surface of the groove 100, the auxiliary electrode 50 is also insulated from the n − layer 20 below it. An insulating film 70 is formed between the auxiliary electrode 50 and the gate electrode 60, and the auxiliary electrode 50 and the gate electrode 60 are insulated.

半導体基板２の表面上に、ソース電極（第１の主電極）８０が形成されており、ソース電極８０は半導体基板２の表面においてｎ＋層４０と接続される。ソース電極８０とゲート電極６０との間に絶縁膜７０が設けられている。上記の構成により、ゲート電極６０上の絶縁膜７０により、ソース電極８０とゲート電極６０とは絶縁される。一方、半導体基板２の裏面全面には、Ｎ＋層（ドレイン領域）１０と電気的に接続されるドレイン電極（第２の主電極）９０が形成されている。   A source electrode (first main electrode) 80 is formed on the surface of the semiconductor substrate 2, and the source electrode 80 is connected to the n + layer 40 on the surface of the semiconductor substrate 2. An insulating film 70 is provided between the source electrode 80 and the gate electrode 60. With the above configuration, the source electrode 80 and the gate electrode 60 are insulated by the insulating film 70 on the gate electrode 60. On the other hand, a drain electrode (second main electrode) 90 electrically connected to the N + layer (drain region) 10 is formed on the entire back surface of the semiconductor substrate 2.

この構造においては、ゲート電極６０が溝１００の底面側に形成されず、溝１００の底部には補助電極５０がソース電極８０と同電位（接地電位）となるよう配置されているため、ゲート・ドレイン間の容量Ｃｇｄ（帰還容量）が低減される。   In this structure, the gate electrode 60 is not formed on the bottom surface side of the groove 100, and the auxiliary electrode 50 is disposed at the bottom of the groove 100 so as to have the same potential (ground potential) as the source electrode 80. The capacitance Cgd (feedback capacitance) between the drains is reduced.

また、補助電極５０をゲート電極６０よりも下側に配置しているので、補助電極５０によって溝２４の底部及び側面からｎ−層２０側に空乏層が良好に広がり、耐圧を向上させることが可能である。   Further, since the auxiliary electrode 50 is disposed below the gate electrode 60, the depletion layer can be satisfactorily spread from the bottom and side surfaces of the groove 24 to the n− layer 20 side by the auxiliary electrode 50, thereby improving the breakdown voltage. Is possible.

活性領域２００の外側には外周領域３００が形成されている。外周領域３００には、ｐ−層３０が設けられておらず、半導体基板２の上面はｎ−層２０となっている。また、外周領域３００には、底部がｎ−層２０に達する複数の離間した外側トレンチ１１０を備える。外側トレンチ１１０の底部及び側面にも溝１００と同じように絶縁膜が設けられている。外側トレンチ１１０の側壁におけるこの絶縁膜の厚みは、溝１００の側壁とゲート電極６０との間に挟まれた絶縁膜７０の厚みよりも厚く形成されている。この絶縁膜を介して外側トレンチ１１０の内側には高濃度にドープされた導電性の多結晶シリコンで形成された外側電極１２０が配置されている。外側電極１２０はソース電極８０と電気的に接続されているか、又はドレイン電極９０・ソース電極８０・ゲート電極６０の何れにも電気的に接続されていないフローティング電位となっている。図１において、複数（７個）の外側電極１２０のうち、内側の４個をソース電極８０と電気的に接続し、外側の３個をフローティング電位となっている。   An outer peripheral region 300 is formed outside the active region 200. In the outer peripheral region 300, the p− layer 30 is not provided, and the upper surface of the semiconductor substrate 2 is the n− layer 20. Further, the outer peripheral region 300 includes a plurality of spaced outer trenches 110 whose bottom reaches the n− layer 20. An insulating film is provided on the bottom and side surfaces of the outer trench 110 in the same manner as the groove 100. The thickness of the insulating film on the side wall of the outer trench 110 is formed to be thicker than the thickness of the insulating film 70 sandwiched between the side wall of the trench 100 and the gate electrode 60. An outer electrode 120 made of conductive polycrystalline silicon doped at a high concentration is disposed inside the outer trench 110 via the insulating film. The outer electrode 120 has a floating potential that is electrically connected to the source electrode 80 or is not electrically connected to any of the drain electrode 90, the source electrode 80, and the gate electrode 60. In FIG. 1, among a plurality (seven) of outer electrodes 120, the inner four are electrically connected to the source electrode 80, and the outer three are at a floating potential.

複数の外側トレンチ１１０のうち、外側の外側トレンチ１１０の上方に周知のフィールドプレート電極１３０が外側トレンチ１１０の開口部から外側に向かって延びるように形成されている。外側トレンチ１１０の開口部から延伸しているフィールドプレート電極１３０はその開口部を介して外側トレンチ１１０内に配置された外側電極１２０と電気的に接続されている。図１の半導体装置１において、フィールドプレート電極１３０はソース電極８０と電気的に接続した外側電極１２０のうち最も外側の外側電極１２０と、その外側に配置されたフローティング電位となっている3個の外側電極１２０上に各々配置されている。   Of the plurality of outer trenches 110, a known field plate electrode 130 is formed above the outer outer trench 110 so as to extend outward from the opening of the outer trench 110. The field plate electrode 130 extending from the opening of the outer trench 110 is electrically connected to the outer electrode 120 disposed in the outer trench 110 through the opening. In the semiconductor device 1 of FIG. 1, the field plate electrode 130 includes the outermost outer electrode 120 out of the outer electrodes 120 electrically connected to the source electrode 80, and three floating potentials arranged outside the outer electrode 120. Each is disposed on the outer electrode 120.

外側トレンチ１２０の側面のｎ−層２０内にはｐ−型のフローティング領域１４０が形成されている。フローティング領域１４０の不純物濃度は、ソース電極８０とドレイン電極９０に所定の電位が印加された半導体装置１のオフ時にフローティング領域１４０が完全空乏化しない程度に、ｐ−層３０の不純物濃度よりも小さい。図１のように外側トレンチ１１０が複数形成されている場合、フローティング領域１４０は隣り合う外側トレンチ１１０間を繋ぐように、一方の外側トレンチ１１０の側面から他方の外側トレンチ１２０の側面へと延伸して配置されている。ここで、外側トレンチ１１０間のフローティング領域１４０は、外側トレンチ１１０の側壁に接する部分の厚みよりもその外側トレンチ１２０の側壁から隣り合う外側トレンチ１１０との間（隣り合う外側トレンチ１１０間）の領域における厚みの方が大きくしても良い。例えば、図１の半導体装置１のように、ある箇所を中心として拡散されて広がっているようなドット状のフローティング領域１４０となっている。隣り合う外側トレンチ１１０間の上記箇所で最も不純物濃度が高く、外側トレンチの側壁側で不純物濃度が低くなるように形成されている。図１の半導体装置において、上記箇所の高さは全てのフローティング領域１４０において同じ高さとなるように形成されているが、フローティング領域１４０の中心の位置は異なる高さであっても良い。   A p − type floating region 140 is formed in the n − layer 20 on the side surface of the outer trench 120. The impurity concentration of the floating region 140 is smaller than the impurity concentration of the p− layer 30 to such an extent that the floating region 140 is not fully depleted when the semiconductor device 1 to which a predetermined potential is applied to the source electrode 80 and the drain electrode 90 is turned off. . When a plurality of outer trenches 110 are formed as shown in FIG. 1, the floating region 140 extends from the side surface of one outer trench 110 to the side surface of the other outer trench 120 so as to connect adjacent outer trenches 110. Are arranged. Here, the floating region 140 between the outer trenches 110 is a region between the side wall of the outer trench 120 and the adjacent outer trench 110 (between adjacent outer trenches 110) rather than the thickness of the portion in contact with the side wall of the outer trench 110. The thickness at may be larger. For example, like the semiconductor device 1 of FIG. 1, the dot-shaped floating region 140 is spread and spread around a certain portion. It is formed so that the impurity concentration is highest at the above-mentioned location between the adjacent outer trenches 110 and the impurity concentration is lower on the side wall side of the outer trench. In the semiconductor device of FIG. 1, the height of the above portion is formed to be the same in all the floating regions 140, but the center position of the floating region 140 may be different.

半導体装置１にドレイン電極９０とソース電極８０との間に所定の電位を与え、半導体装置１がオフとなっている時、半導体装置１における等電位線を図２の一点斜線で示す。図２で示すように、フローティング領域１４０の底部とｎ−層２０とのｐｎ接合界面から空乏層が広がり、フローティング領域１４０の上部とｎ−層２０とのｐｎ接合界面からも空乏層が広がる。また、ｎ−層２０とフィールドプレート電極１３０との間の絶縁膜との界面からも空乏層が広がる。これらによって、外周領域３００において空乏層が横方向に良好に広がる。
更に、ｎ−層２０と外側電極１２０との間の絶縁膜との界面から空乏層が広がり、外周領域３００において空乏層が縦方向（半導体基板２の厚み方向）に良好に広がる。
これらの空乏層の広がりによって、図２で示すようになだらかな等電位線となる。従って、外周領域３００における電界集中を緩和し、半導体装置１の耐圧を向上することができる。 When a predetermined potential is applied to the semiconductor device 1 between the drain electrode 90 and the source electrode 80 and the semiconductor device 1 is turned off, equipotential lines in the semiconductor device 1 are indicated by one-dotted diagonal lines in FIG. As shown in FIG. 2, the depletion layer extends from the pn junction interface between the bottom of the floating region 140 and the n − layer 20, and the depletion layer also extends from the pn junction interface between the upper portion of the floating region 140 and the n − layer 20. A depletion layer also extends from the interface between the n − layer 20 and the field plate electrode 130 and the insulating film. As a result, the depletion layer spreads well in the lateral direction in the outer peripheral region 300.
Furthermore, a depletion layer spreads from the interface between the n− layer 20 and the insulating film between the outer electrode 120, and the depletion layer spreads well in the vertical direction (thickness direction of the semiconductor substrate 2) in the outer peripheral region 300.
Due to the spread of these depletion layers, it becomes a gentle equipotential line as shown in FIG. Therefore, the electric field concentration in the outer peripheral region 300 can be relaxed and the breakdown voltage of the semiconductor device 1 can be improved.

フローティング領域１４０の上面の高さはｐ−層３０の底部の高さよりも下方にある事が望ましい。さらに、その場合、半導体基板２の内側のフローティング領域１４０（図１の紙面から見て左側のフローティング領域１４０）は、外側トレンチ１２０の底部の角部を含むように形成されていることが望ましい。更に、図１のように、図１の紙面から見て左側のフローティング領域１４０は図１の紙面から見て右側のフローティング領域１４０よりも深くなっており、半導体装置１の外周側（図１の紙面から見て右側）ほど浅くなっていることが望ましい。また、外側に向かって（図１の紙面から見て右側に向かって）フローティング領域１４０の厚みが小さくなり、また外側に向かってフローティング領域の不純物濃度が下がっていくことが望ましい。これらによって、半導体装置１の外側に向かう等電位線を更になだらかにすることができ、半導体装置１の耐圧を更に向上することができる。   The height of the upper surface of the floating region 140 is preferably lower than the height of the bottom of the p− layer 30. Furthermore, in that case, it is desirable that the floating region 140 inside the semiconductor substrate 2 (the floating region 140 on the left side when viewed from the paper in FIG. 1) is formed so as to include the corners at the bottom of the outer trench 120. Further, as shown in FIG. 1, the left floating region 140 when viewed from the plane of FIG. 1 is deeper than the right floating region 140 when viewed from the plane of FIG. It is desirable that it is shallower as viewed from the right side of the page. Further, it is desirable that the thickness of the floating region 140 decreases toward the outside (toward the right side when viewed from the paper of FIG. 1), and the impurity concentration of the floating region decreases toward the outside. As a result, the equipotential lines directed to the outside of the semiconductor device 1 can be further smoothed, and the breakdown voltage of the semiconductor device 1 can be further improved.

また、最も外側にあるフローティング領域１４０の幅はその厚みよりも大きく、横方向に長いフローティング領域１４０である事が望ましい。
また、最も外側にあるフローティング領域１４０はフィールドプレート電極１３０よりも外側まで延伸していることが望ましい。下方に設けられたフローティング領域１４０と上方に設けられたフィールドプレート電極１３０の両方の効果によって、最も外側の外側トレンチ１１０の側面及び角部における電界集中を緩和し、半導体装置１の耐圧を更に向上することができる。 In addition, the width of the outermost floating region 140 is preferably larger than the thickness of the floating region 140 and long in the lateral direction.
Further, it is desirable that the outermost floating region 140 extends to the outside of the field plate electrode 130. By the effect of both the floating region 140 provided below and the field plate electrode 130 provided above, the electric field concentration on the side surface and corners of the outermost outer trench 110 is alleviated and the breakdown voltage of the semiconductor device 1 is further improved. can do.

なお、上記において、活性領域２００の素子構造がトレンチゲート型のパワーＭＯＳＦＥＴであるものとしたが、ＩＧＢＴや図１以外のトレンチ内の電極構造を備えるＭＯＳＦＥＴ等のトレンチゲート型の素子を活性領域２００に備える場合においても同様の構造を用いることができる。また、プレーナ型の素子構造においても同様の構造を用いることができる。   In the above description, the element structure of the active region 200 is a trench gate type power MOSFET. However, a trench gate type element such as an IGBT or a MOSFET having an electrode structure in a trench other than that shown in FIG. A similar structure can also be used in the case of preparing for. A similar structure can also be used for a planar element structure.

また、上記の構成は、いずれもｎチャネル型の素子であったが、導電型（ｐ型、ｎ型）を逆転させ、ｐチャネル型の素子を同様に得ることができることは明らかである。この場合、図１に示されたアクセプタ濃度は、ｐ−層２３に対応するｎ−層におけるドナー濃度となる。また、半導体基板、ゲート電極等を構成する材料によらずに、上記の構造、製造方法を実現することができ、同様の効果を奏することも明らかである。   In addition, each of the above configurations is an n-channel element, but it is apparent that a p-channel element can be similarly obtained by reversing the conductivity type (p-type and n-type). In this case, the acceptor concentration shown in FIG. 1 is the donor concentration in the n− layer corresponding to the p− layer 23. In addition, it is obvious that the above-described structure and manufacturing method can be realized without depending on the material constituting the semiconductor substrate, the gate electrode, and the like, and the same effect can be obtained.

１ 半導体装置
２ 半導体基板
１０ N＋層
２０ ｎ−層
３０ ｐ―層
４０ ｎ＋層
５０ 補助電極
６０ ゲート電極
７０ 層間絶縁膜
８０ ソース電極（第１の主電極）
９０ ドレイン電極（第２の主電極）
１００ 溝
１１０ 外側トレンチ
１２０ 外側電極
１３０ フィールドプレート電極
１４０ フローティング領域 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 10 N + layer 20 n− layer 30 p− layer 40 n + layer 50 Auxiliary electrode 60 Gate electrode 70 Interlayer insulating film 80 Source electrode (first main electrode)
90 Drain electrode (second main electrode)
100 groove 110 outer trench 120 outer electrode 130 field plate electrode 140 floating region

Claims (6)

第1導電型の半導体基板に活性領域と活性領域を囲む外周領域とを含み、
前記外周領域内には、
外側トレンチと、
前記外側トレンチ内に配置され、前記半導体基板と電気的に絶縁された外側電極と、
前記外側トレンチの側面に隣接して形成された第2導電型のフローティング領域とを備えることを特徴とする半導体装置。 The first conductivity type semiconductor substrate includes an active region and an outer peripheral region surrounding the active region,
In the outer peripheral area,
An outer trench,
An outer electrode disposed in the outer trench and electrically insulated from the semiconductor substrate;
And a second conductivity type floating region formed adjacent to a side surface of the outer trench. 前記外側トレンチの側壁に接する前記フローティング領域の厚みより前記外側トレンチの側壁から離間した領域における前記フローティング領域の厚みが大きいことを特徴とする請求項１の半導体装置。   2. The semiconductor device according to claim 1, wherein a thickness of the floating region in a region spaced apart from the side wall of the outer trench is larger than a thickness of the floating region in contact with the side wall of the outer trench. 前記フローティング領域の上面は前記半導体基板の上面に達しておらず、
前記半導体基板上を前記外側トレンチよりも外側へ延伸するように、前記電極と電気的に接続されたフィールドプレートとを備えることを特徴とする請求項１又は２の半導体装置。 The upper surface of the floating region does not reach the upper surface of the semiconductor substrate,
3. The semiconductor device according to claim 1, further comprising a field plate electrically connected to the electrode so as to extend outward from the outer trench on the semiconductor substrate. 前記半導体基板上を前記外側トレンチよりも外側へ延伸するように、前記電極と電気的に接続されたフィールドプレートを更に備え、
前記フローティング領域は前記フィールドプレートよりも外側へ延伸することを特徴とする請求項１又は２の半導体装置。 A field plate electrically connected to the electrode so as to extend outward from the outer trench on the semiconductor substrate;
The semiconductor device according to claim 1, wherein the floating region extends outward from the field plate. 前記外側トレンチは複数離間して設けられており、
前記外側トレンチ間の各々には前記埋め込み層が配置されており、
前記半導体基板を上方から見て内側にある前記外側トレンチ間の前記埋め込み層の不純物濃度の最大値は、外側にある前記外側トレンチ間の前記埋め込み層の不純物濃度の最大値よりも高いことを特徴とする請求項１〜４何れか１項に記載の半導体装置。 A plurality of outer trenches are provided apart from each other;
The buried layer is disposed between each of the outer trenches,
The maximum value of the impurity concentration of the buried layer between the outer trenches located on the inner side when the semiconductor substrate is viewed from above is higher than the maximum value of the impurity concentration of the buried layer between the outer trenches located on the outer side. The semiconductor device according to any one of claims 1 to 4. 前記電極はフローティング電位又はソース電極と電気的に接続された電位であることを特徴とする請求項１〜５何れか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the electrode is a floating potential or a potential electrically connected to a source electrode.
JP2015159734A 2015-08-12 2015-08-12 Semiconductor device Active JP6573107B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015159734A JP6573107B2 (en) 2015-08-12 2015-08-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015159734A JP6573107B2 (en) 2015-08-12 2015-08-12 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2017038016A true JP2017038016A (en) 2017-02-16
JP6573107B2 JP6573107B2 (en) 2019-09-11

Family

ID=58049326

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015159734A Active JP6573107B2 (en) 2015-08-12 2015-08-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JP6573107B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110838486A (en) * 2018-08-17 2020-02-25 力智电子股份有限公司 Power transistor element
CN113937149A (en) * 2020-07-13 2022-01-14 苏州东微半导体股份有限公司 Terminal structure of semiconductor power device and manufacturing method thereof
WO2022162894A1 (en) * 2021-01-29 2022-08-04 サンケン電気株式会社 Semiconductor device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283754A (en) * 1996-04-16 1997-10-31 Toshiba Corp High withstand voltage semiconductor device
JPH1187698A (en) * 1997-09-02 1999-03-30 Kansai Electric Power Co Inc:The Semiconductor device having high breakdown strength and power converter employing the same
JP2007123570A (en) * 2005-10-28 2007-05-17 Toyota Industries Corp Semiconductor device
JP2008004643A (en) * 2006-06-20 2008-01-10 Toshiba Corp Semiconductor device
JP2011512676A (en) * 2008-02-14 2011-04-21 マックスパワー・セミコンダクター・インコーポレイテッド Edge termination for improved breakdown voltage
JP2013069866A (en) * 2011-09-22 2013-04-18 Toshiba Corp Semiconductor device
US20150162410A1 (en) * 2011-08-25 2015-06-11 Karthik Padmanabhan Termination design by metal strapping guard ring trenches shorted to a body region to shrink termination area
WO2015098169A1 (en) * 2013-12-26 2015-07-02 トヨタ自動車株式会社 Semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283754A (en) * 1996-04-16 1997-10-31 Toshiba Corp High withstand voltage semiconductor device
JPH1187698A (en) * 1997-09-02 1999-03-30 Kansai Electric Power Co Inc:The Semiconductor device having high breakdown strength and power converter employing the same
JP2007123570A (en) * 2005-10-28 2007-05-17 Toyota Industries Corp Semiconductor device
JP2008004643A (en) * 2006-06-20 2008-01-10 Toshiba Corp Semiconductor device
JP2011512676A (en) * 2008-02-14 2011-04-21 マックスパワー・セミコンダクター・インコーポレイテッド Edge termination for improved breakdown voltage
US20150162410A1 (en) * 2011-08-25 2015-06-11 Karthik Padmanabhan Termination design by metal strapping guard ring trenches shorted to a body region to shrink termination area
JP2013069866A (en) * 2011-09-22 2013-04-18 Toshiba Corp Semiconductor device
WO2015098169A1 (en) * 2013-12-26 2015-07-02 トヨタ自動車株式会社 Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110838486A (en) * 2018-08-17 2020-02-25 力智电子股份有限公司 Power transistor element
CN110838486B (en) * 2018-08-17 2023-04-07 力智电子股份有限公司 Power transistor element
CN113937149A (en) * 2020-07-13 2022-01-14 苏州东微半导体股份有限公司 Terminal structure of semiconductor power device and manufacturing method thereof
WO2022162894A1 (en) * 2021-01-29 2022-08-04 サンケン電気株式会社 Semiconductor device

Also Published As

Publication number Publication date
JP6573107B2 (en) 2019-09-11

Similar Documents

Publication Publication Date Title
US7936013B2 (en) Charge balance techniques for power devices
KR101864889B1 (en) Lateral DMOS transistor and method of fabricating the same
JP5136578B2 (en) Semiconductor device
US20190097005A1 (en) Semiconductor Device Having Termination Trench
JP5833277B1 (en) Semiconductor device
US9818743B2 (en) Power semiconductor device with contiguous gate trenches and offset source trenches
JP2011233701A (en) Power semiconductor device
JP2013069866A (en) Semiconductor device
CN107919383B (en) Switching element
JP6573107B2 (en) Semiconductor device
JP6624370B2 (en) Semiconductor device
JP5694285B2 (en) Semiconductor device
US9704954B2 (en) Semiconductor device and a method for forming a semiconductor device
JP6381101B2 (en) Silicon carbide semiconductor device
JP2017098385A (en) Semiconductor device
JP6458994B2 (en) Semiconductor device
JP6758592B2 (en) Semiconductor device
KR20150142220A (en) Power semiconductor device
CN112889158B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
JP2016072532A (en) Semiconductor element
JP7230477B2 (en) Manufacturing method of trench gate type switching element
JP7326991B2 (en) switching element
JP4846400B2 (en) Semiconductor device
TWI577020B (en) High voltage metal-oxide-semiconductor transistor device
JP6536814B2 (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180606

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190304

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190307

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190417

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20190718

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20190731

R150 Certificate of patent or registration of utility model

Ref document number: 6573107

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250