JP6624370B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a switching element for performing a switching operation and an outer peripheral structure outside the switching element.

  As a switching element (power semiconductor element) that performs a switching operation of a large current, a trench gate type power MOSFET is widely used.

  Trench gate type power MOSFETs generally include a first conductivity type drain region, a first conductivity type drift region formed on the first conductivity type drain region, and a first conductivity type drift region. A base region of the second conductivity type selectively formed on the base region, a source region of the first conductivity type selectively formed on the base region of the second conductivity type, and drift from the source region through the base region. A groove reaching the region, a gate electrode formed on the side wall of the groove facing the base region via an insulating film, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region. Is provided.

  However, in such a trench gate type power MOSFET, since the area where the gate electrode faces the drift region is large, the capacitance between the gate and the drain increases. As a result, there is a problem that the mirror charging period at the time of ON / OFF becomes longer and high-speed switching characteristics cannot be obtained.

  Therefore, in order to reduce the gate-drain capacitance, a part of the gate electrode in the trench is replaced with an auxiliary electrode of source potential insulated from the gate electrode, and the area where the drift region and the control electrode face each other is reduced. It is disclosed in Reference 1.

  Further, as an outer region outside the trench gate type power MOSFET, as shown in Patent Document 2, an outer trench reaching the drift region through the P-type region outside the trench gate type device, and a drift inside the outer trench. A region and a conductor provided via an insulating film. The conductor has a floating potential which is not electrically connected to the drain electrode, the source electrode, or the gate electrode. The structure of Patent Document 2 is shown in FIG.

  According to the structure disclosed in Patent Literature 2, the conductors in the outer trenches are capacitively coupled to each other via the insulating film. Therefore, the potential increases for each outer trench as the distance from the active region increases. Therefore, by dividing the potential applied between the drain and the source for each outer trench, the withstand voltage of the outer region of the semiconductor device can be ensured.

JP-A-2002-083963 Republished WO2011 / 024842

  In the semiconductor device of Patent Document 2, since the conductor closest to the active region has a floating potential, the depletion layer in the edge region near the active region cannot be made gentle, and the trench in the outermost trench in the active region cannot There is a problem that a sufficient withstand voltage cannot be obtained.

  The present invention has been made in view of the above problems, and has as its object to provide an invention that solves the above problems.

The present invention has the following configurations in order to solve the above problems.
The semiconductor device of the present invention
In a semiconductor device having an active region and an edge region outside the active region,
The active region includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type opposite to the first conductivity type on the first semiconductor region, and a first semiconductor region on the second semiconductor region. A conductive third semiconductor region, a control electrode disposed on the second semiconductor region via a gate insulating film, a first main electrode electrically connected to the third semiconductor region, and a first semiconductor region. A second main electrode disposed on the side,
The edge region is provided with a first edge trench dug in the thickness direction of the first conductivity type semiconductor region, and provided outside the first edge trench, and is dug in the thickness direction of the first conductivity type semiconductor region. A second edge trench, a first conductor electrically connected to the first main electrode via an insulating film on the wall surface of the first edge trench, and an insulating film on the wall surface of the second edge trench. look including a second conductor of the floating potential through,
A plurality of first and second edge trenches are arranged, and the width of the semiconductor region sandwiched between the second edge trenches is wider than the width of the semiconductor region sandwiched between the first edge trenches. And

  Since the present invention is configured as described above, the conductor closest to the active region has the source potential, so that the depletion layer from the active region to the edge region can be made gentle, and the conductor of the source potential has Since the conductor in the outer region has a floating potential, the depletion layer from the active region to the edge region can be made gentler than before. As a result, the withstand voltage of the semiconductor device can be increased.

FIG. 2 is a cross-sectional view of the semiconductor device 1. FIG. 4 is an electric line diagram when a predetermined potential is applied to the semiconductor device 1. FIG. 2 is a plan view of the semiconductor device 1. FIG. 14 is a cross-sectional view of a conventional semiconductor device.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described.

  A cross-sectional view of the semiconductor device 1 is shown in FIG. The semiconductor device 1 includes a trench gate type element portion (active region) 200 formed in a semiconductor substrate 2 made of silicon. In the semiconductor substrate 2, an n − layer (first semiconductor region) 20 as a drift region and ap − layer (second semiconductor region) 30 as a base region are formed on the N + layer 10 as a drain region. They are formed sequentially. A groove (gate trench) 100 is formed on the front surface side of the semiconductor substrate 2, penetrating the p − layer 30 and reaching the n − layer at the bottom. The grooves 100 extend in a direction perpendicular to the paper surface of FIG. 1 and are formed in parallel as shown in the plan view of FIG.

  On both sides of the groove 100 on the surface side of the semiconductor substrate 2, n + layers 40 serving as source regions are formed. An insulating film 70 is formed on the inner surface (side surface and bottom surface) of the groove 100.

  First, the gate electrode 60 is provided so as to face the p − layer 30 via the insulating film 70. The gate electrode 60 is made of, for example, highly doped conductive polycrystalline silicon. The gate electrodes 60 may be arranged one by one in the groove 100 as shown in FIG. 1, or the left and right gate electrodes 60 may be provided on the left and right side walls of the groove 100. In this case, each of the left and right gate electrodes 60 is electrically connected.

  An auxiliary electrode 50 separated (insulated) from the gate electrode 60 is formed below the gate electrode 60. Since the insulating film 70 is also formed on the bottom surface of the groove 100, the auxiliary electrode 50 is also insulated from the n − layer 20 thereunder. An insulating film 70 is formed between the auxiliary electrode 50 and the gate electrode 60.

  A source electrode (first main electrode) 80 is formed on the surface of the semiconductor substrate 2, and the source electrode 80 is connected to the n + layer 40 on the surface of the semiconductor substrate 2. The source electrode 80 and the gate electrode 60 are insulated. Note that the source electrode 80 may be connected to the p − layer 30 as well. On the entire back surface of the semiconductor substrate 2, a drain electrode (second main electrode) 90 electrically connected to the N + layer (drain region) 10 is formed.

  In this structure, the gate electrode 60 is not formed on the bottom surface side of the groove 100, and the auxiliary electrode 50 is arranged at the bottom of the groove 100 so as to have the same potential (ground potential) as the source electrode 80. The capacitance Cgd (feedback capacitance) between the drains is reduced.

  Further, since the auxiliary electrode 50 is disposed below the gate electrode 60, the depletion layer can be favorably spread from the bottom and side surfaces of the groove 24 to the n − layer 20 side by the auxiliary electrode 50, and the breakdown voltage can be improved. It is possible.

  An edge region 300 is formed outside the active region 200. In the edge region 300, the n + layer 40 is not provided, and the edge region 300 is a region that does not function as a transistor. The edge region 300 includes one or more first and second edge trenches 110 and 210 that are dug from the surface of the semiconductor substrate 2 in the thickness direction of the n − layer 20 and are separated from each other. The second edge trench 210 is a trench provided outside the first edge trench 110. In the semiconductor device of FIG. 1, four first edge trenches 110 and three second edge trenches 210 are provided.

  When the first and second edge trenches 110 and 210 are viewed in a plan view, they are arranged as shown in FIG. The first edge trench 110 closest to the active region 200 is provided in parallel with the groove 100, and the other first edge trench 110 and second edge trench 210 are the first edge trench closest to the active region 200. It is formed outside the active region 200 so as to surround the groove 110 and the groove 110.

  An insulating film is provided on the bottom and side surfaces of the first and second edge trenches 110 and 210 in the same manner as the groove 100. Edge electrodes 120 and 220 made of highly doped conductive polycrystalline silicon are arranged inside the first and second edge trenches 110 and 210 with the insulating film interposed therebetween. The edge electrode 120 is electrically connected to the source electrode 80, and the edge electrode 220 has a floating potential that is not electrically connected to the drain electrode 90, the source electrode 80, or the gate electrode 60.

  In the semiconductor device 1 of FIG. 1, at least above the outermost first edge trench 110, a well-known field plate electrode 130 is formed so as to extend outward from the opening of the first edge trench 110. I have. The field plate electrode 130 extending from the opening of the first edge trench 110 is electrically connected to the edge electrode 120 disposed in the first edge trench 110 via the opening of the first edge trench 110. Have been.

  A well-known field plate electrode 130 is formed above the second edge trench 210 so as to extend outward from the opening of the second edge trench 210. The field plate electrode 130 extending from the opening of the second edge trench 210 is electrically connected to the edge electrode 220 disposed in the second edge trench 210 via the opening of the second edge trench 210. Have been. Although the field plate electrode 130 is provided above all the second edge trenches 210 in the semiconductor device 1 of FIG. 1, the field plate electrode 130 may not be provided above all the second edge trenches 210. good.

  A region of the semiconductor body 2 (n-layer 20) sandwiched between the outermost first edge trench 110 and the second edge trench 210, and sandwiched between adjacent second edge trenches 210 In the region of the semiconductor substrate 2 (n− layer 20), a p− type floating region 140 is embedded in the n− layer 20, and the surface of the semiconductor substrate 2 is the n− layer 20. As can be seen from FIG. 3, the floating region 140 is formed so as to surround the active region 200, and is separated from the inner and outer floating regions 140 by edge trenches at least when viewed from the upper surface of the substrate 2. The impurity concentration of floating region 140 is lower than the impurity concentration of p − layer 30 such that floating region 140 is not completely depleted when semiconductor device 1 with a predetermined potential applied to source electrode 80 and drain electrode 90 is turned off. .

  In addition, any of the floating regions 140 between the adjacent first edge trenches 110, between the adjacent second edge trenches 210, and between the first edge trenches 110 and the second edge trenches 210, The thickness in the region between the side wall of the outer trench 120 and the adjacent outer trench 110 (between the adjacent outer trenches 110) may be larger than the thickness of the portion in contact with the side wall. As in the semiconductor device 1 of FIG. 1, the impurity concentration may be the highest at the point between the adjacent outer trenches 110 and the impurity concentration may be lower on the side walls of the outer trenches. What is necessary is just to be provided so that the side which connects may be provided.

A predetermined potential is applied between the drain electrode 90 and the source electrode 80 to the semiconductor device 1, and the semiconductor device 1 is turned off. Equipotential lines in the semiconductor device 1 when turned off are shown by hatched lines in FIG.
As shown in FIG. 2, the depletion layer extends from the pn junction interface between the bottom of floating region 140 and n − layer 20, and the depletion layer also extends from the pn junction interface between the upper portion of floating region 140 and n − layer 20.
a depletion layer extending from the interface between the n − layer 20 and the insulating film between the edge electrodes 120 and 220 in the first edge trench 110 and the second edge trench 210, and the n − layer 20 and the field plate electrode 130. Are connected to the depletion layer extending from the interface with the insulating film between them, thereby forming an equipotential line as shown in FIG.

  Since the depth of the depletion layer below the edge electrode 120 in the first edge trench 110 is connected to the source electrode 80, the depth of the depletion layer is almost the same as the depth of the depletion layer spread by the auxiliary electrode 50 in the active region. Therefore, the depletion layer below the edge electrode 120 in the edge region 300 can be made flatter than before. Therefore, in the conventional semiconductor device, the depletion layer becomes close to the corner of the outermost groove 100 of the active region 200, and a breakdown occurs near the corner. The problem can be suppressed because the edge electrode 120 in the edge trench 110 is electrically connected to the source electrode.

  Further, the wall surface of the first edge trench 110 and the wall surface of the second edge trench 210 are arranged so as to sandwich the p − type floating region 140. Therefore, the insulating film on the wall of the trench is formed between the edge electrode 120 in the first edge trench 110 and the p − type floating region 140 and between the edge electrode 220 in the second edge trench 210 and the p − type floating region 140. Through capacitive coupling. The edge electrode 220 in the second edge trench 210 has a floating potential, and the second edge trench 210 is arranged so as to sandwich the p − type floating region 140. Therefore, the edge electrode 220 in the edge trench 210 and the floating region 140 are capacitively coupled via the insulating film on the wall surface of the edge trench 210.

Therefore, the edge electrode 140 in the outermost first edge trench 110 to the edge electrode 220 in the outer edge trench and the floating region 140 share the potential difference between the drain and the source by capacitive coupling. The shared potential is generated in the edge electrode 220 and the floating region 140. Therefore, the equipotential lines toward the outside of the semiconductor device 1 can be made gentle, and the withstand voltage of the semiconductor device 1 can be further improved.
Here, the width of the semiconductor region (n− layer 20) sandwiched between the outermost first edge trench 110 and the innermost second edge trench 210, and / or the width of the semiconductor region (n− layer 20) sandwiched between the second edge trenches 210. It is desirable that the width of the semiconductor region (n− layer 20) formed is larger than the width of the semiconductor region (n− layer 20) interposed between the first edge trenches 110. Thus, the breakdown voltage of the semiconductor device 1 can be further improved by moving the high-potential region outward to make the depletion layer on the active region side of the edge region gentle.

  In the semiconductor device 1, the floating region 140 is not exposed on the surface of the semiconductor substrate 2. If mobile ions, negative ions, or moisture enter the oxide film surface on the outer peripheral structure surface, even if a positive charge is induced on the surface of the semiconductor substrate 2 under the oxide film, the p − -type floating region 140 remains 2 is embedded in the n − layer 20 instead of the surface, so that a non-uniform portion is generated in the potential distribution of the p − type floating region 140, and it is possible to suppress a decrease in breakdown voltage.

  It is desirable that the height of the upper surface of floating region 140 be lower than the height of the bottom of p − layer 30. Further, the floating region 140 inside the semiconductor substrate 2 (the floating region 140 on the left side when viewed from the plane of FIG. 1) is formed to include the bottom corners of the first edge trench 110 and the second edge trench 210. It is desirable to have been. Further, as shown in FIG. 1, the floating region 140 on the left side when viewed from the plane of FIG. 1 is deeper than the floating area 140 on the right side when viewed from the plane of FIG. It is desirable that the depth becomes shallower (right side as viewed from the paper). Further, it is desirable that the thickness of the floating region 140 in the depth direction becomes smaller toward the outside (toward the right as viewed from the plane of FIG. 1), and that the impurity concentration of the floating region be reduced toward the outside. Accordingly, the equipotential lines toward the outside of the semiconductor device 1 can be made more gentle, and the withstand voltage of the semiconductor device 1 can be further improved.

Further, it is desirable that the outermost floating region 140 is longer in the lateral direction than the thickness.
Further, it is desirable that the outermost floating region 140 extends to the outside of the field plate electrode 130. By the effects of both the floating region 140 provided below and the field plate electrode 130 provided above, the electric field concentration on the side surfaces and corners of the outermost second edge trench 210 is reduced, and the breakdown voltage of the semiconductor device 1 is reduced. Can be further improved.

  In the above description, the element structure of the active region 200 is a trench gate type power MOSFET. However, a trench gate type element such as an IGBT or a MOSFET having an electrode structure in a trench other than FIG. A similar structure can also be used when preparing for

  In addition, although the above-described configurations are all n-channel elements, it is obvious that p-channel elements can be similarly obtained by reversing the conductivity type (p-type and n-type). In this case, the acceptor concentration shown in FIG. 1 is the donor concentration in the n − layer corresponding to the p − layer 23. In addition, it is apparent that the above-described structure and manufacturing method can be realized irrespective of the materials constituting the semiconductor substrate, the gate electrode, and the like, and the same effects are obtained.

Reference Signs List 1 semiconductor device 2 semiconductor substrate 10 N + layer 20 n− layer 30 p− layer 40 n + layer 50 auxiliary electrode 60 gate electrode 70 insulating film 80 source electrode (first main electrode)
90 drain electrode (second main electrode)
Reference Signs List 100 groove 110 first edge trench 120 first edge electrode 130 field plate electrode 140 floating region 210 second edge trench 220 second edge electrode

Claims (5)

In a semiconductor device having an active region and an edge region outside the active region,
The active area is
A first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type having a conductivity type opposite to the first conductivity type on the first semiconductor region;
A third semiconductor region of a first conductivity type on the second semiconductor region;
A control electrode disposed on the second semiconductor region via a gate insulating film,
A first main electrode electrically connected to the third semiconductor region;
A second main electrode disposed on the first semiconductor region side;
Including
The edge area is
A first edge trench dug in the thickness direction of the semiconductor region of the first conductivity type;
A second edge trench provided outside the first edge trench and dug in a thickness direction of the semiconductor region of the first conductivity type;
A first conductor electrically connected to the first main electrode via an insulating film on a wall surface of the first edge trench,
Look including a second conductor of the floating potential via an insulating film on the walls of the second edge trench,
A plurality of the first and second edge trenches are arranged,
A semiconductor device, wherein a width of a semiconductor region sandwiched between the second edge trenches is wider than a width of a semiconductor region sandwiched between the first edge trenches . In a semiconductor device having an active region and an edge region outside the active region,
The active area is
A first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type having a conductivity type opposite to the first conductivity type on the first semiconductor region;
A third semiconductor region of a first conductivity type on the second semiconductor region;
A control electrode disposed on the second semiconductor region via a gate insulating film,
A first main electrode electrically connected to the third semiconductor region;
A second main electrode disposed on the first semiconductor region side;
Including
The edge area is
A first edge trench dug in the thickness direction of the semiconductor region of the first conductivity type;
A second edge trench provided outside the first edge trench and dug in a thickness direction of the semiconductor region of the first conductivity type;
A first conductor electrically connected to the first main electrode via an insulating film on a wall surface of the first edge trench,
Look including a second conductor of the floating potential via an insulating film on the walls of the second edge trench,
A plurality of the first edge trench is arranged,
A semiconductor device, wherein a width of a semiconductor region sandwiched between the first edge trench and the second edge trench is wider than a width of a semiconductor region sandwiched between the first edge trenches . In a semiconductor device having an active region and an edge region outside the active region,
The active area is
A first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type having a conductivity type opposite to the first conductivity type on the first semiconductor region;
A third semiconductor region of a first conductivity type on the second semiconductor region;
A control electrode disposed on the second semiconductor region via a gate insulating film,
A first main electrode electrically connected to the third semiconductor region;
A second main electrode disposed on the first semiconductor region side;
Including
The edge area is
A first edge trench dug in the thickness direction of the semiconductor region of the first conductivity type;
A second edge trench provided outside the first edge trench and dug in a thickness direction of the semiconductor region of the first conductivity type;
A first conductor electrically connected to the first main electrode via an insulating film on a wall surface of the first edge trench,
Look including a second conductor of the floating potential via an insulating film on the walls of the second edge trench,
A plurality of the first edge trenches are arranged;
A semiconductor device, wherein a fourth semiconductor region of a second conductivity type embedded in the first semiconductor region between the first edge trenches is arranged .   2. The semiconductor device according to claim 1, wherein a fifth semiconductor region of a second conductivity type buried in the first semiconductor region between the first edge trench and the second edge trench is arranged. . A plurality of the second edge trenches are arranged;
2. The semiconductor device according to claim 1 , wherein a sixth semiconductor region of a second conductivity type embedded in the first semiconductor region between the second edge trenches is arranged.

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