JP2018181933A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor device in which avalanche breakdown is hard to occur and which enables a fast operation.SOLUTION: In a semiconductor device, a gate electrode 14 and a shield electrode 15 are capacitively coupled with an inner surface of a trench 10A. Between the gate electrode 14 on the upper side and the inner surface, a gate oxide film 16B is formed uniformly. Because of this, an operation as a MOSFET as described above is performed. On the other hand, between the shield electrode 15 on the lower side and the inner surface, a bottom face oxide film 16C composed of SiOis provided similar to the gate oxide film 16B except both corners of a bottom face of the trench 10A; and at both corners of the bottom face, corner insulation structures 30 each composed to include a high-dielectric substance are formed.SELECTED DRAWING: Figure 1

Description

  The present invention relates to the structure of a semiconductor device in which a gate electrode (control electrode) is provided in a trench (groove) formed in a semiconductor substrate.

  Semiconductor devices (power semiconductor elements: power MOSFETs, IGBTs, etc.) in which on / off of current between the front side and the back side of the semiconductor layer is controlled by the potential of the gate electrode are used. In such a semiconductor device, the channel formed in the semiconductor layer facing the gate electrode becomes a current path by the potential of the gate electrode, and the on / off of the current is controlled by controlling the on / off of the channel. . In addition, in a trench type device in which a trench (groove) is formed on the surface side of the semiconductor layer and the gate electrode is provided in this trench, miniaturization of the cell is easy, and the resistance at the on time (on resistance) It is particularly preferably used because it can reduce the In the trench type device, a thin gate oxide film is formed on the inner wall of the trench, and the semiconductor layer forming the inner wall of the trench and the gate electrode oppose each other through the gate oxide film, and a channel in this portion of the semiconductor layer ON / OFF is controlled by the potential of the gate electrode (gate potential).

  Here, in the power MOSFET or IGBT, apart from the above-described structure for forming the channel and using it as a current path, a structure (parasitic transistor) equivalent to a bipolar transistor is additionally formed in the semiconductor layer . When using a power MOSFET or IGBT as a switching element, short-circuiting between the electrode on the front side (the source electrode in the power MOSFET, the emitter electrode in the IGBT) and the electrode on the back side (the drain electrode in the power MOSFET, collector electrode in the IGBT) When a large voltage (surge voltage) is applied during time, this parasitic transistor is turned on, so a large current flows in the semiconductor layer between the electrode on the front side and the electrode on the back side regardless of the gate voltage. This may cause the element to be destroyed (avalanche destruction).

For this reason, it is required that such an avalanche breakdown does not easily occur (the avalanche withstand capability is high) in the power MOSFET or the IGBT. As described in Patent Document 1, it is described that avalanche breakdown tends to occur particularly when the electric field strength in the gate oxide film at the bottom of the trench becomes high. For this reason, in Patent Document 1, a gate oxide film is formed of a high dielectric layer made of a material having a dielectric constant higher than that of SiO ₂ (gate oxide film) between the inner wall on the bottom side of the trench and the gate electrode. It is laminated and used. As a result, the electric field strength at the bottom of the trench can be reduced and avalanche breakdown is less likely to occur. On the other hand, since only a thin gate oxide film is formed in the region where the channel is formed above the trench, the on / off of the channel can be controlled by the gate voltage, and the switching operation can be performed.

  Further, for example, in order to operate the power MOSFET at high speed, it is necessary to reduce the feedback capacitance Crss, the input capacitance Ciss, and the output capacitance Coss. Here, the feedback capacitance Crss is the capacitance between the gate and the drain, and the input capacitance Ciss is the sum of the capacitance between the gate and the source and the feedback capacitance Crss. It is known to reduce Crss (gate-drain capacitance) by providing a shield electrode electrically connected to the source and at the same potential (ground potential) below the gate electrode in the trench. Patent Document 1 describes that the high dielectric layer may be provided around the shield electrode as described above. The power MOSFET can be operated at high speed by providing the shield electrode.

U.S. Patent Application Publication No. 2014/0027812 A1

  When the high dielectric layer is provided on the bottom side of the trench, the capacitance between the gate and the source is increased because the capacitance around the gate electrode is increased. Further, even when the shield electrode connected to the source is provided as described above, the capacitance component formed around the shield electrode is increased by providing the high dielectric layer. For this reason, Crss and Coss can not be reduced sufficiently, and this power MOSFET can not be operated at a sufficiently high speed.

  The present invention has been made in view of such problems, and an object of the present invention is to provide an invention for solving the problems.

The present invention has the following configuration in order to solve the above-mentioned problems.
The semiconductor device according to the present invention comprises a first semiconductor layer made of a semiconductor material having a first conductivity type, and a second conductivity type opposite to the first conductivity type, of the first semiconductor layer. A semiconductor substrate provided with a second semiconductor layer formed thereon, wherein a groove is provided so as to penetrate the second semiconductor layer from the surface side and reach the first semiconductor layer; A silicon oxide film is sandwiched between the first main electrode connected to the front side of the semiconductor substrate, the second main electrode connected to the back side of the semiconductor substrate, and the inner surface of the groove in the groove. A semiconductor device comprising the formed control electrode, wherein a corner insulating structure partially including a high dielectric having a relative dielectric constant higher than that of a silicon oxide film in a cross sectional view perpendicular to the extending direction of the groove But at each of the lower corners of the groove at the bottom of the groove Characterized in that it is formed across the oxide film.
In the semiconductor device according to the present invention, the corner insulating structure is formed of an outer oxide film in contact with the inner surface and made of a silicon oxide film, and the high dielectric in contact with the outer oxide film on the opposite side to the inner surface. A high dielectric layer and an inner oxide film formed of a silicon oxide film in contact with the high dielectric layer on the side opposite to the outer oxide film are laminated and configured.
In the semiconductor device of the present invention, the high dielectric layer is formed by laminating a first high dielectric layer in contact with the outer oxide film and a second high dielectric layer in contact with the inner oxide film. The dielectric constant of the first high dielectric layer is made larger than the dielectric constant of the second high dielectric layer.
In the semiconductor device according to the present invention, a shield electrode insulated from the control electrode and capacitively coupled to the first semiconductor layer is provided in the groove below the control electrode, in the corner insulating structure. The inner oxide film is in contact with the shield electrode.
The semiconductor device of the present invention is characterized in that, in the groove, the inner oxide film in the corner insulating structure is in contact with the control electrode.

  Since the present invention is configured as described above, it is possible to obtain a semiconductor device which is less susceptible to avalanche breakdown and capable of high speed operation.

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 6 is an enlarged cross-sectional view of a trench bottom portion in the semiconductor device according to the embodiment of the present invention. FIG. 7 is a cross-sectional view of a modified example of the semiconductor device according to the embodiment of the present invention.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device 1. The semiconductor device 1 is an n-channel power MOSFET. The semiconductor device 1 is a trench type in which the gate electrode 14 is formed in the trench (groove) 10A. In FIG. 1, in the semiconductor substrate 10 made of a semiconductor material (Si), a trench (groove) 10A is formed by being dug down from the surface (upper surface) side.

In the semiconductor substrate 10, a p-type (second conductivity type) body layer (second semiconductor layer) is formed on the upper side of the n-type (first conductivity type) drift layer (first semiconductor layer) 11. 12 is formed by laminating. Trench 10A is formed to penetrate body layer 12 from the surface side of semiconductor substrate 10 so that the bottom surface thereof is in drift layer 11. In the body layer 12 on the surface of the semiconductor substrate 10, a source region 13 to be a high concentration n-type layer (n ⁺ layer) is selectively formed adjacent to both sides of the trench 10A. The body layer 12 can be formed by epitaxial growth on the drift layer 11 or ion implantation or the like on the surface of the semiconductor substrate 10 in a state where the drift layer 11 is provided on the surface. Source region 13 can be formed by locally implanting ions on the surface of body layer 12.

  Inside the trench 10A, a gate electrode (control electrode) 14 on the upper side and a shield electrode 15 on the lower side are provided in capacitive coupling with the body layer 12 forming the inner surface of the trench 10A and the drift layer 11. The gate electrode 14 and the shield electrode 15 are both made of a conductive metal material or conductive polycrystalline silicon to which an impurity is added at a high concentration. The gate electrode 14 is provided at a height such that the side thereof becomes the source region 13 and the body layer 12, and the bottom surface of the gate electrode 14 is set to be at the height where the drift layer 11 is located. The shield electrode 15 is provided at a height below the gate electrode 14 where the drift layer 11 is located. Since the gate electrode 14 and the shield electrode 15 are insulated by the oxide film 16A, these potentials are independent. In addition, a thin gate oxide film 16B is formed between the gate electrode 14 and the body layer 12 in the trench 10A.

  Further, on the upper side of the trench 10A, the interlayer insulating layer 17 is locally formed thick so as to cover the gate electrode 14 from the upper side. However, the side of source region 13 separated from trench 10A is not covered with interlayer insulating layer 17. The oxide film 16A and the interlayer insulating layer 17 are both formed by the CVD method or the like. On the other hand, gate oxide film 16B is thin so that on / off of the channel in body layer 12 forming the inner surface of trench 10A can be controlled by the potential of gate electrode 14, and the surface state between body layer 12 is reduced. It is formed by thermal oxidation.

  In this state, the front surface side of the semiconductor substrate 10 is covered with the source electrode (first main electrode) 18 made of a metal material (such as Al) having a low resistivity over the entire surface. As described above, since interlayer insulating layer 17 is provided, source electrode 18 is electrically connected to body layer 12 and source region 13 on the surface of semiconductor substrate 10 and is not connected to gate electrode 14.

On the other hand, in the semiconductor substrate 10, a drain layer 19 to be a high concentration n-type layer (n ⁺ layer) is provided on the entire surface below the drift layer 11. In this state, the back surface side of the semiconductor substrate 10 is entirely covered with a drain electrode (second main electrode) 20 made of a metal material in ohmic contact with the drain layer 19.

  Although only the structure relating to a single trench 10A is described in FIG. 1, actually, in this semiconductor substrate 10, a larger number of trenches 10A and their accompanying source regions 13 and gate electrodes 14 are described. Etc. are similarly formed. The gate electrode 14 in each trench 10A is electrically connected outside the illustrated range, and the source electrode 18 and the drain electrode 20 are also formed over the entire surface as described above. 14, the source electrode 18, and the drain electrode 20 are electrically connected to each other. Further, the shield electrode 15 of each trench 10A is connected to the source electrode 18 outside the illustrated range.

  The structure relating to the trench 10A as described above functions as a power MOSFET in which on / off of the current flowing between the source electrode 18 and the drain electrode 20 is controlled by the voltage (gate voltage) applied to the gate electrode 15. That is, the on / off (presence or absence) of the channel in the body layer 12 constituting the inner surface of the trench 10A is controlled by the gate voltage, thereby turning on / off the flow of electrons between the source region 13 and the drift layer 11. The on / off of the current between the source electrode 18 and the drain electrode 20 is controlled by this. At this time, generally, the source electrode 18 is set to the ground potential, and the shield electrode 15 similarly set to the ground potential is provided below the gate electrode 15 in the trench 10A to provide a feedback capacitance Crss (between gate and drain). Of the power MOSFET can be reduced, and the power MOSFET can be operated at higher speed. The above configuration is similar to, for example, a portion functioning as a power MOSFET in the semiconductor device described in Patent Document 1.

  However, if the operation speed is sufficient without providing the shield electrode 15, only the gate electrode 14 may be provided in the trench 10 </ b> A without providing the shield electrode 15. In this case, the trench 10A can be shallower than the configuration of FIG.

Here, the semiconductor device 100 is characterized in the structure of the insulating layer formed on the inner surface of the trench 10A. In FIG. 1, the gate electrode 14, the shield electrode 15 and the inner surface of the trench 10A are capacitively coupled. A gate oxide film 16B is uniformly formed between the upper gate electrode 14 and the inner surface. Therefore, the operation as the above-described MOSFET is performed. On the other hand, between the lower shield electrode 15 and the inner surface, a bottom oxide film 16C made of SiO ₂ is provided similarly to the gate oxide film 16B except for the bottom corners of the trench 10A. At the corners, a corner insulation structure 30 is formed, which comprises a high dielectric. 2 is an enlarged cross-sectional view showing the structure of region A in FIG. 1, and here the structure around the corner insulating structure 30 at the lower left corner of shield electrode 15 in FIG. 1 is shown enlarged. . The corner insulation structure 30 on the right side in FIG. 1 has a structure in which the left and right are reversed from those in FIG.

In FIG. 2, the corner insulating structure 30 is formed of a laminated structure of four insulating layers. An outer oxide film 31 made of SiO ₂ is provided on the outermost side (inner surface side of the trench 10A). The outer oxide film 31 can be the same as the gate oxide film 16B described above. Thus, the interface state density between the outer oxide film 31 and the inner surface (drift layer 11) of the trench 10A can be reduced, and adverse effects such as traps formed at this interface can be reduced. Further, the innermost (shield electrode 15 side) layer in the corner insulation structure 30 is also the inner oxide film 32 made of SiO ₂ .

Between the outer oxide film 31 and the inner oxide film 32 in the corner insulating structure 30, an insulating layer having a dielectric constant (relative ratio) higher than that of SiO ₂ is formed. This insulating layer is a first high dielectric layer (high dielectric layer) 33 on the outer side (outside oxide film 31 side), and a second high dielectric layer (high dielectric layer) 34 on the inner side (inner oxide film 32 side). It has a two-layer structure. While the relative dielectric constant of SiO ₂ is about 4.0, both of the first high dielectric layer 33 and the second high dielectric layer 34 are made of a material having a dielectric constant higher than that (relative ratio). Ru. Specifically, as such materials, ZrO ₂ (dielectric constant: about 15 to 40), Ta ₂ O ₅ (dielectric constant: about 20 to 25), Al ₂ O ₃ (dielectric constant: about 10) There is. However, the relative permittivity of the outer first high dielectric layer 33 is set to be larger than the relative permittivity of the inner second high dielectric layer 34. These materials can be deposited by, for example, a high frequency sputtering method, a CVD method, etc., and the first high dielectric layer 33 and the second high dielectric layer 34 are continuously formed by the same deposition apparatus. Is also possible. Thereafter, they can be patterned to have the form of FIG. 2 by dry etching or wet etching.

When polycrystalline silicon is used as the material of the shield electrode 15, it is desirable to remove adverse effects such as traps at the interface with the shield electrode 15 as well as the interface with the drift layer 11, in this point, avoiding high dielectric such as described above is in contact with the shield electrode 15 directly, as with the outer oxide layer 31, an inner oxide which is composed of SiO ₂ which may be the state of the interface relatively good It is preferred to use the membrane 32 on the inside.

  In the corner insulating structure 30 in the above configuration, the high dielectric is used as in the structure at the bottom of the trench in the structure described in Patent Document 1, so the same effect as the structure described in Patent Document 1 can be obtained. It is clear. That is, by providing an insulating structure using a high dielectric, the maximum electric field at the time of off can be reduced, and the avalanche resistance can be increased.

  However, in general, the place where the maximum electric field (field concentration) occurs is at the lower corners of the trench. Therefore, the same effect can be obtained even if the insulating structure using the high dielectric is not provided in all the lower region of the trench 10A but only in the lower corners of the trench 10A.

  On the other hand, in order to enable high-speed switching operation of the semiconductor device 100, it is necessary to reduce the feedback capacitance Crss (capacitance between gate and drain), the input capacitance Ciss, and the output capacitance Coss. As described above, Crss can be reduced by providing the shield electrode 15 electrically connected to the source electrode 18 and set to the same potential (ground potential) below the gate electrode 14 in the trench 10A. However, when a high dielectric is provided all over the lower part of the trench as in the semiconductor device described in Patent Document 1, the capacitance component formed around the shield electrode 15 is large due to the presence of the high dielectric. became. On the other hand, in the semiconductor device 100 described above, the high dielectric (corner insulating structure 30) is provided only at both corners of the trench 10A where electric field concentration occurs, ie, corner insulation at the bottom side of the trench 10A. Such a structure in which the structure 30 (high dielectric) is not provided can suppress such an increase in capacitance component.

  Therefore, in the semiconductor device 100 described above, a high avalanche withstand capability can be obtained, and the switching speed can also be increased.

  At this time, the electric field strength at the bottom of the trench can be optimized by making the relative dielectric constant of the outer first high dielectric layer 33 larger than the relative dielectric constant of the inner second high dielectric layer 34, and IGBT, power The oscillation at the time of turning off the MOSFET can be reduced, and the electrical characteristics can be stabilized.

  Although the shield electrode 15 is provided below the gate electrode 14 in the above example, the above configuration is effective even when the shield electrode 15 is not provided. FIG. 3 is a cross-sectional view showing the structure of the semiconductor device 2 in the same manner as FIG. In the semiconductor device 2, the trench 10B is formed shallower than the trench 10A, and the structure in the trench 10B is different from that of the semiconductor device 1 described above.

  In the trench 10B, only the gate electrode 14 is formed, and between the side surface of the gate electrode 14 and the inner surface of the trench 10B, the gate oxide film 16B is formed in the same manner as described above. Further, in the same manner as described above, the same corner insulating structures 30 as described above are formed at both corners of the bottom of the trench 10B, with the bottom oxide film 16C at the bottom of the trench 10B being sandwiched.

  In the semiconductor device 2 as well, as with the semiconductor device 1 described above, the avalanche insulation structure 30 can increase the avalanche withstand capability. On the other hand, although the gate-drain capacitance is increased due to the presence of the high dielectric, the increase in the capacitance is suppressed by providing the bottom oxide film 16C between the corner insulating structures 30. Therefore, high switching speed can be obtained.

  In the above configuration, an n-channel power MOSFET having an n-type drift layer, a p-type body layer and the like has been described, but a p-channel power MOSFET in which the conductivity types are reversed is described. It is obvious that the same configuration can be applied. Further, the same applies to IGBTs as well as power MOSFETs.

1, 2 Semiconductor devices (power MOSFET)
10 semiconductor substrate 10A, 10B trench
11 drift layer (first semiconductor layer)
12 Body layer (second semiconductor layer)
13 source region 14 gate electrode (control electrode)
15 shield electrode 16A oxide film 16B gate oxide film 16C bottom oxide film 17 interlayer insulating layer 18 source electrode (first main electrode)
19 drain layer 20 drain electrode (second main electrode)
30 corner insulation structure 31 outer oxide film 32 inner oxide film 33 first high dielectric layer (high dielectric layer)
34 Second high dielectric layer (high dielectric layer)

Claims (5)

A first semiconductor layer made of a semiconductor material having a first conductivity type, and a second semiconductor layer formed on the first semiconductor layer having a second conductivity type opposite to the first conductivity type A semiconductor substrate, provided with a semiconductor layer, and provided with a trench which is dug down so as to penetrate the second semiconductor layer from the surface side to reach the first semiconductor layer;
A first main electrode connected to the front side of the semiconductor substrate;
A second main electrode connected to the back side of the semiconductor substrate;
A control electrode formed by sandwiching a silicon oxide film between the groove and the inner surface of the groove;
In a sectional view perpendicular to the extending direction of the groove,
A corner insulating structure partially including a high dielectric having a relative permittivity higher than that of a silicon oxide film is formed by sandwiching the silicon oxide film at the bottom of the groove at each of the lower corners of the groove. Semiconductor device characterized by The corner insulation structure is
An outer oxide film in contact with the inner surface and made of a silicon oxide film;
A high dielectric layer made of the high dielectric and in contact with the outer oxide film on the side opposite to the inner surface;
An inner oxide film formed of a silicon oxide film in contact with the high dielectric layer on the side opposite to the outer oxide film;
The semiconductor device according to claim 1, wherein the semiconductor device is stacked. The high dielectric layer is
A first high dielectric layer in contact with the outer oxide film;
A second high dielectric layer in contact with the inner oxide film;
Are stacked and configured,
3. The semiconductor device according to claim 2, wherein a relative dielectric constant of the first high dielectric layer is made larger than a relative dielectric constant of the second high dielectric layer. In the groove,
A shield electrode insulated from the control electrode and capacitively coupled to the first semiconductor layer is provided below the control electrode.
The semiconductor device according to claim 2, wherein the inner oxide film in the corner insulating structure is in contact with the shield electrode. In the groove,
The semiconductor device according to claim 2, wherein the inner oxide film in the corner insulating structure is in contact with the control electrode.

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