JP2798023B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pnpn thyristor used for a switching power device or the like, and more particularly to two types of MOSFETs (MISFETs).
The present invention relates to a double MOS gate type thyristor semiconductor device capable of turn-on / turn-off control.

[0002]

2. Description of the Related Art Recently, an MCT (MOS gate control thyristor) has been developed for the purpose of reducing on-voltage by a thyristor structure and achieving high speed and low driving power by a MOS gate device. The MCT has a fast turn-on and an excellent on-voltage of about 1 V, but has a very long turn-off time of 2 to 3 μs and is difficult to use at high frequencies. Therefore, the applicant of the present application has previously filed Japanese Patent Application No.
No. 2884 (JP-A-6-125078) discloses a semiconductor device in which a gate-driven thyristor and a bipolar transistor are combined.

In the semiconductor device, as shown in FIG. 35, a ^{p.sup. +} Type (first
An n ⁻ -type (second conductivity type) base layer 3 is formed on the anode layer 2 by epitaxial growth using a semiconductor substrate of conductivity type as an anode layer 2. Note that an n ⁺ type buffer layer may be provided between the anode layer 2 and the n ⁻ type base layer 3. On the surface side of the n ⁻ -type base layer 3, a p-type well-shaped base layer 4 is formed by diffusion. Further, the first cathode layer 5a of the p-type surface of the inner base layer 4, n ⁺ -type well-shaped outer periphery of,
The central second cathode layer 5b and the inner peripheral drain layer 6 are formed independently of each other. On the p-type base layer 4 and the n ⁺ -type drain layer 6, a short-circuiting electrode (metal electrode) 8 for carrier conversion, which is conductively connected to these, is connected. The n ⁺ -type cathode layers 5a and 5b are interconnected via a second-layer cathode electrode layer 7 formed on the interlayer insulating film.

[0004] From the n ⁺ -type first cathode layer 5 a to the surfaces of the p-type base layer 4 and the n ^-- type base layer 3, the first layer is interposed via a gate oxide film (gate insulating film) 9. A first gate electrode 10 made of polycrystalline silicon constituting a MOSFET (VDMOS structure) 12 is formed, while an n ⁺ type drain layer 6 to a p type base layer 4 and an n ⁺ type second A second gate electrode 11 of polycrystalline silicon constituting the second MOSFET 13 is formed over the surface of the cathode layer 5b via the gate oxide film 9. The first gate electrode 10 and the second gate electrode 11 can be controlled electrically independently. It should be noted that a first MOSFET 12 formed by the first gate electrode 10 and a second MOSFET formed by the second gate electrode 11
ET13 are both n-channel MOSFETs (insulated gate field effect transistors).

FIG. 36 shows an equivalent circuit of the thyristor semiconductor device of FIG. In this semiconductor structure, n
⁺ -Type first cathode layer 5a, p-type base layer 4 and n
^An npn-type bipolar transistor Qnpn 1 is constituted by the-type base layer 3, and an npn-type bipolar transistor is constituted by the second n ⁺ -type cathode layer 5b, the p-type base layer 4 and the n ^-- type base layer 3. The transistor Qnpn2 is configured. Further, a pnp transistor Qpnp is constituted by the p-type base layer 4, the n ⁻ -type base layer 3 and the p ⁺ -type anode layer 2. Therefore, the cathode layer 5
a, 5b are connected in parallel, and transistors Qnpn1,
A thyristor structure (pnpn structure) composed of a series connection of Qnpn2 and transistor Qpnp is formed.

The transistors Qnpn 1 and Qnpn 2
And Qpnp, the first MOSFET 12 connects the n ⁻ -type base layer 3, which is the collector of the transistor Qnpn 1, and the first cathode layer 5 a via the channel on the surface of the p-type base layer 4, and n ⁻ Electrons are injected into the base layer 3 of the mold. In addition, the short-circuit electrode 8 and the second MOSFET 13
Are a drain layer 6 and a second cathode layer 5b as a source layer.
Are connected, and holes are extracted from the inside of the p-type base layer 4.

In such a configuration, when the first gate electrode 10 is set to a high potential in a state where no potential is applied to the second gate electrode 11 or a state where a negative potential is applied, the first gate electrode P which is the back gate just below 10
The surface of the base layer 4 becomes an n-type inversion layer, and the n-type inversion layer (channel) immediately below the n ⁺ -type first cathode layer 5a as a source layer and the first gate electrode 10 from the cathode electrode layer 7 , And an n ⁻ -type base layer 3 as a drain layer
Are connected. Accordingly, electrons (n) are transferred from the cathode electrode layer 7 to the n ⁻ type base layer 3 which is a drain drift region.
The majority carriers of the ⁻ type base layer 3 are injected, and in response thereto, holes (the majority carriers of the anode layer 2) are injected from the p ⁺ type anode layer 2 to the n ⁻ type base layer 3. This means that the conductivity of the n ⁻ -type base layer 3 is modulated,
This means that the np-type transistor Qpnp is turned on. Further, since the hole current of the transistor Qpnp becomes the base current of the transistors Qnpn1 and Qnpn2, the transistors Qnpn1 and Qnpn2 are turned on. That is, the p ⁺ type anode layer 2, the n ⁻ type base layer 3, the p type base layer 4 and the n ⁺ type cathode layers 5 a, 5
b, the thyristor (pnpn structure) is turned on, a high concentration of carriers is present in the device,
The device enters a low resistance state. As described above, by setting the first gate electrode 10 to a high potential in a state where the second gate electrode 11 is set to a zero potential or lower, a thyristor state is formed as in the case of the MCT. Become a power device.

In this thyristor state, when the second gate electrode 11 is set at a high potential while the first gate electrode 10 is kept at a high potential, the second MOSFET 13 is also turned on, and the p-type transistor immediately below the second gate electrode 11 is turned on. The surface of the mold base layer 4 is inverted to n-type. Thereby, the p-type base layer 4, the short-circuit electrode 8, the n ⁺ -type drain layer 6, the second gate electrode 1
The n-type inversion layer (channel) immediately below 1 and the n ⁺ -type cathode layer 5b enter a conductive state. Since holes in the p-type base layer 4 are converted into electrons in the short-circuit electrode 8, the hole current injected from the p ⁺ -type collector layer 2 is:
The p-type base layer 4 is converted into an electron current by the short-circuit electrode 8, and the electron current flows out to the cathode electrode layer 7. Therefore, the bipolar transistors Qnpn1 and Qnpn2 are turned off. As a result, the thyristor operation is extinguished, and a bipolar transistor state in which only bipolar transistor Qpnp operates is attained. This state corresponds to the IG described earlier.
This is similar to the operating state of a BT (conductivity modulation transistor) (a state in which electrons are injected by the first MOSFET 12 and the electric conductivity of the base layer 3 is modulated). The existing carrier density is reduced. Therefore, at the time of turning off the first gate electrode 10 to zero or negative potential thereafter, the time required for sweeping out the carriers can be reduced, and the turn-off time can be shortened.

FIGS. 37 (a) and 37 (b) show current flows in the thyristor state and the bipolar transistor state (IGBT state). In the thyristor state shown in FIG. 37A, a hole current and an electron current flow uniformly from the n ⁻ type base layer 3 to the p type base layer 4 toward the cathode electrodes 5a and 5b, and the thyristor operation is achieved. ing. In particular, the main current flows in the vertical direction immediately below the central n ⁺ -type second cathode layer 5b, and the n ⁺ -type second cathode layer 5b substantially functions as a cathode during thyristor operation. ing.

On the other hand, in the bipolar transistor state shown in FIG. 37B, the main electron current of the device is I
As with GBT, n ^- first MOS -type base layer 3
The hole current flows through the channel of the FET 12 to the first cathode layer 5a, and the hole current enters the p-type base layer 4 from the side of the first MOSFET 12, and the short-circuit electrode 8 and the n ⁺
It flows out to the cathode electrode layer 7 through the second MOSFET 13 via the drain layer 6 of the type. As described above, the main current in the transistor state does not flow through the region under the n ⁺ -type second cathode layer 5b at the center, which is the main current path in the thyristor state, and the main current path in the thyristor state and the transistor in the transistor state do not flow. The main current path is separated.

That is, in the semiconductor device shown in FIG. 35, the first MOSFET 12 which injects the majority carrier electrons to turn on the thyristor is the first MOSFET 12 which is the source.
Of the second cathode layer 5b, which is a substantial cathode through which a main current flows during thyristor operation, is separated from the cathode layer 5a. Since the impurity concentration in the lower region of the first cathode layer 5a and the impurity concentration in the lower region of the second cathode layer 5b can be controlled independently, a thyristor operation can be performed at a low on-voltage and the turn-off time can be reduced. Of course, the parasitic resistance R _B
, It is possible to increase the latch-up withstand capability.

[0012]

However, the above-described semiconductor structure has the following problems.

When a transition is made from the thyristor state to the bipolar transistor state (IGBT state), holes are extracted from the p-type base layer 4. However, in this case, the holes to be extracted are set in the second MO.
In order to convert it into electrons which are monopolar of SFET13,
On the p-type base layer 4 and the n ⁺ -type drain layer 6, a short-circuit electrode (metal electrode) 8 extending between them must be isolated and finely formed. However, it is generally difficult to finely form the metal electrode 8 in contact with the semiconductor region. Further, the first cathode layer 5a and the second cathode layer 5b sandwiching the first layer metal electrode 8 are connected to a second layer cathode electrode (power supply wiring layer) formed on the interlayer insulating film 14. However, in the power device, the structure of the two-layer electrode wiring which overlaps vertically does not conform to the actual state in terms of process and insulation.

When the on-resistance of the second MOSFET 13 is reduced, it is possible to expedite the extraction of holes from the p-type base 4 during the operation of the bipolar transistor,
Turn-off speed can be increased. However, the second
MOSFET 13 is formed by self-aligning (self-alignment) source / drain regions (6, 5b) on both sides of the body under the gate using polycrystalline silicon gate electrode 11 as a mask, similarly to first MOSFET 12. It is. The effective channel length is determined by the gate length of the polycrystalline silicon gate electrode 11 serving as a mask.
The length of the gate electrode 11 is practically about 1 μm even in the miniaturization process, and there is a limit to shortening the channel, and it is difficult to reduce the on-resistance. In addition, variation in characteristics of the MOS transistor is likely to occur.

In view of the above problems, an object of the present invention is to make the second MOSFET for hole extraction have a conductivity type opposite to that of the first MOSFET for electron injection, so that the second MOSFET for electron injection has the opposite conductivity type. A thyristor semiconductor device that eliminates the need to form a short-circuit electrode for carrier conversion at the time, avoids the difficulty of forming a fine electrode and the two-layer structure of the electrode wiring, and can reduce the on-resistance of the second MOSFET itself. To provide.

[0016]

According to the present invention, there is provided a MIS for majority carrier injection.
The MISFET for extracting majority carriers has a double diffusion type (DMOS structure) so that the FET and the MISFET for extracting majority carriers have opposite conductivity types.
That is, the semiconductor device according to the present invention comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type formed thereon, and a first semiconductor region formed in a well shape in the second semiconductor region. A third semiconductor region of one conductivity type; a fourth semiconductor region of second conductivity type formed in a well shape on the surface side in the third semiconductor region; Of the second conductive type fifth semiconductor region formed in the first conductive type, the first conductive type sixth semiconductor region, the third semiconductor region, and the fifth semiconductor region formed in a well shape on the surface side in the fourth semiconductor region. A second conductivity type MISFET for injecting majority carriers from the fifth semiconductor region into the second semiconductor region, having a double diffusion type structure, and a second conductivity type M
It can be opened and closed independently of the ISFET, has a double diffusion structure with a fourth semiconductor region and a sixth semiconductor region, and has a third
A first conductivity type MISFE for extracting majority carriers from the semiconductor region to the sixth semiconductor region;
T.

Here, the present invention is directed to the third semiconductor region.
The entire well end region from immediately below the fifth semiconductor region to the outside is
3 High concentration higher than the impurity concentration in the inner region of the semiconductor region
It is a region.

The fifth semiconductor region is formed on the side of the first semiconductor MISFET for extracting majority carriers in the third semiconductor region, and the inner well region with a high impurity concentration is formed on the well end side of the third semiconductor region. Thus, an overlap region with the outer well region having a lower concentration than the impurity concentration of the inner well region can be obtained.

In the third semiconductor region immediately below the fifth semiconductor region, a seventh semiconductor region of the first conductivity type having a higher concentration than the impurity concentration of the third semiconductor region may be formed. As the seventh semiconductor region, a shallow well region enough to leave a portion of the third semiconductor region directly below the fifth semiconductor region.

In the third semiconductor region immediately below the gate electrode of the first conductivity type MISFET for extracting majority carriers,
A ninth semiconductor region of the first conductivity type with a high impurity concentration may be formed.

MISFE of the second conductivity type for majority carrier injection
It is preferable that one of T and the first conductivity type MISFET for majority carrier extraction is an enhancement type and the other is a depletion type.

Note that the first semiconductor region and the second semiconductor region
A second conductivity type buffer layer may be provided between them.

Further, both of the six semiconductor regions are referred to as a reference.
The second conductive type MISFET and the first conductive type MISFE
T may be provided respectively.

A short-circuit electrode connected to an electrode which is in conductive contact with the fifth semiconductor region may be connected to the third semiconductor region. Here, it is preferable that the third semiconductor region is a stripe-shaped well, and the short-circuit electrode is formed on a longitudinal end surface of the well.

A plurality of first-conductivity-type MISFET sections for majority carrier extraction may be formed in a region between a pair of fifth semiconductor regions formed at opposed well ends of the third semiconductor region. It is preferable to form a well-shaped eighth semiconductor region of the first conductivity type on the surface side of the third semiconductor region between the plurality of MISFET portions for extracting the majority carrier.

On the other hand, the fourth semiconductor region and the sixth semiconductor region formed on the opposite side of the third semiconductor region on the side of the well end have a double diffusion structure, and a region between the double diffusion structures has a second diffusion region. A configuration having a first conductivity type eighth semiconductor region formed in a well shape on the surface side of the three semiconductor regions can be adopted.

It is preferable that the fifth semiconductor region and the eighth semiconductor region are connected via a first conductivity type connection diffusion layer, and an electrode is brought into conductive contact with the eighth semiconductor region.

It is preferable that a second-conductivity-type MISFET for path switching for conducting and blocking the fifth semiconductor region and the eighth semiconductor region be formed, and that an electrode be brought into conductive contact with the eighth semiconductor region. Here, it is preferable that a part of the gate electrode of the second conductivity type MISFET for majority carrier injection is used as the gate electrode of the second conductivity type MISFET for path switching.

MISFE of second conductivity type for majority carrier injection
A plurality of T gate electrodes are arranged in stripes on the chip layout, and a configuration in which a plurality of gate wirings connected to gate pads are electrically connected in a grid pattern to the plurality of gate electrodes can be adopted.

Further, the second conductivity type MI for majority carrier injection.
The gate electrode of the SFET has an island shape provided at a lattice point on a chip layout, and a plurality of gate wirings connected to a gate pad are electrically connected to the gate electrode in a lattice shape.
It is possible to adopt a configuration in which the in-grating region divided by the gate wiring is divided by the lattice-shaped gate electrode of the first conductivity type MISFET in which majority carriers are extracted.

[Operation] In the semiconductor device according to the present invention, the first conductivity type first
In a state where an anode potential is applied to the semiconductor region and a cathode potential is applied to the fifth semiconductor region of the second conductivity type and the sixth semiconductor region of the first conductivity type, the MISF of the first conductivity type is applied.
When the MISFET of the second conductivity type is turned on with the ET kept off, majority carriers are injected from the fifth semiconductor region as the source region of the second MISFET into the second semiconductor region of the second conductivity type. In response, the minority carriers are injected from the first semiconductor region of the first conductivity type into the second semiconductor region of the second conductivity type. Therefore, the first
The transistor including the first semiconductor region of the conductivity type, the second semiconductor region of the second conductivity type, and the third semiconductor region of the first conductivity type is turned on. Thereby, the majority carriers are injected into the third semiconductor region of the first conductivity type,
At the same time, the second semiconductor region of the second conductivity type and the third semiconductor region of the first conductivity type
The transistor including the semiconductor region and the fifth semiconductor region of the second conductivity type is turned on. Therefore, the first
The thyristor having the pnpn structure including the first semiconductor region of the conductivity type, the second semiconductor region of the second conductivity type, the third semiconductor region of the first conductivity type, and the fifth semiconductor region of the second conductivity type is turned on. Therefore, the on-voltage can be reduced by the thyristor operation.

On the other hand, when the MISFET of the first conductivity type is turned on while the MISFET of the second conductivity type is turned on, majority carriers in the third semiconductor region of the first conductivity type cause the MISFET of the first conductivity type to turn on. Flows to the sixth region of the first conductivity type through the second semiconductor region, a transistor constituted by the second semiconductor region of the second conductivity type, the third semiconductor region of the first conductivity type, and the fifth semiconductor region of the second conductivity type. It turns off. For this reason, the thyristor state changes to a transistor state similar to that of the IGBT, and the carrier density in the device decreases. Thereafter, when the MISFET of the second conductivity type is turned off, the transistor state is turned off instantaneously, so that high-speed turn-off is possible.

The MISFET for extracting majority carriers in the third semiconductor region has a first conductivity type opposite to that of the M1SFET for majority carrier injection in the second semiconductor region. The majority carrier of this first
It can be pulled out directly through the conductive type MISFET, eliminating the need to form a short-circuit electrode (metal electrode) for converting carriers as in the conventional structure as the first-layer electrode wiring. Therefore, it is possible to avoid the difficulty of forming a fine electrode and the two-layer structure of electrode wiring.

Further, since the first conductivity type MISFET is a MISFET having a double diffusion type structure, a channel length can be determined by a difference in diffusion length, so that a short channel can be realized.
The on-resistance of the ISFET itself can be reduced. For this reason, the majority carrier can be strongly extracted, and the turn-off speed can be increased. Further, variation in characteristics of the MISFET can be suppressed.

In particular, according to the present invention, in the third semiconductor region,
The entire well end region from immediately below the fifth semiconductor region to the outside is
3 High concentration higher than the impurity concentration in the inner region of the semiconductor region
It is a region. Since the parasitic resistance value of the majority carrier extraction current path in the IGBT state can be reduced, the latch-up resistance can be increased.

A fifth semiconductor region is formed on the inner side of the high impurity concentration well formed on the side of the first conductivity type MISFET for majority carrier extraction in the third semiconductor region, and on the well end side of the third semiconductor region. In a structure in which the impurity concentration of the inner well region overlaps with the outer well region having a lower concentration than that of the inner well region, the current amplification factor of the portion is higher than that of the outer well region because the concentration of the inner well region is higher. Higher than that. Therefore, the inner well region functions as a substantial cathode region in the thyristor state. IGB
In the T operation, the voltage around the outer well region decreases due to the voltage drop of the diffusion resistance. However, since the current amplification factor in that portion is low, it is difficult to latch up during the IGBT operation. Therefore, the controllable current capacity can be increased.

In the structure in which the seventh semiconductor region of the first conductivity type having a higher concentration than the impurity concentration of the third semiconductor region is formed in the third semiconductor region immediately below the fifth semiconductor region, the fifth semiconductor region is formed. , The latch-up in the IGBT state can be suppressed, and the controllable current value can be increased. In particular, the seventh semi
The body region is located immediately below the fifth semiconductor region.
If it is shallow-well area of enough to leave a part, deep well
In the thyristor state, compared to the case where the
This does not cause an increase in the supply voltage.

First conductivity type MIS for extracting majority carriers
In the structure in which the ninth semiconductor region of the first conductivity type having a high impurity concentration is formed in the third semiconductor region immediately below the gate electrode of the FET, the value of the diffusion resistance immediately below the gate electrode can be reduced, so that the latch-up withstand capability is reduced. Increase can be achieved.

A first conductivity type MISFET and a second conductivity type MISFET
If one of the SFETs is an enhancement type and the other is a depletion type,
Since the ON / OFF control of the FET can be performed with either the positive power supply or the negative power supply of the gate voltage, the gate drive circuit can be simplified.

In the structure in which the short-circuit electrode connected to the electrode which makes conductive contact with the fifth semiconductor region is connected to the third semiconductor region, the majority carriers in the third semiconductor region can be directly extracted in the transistor state. The controllable current value can be increased.

In particular, electric field concentration occurs at the corners,
Although the third semiconductor region is a stripe-shaped well, and the short-circuit electrode is formed on the longitudinal end surface of the well, it is easy to suppress the latch-up at the corner. At the same time, the majority carrier density in the third semiconductor region can be increased even in the thyristor operation mode. MI of the first conductivity type
Even if the voltage between the anode and the cathode is applied while the SFET and the MISFET of the second conductivity type are turned off, current leaks to the cathode via the short-circuit electrode, so that latch-up at power-on can be prevented. .

In a structure in which a plurality of first-conductivity-type MISFET sections for majority carrier extraction are formed in a region sandwiched between a pair of fifth semiconductor regions formed at opposed well ends of the third semiconductor region, The extraction of majority carriers in the IGBT state can be enhanced, and the controllable current can be increased.

In a structure in which a well-shaped eighth semiconductor region of the first conductivity type is formed on the surface side of the third semiconductor region between the plurality of MISFET portions for extracting the majority carrier, the eighth semiconductor region is formed. Therefore, the current capacity at the time of the thyristor can be increased.

The fourth semiconductor region and the sixth semiconductor region formed on the opposed well end side of the third semiconductor region have a double diffusion structure, and the region sandwiched by these double diffusion structures has a third diffusion structure.
In the case of employing a configuration having an eighth semiconductor region of the first conductivity type formed in a well shape on the surface side of the semiconductor region,
Since the current path for extracting majority carriers can be shortened, the controllable current capacity can be increased.

The fifth semiconductor region and the eighth semiconductor region are connected to the first semiconductor region.
In a structure in which an electrode is conductively connected to the eighth semiconductor region through a connection via a conductive type connection diffusion layer, a current path from the fifth semiconductor region to the electrode via the connection diffusion layer and the eighth semiconductor region. Has a parasitic resistance, the forward voltage of the fifth semiconductor region on the well end side and the third semiconductor region immediately below the fifth semiconductor region do not become relatively high due to the voltage drop of the diffused resistor. The controllable current capacity can be increased.

In a structure in which a second-conduction-type MISFET for path switching that conducts and cuts off the fifth semiconductor region and the eighth semiconductor region is formed and an electrode is brought into conductive contact with the eighth semiconductor region, the MISFET for path switching is turned off at the time of turn-off. When the two-conductivity MISFET is turned on, the current flowing through the fifth semiconductor region disappears, so that latch-up can be eliminated.

In particular, when a part of the gate electrode of the second-conductivity-type MISFET for majority carrier injection is used as the gate electrode of the second-conduction-type MISFET for path switching, the number of manufacturing steps can be reduced and the size can be reduced. Becomes

Second conductivity type MISFE for majority carrier injection
A plurality of T gate electrodes are arranged in a stripe pattern on a chip layout, and a plurality of gate electrodes connected to a gate pad are connected to the plurality of gate electrodes in a grid pattern. Since the wiring resistance from the gate pad to the farthest gate electrode is reduced, the propagation delay of the gate signal is reduced, and current concentration in the cell of the farthest gate electrode during turn-off is suppressed. For this reason, not only is the turn-off speeded up, but also the breakdown of the cell at the farthest gate electrode is unlikely to occur, and the controllable current capacity can be increased.

Also, the second conductivity type MI for majority carrier injection.
The gate electrode of the SFET has an island shape provided at a lattice point on a chip layout, and a plurality of gate wirings connected to a gate pad are electrically connected to the gate electrode in a lattice shape.
In the case where a structure in which the in-grating region divided by the gate wiring is divided by the lattice-like gate electrode of the first-conductivity-type MISFET in which majority carriers are extracted is adopted, the propagation also occurs in the gate electrode of the second-conductivity-type MISFET far from the gate pad. Since the delay is suppressed, it is possible to increase the speed of turn-off and increase the controllable current capacity. Also, the first conductivity type MI
Since the gate electrode of the SFET is formed in a vertical and horizontal lattice, the signal delay is reduced even at a gate electrode far from the gate pad, contributing to a faster turn-on. Since the region within one lattice is divided by the gate electrode, the current capacity can be increased during the thyristor operation. Also, IG
The majority carriers can be extracted in a BT operation in a distributed manner, which contributes to an increase in the latch-up tolerance.

[0050]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 shows a structure of a thyristor semiconductor device having a double gate according to Embodiment 1 of the present invention. In the semiconductor device of the present example, a p ⁺⁺ (first conductivity type) semiconductor substrate having an anode electrode 1 provided on the back surface is defined as a first semiconductor region (anode region) 2, The n ⁻ -type (second conductivity type) second through the n ⁺ -type buffer layer 3a
A semiconductor region (n ⁻ type base layer) 3 is formed by epitaxial growth. This n ⁻ type second semiconductor region 3
A p-type well-shaped third semiconductor region (p-type base layer) 4 is formed on the surface side of. Further, a well-shaped n-type fourth semiconductor region (channel diffusion layer) 15 is formed at the center of the p-type third semiconductor region 4 on the well surface side, and the well of the third semiconductor region 4 is formed. A ring-shaped n ⁺ -type fifth semiconductor region (cathode region) 16 is formed along the end and separated from the fourth semiconductor region 15 to surround it in a plane. A p ⁺ well-shaped sixth semiconductor region 17 is formed on the surface side of the fourth semiconductor region 15 at the center of the well.

The n-type fifth semiconductor region 16 and the p ⁺ -type sixth semiconductor region 17 have the first metal electrode as the first layer.
And the second cathode electrode 18b are in conductive contact.

Then, from the n ⁺ -type fifth semiconductor region 16 to the p-type third semiconductor region 4 and the n ⁻ -type second semiconductor region 3
A first gate electrode 10 of polycrystalline silicon constituting an n-channel type first MOSFET (VDMOS structure) 12 is provided via a gate oxide film (gate insulating film) 9 over the surface of On the other hand, the gate oxide film 9 is formed from the p ⁺ -type sixth semiconductor region 17 to the n-type fourth semiconductor region 15, the n ⁺ -type fifth semiconductor region 16, and the surface of the p-type third semiconductor region 4. Via a second MO of p-channel type
A second gate electrode 21 made of polycrystalline silicon constituting the SFET (DMOS structure) 23 is provided. 2nd M
The OSFET 23 is a double-diffusion type MOSFET. After the n-type fourth semiconductor region 15 is formed as a channel diffusion layer on the surface side of the well-shaped p-type third semiconductor region 4 using the gate electrode 21 as a mask, The p ⁺ -type sixth semiconductor region 17 is formed as a source layer on the surface side of the fourth semiconductor region 15 by diffusion using the electrode 21 as a mask. While the first MOSFET 12 for electron injection is an n-channel DMOS, the second MOSFET 12 for hole extraction is
The SFET 23 is a p-channel type DMOS. Therefore, the channel of the second MOSFET 23 is a portion sandwiched between the third semiconductor region 4 and the sixth semiconductor region 17, and the channel length is determined by the difference in the lateral diffusion length, so that the channel is shortened. Note that the first gate electrode 10 and the second gate electrode 21 can be electrically controlled independently of each other.

FIG. 2 shows an equivalent circuit of the present apparatus. In this device, the n ⁺ -type fifth semiconductor region 16, the p-type third semiconductor region 4, and the n ⁻ -type second semiconductor region 3 form an npn-type bipolar transistor Qnpn. 3 semiconductor region 4, n ⁻ -type second semiconductor region 3 and p ⁺⁺ -type first semiconductor region 2
A bipolar transistor Qpnp is formed.
Therefore, a thyristor structure (pnpn structure) is formed by the bipolar transistors Qnpn and Qpnp. Here, the p-type third semiconductor region 4, the n-type fourth semiconductor region 15, and the p ⁺ -type sixth semiconductor region 17 constitute a pnp-type parasitic transistor q _pnp as shown by a broken line. Since the p-type third semiconductor region 4 is short-circuited to the first cathode electrode 18a via the n ⁺ -type fifth semiconductor region 16, the transistor function is suppressed. First MO
The SFET 12 injects majority carriers (electrons) from the fifth semiconductor region 16 through the third semiconductor region 4 to the second semiconductor region 3 which is the base layer of the transistor Qpnp. Further, the second MOSFET 23 extracts majority carriers (holes) in the third semiconductor region 4 to the sixth semiconductor region 17 via the channel of the fourth semiconductor region 15.

In this device having such a structure, when the first gate electrode 10 is set to a high potential in a state where a high potential is applied to the second gate electrode 21, the first gate electrode 10
The back gate serving as p-type third well end surface of the semiconductor region 4 immediately below becomes a n-type inversion layer, the cathode electrode 18a fifth semiconductor region 16 of n ⁺ -type as the source region, the first gate electrode 10 The n-type inversion layer immediately below and the n ⁻ -type second semiconductor region 3 as a drain are connected.
Therefore, electrons as majority carriers are injected from the cathode electrode 18a into the n ⁻ -type second semiconductor region 3, which is a drain drift region, and in response thereto, the p ⁺ -type first semiconductor region 3 is formed.
Holes are injected from the semiconductor region 2. As a result, the conductivity is modulated, and the pnp transistor Qpnp is turned on (IGBT state). Further, since the hole current of the transistor Qpnp becomes the base current of the transistor Qnpn, the transistor Qnpn is turned on. That is, a thyristor (p) composed of the p ⁺ -type first semiconductor region 2, the n ^-- type second semiconductor region 3, the p-type third semiconductor region 4, and the n ⁺ -type fifth semiconductor region 16
npn structure) is turned on, a high concentration of carriers is present in the device, and the device enters a low resistance state.

As described above, in this device, by setting the first gate electrode 10 to a high potential while the second gate electrode 21 is set to a high potential, the device becomes a thyristor state similarly to the above-mentioned MCT. Therefore, the power device has a low on-voltage. In this thyristor state (thyristor mode), as shown in FIG. 3A, the first gate electrode 10 from the second semiconductor region 3 to the well end of the third semiconductor region 4
An electron current (solid line) for electron injection flows into the fifth semiconductor region 16 via a channel immediately below, and a main current of the thyristor (solid line) flows in a region of the third semiconductor region immediately below the fifth semiconductor region 16. An electron current and a dashed hole current flow. Here, the p-type third semiconductor region 4 and the n-type fourth semiconductor region
The semiconductor region 15 and the p-type sixth semiconductor region 17 are shown in FIG.
Pnp type parasitic transistor q _{pnp as} shown by the broken line
However, since the third semiconductor region 4 is pn-connected to the cathode electrode 18a via the fifth semiconductor region 16, the transistor function is suppressed. However, although there is a slight hole extracting action from the p-type third region 4,
In the thyristor operation, there is no problem because the carriers in the third semiconductor region 4 are very abundant.

From this thyristor state, when the second gate electrode 21 is set to zero or low potential while the first gate electrode 10 is kept at high potential, the second MOSFET 23 is also turned on, and the second MOSFET 23 is placed immediately below the second gate electrode 21. The surface of the n-type fourth semiconductor region 15 is inverted to p-type. Here, the holes in the p-type third semiconductor region 4 are the short-channel second MOSFETs.
Since the transistor Qnpn is directly pulled out to the sixth semiconductor region 17 through the transistor 23, the transistor Qnpn formed by the second semiconductor region 3, the third semiconductor region 4, and the fifth semiconductor region 16 is turned off. As a result, the thyristor operation is extinguished, and the transistor enters a state where only the transistor Qpnp operates.
This state is an operation state of the IGBT in which electrons are injected into the second semiconductor region 3 by the first MOSFET 12. In such a state, as shown in FIG. 3B, the first M from the second semiconductor region 3 to the well ends of the third semiconductor region 4 are formed.
An electron current (solid line) for electron injection flows into the fifth region 16 via the channel of the OSFET 12, and a hole current (dashed line) along the electron current flows from the second semiconductor region 3 to the third semiconductor region 4. Fifth semiconductor region 1 through well end
6 and the second MOS just below the gate electrode 21.
It flows to the sixth semiconductor region 17 via the channel of the FET 23.

Thereafter, when the first MOSFET 12 is turned off by setting the first gate electrode 10 to zero or low potential while keeping the second gate electrode 21 at zero or low potential, electron injection stops instantaneously. Since the flow of holes from the first semiconductor region 2 to the second semiconductor region 3 corresponding thereto is also stopped,
The time required for sweeping out the carriers can be reduced, and the turn-off time can be shortened.

FIG. 4 shows the first gate electrode 10 and the second gate electrode 10.
Between the potential applied to the gate electrode 21 of the anode-cathode is shown the relationship between the voltage V _AK and anode current I _A.

When 0 V is applied to the first gate electrode 10 and −15 V is applied to the second gate electrode 21, the first MOSFET 12 is off, but the second MOSFET 23 is turned off. Is on,
The thyristor structure is turned off. Here, the anode current I _A is zero, anode-cathode voltage V _AK is approximately 300 V. As described above, while -15 V is applied to the second gate electrode 21, the first gate electrode 10
When a high potential (15V) is applied to the first MOSFET,
12 is turned on, and the device shifts to the IGBT mode in which electrons are injected and only the transistor Qpnp operates. Thus the anode current I _A saturated instantaneously, the anode-cathode voltage (ON voltage) V _AK is about 0.2
It saturates to about 3 V in μsec.

When 0V is applied to the second gate electrode 21 from the IGBT mode to turn off the second MOSFET 23, the hole extracting operation stops, so that the transistor Q
npn is turned on, the device is completely turned on,
Shift to thyristor mode instantly. The anode-cathode voltage (ON voltage) V _AK of thyristor mode shows a low value of about 1V. Next, the second gate electrode 21
When -15V is applied to the second MOSFET 23 to turn on the second MOSFET 23, holes are extracted, so that the IGB
The mode shifts to the T mode, and the anode-cathode voltage (ON voltage) V _AK becomes about 3V. Thereafter, when the first MOSFET12 the off state by applying 0V to the first gate electrode 10 of, IGBT operation at a rate of about 0.4μ seconds ceased, the device is turned off, the anode current I _A is At zero, the anode-cathode voltage V _AK becomes about 300V. As described above, the present device operates at the same low on-voltage as the MCT in the on state, and operates as the IGBT in the off state.
It turns off in the same short turn-off time as. Therefore, even in high frequency applications, a power device with small switching loss can be realized.

In this example, the second MOSFET 23 for extracting holes in the third semiconductor region 4 is the first MOSFET.
Conduction type opposite to that of ET12, double diffusion type MOSF
It is ET. This eliminates the need to finely form a short-circuit electrode (metal electrode) for converting holes into electrons as in the conventional structure as the first-layer electrode wiring. Therefore, it is possible to avoid the difficulty of forming a fine electrode and the two-layer structure of the electrode wiring. Furthermore, since the second MOSFET 23 is a double-diffusion MOSFET, a short channel can be realized, and the on-resistance of the second MOSFET 23 itself can be reduced, so that the hole extraction speed can be increased. Turn-off speed can be increased. Also, the second MOSF
Variations in the characteristics of ET23 can also be suppressed. Furthermore,
Latch-up tolerance can be increased, and controllable current capacity can be increased.

Embodiment 2 FIG. 5 is a sectional view showing the structure of a thyristor semiconductor device having a double gate according to Embodiment 2 of the present invention. In the semiconductor structure of the present embodiment, a high-concentration p ⁺ -type shallow well-shaped seventh semiconductor
A semiconductor region 19 is formed. Seventh semiconductor region 19
The third semiconductor region 4 remains immediately below the third semiconductor region 4. The fifth
The channel side well end of the semiconductor region 16 is not covered with the seventh semiconductor region 19.

In the structure of the first embodiment, the operation mode is temporarily shifted from the thyristor state to the transistor (IGBT) state, and then the transistor state is turned off to turn off the transistor. There is a problem that the controllable current value cannot be increased due to latch-up due to resistance or the like. That is, as shown in FIG. 3, the main current is equal to the fifth current in any operation state.
It flows in the third semiconductor region 4 below the semiconductor region 16. In particular, the path of the hole current (indicated by the broken line) in the transistor state shown in FIG. 3B enters from the well end side of the third semiconductor region 4 along the path of the electron current, and the fifth semiconductor region 16 Through the lower region of the third semiconductor region 4 to flow directly below the second gate electrode 21 at the center of the well of the third semiconductor region 4, and are drawn out to the sixth semiconductor region 17 through the channel of the second MOSFET 23. I have. Third semiconductor region 4 in the lower region of fifth semiconductor region 16
Since a diffusion resistance (base resistance R _B ) is parasitic therein, if a current for extracting holes excessively flows through the parasitic resistance, the voltage drop causes an n ⁻ -type second semiconductor region 3, p. The trigger current of the npn-type transistor Qnpn composed of the third semiconductor region 4 of the n-type and the fifth semiconductor region 16 of the n ⁺ -type is used. Also does not enter the OFF state, but enters the latch-up state.

In order to suppress the latch-up in this transistor state (to increase the controllable current until the latch-up occurs), in the present embodiment, the fifth semiconductor region 1
In order to reduce the parasitic resistance value below 6, a shallow well-shaped seventh semiconductor region 19 of high concentration p ⁺ type is formed immediately below the fifth semiconductor region 16. Base resistance R resistance by the hole pulling current much flow npn type transistor Qnpn be of _B is less likely to latch-up, it is possible to increase the controllable current.

Third Embodiment FIG. 6 is a sectional view showing a structure of a thyristor semiconductor device having a double gate according to a third embodiment of the present invention. In this embodiment, a high-concentration p ⁺ -type deep well-shaped seventh semiconductor region 20 is formed immediately below the fifth semiconductor region 16. The channel-side well end of the fifth semiconductor region 16 is the seventh end.
It is not covered with the semiconductor region 20. The seventh semiconductor region 20 of the present example has a depth enough to penetrate the third semiconductor region 4 as compared with the shallow well-shaped seventh semiconductor region 19 of the second embodiment (see FIG. 5). Most of the hole current passes through the deep well-shaped seventh semiconductor region 20. Therefore, the parasitic resistance can be significantly reduced. However, if the impurity concentration immediately below the fifth semiconductor region 16 is too high, the on-state voltage in the thyristor state is increased, so that the shallow seventh semiconductor region as in the second embodiment is used.
It is desirable to form the semiconductor region 19 or, in the case of this example, to set the impurity concentration appropriately.

Fourth Embodiment FIG. 7 is a sectional view showing a structure of a thyristor semiconductor device having a double gate according to a fourth embodiment of the present invention. In this embodiment, the fifth semiconductor region 16 is an overlap region of the shallow n ⁺ -type inner well region 16a on the gate electrode 21 side and the deep n-type outer well region 16b on the gate electrode 10 side (well end side). . Since the concentration of the shallow n ⁺ -type inner well region 16a is higher than the concentration of the p-type third semiconductor region 4, the current amplification factor h _FE of the npn-type transistor Qnpn is high. Therefore, the shallow n ⁺ -type inner well region 16a functions as a substantial cathode region in the thyristor state, and a main current flows in the vertical direction through the bottom surface of the well. It is important that the n-type outer well region 16b has a lower concentration than the n ⁺ -type inner well region 16a, and does not have to be particularly deep. Voltage around the n-type outer well region 16b than the circumference of the n ⁺ -type inner well region 16a of the third semiconductor region 4 by the voltage drop across the diffusion resistance R _B described above is lowered than at IGBT operation, the n-type Outer well area 1
Although the npn transistor Qnpn on the 6b side tends to latch up, the concentration of the deep n-type well outer region 16b is lower than the concentration of the shallow n ⁺ -type inner well region 16a, so that the current of the npn-type transistor Qnpn The amplification factor h _FE is low, and it is difficult to latch up during IGBT operation. Therefore, the controllable current capacity can be increased.

Fifth Embodiment FIG. 8 is a sectional view showing a structure of a thyristor semiconductor device having a double gate according to a fifth embodiment of the present invention. This embodiment has the structure of the third embodiment shown in FIG. 6 and the fourth embodiment shown in FIG.
And the structure of That is, the fifth semiconductor region 16 is a shallow n ⁺ inner well region 1 on the gate electrode 21 side.
6a and the deep n-type outer well region 16 on the gate electrode 10 side
The p ⁺ -type deep semiconductor region 20 is formed immediately below the fifth semiconductor region 16. The current amplification factor h _FE of the npn-type transistor Qnpn is reduced by the presence of the n-type outer well region 16b, and the parasitic resistance value can be significantly reduced by the presence of the high-concentration seventh semiconductor region 20. Therefore, the latch-up resistance can be increased synergistically, and the controllable current capacity can be increased. In this case as well, as in the fourth embodiment, it is important that the n-type outer well region 16b has a lower concentration than the n ⁺ -type inner well region 16a, and does not have to be particularly deep.

Sixth Embodiment FIG. 9 is a sectional view showing a structure of a thyristor semiconductor device having a double gate according to a sixth embodiment of the present invention. This embodiment is a modification of the fifth embodiment, in which the fifth semiconductor region 16 is an overlap region of a shallow n ⁺ -type inner well region 16a on the gate electrode 21 side and a deep n-type well outer region 16b on the gate electrode 10 side. Thus, the well end side of the p-type third semiconductor region 4 is formed as a high concentration region 4b higher than the concentration of the inner region 4a. The current amplification factor h _FE of the npn type transistor Qnpn including the n ⁺ type inner well region 16a is low,
In addition, since the parasitic resistance value can be reduced, the latch-up resistance can be increased. However, when the concentration of the high-concentration region 4b at the well end becomes about p ⁺ -type, the first MOSFET
Since the threshold voltage of Twelve becomes high, it is necessary to adjust the density in consideration of this point.

Seventh Embodiment FIG. 10 is a sectional view showing the structure of a thyristor semiconductor device having a double gate according to a seventh embodiment of the present invention. In this example, the fifth semiconductor region 16 is formed as an n ⁺ -type region, and the well end side of the p-type third semiconductor region 4 is formed as a high-concentration region 4b higher than the concentration of the inner region 4a. IG
Since the parasitic resistance value of the hole extraction current path in the BT state can be reduced, the latch-up resistance can be increased. Also in this example, when the concentration of the high-concentration region 4b on the well end side becomes about p ⁺ -type, the threshold voltage of the first MOSFET increases, so that the concentration is adjusted in consideration of this point.

Eighth Embodiment FIG. 11 is a sectional view showing a structure of a thyristor semiconductor device having a double gate according to an eighth embodiment of the present invention. This embodiment is characterized in that the p-channel type second MOSFET 23 has a depletion type structure. Second
A low-concentration surface layer p doped with a p-type impurity is formed on the surface side channel portion of the n-type fourth semiconductor region 15 constituting the back gate of the double diffusion type MOSFET of the MOSFET 23.
The mold region 30 is formed with no gate voltage applied.

In the first to seventh embodiments, the enhancement-type n-channel first MOSFET 12 is turned off at a gate voltage of 0 V, and the gate voltages of 10 to 15 are applied.
V turns on. On the other hand, the enhancement-type p-channel second MOSFET 23 is turned on at a gate voltage of −10 V and turned off at a gate voltage of 0 V.

Therefore, the gate drive circuit requires a negative power supply (−10 V) in addition to the positive power supply (+10 to 15 V). In order to simplify the configuration of the gate circuit system, in this example, as described above, the surface layer p-type region 30 is formed, and the second MOSFET 23 is of a depletion type. For this reason, the second MOSFET 23 is turned on at a gate voltage of 0 V, the depletion layer expands to a low concentration surface p-type region 30 at a gate voltage of 10 to 15 V and turned off, and the gate voltage is exclusive of that of the first MOSFET 12. Open (close) symmetrically. Therefore, the control system of the present semiconductor device can be operated with a single power supply. Of course, the first MOSFET 12 may be of a depletion type.

Ninth Embodiment FIG. 12 is a sectional view showing the structure of a thyristor semiconductor device having a double gate according to a ninth embodiment of the present invention. In this example, a second gate electrode 121 of polycrystalline silicon is buried in a trench groove dug in the center of the sixth semiconductor region 17 and the fourth semiconductor region 15 via a gate insulating film 121a, and a trench gate type is formed. Of the second MOSFET 12
3. In the IGBT state, the gate electrode 21 is provided in a hole extraction path toward the second cathode electrode 18b.
Trench gate type MOSF in addition to the horizontal channel directly below
Since the vertical channels on both sides of the gate electrode 121 of the ET 123 are increased in parallel, the channel width is increased as a whole, the hole extraction force is increased, and the turn-off time can be shortened. Further, since the hole extraction current is dispersed immediately below the fifth semiconductor region 16, the voltage drop due to the parasitic resistance can be suppressed, and the latch-up resistance can be increased.

Embodiment 10 FIG. 13 is a sectional view showing a structure of a thyristor semiconductor device having a double gate according to Embodiment 10 of the present invention. In this example, only the trench-type second MOSFET 123 is formed as the hole extraction MOSFET. Further, a trench gate type first MOSFET 112 is formed as an electron injection MOSFET. The trench type MOSFET 112 is formed by forming a first trench of polycrystalline silicon through a gate insulating film 110 a in a trench trench dug at the center of the fifth semiconductor region 16 (well end of the third semiconductor region 4).
Gate electrode 110 is embedded. The first MOSFET 112 shown in FIG. 12 is a vertical DMOS (VDOS)
Because of the structure, electrons flow from the horizontal channel directly below the gate electrode 10 while changing the direction in the vertical direction.
In order to reduce the pinch resistance of the drift portion, it is necessary to widen the gate length of the gate electrode 10 to about 20 to 30 μm and widen the resistance sectional area of the drain drift portion. However, as in this example, the trench gate type MOSFE
When T112 is employed, an electron current flows in the vertical direction from the beginning along the side wall of the gate electrode 110, so that the gate electrode 110 can be miniaturized.
Only about 3 μm is required. Further, since the on-resistance is reduced, the switching loss can be reduced.

[Eleventh Embodiment] FIG. 14 is a sectional view showing a structure of a thyristor semiconductor device having a double gate according to an eleventh embodiment of the present invention. The structure of this example is different from the structure of Example 10 (see FIG. 13) in that the n-type fourth semiconductor region 15 is replaced by the n ⁺ -type fifth semiconductor region 1.
6 and overlapped. Therefore, in the thyristor state, not only the n ⁺ -type fifth semiconductor region 16 but also n
Type fourth semiconductor region 15 also functions as a cathode region,
The cathode current capacity can be increased.

Embodiment 12 FIG. 15 is a sectional view showing a structure of a thyristor semiconductor device having a double gate according to Embodiment 12 of the present invention. In this example, a trench gate type MOSFET is used as the second MOSFET 123, and a pair of gate electrodes 12
1, 121 are opposed to each other. A pair of gate electrodes 1
An n-type fourth semiconductor region 15 is formed on the surface side of the p-type third semiconductor region 4 sandwiched between the first and second semiconductor regions 21 and 121.
On the surface side of the semiconductor region 15, a sixth semiconductor region 17 of p ⁺ type (or p ⁺ type) is formed. In this example,
Since the distance between the pair of gate electrodes 121 can be reduced, the planar occupancy of the fifth semiconductor region 16 can be increased, and the cathode current capacity can be increased.

Embodiment 13 FIG. 16 is a sectional view showing a structure of a thyristor semiconductor device having a double gate according to Embodiment 13 of the present invention. This embodiment is different from the twelfth embodiment shown in FIG.
5 'is epitaxially grown as a p ^- type region. Further, a p ⁺ type (or p ⁺ type) sixth semiconductor region 17 is formed on the surface side of the fourth semiconductor region 15 ′. When a zero voltage is applied to the gate electrode 121, the trench gate type MOSFET 123 is in an ON state.
When a voltage higher than zero voltage is applied to the gate electrode 121, the p ⁻ -type fourth semiconductor region 15 ′ is depleted, and the trench gate type MOSFET 123 is turned off. That is, a trench gate type MOSFET 1 for extracting holes
23 is a depression type. Therefore, the control system of the present semiconductor device can be operated with a single power supply. Of course, the first MOSFET 112 may be of a depletion type.

Embodiment 14 FIG. 17A is a schematic diagram showing a cell pattern of a thyristor semiconductor device having a double gate according to Embodiment 14 of the present invention. The cell of the semiconductor device provided with the double gate has the third semiconductor region 4 formed in the second semiconductor region 3 as a striped well. As described above, in the third semiconductor region 4 of the striped well,
Fifth semiconductor regions 16 are formed at both ends in the width direction of the wells as stripe-shaped wells, and a fourth semiconductor region 15 and a sixth semiconductor region are formed at the center of the stripe-shaped well in the third semiconductor region 4. The region 17 is formed as a double diffusion type stripe well. A short-circuit electrode 18c that is in conductive contact with the third semiconductor region 4 is formed on the surface of the longitudinal end of the third semiconductor region 4. The cathode electrode 18c is connected to the fifth semiconductor region 16 and the sixth semiconductor region 17 by conductive contact with the cathode electrodes 18a and 18b (FIG. 1).
And the first layer electrode wiring. A relatively small wiring resistance exists between the short-circuit electrode 18c and the cathode terminal K.
The equivalent circuit shown in FIG. The equivalent circuit shown in FIG. 17B is different from the equivalent circuit shown in FIG. 2 in that the short-circuit resistance R
_This corresponds to a state where ₀ is inserted.

By the way, since electric field concentration occurs at the corner of the third semiconductor region 4 of the well in the same cell, even if the second MOSFET 23 is turned on to extract holes, the transistor Qnpn remains on. And it is easy to latch up. Since the latch-up easily occurs at the corner, the controllable current capacity is limited in this portion. Therefore,
In this embodiment, a short-circuit resistance R ₀ for directly extracting holes from a corner (end) in the third semiconductor region 4 is provided together with the second MOSFET 23. On the other hand, the first
Of the second MOSFET 2
In the thyristor operation mode in which 3 is off,
The short-circuit resistance R ₀ starts from the corner in the third semiconductor region 4.
Holes leak out through the holes, which may hinder the thyristor operation. Therefore, the first MOSFET 12
Is turned on and the second MOSFET 23 is turned off, in order to enrich the hole density, in this example,
The third and the semiconductor region 4 a striped (elongated) so as to reduce the area ratio occupied by the corner section, forming a short circuit electrode 18c in the width direction across the corner portion C _1, C ₂ in the longitudinal direction of the end portion I have. FIG. 17A shows only one half of the striped third semiconductor region 4, but a similar short-circuit electrode 18c is formed at the other end. In the thyristor state, the longer the end portion of the third semiconductor region 4 in the width direction can secure the current capacity. Leakage of holes at the end where the short-circuit electrode 18c is formed does not pose a significant problem.
Since the IGBT state hole of the corner portion C _1, C ₂ is pulled directly through the short-circuit electrode 18c in the longitudinal direction of the end of the stripe, it is possible to base current of the transistor Qnpn to prevent latch-up in little reduction . As a result, the controllable current capacity can be increased.

When there is no short-circuit resistance R ₀ , the first M
When an anode-cathode voltage is applied while the OSFET 12 and the second MOSFET 23 are turned off,
When the blocking voltage is exceeded, a pnpn thyristor is likely to latch up. Therefore, the voltage between the anode and the cathode is increased after the second MOSFET 23 is turned on. However, in this example, since there is a short-circuit resistance R ₀ , the first MOSFET 12 and the second MOSFET
ET23 while off state, even by applying a voltage between the anode and the cathode, short-circuited through the short circuit resistance R ₀ electrode 18
Since the current leaks to c, it is difficult for the transistor Qnpn to turn on, so that latch-up can be prevented.

Fifteenth Embodiment FIG. 18 is a sectional view showing a structure of a thyristor semiconductor device having a double gate according to a fifteenth embodiment of the present invention. In this example, the second MOSFET 23 (MOS portion) for extracting holes from the third semiconductor region 4 during the IGBT operation is provided in a large number at the center of the well of the third semiconductor region 4. That is, an isolated 3 is formed between the fifth semiconductor regions 16 formed at both ends of the well of the third semiconductor region 4.
Four fourth semiconductor regions 15, 15, 15 are formed, in which sixth semiconductor regions 17, 17, 17 are formed. Then, four second gate electrodes 21 are provided via a gate insulating film. First MOSFET
When the second MOSFET 23 is in the off state and the second MOSFET 23 is in the on state, the thyristor operation starts in the central portion of the well just below the fifth semiconductor regions 16 and 16 at both ends of the well of the third semiconductor region 4 as described above. Because of the spread, even if the area ratio of the first gate electrodes 10, 10 in the cell is low, a sufficient thyristor operation can be performed. Therefore, in this example, a large number of dispersive second MOSFETs 23 are provided in the center to perform hole extraction in a dispersive manner, thereby effectively preventing latch-up, thereby increasing the controllable current. I have.

Embodiment 16 FIG. 19 is a sectional view showing the structure of a thyristor semiconductor device having a double gate according to Embodiment 16 of the present invention. In this embodiment, holes are drawn out from the third semiconductor region 4 during the IGBT operation, so that the second MOSF
A large number of ETs 23 (MOS parts) are provided at the center of the well of the third semiconductor region 4. The central portion of the well is the contact territory <br/> region 32 of the p ⁺ type not covered by the fourth semiconductor region 15 is formed. The short-circuit electrode 18c is in conductive contact with the p ⁺ -type contact region 32. For this reason, holes can be pulled out directly via the short-circuit electrode 18c during the IGBT operation.

Seventeenth Embodiment FIG. 20 is a schematic perspective view showing the structure of a thyristor semiconductor device having a double gate according to a seventeenth embodiment of the present invention. In this example, the stripe-shaped n ⁺ is also provided in a portion sandwiched between the stripe-shaped second gate electrodes 21 and 21 at the center.
An eighth semiconductor region 36 is formed, and the fifth semiconductor region 16 on the well end side of the third semiconductor region 3 and the eighth semiconductor region 36 at the center are connected to the n ⁺ -type constricted connection diffusion layer 16.
M. The cathode electrode 18d is in conductive contact with the central eighth semiconductor region 36.
From the fifth semiconductor region 16 on the well end side to the connection diffusion layer 16M
A diffusion resistance _RM is parasitic on the current path reaching the cathode electrode 18d via the central eighth semiconductor region 36. Therefore, the equivalent circuit of the apparatus as shown in FIG. 21, in a state of diffusion resistance R _M is interposed between the emitter E and the cathode electrode 18d of the transistor Qnpn. When the current in the first MOSFET12 flows when IGBT state, the third diffusion resistance R base voltage of the transistor Qnpn by the voltage drop of the _B semiconductor region 4 but is higher, the emitter of the transistor Qnpn by the voltage drop across the diffusion resistance R _M Since the voltage also becomes higher, the forward voltage between the fifth semiconductor region 16 on the well end side and the third semiconductor region 4 immediately below the fifth semiconductor region 16 does not become relatively high, so that the latch-up of the transistor Qnpn can be suppressed. Thus, the controllable current capacity can be increased. Of course, at the time of the thyristor operation, the cathode current flows through the bottom surface of the central eighth semiconductor region 36, which also contributes to an increase in current capacity.

Embodiment 18 FIG. 22 is a schematic diagram showing a structure of a thyristor semiconductor device having a double gate according to Embodiment 18 of the present invention. In this example, a striped n ⁺ -type eighth semiconductor region 36 is formed at a portion sandwiched between the striped second gate electrodes 21 and 21 at the center, and the first gate electrode 10 A double diffusion structure of the fourth semiconductor region 15 and the sixth semiconductor region 17 is formed in a portion sandwiched between the second semiconductor layer 15 and the second gate electrode 21. Then, the first MO for electron injection
The MOS portion 12a constituting the SFET 12 is located at the center of the eighth portion.
This is the tip of an n ⁺ -type overhanging region 16N that extends from the semiconductor region 36 directly below the first gate electrode 10. Example 1
7 in the same manner as (see FIG. 20), since the protruding region 16N is present diffusion resistance R _N, the transistor Qnpn is hardly latched up at IGBT state. Further, since the hole extraction current flows through the outside just below the second gate electrode 21 as shown by the arrow, the path length can be shortened. Therefore, since it reduces the value of the diffusion resistance R _B of the third semiconductor region 4, Example 1
7, the controllable current capacity can be increased.

[Embodiment 19] FIG. 23A is a schematic perspective view showing the structure of a thyristor semiconductor device having a double gate according to Embodiment 19 of the present invention. In this example, the first gate electrode 10 and the second
The portion of the n ⁺ -type fifth semiconductor region 16 sandwiched between the gate electrodes 21 is separated by the separation layer 4c of the p-type third semiconductor region 4. A gate oxide film 9 is formed on the isolation layer 4c.
Through the overhanging gate electrode portion 10 of the first gate electrode 10
a is straddling. The cathode electrode 18a is in conductive contact with one of the eighth semiconductor regions 36 separated by the p-type separation layer 4c. The eighth semiconductor region 36 to which the cathode electrode 18a makes conductive contact is formed on the p ⁺ -type third semiconductor region 4d. Therefore, as shown in FIG.
Since the p ⁺ -type third semiconductor region 4d has a high concentration immediately below the gate electrode 10 along the line A ', the channel inversion layer is not formed even when a high voltage is applied to the gate electrode 10. But,
As shown in FIG. 23C, the p-type isolation layer 4 is located immediately below the overhanging gate electrode portion 10a of the gate electrode 10 along the line BB '.
c, when a high voltage is applied to the gate electrode 10,
A channel inversion layer is formed below the overhanging gate electrode portion 10a. The overhanging electrode section 10a constitutes a path switching MOS section. When the voltage applied to the first gate electrode 10 at the time of turn-off is reduced, the channel inversion layer immediately below the overhanging gate electrode portion 10a disappears, and thus the region 3 includes the region 3, the region 4, and the region 16 in contact with the cathode electrode 18a. Since the npn-type transistor Qnpn is separated, latch-up can be eliminated. It should be noted that the npn transistor Qnpn composed of the region 3, the p ⁺ -type region 4d and the eighth semiconductor region 36 in contact with the cathode electrode 18a does not operate even with overcurrent because the current amplification factor h _FE is low. In particular, since the overhanging gate electrode portion 10a of this example uses a part of the gate electrode 10, the number of manufacturing steps can be reduced and the size can be reduced.

[Embodiment 20] By the way, as shown in FIG. 24, the chip layout of the semiconductor device having the double gate according to the embodiment 1 is such that the first chip formed at the center of one long side of the semiconductor chip 50 is formed. MO
The first gate pad 51 for the SFET 12 and the second gate 23 for the second MOSFET 23 formed at the center of the edge of the opposite long side.
And a metal (aluminum) wiring extending from the long side to the short side and extending from the first gate pad 51 and a first-level gate wiring (gate runner) 5.
1 a, 51 b, a metal (aluminum) wiring extending from the second gate pad 52 and approaching the first gate pad 51, and a first-layer gate wiring (gate runner) 52.
a, a plurality of stripe-shaped first gate electrodes 10 of polycrystalline silicon extending in a long-side direction from the gate lines 51a and 51b, and extending in a long-side direction from the gate line 52a. A plurality of stripe-shaped second gate electrodes 21 made of polycrystalline silicon, and two first gate electrodes 10, 10 and two second gate electrodes 21 sandwiched therebetween. 21 form the striped cells C _{1 to} C _n .

In the IGBT operation mode of the semiconductor device, as shown in FIG.
An electron current (solid line) for electron injection flows through the channel of the first MOSFET 12 at the well end of the semiconductor region 4 into the fifth semiconductor region 16, and a hole current (dashed line) follows the electron current. From the second semiconductor region 3, it passes right below the fifth semiconductor region 16 via the well end of the third semiconductor region 4 and flows to the sixth semiconductor region 17 via the channel of the second MOSFET 23. First
When a low-level gate signal is applied to the first gate pad 51 to turn off the MOSFET 12, the cell C ₁ near the gate pad 51 is immediately switched to the off state, but the propagation delay (the resistance between the wiring resistance and the wiring) the capacity), the arrival of the low level of the gate signal is delayed to the distant cell C _n from the gate pad 51. Therefore, at the time of turn-off, since the current of the short-range cell that is turned off earlier sequentially cumulatively spread to distant cell that is not yet turned off, excessive distally MOS portion of the farthest cell C _n from the gate Tsu pad 51 It is easy to break down due to the flow of current. This tendency is particularly strong in the case of an inductance load. Therefore, the reduction of the turn-off time and the increase of the controllable current capacity are in a trade-off relationship.

FIG. 25 is a chip layout diagram of a thyristor semiconductor device having a double gate according to the twentieth embodiment. The chip layout of the present example includes a first gate pad 61 for the first MOSFET 12 formed at the center of one long side of the semiconductor chip 60 and a second gate 23 formed at the center of the long side of the opposing long side. Second gate pad 6
2, metal (aluminum) wiring first-layer gate wirings (gate runners) 61a and 61b extending from the long side to the short side and extending from the first gate pad 61;
A metal (aluminum) wiring extending from the second gate pad 62 to reach the vicinity of the first gate pad 61; a first-layer gate wiring (gate runner) 62a; A plurality of stripe-shaped first gate electrodes 10 of polycrystalline silicon extending in a comb shape
And a plurality of stripe-shaped second gate electrodes 21 of polycrystalline silicon extending in a long-side direction from the gate wiring 62a in a comb-like shape. Two first gate electrodes 10,
10 and two second gate electrodes 21 interposed therebetween,
21 form the striped cells C _{1 to} C _n . In the present example, as shown in FIG. 26, a first-layer metal (aluminum) wiring 65 (gate runner) that is conductively connected to each gate electrode 10 across the stripe-shaped gate electrodes 10 and 21 is formed. Are formed in a lattice shape. Therefore, since the reduction of the wiring resistance of a plurality of gate lines 65 at the gate Tsu pad 51 to the furthest cell C _n is realized, the propagation delay of the gate signal decreases, the cell C ₁ -C _n current at turn-off deviation of the distribution can be relaxed, current concentration at the farthest cell C _n is suppressed. Thus, faster turn-off, of course, it is possible to increase the controllable current capacity because destruction in the farthest cell C _n is less likely to occur.

Embodiment 21 FIG. 27A is a chip layout diagram of a thyristor semiconductor device having a double gate according to Embodiment 21. The chip layout of the present example includes a rectangular first gate electrode 10 of polycrystalline silicon formed at a lattice point on a chip plane;
A metal (aluminum) wiring conductive to each first gate electrode 10 through a contact hole H; a first-layer lattice gate wiring 110; and polycrystalline silicon running between adjacent first gate electrodes 10, 10 And two second gate electrodes 21 vertically and horizontally. Therefore, one cell divided by the lattice gate wiring 110 is divided into nine by the second gate electrode 21. The fifth semiconductor region 16 is formed in the center section and the diagonal section of the nine sections,
The remaining sections include the fourth semiconductor region 15 and the sixth semiconductor region 1
7 are formed. The cathode electrode layer 18 conductively connected to the fifth semiconductor region 16 and the sixth semiconductor region 17 is formed as a second layer of metal (aluminum) wiring.

In this example, the first gate electrode 10 is formed for each grid point, and these grid points are
, The propagation delay is suppressed even in cells far from the gate pad. Therefore, it is possible to increase the speed of turn-off and increase the controllable current capacity.

In this embodiment, since the second gate electrode 21 is also formed in a vertical and horizontal lattice, the signal delay is reduced even in a cell far from the gate pad, contributing to a faster turn-on.

Further, the fifth region 16 occupies the central section and the diagonal section in one cell, and is formed in a dispersed and wide manner. Therefore, the current capacity can be increased during the thyristor operation. Since the sixth region 17 is formed in a checkered arrangement with respect to the fifth region 16,
Hole extraction in the IGBT operation can be performed in a distributed manner, which contributes to an increase in latch-up resistance.

[Embodiment 22] FIGS. 28A to 28D are process sectional views showing a method for manufacturing a basic structure of the present invention. As shown in FIG. 1, n ⁺ is formed through an n ⁺ type buffer layer 3a formed on a p ⁺⁺ type semiconductor substrate.
^{After the-} type second semiconductor region 3 is formed by epitaxial growth, the first MOSFET gate electrode 10 made of polycrystalline silicon is formed at a position separated by a gate oxide film 9 thereon as shown in FIG. , 10 and the second MOSFET gate electrodes 21 and 21 are formed at intermediate positions. Thereafter, boron (B) ions are implanted at a dose of 7 × 10 ¹³ cm ^{−2 using} the gate electrodes 10, 10, 21 and 21 as a mask.

Next, as shown in FIG. 28B, an opening between the outer gate electrode 10 and the inner gate electrode 21 is covered with a resist 42, and then the gate electrodes 10, 10, 21,.
21 and the gate electrodes 21 and 22 using the resist 42 as a mask.
Performing ion implantation of arsenic (As) or antimony (Sb) in a dose of 7 × 10 ¹³ cm ^-2 through the opening between the 1.

Then, after removing the resist 42, FIG.
As shown in FIG. 8 (c), two types of impurities are simultaneously thermally diffused by drive-in at 1150 ° C. for 3 hours, and a well of a deep p-type third semiconductor region 4 and a shallow n-type fourth semiconductor therein. A well in the region 15 is formed. When simultaneous thermal diffusion is not performed, boron (B) is thermally diffused by drive-in at 1150 ° C. for 3 hours, and arsenic (As), antimony (Sb) or phosphorus (P) is thermally diffused at 1100 ° C. for 2 hours. Let it. In the process of thermal diffusion of the p-type third semiconductor region 4, as shown in FIG.
28. The p-type diffusion layers 4s, 4s diffused from a are connected to each other immediately below the gate electrode 21 by lateral diffusion, and FIG.
As shown in (c), a single well of the p-type third semiconductor region 4 is formed. Therefore, the p-type third semiconductor region 4
Are self-aligned (self-aligned) after forming the gate electrodes 10, 10, 21, 21 using them as a mask.
Therefore, the number of steps can be reduced and the accuracy of forming a semiconductor region can be increased.

Here, considering the conditions for interconnecting the p-type diffusion layers 4s, 4s diffused from the openings 21a, 21a immediately below the gate electrode 21, the longitudinal direction of thermal diffusion of the acceptor impurity (boron) is considered. In general, the following expression is established between the diffusion length X _J (in the depth direction) and the lateral diffusion length Y _J. Y _j = (0.7-0.8) X _j (1) Accordingly, the gate length L of the gate electrode 21 must satisfy the following equation. L <2X _j ≒ 1.6 X _j (2) For example, when X _j = 3 μm, if the gate length L is shorter than 4.8 μm, the diffusion layers 4s, 4s are interconnected directly under the gate electrode 21 in the thermal diffusion step. Then, a single well of the third p-type third semiconductor region 4 can be formed successfully. The fact that the third semiconductor region 4 can be formed by interconnection ensures the formation of the gate electrodes 10, 10, 21, 21 even in one step, and contributes to a reduction in the number of steps.

In this embodiment, boron, arsenic, or antimony is used as the acceptor impurity so that the diffusion coefficient becomes larger than that of the donor impurity. Therefore, the p-type third semiconductor region 4 having a deep well and the fourth semiconductor region 15 having a shallow well can be simultaneously diffused and formed in one drive-in step, which contributes to a reduction in the number of steps.

Thereafter, the gate electrodes 10, 10, 21, 22
1 as a mask, ion implantation of arsenic (As) with a dose of 5 × 10 ¹⁵ cm ⁻² is performed again.
Dose amount 2 × 10 using 0, 10, 21, 21 as a mask
BF ₂ ions of ¹⁵ cm ⁻² are implanted. And FIG.
As shown in (d), the shallow p-type sixth semiconductor region 17 having a shallow surface layer of the n-type fourth semiconductor region 15 is formed by annealing at 1000 ° C. for 10 minutes, and the n ⁺ -type fifth semiconductor region is formed. 16 are formed. The reason for using BF _{2 is} that the depth of the p ⁺ -type sixth semiconductor region 17 can be set to about 0.5 μm because the range of ion implantation becomes shallow. The n-type fifth semiconductor region 16 and p ⁺
The sixth semiconductor region 17 of the mold can be simultaneously formed by diffusion, which contributes to a reduction in the number of steps.

Thereafter, a cathode electrode 18 is formed by making holes in an interlayer insulating film (not shown), and a passivation film (not shown) is formed thereon. As described above, in this example, the third semiconductor region 4, the fourth semiconductor region 15, the n-type fifth semiconductor region 16 and the sixth semiconductor region 17 are self-aligned using the gate electrodes 10, 10, 21, 21 as a mask. All can be formed, and characteristic variations can be reduced.

However, when the method of forming the well of the third semiconductor region 4 employs the method of interconnecting the diffusion layers 4s, 4s directly below the gate electrode 21 as described above, the latch is formed as described below. There is a possibility that a problem may occur in terms of the up withstand capability. That is, as shown in FIG. 30A, in a semiconductor device using a single well third semiconductor region 4 formed by interconnecting diffusion layers 4s on both sides immediately below a gate electrode 21 by thermal diffusion. A semiconductor surface from the surface of the n ⁺ -type fifth semiconductor region 16 to the surface of the n-type fourth semiconductor region 15 and the p ⁺ -type sixth semiconductor region 17 via the surface of the third semiconductor region 4 immediately below the gate 21. The relationship between the impurity concentration and the position has a distribution as shown in FIG. Since the diffusion layers 4s, 4s are spread right below the gate electrode 21 by lateral diffusion by the side ends A, B of the gate electrode 21 and meet at the central portion 21b, the more the diffusion, the lower the impurity concentration. The central portion 21b immediately below 21 is a particularly low impurity concentration region. For this reason, at the time of the hole extraction in the IGBT operation, from the channel immediately below the n ⁺ -type fifth semiconductor region 16 to the channel immediately below the gate electrode 21 and from the channel of the n-type fourth semiconductor region 15 to the p ⁺ -type sixth semiconductor region 17. Hole current path (FIG. 30)
(Shown by a broken line in (a)), as shown in FIG.
The path potential (the amount of voltage drop) V _AB from the side end A of the gate electrode 21 to the channel end B is an extremely large value compared to the path potential (the amount of voltage drop due to on-resistance) V _BC of the channel. Thus, the gate electrode 21
If there is a low concentration directly below and the diffusion resistance r _B is parasitic, IGB
At the time of hole extraction in the T operation, the voltage immediately below the n ⁺ -type fifth semiconductor region 16 tends to increase due to the voltage drop of the hole current, so that the n ⁺ -type fifth semiconductor region 16 and the p-type third semiconductor region 16
The npn-type bipolar transistor Qnpn constituted by the semiconductor region 4 and the n ⁻ -type second semiconductor region 3 is liable to latch up, and the controllable current capacity cannot be increased.

Here, the impurity concentration immediately below the gate electrode 21 decreases as the gate length L increases, so that the gate length L may be reduced. However, the gate electrode 21 is generally formed in a stripe shape (for example, 5 mm) in order to increase the gate width and increase the current capacity. On the semiconductor chip, the gate electrode 21 has a comb-like shape extending from the gate runner (main wiring) extending from the gate pad. Gate electrodes (branch wiring)
Since the gate electrode 21 extends, a time lag occurs between the gate signal and the gate electrode 21 which is farther from the gate pad than the gate electrode 21 near the gate pad. is there. Therefore, there is a limit to the reduction of the gate length of the polycrystalline silicon gate electrode 21 in order to reduce the wiring resistance of the striped gate electrode 21 to suppress the signal delay and increase the operation switching speed.

[Embodiment 23] Therefore, in the present embodiment, in order to reduce the gate length, the second M
Instead of using the gate electrode 21 of the OSFET 23 as a polycrystalline silicon gate, a gate of a single layer structure of a metal or metal silicide having a lower resistivity than polycrystalline silicon, a polycrystalline silicon layer and a metal or metal silicide layer 2 The gate has a double structure. With such a gate electrode using a metal or metal silicide, it is possible to avoid the disadvantage that the propagation delay becomes remarkable even if the gate length L is reduced, and it is possible to increase the impurity concentration immediately below the gate electrode 21 and controllability. The current capacity can be increased. Note that the second MOSFET 2
3 as well as the first MOSFET 2
The third gate electrode 10 may also be a gate having a single layer structure of metal or metal silicide, or a gate having a double structure of a polycrystalline silicon layer and a layer of metal or metal silicide. This leads to an improvement in the operation switching speed, and the turn-on time can be further reduced.

[Embodiment 24] FIGS. 31A to 31D are process sectional views showing another method of manufacturing the basic structure of the present invention. In the manufacturing method of this example, the gate electrodes 21 and 10 are not formed at the same time, and the gate electrode 21 is formed after ion implantation of boron (an acceptor impurity for the fourth semiconductor region 15).

That is, as shown in FIG. 1, after forming an n ⁻ type second semiconductor region 3 by epitaxial growth via an n ⁺ type buffer layer 3a formed on a p ⁺⁺ type semiconductor substrate, FIG. As shown in a), a gate oxide film 9 is formed thereon.
First MOS of polycrystalline silicon at a position separated through
The FET gate electrodes 10 and 10 are formed. Thereafter, the dose is 7 × 10 ¹³ using the gate electrodes 10 and 10 as a mask.
Boron (B) of cm ^-2 is ion-implanted into the opening.

Next, as shown in FIG. 31B, the second MOSFET gate electrode 2 made of polycrystalline silicon is located at a position separated by the gate oxide film 9 between the gate electrodes 10 and 10.
After forming the gate electrodes 10 and 21, the opening between the outer gate electrode 10 and the inner gate electrode 21 is covered with a resist 42, and then the gate electrodes 10, 10, 21 and 21 are formed.
Is used as a mask, ions of arsenic (As) or antimony (Sb) are implanted at a dose of 7 × 10 ¹³ cm ⁻² through an opening between the gate electrodes 21 and 21.

In the subsequent steps, as in the embodiment shown in FIG. 28, after removing the resist 42, as shown in FIG. 31C, two kinds of impurities are simultaneously thermally diffused by drive-in at 1150 ° C. for 3 hours. Then, a well of the deep p-type third semiconductor region 4 and a well of the shallow n-type fourth semiconductor region 15 are formed therein. When not performing simultaneous thermal diffusion, add boron (B)
Thermal diffusion by drive-in at 1150 ° C for 3 hours, arsenic (As), antimony (Sb) or phosphorus (P)
Heat diffusion at 2 ° C for 2 hours. After this, the gate electrode 1
Using 0, 10, 21, 21 as a mask, the dose amount 5 × again
Arsenic (As) ions of 10 ¹⁵ cm ⁻² are implanted, and subsequently, BF ₂ ions of a dose of 2 × 10 ¹⁵ cm ⁻² are implanted using the gate electrodes 10, 10, 21 and 21 as a mask.

Then, as shown in FIG.
C, n-type fourth semiconductor region 15 by annealing for 10 minutes
The p-type sixth semiconductor region 17 having a shallow surface layer is formed, and the n ⁺ -type fifth semiconductor region 16 is formed. In one drive-in step, the n-type fifth semiconductor region 16 and the p ⁺ -type sixth semiconductor region 17 can be simultaneously formed by diffusion, which contributes to the reduction in the number of steps. Thereafter, an interlayer insulating film (not shown)
Then, a cathode electrode 18 is formed, and a passivation film (not shown) is formed thereon. Of course, the ion implantation / diffusion of the fifth semiconductor region 16 and the sixth semiconductor region 17
May be performed separately.

As described above, in the manufacturing method of the present example, the third semiconductor region 4 is formed so that the impurity concentration in the region directly below the gate electrode 21 in the third semiconductor region 4 is not made lower than in other portions. Therefore, the gate electrode 21 is provided thereon. Therefore, the latch-up resistance can be increased without reducing the gate length of the gate electrode 21 made of polycrystalline silicon. Of course, the gate electrode 10,
The gate 21 may be a single-layer metal or metal silicide gate, or a double-layer gate of a polycrystalline silicon layer and a metal or metal silicide layer, instead of a single-layer polysilicon layer. Since the propagation delay amount can be reduced by shortening the gate length, the operation switching speed is improved and the controllable current capacity is increased.

Embodiment 25 FIGS. 32A to 32E are process cross-sectional views showing still another method of manufacturing the basic structure of the present invention. In the manufacturing method of this example, the gate electrodes 21 and 10 are not formed at the same time, and the gate electrode 21 is formed after the diffusion formation of the third semiconductor region 4.

That is, as shown in FIG. 1, after forming an n ⁻ type second semiconductor region 3 by epitaxial growth via an n ⁺ type buffer layer 3a formed on a p ⁺⁺ type semiconductor substrate, FIG. As shown in a), a gate oxide film 9 is formed thereon.
First MOS of polycrystalline silicon at a position separated through
The FET gate electrodes 10 and 10 are formed. Thereafter, the dose is 7 × 10 ¹³ using the gate electrodes 10 and 10 as a mask.
Boron (B) of cm ^-2 is ion-implanted into the opening. Then, as shown in FIG. 32B, the well of the p-type third region 4 is formed by diffusion by drive-in.

Thereafter, as shown in FIG. 32C, the second MOSFET gate electrodes 21 and 21 made of polycrystalline silicon are formed at positions separated by the gate oxide film 9 between the gate electrodes 10 and 10. Thereafter, the opening between the outer gate electrode 10 and the inner gate electrode 21 is covered with a resist 42,
Thereafter, arsenic (As), antimony (Sb) or phosphorus having a dose of 7 × 10 ¹³ cm ⁻² is passed through the opening between the gate electrodes 21 and 21 using the gate electrodes 10, 10, 21 and 21 as a mask. The ion implantation of (P) is performed. Then, as shown in FIG.
The region 15 is formed by diffusion.

Thereafter, the gate electrodes 10, 10, 21, 22
1 as a mask, ion implantation of arsenic (As) with a dose of 5 × 10 ¹⁵ cm ⁻² is performed again.
Dose amount 2 × 10 using 0, 10, 21, 21 as a mask
BF ₂ ions of ¹⁵ cm ⁻² are implanted. And FIG.
As shown in (e), the n-type fifth semiconductor region 16 and the p ⁺ -type sixth semiconductor region 17 are simultaneously diffused by drive-in. Of course, the ion implantation / diffusion of the fifth semiconductor region 16 and the ion implantation / diffusion of the sixth semiconductor region 17 may be performed separately.

Also in such a manufacturing method, since the impurity concentration in the region directly below the gate electrode 21 in the third semiconductor region 4 is equal to that of the other portions, the gate length of the polycrystalline silicon gate electrode 21 can be reduced. The latch-up tolerance can be increased. Of course, in this example, the gate electrodes 10 and
The gate 21 may be a single-layer metal or metal silicide gate or a double-layer gate of a polycrystalline silicon layer and a metal or metal silicide layer without using a single polysilicon layer.

Embodiment 26 FIG. 33 is a sectional view showing a structure of a thyristor semiconductor device having a double gate according to Embodiment 26 of the present invention. In the semiconductor structure of this embodiment, a well of a p ⁺ type ninth semiconductor region 33 is formed as a drift region from the region immediately below the fifth semiconductor region 16 to the region immediately below the gate electrode 21 with respect to the basic structure of the first embodiment. Is embedded.

Since the p ⁺ type ninth semiconductor region 33 immediately below the gate electrode 21 except for the channel (the surface layer of the fourth semiconductor region 15), the value of the diffusion resistance r _B immediately below the gate electrode 21 is obtained. Can be further reduced. Therefore, the latch-up tolerance can be increased.

The method of manufacturing the semiconductor structure shown in FIG. 33 will be described. First, as shown in FIG. 33, an n ⁻ -type second layer is formed via an n ⁺ -type buffer layer 3a formed on a p ⁺⁺ -type semiconductor substrate. After the semiconductor region 3 is formed by epitaxial growth, a gate oxide film 9 is formed thereon as shown in FIG.
First MOS of polycrystalline silicon at a position separated through
The FET gate electrodes 10 and 10 are formed. Thereafter, the dose is 7 × 10 ¹³ using the gate electrodes 10 and 10 as a mask.
Ion implantation of boron (B) of cm ⁻² into the opening is performed, and a well of the p-type third semiconductor region 4 is diffused by drive-in.

[0118] After this, as shown in FIG. 34 (b), through the opening between the gate electrodes 10, 10 by using a resist mask dose 7 × 10 ¹³ cm ^-2 of arsenic (As), antimony (Sb) Alternatively, phosphorus (P) ions are implanted, and the n-type fourth semiconductor region 15 having a shallow well is diffused by drive-in.

Then, using a resist mask, B ⁺ or BF ₂ is superimposed on the gate electrode 12 side of the fourth semiconductor region 15.
Then, as shown in FIG. 34C, a well of the p ⁺ type ninth semiconductor region 33 is diffused by drive-in.

Next, as shown in FIG. 34D, a second portion of the polycrystalline silicon is interposed via the gate oxide film 9 so as to cover the surface boundary between the fourth semiconductor region 15 and the ninth semiconductor region 33. Gate electrodes 21 and 21 for MOSFET are formed. Thereafter, ions of BF ₂ are implanted through openings between the gate electrodes 21 and 21 using the gate electrodes 10, 10, 21 and 21 as a mask and the gate electrode 2 is formed.
Arsenic (As) or antimony (Sb) ions are implanted through the opening between the first and the tenth. Then, the p ⁺ -type sixth semiconductor region 17 and the n ⁺ -type fifth semiconductor region 16 are formed by self-alignment by annealing. Thereafter, a cathode electrode 18 is formed by making holes in an interlayer insulating film (not shown), and a passivation film (not shown) is formed thereon.

The conductivity type of each region in this embodiment may be the opposite conductivity type.

[0122]

As described above, in the semiconductor device according to the present invention, the MISFET for majority carrier injection is used.
The MISFET for extracting majority carriers has a double diffusion structure so that the MISFET for extracting majority carriers has the opposite conductivity type.

Therefore, the following effects can be obtained.

(1) Majority carriers in the third semiconductor region can be directly extracted via the first conductivity type MISFET, and a short-circuit electrode for carrier conversion is not required. Therefore, it is possible to avoid the difficulty of forming a fine electrode and the two-layer structure of electrode wiring. Further, since the first conductivity type MISFET has a double diffusion type structure, a short channel can be realized.
The ON resistance of the MISFET itself can be reduced. Therefore, the switching loss can be reduced, the speed of majority carrier extraction can be increased, and the turn-off speed can be increased. Further, variation in characteristics of the MISFET can be suppressed.

In particular, according to the present invention, in the third semiconductor region,
The entire well end region from immediately below the fifth semiconductor region to the outside is
3 High concentration higher than the impurity concentration in the inner region of the semiconductor region
It is a region. Since the parasitic resistance value of the majority carrier extraction current path in the IGBT state can be reduced, the latch-up resistance can be increased.

( 2 ) In a structure in which the fifth semiconductor region is an overlapping region of an inner well region having a high impurity concentration and an outer well region having a low impurity concentration, the inner well region functions as a substantial cathode region in a thyristor state. And IGBT
During operation, the voltage around the outer well region decreases due to the voltage drop of the diffusion resistance, but the current amplification factor at that portion is low, so it is difficult to latch up during IGBT operation. Therefore, the controllable current capacity can be increased.

( 3 ) In a structure in which a high-concentration seventh semiconductor region of the first conductivity type is formed immediately below the fifth semiconductor region, the parasitic resistance can be reduced, so that latch-up in the IGBT state is suppressed. Thus, the controllable current value can be increased.

Particularly, the seventh semiconductor region corresponds to the fifth semiconductor region.
A well region shallow enough to leave a portion of the third semiconductor region immediately below
Is larger than when a deep well region is formed.
It is not necessary to increase the ON voltage in the iristor state.

( 4 ) In a structure in which the ninth semiconductor region of the first conductivity type having a high impurity concentration is formed in the third semiconductor region immediately below the gate electrode of the MISFET of the first conductivity type, the value of the diffusion resistance immediately below the gate electrode is obtained. Can be reduced, so that the latch-up resistance can be increased.

( 5 ) If one of the first conductivity type MISFET and the second conductivity type MISFET is an enhancement type and the other is a depletion type, the gate voltage of the MISFET and the ON / OFF control of either MISFET are set to the positive power supply. Alternatively, since the operation can be performed using one of the negative power supplies, the gate drive circuit can be simplified.

( 6 ) In a structure in which a short-circuit electrode connected to an electrode that is in conductive contact with the fifth semiconductor region is connected to the third semiconductor region, majority carriers in the third semiconductor region are directly extracted in the transistor state. The controllable current value can be increased. In particular, in the structure in which the third semiconductor region is a stripe-shaped well and the short-circuit electrode is formed on the surface of the well in the longitudinal direction, latch-up at the corner can be suppressed and the thyristor can be suppressed. Also in the operation mode, the majority carrier density in the third semiconductor region can be increased. Further, even if the voltage between the anode and the cathode is applied while the MISFET of the first conductivity type and the MISFET of the second conductivity type are turned off, the current leaks to the cathode via the short-circuit electrode. Up can be prevented.

( 7 ) A structure in which a plurality of first-conductivity-type MISFET sections for majority carrier extraction are formed in a region between a pair of fifth semiconductor regions formed at opposed well ends of the third semiconductor region. In, the majority carrier extraction in the IGBT state can be enhanced, and the controllable current can be increased.

( 8 ) In the structure in which the well-shaped eighth semiconductor region of the first conductivity type is formed on the surface side of the third semiconductor region between the plurality of first conductivity type MISFET portions for extracting majority carriers, Since the current collecting capability of the eight semiconductor regions is increased, the current capacity at the time of the thyristor can be increased.

( 9 ) A double diffusion structure of the fourth semiconductor region and the sixth semiconductor region formed on the opposite well end side of the third semiconductor region, and a region interposed between these double diffusion structures. In the case of adopting a configuration including the first semiconductor type eighth semiconductor region formed in a well shape on the surface side of the three semiconductor regions, the current path for extracting majority carriers can be shortened. Increase can be achieved.

( 10 ) In the structure in which the fifth semiconductor region and the eighth semiconductor region are connected via the first conductive type connection diffusion layer, and the electrode is brought into conductive contact with the eighth semiconductor region, the fifth semiconductor region A diffusion resistance is parasitic on a current path from the first through the connection diffusion layer and the eighth semiconductor region to the electrode.
Due to the voltage drop of the diffusion resistance, the forward voltage between the fifth semiconductor region on the well end side and the third semiconductor region immediately below the fifth semiconductor region does not become relatively high, so that latch-up can be suppressed and the controllable current capacity is increased. be able to.

( 11 ) Second conductivity type MIS for path switching for conducting / cutting off the fifth semiconductor region and the eighth semiconductor region
In the structure in which the FET is formed and the electrode is brought into conductive contact with the eighth semiconductor region, turning on the second MISFET for path switching at the time of turn-off causes the current flowing through the fifth semiconductor region to disappear, so that the latch-up occurs. Can be eliminated. In particular, the second conductive type MISFET is used as the gate electrode of the path switching second conductive type MISFET.
When a part of the gate electrode of ET is used, the number of manufacturing steps can be reduced and the size can be reduced.

( 12 ) A plurality of gate electrodes of the second conductivity type MISFET are arranged side by side in a stripe on the chip layout, and a plurality of gate wirings connected to the gate pad are arranged in a grid on the plurality of gate electrodes. When a conductive configuration is employed, the propagation delay of the gate signal is reduced, and current concentration at the farthest gate electrode during turn-off is suppressed. For this reason, of course, the turn-off speed is increased,
Breakdown at the farthest gate electrode is less likely to occur, and controllable current capacity can be increased.

( 13 ) The gate electrode of the second conductivity type MISFET has an island shape provided at a lattice point on a chip layout, and a plurality of gate wirings connected to a gate pad are electrically connected to the gate electrode in a lattice shape. In the case where a configuration in which the in-grating region divided by the gate wiring is divided by the lattice-shaped gate electrode of the first conductivity type MISFET is adopted,
Since the propagation delay is suppressed even at the gate electrode of the second conductivity type MISFET far from the gate pad, it is possible to increase the turn-off speed and increase the controllable current capacity.

Further, since the gate electrodes of the first conductivity type MISFET are also formed in a vertical and horizontal lattice, it contributes to a high-speed turn-on. Since the region within one lattice is divided by the gate electrode, the current capacity can be increased during the thyristor operation. In addition, majority carriers can be extracted in an IGBT operation in a distributed manner, which contributes to an increase in latch-up tolerance.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a thyristor semiconductor device including a double gate according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit of the semiconductor device according to the first embodiment.

FIG. 3A is an explanatory diagram showing a flow of an electron current and a hole current in a thyristor state of the semiconductor device according to the first embodiment;
(B) shows the transistor state (I) of the semiconductor device of the first embodiment.
FIG. 4 is an explanatory diagram showing flows of an electron current and a hole current in a GBT state).

4 is a waveform diagram showing the relationship between the first gate electrode and between the second potential applied to the gate electrode of the anode-cathode voltage V _AK and anode current I _A in the semiconductor device of the first embodiment.

FIG. 5 is a cross-sectional view illustrating a structure of a thyristor semiconductor device including a double gate according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a structure of a thyristor semiconductor device including a double gate according to a third embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a structure of a thyristor semiconductor device including a double gate according to a fourth embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a structure of a thyristor semiconductor device including a double gate according to a fifth embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a structure of a thyristor semiconductor device including a double gate according to a sixth embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating a structure of a thyristor semiconductor device including a double gate according to a seventh embodiment of the present invention.

FIG. 11 is a cross-sectional view illustrating a structure of a thyristor semiconductor device including a double gate according to an eighth embodiment of the present invention.

FIG. 12 is a cross-sectional view illustrating a structure of a thyristor semiconductor device including a double gate according to a ninth embodiment of the present invention.

FIG. 13 is a cross-sectional view illustrating a structure of a thyristor semiconductor device including a double gate according to a tenth embodiment of the present invention.

FIG. 14 is a sectional view showing a structure of a thyristor semiconductor device including a double gate according to Example 11 of the present invention.

FIG. 15 is a cross-sectional view illustrating a structure of a thyristor semiconductor device including a double gate according to Example 12 of the present invention.

FIG. 16 is a sectional view showing a structure of a thyristor semiconductor device including a double gate according to Embodiment 13 of the present invention.

17A is a schematic perspective view showing a cell pattern of a thyristor semiconductor device having a double gate according to Embodiment 14 of the present invention, and FIG. 17B is a circuit diagram showing an equivalent circuit thereof.

FIG. 18 is a cross-sectional view illustrating a structure of a thyristor semiconductor device including a double gate according to Embodiment 15 of the present invention.

FIG. 19 is a sectional view showing a structure of a thyristor semiconductor device including a double gate according to Example 16 of the present invention.

FIG. 20 is a schematic perspective view showing the structure of a thyristor semiconductor device having a double gate according to Example 17 of the present invention.

FIG. 21 is a circuit diagram showing an equivalent circuit of the semiconductor device of Example 17;

FIG. 22 is a schematic perspective view showing the structure of a thyristor semiconductor device having a double gate according to Embodiment 18 of the present invention.

23A is a schematic perspective view showing a structure of a thyristor semiconductor device having a double gate according to Embodiment 19 of the present invention, and FIG. 23B is a sectional view taken along line AA ′ in FIG. (C) is an arrow view taken along the line BB 'in (a).

FIG. 24 is a plan view illustrating a chip layout of the thyristor semiconductor device including the double gate according to the first embodiment.

FIG. 25 is a plan view showing a chip layout of a thyristor semiconductor device having a double gate according to Example 20 of the invention.

FIG. 26 is a schematic perspective view taken along the line BB ′ in FIG. 25.

FIG. 27A is a plan view showing a chip layout of a thyristor semiconductor device having a double gate according to Example 21 of the present invention, and FIG. 27B is a sectional view taken along line AA ′ in FIG. FIG. FIG.

FIGS. 28 (a) to (d) are process cross-sectional views illustrating a method for manufacturing a basic structure of the present invention (Example 22).

FIG. 29 is an explanatory diagram showing a method for forming the third semiconductor region in Example 22.

FIG. 30A is a cross-sectional view showing a structure immediately below a second gate electrode of a semiconductor device formed by using the manufacturing method of Example 22, and FIG. 30B shows a surface concentration distribution in FIG. (C) is a graph showing the relationship between the position of the broken line (hole current path) in (a) and the potential.

FIGS. 31A to 31D are process cross-sectional views illustrating another method (Example 24) for manufacturing a basic structure of the present invention.

32 (a) to (e) are process cross-sectional views illustrating still another method (Example 25) of manufacturing the basic structure of the present invention.

FIG. 33 is a sectional view showing a structure of a thyristor semiconductor device including a double gate according to Example 26 of the present invention.

FIGS. 34A to 34E are cross-sectional views illustrating a method for manufacturing the semiconductor device of Example 26. FIGS.

FIG. 35 is a cross-sectional view showing an example of the structure of a conventional double-gate semiconductor device.

36 is a circuit diagram showing an equivalent circuit of the semiconductor device shown in FIG.

37A is a cross-sectional view showing the flow of electron current and hole current in the thyristor state of the semiconductor device shown in FIG. 35, and FIG. 37B is a transistor state (IGB) of the semiconductor device.
FIG. 4 is a cross-sectional view showing flows of an electron current and a hole current in a (T state).

[Explanation of symbols]

1 ... anode 2 ... p ⁺⁺ type collector layer (first semiconductor region) 3a ... n ⁺ -type buffer layer 3 ... n ^- -type base layer (second semiconductor region) 4 ... p-type base layer (second third semiconductor region) 4a ... inner region 4b ... high concentration region 4c ... p-type isolation layer 4d ... p ⁺ -type third semiconductor region 4s ... diffusion layer 9,110a, 121a ... gate oxide film (gate insulating film) 10, 110 ... First gate electrode 10a Projecting gate electrode portion 21, 121 Second gate electrode 12, 112 First MOSFET 15, 15 'Fourth semiconductor region 16 Fifth semiconductor region 16a Shallow n ⁺ type inner well 16b ... deep n-type outer well 16M ... n ⁺ -type connecting diffusion layer 16N ... n ⁺ KataCho out region 17 ... sixth semiconductor regions 18a, 18b, 18d ... cathode electrode 18c ... short-circuit electrode 19 ... shallow seventh semiconductor region 20 ... deep seventh semiconductor regions 23, 123 ... second MOSFET 30 ... surface layer p-type region 32 ... eighth semiconductor region. 33 ninth semiconductor region 36 eighth semiconductor region 61, 62 gate pad 65 gate runner (gate wiring).

Claims (26)

(57) [Claims] 1. A first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type formed thereon, and a first semiconductor region of a first conductivity type formed in a well shape in the second semiconductor region. A third semiconductor region, a fourth semiconductor region of the second conductivity type formed in a well shape on the surface side in the third semiconductor region, and a well shape formed on the well end side on the surface side in the third semiconductor region; A second conductive type fifth semiconductor region, a first conductive type sixth semiconductor region formed in a well shape on the surface side in the fourth semiconductor region, the third semiconductor region and the fifth semiconductor region.
A second semiconductor region having a heavy diffusion type structure;
A second-conductivity-type second MISFET for injecting the majority carrier into the semiconductor region; and a MISFET that can be opened and closed independently of the second-conductivity-type MISFET, and is connected to the fourth semiconductor region and the sixth semiconductor region. has a double diffusion structure, Available from said third semiconductor region and the sixth first conductivity type MISFET for many carrier extracting pulling the majority carriers in the semiconductor region, the semiconductor device including a
And from immediately below the fifth semiconductor region in the third semiconductor region.
All of the outer well end regions are inside the third semiconductor region.
A semiconductor device, which is a high-concentration region that is higher in impurity concentration than the region . 2. A first semiconductor region of a first conductivity type, on which a first semiconductor region of a first conductivity type is formed.
The formed second semiconductor region of the second conductivity type, the second semiconductor region
Third semiconductor of the first conductivity type formed in a well shape in the body region
Body region, formed in a well shape on the surface side in the third semiconductor region.
The fourth semiconductor region of the second conductivity type formed, the third semiconductor
A well formed at the well end on the surface side in the region
Fifth semiconductor region of two conductivity type, table in the fourth semiconductor region
Sixth semiconductor region of first conductivity type formed in a well shape on the surface side
Area, the third semiconductor region and the fifth semiconductor region.
A second semiconductor region having a heavy diffusion type structure;
Majority carriers injecting the majority carriers into the semiconductor region
MISFET of second conductivity type for rear injection and second conductive type MISFET
The MISFET can be opened and closed independently of the MISFET.
A double diffusion type structure with a fourth semiconductor region and the sixth semiconductor region.
The third semiconductor region to the sixth semiconductor region.
For many career pull to pull out the majority carriers in
A first conductivity type MISFET.
And the fifth semiconductor region is the multiple semiconductor region in the third semiconductor region.
Formed on the first conductivity type MISFET side for extracting several carriers
Inner well region with a high impurity concentration
Formed at the well end side of the body region,
Overlap with outer well region with low concentration compared to impurity concentration
A semiconductor device, which is a region . 3. A first semiconductor region of a first conductivity type, on which a first semiconductor region of a first conductivity type is formed.
The formed second semiconductor region of the second conductivity type, the second semiconductor region
Third semiconductor of the first conductivity type formed in a well shape in the body region
Body region, formed in a well shape on the surface side in the third semiconductor region.
The fourth semiconductor region of the second conductivity type formed, the third semiconductor
A well formed at the well end on the surface side in the region
Fifth semiconductor region of two conductivity type, table in the fourth semiconductor region
Sixth semiconductor region of first conductivity type formed in a well shape on the surface side
Area, the third semiconductor region and the fifth semiconductor region.
A second semiconductor region having a heavy diffusion type structure;
Majority carriers injecting the majority carriers into the semiconductor region
MISFET of second conductivity type for rear injection and second conductive type MISFET
The MISFET can be opened and closed independently of the MISFET.
A double diffusion type structure with a fourth semiconductor region and the sixth semiconductor region.
The third semiconductor region to the sixth semiconductor region.
To pull out the majority carrier
A first conductivity type MISFET.
And the third semiconductor region immediately below the fifth semiconductor region includes:
The first conductive layer having a higher concentration than the impurity concentration of the third semiconductor region.
An electrically-conductive seventh semiconductor region is formed, and the seventh semiconductor region is formed.
The third semiconductor region is located immediately below the fifth semiconductor region.
A semiconductor device, which is a shallow well region that leaves a part of the region . 4. A first semiconductor region of a first conductivity type, on which a first semiconductor region of a first conductivity type is formed.
The formed second semiconductor region of the second conductivity type, the second semiconductor region
Third semiconductor of the first conductivity type formed in a well shape in the body region
Body region, formed in a well shape on the surface side in the third semiconductor region.
The fourth semiconductor region of the second conductivity type formed, the third semiconductor
A well formed at the well end on the surface side in the region
Fifth semiconductor region of two conductivity type, table in the fourth semiconductor region
Sixth semiconductor region of first conductivity type formed in a well shape on the surface side
Area, the third semiconductor region and the fifth semiconductor region.
A second semiconductor region having a heavy diffusion type structure;
Majority carriers injecting the majority carriers into the semiconductor region
MISFET of second conductivity type for rear injection and second conductive type MISFET
The MISFET can be opened and closed independently of the MISFET.
A double diffusion type structure with a fourth semiconductor region and the sixth semiconductor region.
The third semiconductor region to the sixth semiconductor region.
To pull out the majority carrier
A first conductivity type MISFET.
There are, of the first conductivity type MISFET for the majority carrier pull out
The third semiconductor region immediately below the gate electrode has a high impurity concentration.
A ninth semiconductor region of the first conductivity type is formed . 5. A first semiconductor region of a first conductivity type, on which a first semiconductor region of a first conductivity type is formed.
The formed second semiconductor region of the second conductivity type, the second semiconductor region
Third semiconductor of the first conductivity type formed in a well shape in the body region
Body region, formed in a well shape on the surface side in the third semiconductor region.
The fourth semiconductor region of the second conductivity type formed, the third semiconductor
A well formed at the well end on the surface side in the region
Fifth semiconductor region of two conductivity type, table in the fourth semiconductor region
Sixth semiconductor region of first conductivity type formed in a well shape on the surface side
Area, the third semiconductor region and the fifth semiconductor region.
A second semiconductor region having a heavy diffusion type structure;
Majority carriers injecting the majority carriers into the semiconductor region
MISFET of second conductivity type for rear injection and second conductive type MISFET
The MISFET can be opened and closed independently of the MISFET.
A double diffusion type structure with a fourth semiconductor region and the sixth semiconductor region.
The third semiconductor region to the sixth semiconductor region.
To pull out the majority carrier
A first conductivity type MISFET.
And the second conductivity type MISFET for majority carrier injection and the second conductivity type MISFET.
Of the first conductivity type MISFETs for majority carrier extraction
One is enhancement type and the other is
A semiconductor device characterized in that it is a semiconductor device. 6. The method according to claim 1 or claim 3 to claim 5.
5. The semiconductor device according to claim 1, wherein the fifth semiconductor
The body region includes the majority carrier pull in the third semiconductor region.
Impurities formed on the first conductivity type MISFET side for punching
A high-concentration inner well region and a well of the third semiconductor region;
Formed at the end of the inner well region, and
A semiconductor device, which is an overlapping region with an outer well region having a relatively low concentration . 7. The method of claim 1 or claim 2 or claim 4.
6. The semiconductor device according to claim 5, wherein
In the third semiconductor region immediately below the fifth semiconductor region,
Is higher than the impurity concentration of the third semiconductor region.
A seventh semiconductor region of one conductivity type is formed;
The third semiconductor region is located immediately below the fifth semiconductor region.
Depth enough to penetrate the conductor region and contact the second semiconductor region
A semiconductor device, which is a well region . 8. The method according to claim 1, wherein
6. The semiconductor device according to claim 5, wherein
Of the gate electrode of the first conductive type MISFET for rear extraction
Immediately below the third semiconductor region, a first conductive material having a high impurity concentration is provided.
A semiconductor device comprising: a ninth semiconductor region ; 9. to any one of claims 1 to 4
The semiconductor device according to claim 1, wherein
Two-conductivity MISFET and the majority carrier extraction
One of MISFET of one conductivity type is enhancement type
And a depletion type semiconductor device. 10. The method according to claim 1, wherein
The semiconductor device according to claim 1, wherein the first semiconductor region and the
A second conductivity type buffer layer between the second semiconductor region and the second semiconductor region;
A semiconductor device comprising: 11. any one of claims 1 to 9
6. The semiconductor device according to claim 1, wherein the sixth semiconductor region is referred to.
The second conductivity type MISFET on both sides thereof and the
A semiconductor device having a first conductivity type MISFET . The semiconductor device according to any one of 12. The method of claim 1 to claim 11, formed by connecting a short circuit electrode connected to electrodes conductively contacting said fifth semiconductor region to the third semiconductor region A semiconductor device characterized by the above-mentioned. 13. A first semiconductor region of a first conductivity type and a first semiconductor region thereon.
Second semiconductor region of the second conductivity type formed in
Third half of the first conductivity type formed in a well shape in the conductor region
A conductor region, in the form of a well on the surface side in the third semiconductor region;
The formed fourth semiconductor region of the second conductivity type, the third semiconductor region;
Well-shaped on the edge of the well on the surface side in the body region
A fifth semiconductor region of the second conductivity type, and
Sixth semiconductor of first conductivity type formed in a well shape on the surface side
Region, the third semiconductor region and the fifth semiconductor region.
A double diffusion type structure, wherein the fifth semiconductor region
Majority key to inject majority carriers into two semiconductor regions
Carrier-injection second conductivity type MISFET and this second conductivity type MISFET.
It can be opened and closed independently of the conductivity type MISFET,
Double diffusion type with the fourth semiconductor region and the sixth semiconductor region
A third semiconductor region extending from the third semiconductor region to the sixth semiconductor region.
Pulling out the majority carrier to the area
A semiconductor device comprising: a first conductive type MISFET for use in a semiconductor device, wherein a short-circuit electrode connected to an electrode in conductive contact with the fifth semiconductor region is connected to the third semiconductor region. 14. The semiconductor device according to claim 12 , wherein the third semiconductor region is a stripe-shaped well, and the short-circuit electrode is formed on a longitudinal end surface of the well. A semiconductor device characterized by the above-mentioned. The semiconductor device according to any one of 15. The method of claim 1 to claim 14, sandwiched by the fifth semiconductor region of the pair formed in the well end opposing said third semiconductor region A plurality of the first-conductivity-type MISFET sections for majority carrier extraction in a region formed by the extraction. 16. A first semiconductor region of a first conductivity type and a first semiconductor region thereon.
Second semiconductor region of the second conductivity type formed in
Third half of the first conductivity type formed in a well shape in the conductor region
A conductor region, in the form of a well on the surface side in the third semiconductor region;
The formed fourth semiconductor region of the second conductivity type, the third semiconductor region;
Well-shaped on the edge of the well on the surface side in the body region
A fifth semiconductor region of the second conductivity type, and
Sixth semiconductor of first conductivity type formed in a well shape on the surface side
Region, the third semiconductor region and the fifth semiconductor region.
A double diffusion type structure, wherein the fifth semiconductor region
Majority key to inject majority carriers into two semiconductor regions
Carrier-injection second conductivity type MISFET and this second conductivity type MISFET.
It can be opened and closed independently of the conductivity type MISFET,
Double diffusion type with the fourth semiconductor region and the sixth semiconductor region
A third semiconductor region extending from the third semiconductor region to the sixth semiconductor region.
Pulling out the majority carrier to the area
A first conductivity type MISFET for use , wherein the majority carrier extraction is performed in a region between a pair of the fifth semiconductor regions formed at opposed well ends of the third semiconductor region. A semiconductor device comprising a plurality of first conductivity type MISFET sections for use. 17. The semiconductor device according to claim 15 , wherein the plurality of first-conductivity-type MISFET sections for extracting majority carriers is formed in a well shape on the surface side of the third semiconductor region. A semiconductor device having an eighth semiconductor region of the first conductivity type. The semiconductor device according to any one of 18. The method of claim 1 to claim 17, wherein the third said formed well end side opposing the semiconductor region the fourth semiconductor region and the sixth semiconductor Double diffusion structure with the
A semiconductor device comprising: a first conductivity type eighth semiconductor region formed in a well shape on a surface side of the third semiconductor region in a region sandwiched by the heavy diffusion structures. 19. A first semiconductor region of a first conductivity type, over which a first semiconductor region of a first conductivity type is formed.
Second semiconductor region of the second conductivity type formed in
Third half of the first conductivity type formed in a well shape in the conductor region
A conductor region, in the form of a well on the surface side in the third semiconductor region;
The formed fourth semiconductor region of the second conductivity type, the third semiconductor region;
Well-shaped on the edge of the well on the surface side in the body region
A fifth semiconductor region of the second conductivity type, and
Sixth semiconductor of first conductivity type formed in a well shape on the surface side
Region, the third semiconductor region and the fifth semiconductor region.
A double diffusion type structure, wherein the fifth semiconductor region
Majority key to inject majority carriers into two semiconductor regions
Carrier-injection second conductivity type MISFET and this second conductivity type MISFET.
It can be opened and closed independently of the conductivity type MISFET,
Double diffusion type with the fourth semiconductor region and the sixth semiconductor region
A third semiconductor region extending from the third semiconductor region to the sixth semiconductor region.
Pulling out the majority carrier to the area
A first conductivity type MISFET for use in the semiconductor device, comprising: a double diffusion structure of the fourth semiconductor region and the sixth semiconductor region formed on the opposed well end side of the third semiconductor region; A semiconductor device comprising: a first conductivity type eighth semiconductor region formed in a well shape on the surface side of the third semiconductor region in a region sandwiched by these double diffusion structures. Any of 20. The method of claim 17 or claim 19
2. The semiconductor device according to claim 1, wherein the fifth semiconductor region and the eighth semiconductor region are connected via a first conductivity type connection diffusion layer, and have an electrode which is in conductive contact with the eighth semiconductor region. A semiconductor device comprising: Any of 21. The method of claim 17 or claim 19
2. The semiconductor device according to claim 1 , further comprising: a second-conduction-type MISFET for path switching that cuts off conduction between the fifth semiconductor region and the eighth semiconductor region; and an electrode that is in conductive contact with the eighth semiconductor region. A semiconductor device, comprising: 22. The semiconductor device according to claim 21 , wherein a gate electrode of the second MISFET for path switching is a second conductive type MIS for majority carrier injection.
A semiconductor device comprising a part of a gate electrode of an FET. 23. The semiconductor device according to any one of claims 1 to 22, a gate electrode of said plurality second conductivity type MISFET for carrier injection is more Hon'nami set in stripes on the chip layout And a plurality of gate wirings connected to a gate pad are connected to the plurality of gate electrodes in a grid pattern. 24. A first semiconductor region of a first conductivity type, over which a first semiconductor region of a first conductivity type is formed.
Second semiconductor region of the second conductivity type formed in
Third half of the first conductivity type formed in a well shape in the conductor region
A conductor region, in the form of a well on the surface side in the third semiconductor region;
The formed fourth semiconductor region of the second conductivity type, the third semiconductor region;
Well-shaped on the edge of the well on the surface side in the body region
A fifth semiconductor region of the second conductivity type, and
Sixth semiconductor of first conductivity type formed in a well shape on the surface side
Region, the third semiconductor region and the fifth semiconductor region.
A double diffusion type structure, wherein the fifth semiconductor region
Majority key to inject majority carriers into two semiconductor regions
Carrier-injection second conductivity type MISFET and this second conductivity type MISFET.
It can be opened and closed independently of the conductivity type MISFET,
Double diffusion type with the fourth semiconductor region and the sixth semiconductor region
A third semiconductor region extending from the third semiconductor region to the sixth semiconductor region.
Pulling out the majority carrier to the area
The first conductivity type MISFET for the majority carrier, the second conductivity type MISFE for the majority carrier injection.
A plurality of T gate electrodes are arranged in stripes on a chip layout, and a plurality of gate wirings connected to gate pads are connected to the plurality of gate electrodes in a grid pattern. Semiconductor device. The semiconductor device according to any one of the claims 25] claims 1 to 24, a gate electrode of said plurality second conductivity type MISFET for carrier injection-shaped islands provided at grid points on the chip layout A plurality of gate wirings connected to a gate pad are connected to the gate electrode in a grid pattern, and a region in the grid divided by the gate wiring is the majority-carrier-extracted first conductivity type MISFET.
A semiconductor device which is divided by a lattice-shaped gate electrode. 26. A first semiconductor region of a first conductivity type, over which a first semiconductor region of a first conductivity type is formed.
Second semiconductor region of the second conductivity type formed in
Third half of the first conductivity type formed in a well shape in the conductor region
A conductor region, in the form of a well on the surface side in the third semiconductor region;
The formed fourth semiconductor region of the second conductivity type, the third semiconductor region;
Well-shaped on the edge of the well on the surface side in the body region
A fifth semiconductor region of the second conductivity type, and
Sixth semiconductor of first conductivity type formed in a well shape on the surface side
Region, the third semiconductor region and the fifth semiconductor region.
A double diffusion type structure, wherein the fifth semiconductor region
Majority key to inject majority carriers into two semiconductor regions
Carrier-injection second conductivity type MISFET and this second conductivity type MISFET.
It can be opened and closed independently of the conductivity type MISFET,
Double diffusion type with the fourth semiconductor region and the sixth semiconductor region
A third semiconductor region extending from the third semiconductor region to the sixth semiconductor region.
Pulling out the majority carrier to the area
The first conductivity type MISFET for the majority carrier, the second conductivity type MISFE for the majority carrier injection.
The gate electrode of T has an island shape provided at a grid point on a chip layout, and a plurality of gate wirings connected to a gate pad are electrically connected to the gate electrode in a grid shape. A semiconductor device, wherein an inner region is divided by a lattice-shaped gate electrode of the majority-conducting first conductivity type MISFET.