JP4935037B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device such as a high breakdown voltage lateral diode.

In recent years, with the advancement of isolation technologies such as junction isolation and dielectric isolation, high breakdown voltage lateral devices such as diodes, insulated gate bipolar transistors (hereinafter abbreviated as IGBTs) and MOSFETs and the drive, control, and protection circuits of the devices have been integrated. Development of high voltage power ICs integrated on two silicon substrates has been actively conducted. In particular, the progress of SOI-type dielectric isolation technology that combines trench isolation technology with SOI (Semiconductor On Insulator) substrates such as bonded substrates enables the production of power ICs that integrate multiple high voltage devices. It is spurring high IC withstand voltage. For example, a totem pole circuit to which a high voltage device such as IGBT is applied is made into one chip, and a display driving IC having a multi-output to which a high voltage device such as IGBT is applied.
Among applied products equipped with high voltage power ICs, the market for flat panel displays, automotive electronics, and motor control devices is expanding rapidly. In order to increase the added value of these products, low power consumption is required. A large part of the power loss during the operation of the product is generated from the output stage of the high voltage power IC, and when a high voltage diode is used in the output stage, it is necessary to reduce the power loss.

FIG. 10 is a configuration diagram of a conventional high voltage diode formed on an SOI substrate. FIG. 10 (a) is a plan view of the main part, and FIG. 10 (b) is an XX line in FIG. 10 (a). It is the principal part sectional drawing cut | disconnected.
Using an SOI substrate 200 in which an n-type semiconductor layer 53 is formed on an n-type or p-type semiconductor substrate 51 via an oxide film 52, an n-type diffusion region 54 and the n-type diffusion region 54 are formed on the surface layer of the n-type semiconductor layer 53. A p-type diffusion region 55 is formed apart from the n-type diffusion region 54. This distance is determined by the breakdown voltage required for the diode. An n-type cathode region 56 is formed on the surface layer of the n-type diffusion region 54, and a p-type anode region 57 is formed on the surface layer of the p-type diffusion region 55. A cathode electrode 58 is formed on the n-type cathode region 56, and an anode electrode 59 is formed on the p-type anode region 57.
The planar patterns of the n-type diffusion region 54 and the p-type diffusion region 55 are rectangular and are arranged to face each other. The planar patterns of the n-type cathode region 56 and the p-type anode region 57 are similar to the planar patterns of the n-type diffusion region 54 and the p-type diffusion region 55, and are arranged to face each other.

The operation of the diode will be briefly described with reference to FIG. During forward operation of the diode, the voltage of the anode electrode 59 is forward biased to +0.6 V or more with respect to the cathode electrode 58. This forward bias injects holes from the p-type anode region 57 and electrons from the n-type cathode region 56 into the n-type semiconductor layer 53, and the diode becomes conductive.
On the other hand, when shifting from the forward operation to the reverse recovery operation, the voltage of the anode electrode 59 is made negative (reverse biased) with respect to the cathode electrode 58. As a result, injection of holes from the p-type anode region 57 and injection of electrons from the n-type cathode region 56 are suppressed, and the diode enters a blocking state through a reverse recovery operation.
Here, at the time of reverse recovery, a reverse recovery current flows by sweeping out and recombining holes and electrons accumulated in the n-type diffusion region 54, the n-type semiconductor layer 53, and the p-type diffusion region 55 during forward operation. This reverse recovery current flows until the accumulated holes and electrons disappear. Further, the reverse recovery current has the opposite direction of the forward current flowing during the forward operation.

The forward voltage drop (hereinafter referred to as Vf) of the diode that occurs during forward operation becomes an on-loss due to the product of the forward current. On the other hand, the reverse recovery current becomes a reverse recovery loss due to the product of the reverse recovery voltage of the diode. Further, when the diode is incorporated in the circuit, the reverse recovery current becomes a consumption current of the circuit, and a product of the consumption current and the circuit resistance results in a circuit loss. Therefore, in order to reduce the loss related to the diode, it is necessary to lower the Vf and the reverse recovery current.
When the power IC operates at a high frequency, the reverse recovery loss generated in the element due to the reverse recovery current increases, and the power IC may be destroyed. Therefore, the high breakdown voltage lateral diode mounted on the power IC uses this reverse recovery current. It is important to keep it small.
In order to reduce the reverse recovery current, the amount of holes and electrons accumulated during forward operation is reduced, that is, the amount of holes and electrons injected during forward operation is reduced, and the amount of recombination of holes and electrons is reduced. It is necessary to reduce the amount of accumulated holes and electrons, and to quickly extract the accumulated holes and electrons.

On the other hand, in order to lower Vf, the injection amount of holes and electrons is increased, the recombination amount of holes and electrons is decreased, the amount of accumulated holes and electrons is increased, and the accumulated positive amount is increased. It is necessary to prevent the holes and electrons from disappearing rapidly due to recombination.
In other words, the reverse recovery current and Vf are in a trade-off (reciprocal) relationship that Vf increases when a measure for reducing the reverse recovery current is taken.
In a high breakdown voltage lateral diode mounted on a high breakdown voltage power IC, how to reduce the reverse recovery current while suppressing an increase in Vf is a problem.
As a technique for solving this problem, a technique of introducing a lifetime killer such as He into a carrier (hole and electron) accumulation layer is disclosed (for example, Patent Document 1). In this method, by introducing a lifetime killer into the carrier accumulation layer, the recombination time (lifetime) of minority carriers can be shortened, and the reverse recovery current can be reduced while suppressing an increase in Vf.

However, when He is ion-implanted into a high voltage power IC, since He is ion-implanted on the entire surface (because it is difficult to finely process the lead mask), it is also applied to circuit parts other than the diode part that requires ion implantation. He is ion-implanted to shorten the circuit part lifetime and deteriorate the circuit characteristics. In addition, the introduction of a lifetime killer by He increases the manufacturing cost.
As another means, a method of forming Schottky contacts on the anode electrode and the cathode electrode of a high voltage lateral diode is disclosed (for example, Patent Document 2). In this method, the amount of injected carriers is suppressed by the Schottky barrier contact, and the reverse recovery current is smaller than that of a diode having only an ohmic contact. However, the formation of the Schottky contact requires a metal for Schottky junction separately, which increases the manufacturing cost. In addition, it is very difficult to form a Schottky contact that is stable against temperature changes and highly reliable.

  Further, in the prior art described in Patent Document 2, as shown in FIG. 11, an n-type short region 79 and a p-type short region 78 are provided adjacent to the p-type anode region 77 and the n-type cathode region 76, respectively. Has been. With this structure, electrons injected from the n-type cathode region 76 during forward operation are extracted from the n-type short region 79, and holes injected from the p-type anode region 77 are extracted from the p-type short region 78. Further, by reducing the areas of the n-type cathode region 76 and the p-type anode region 77, the amount of holes and electrons accumulated in the n-type semiconductor layer 73 is reduced, and the reverse recovery current is reduced. However, in this structure, the current due to the holes 83 out of the reverse recovery current during the reverse recovery operation flows directly under the n-type short region 79 and enters the p-type anode region 77, and the p-type immediately under the n-type short region 79. When the potential of the p-type diffusion region 75 is raised to 0.6 V (built-in potential) or more by the lateral resistance 84 of the diffusion region 75, electrons 82 are injected from the n-type short region 79 into the p-type diffusion region 75, and a parasitic thyristor. (N-type short region 79-p-type diffusion region 75-n-type semiconductor layer 73-n-type diffusion region 74-npnp structure constituted by p-type short region 78) is turned on and latched up. When the parasitic thyristor latches up, destruction occurs at the latched-up location, and the reverse recovery tolerance of the diode is reduced.

In the figure, 71 is a semiconductor substrate, 72 is an oxide film, 80 is a cathode electrode, 81 is an anode electrode, and 300 is an SOI substrate.
Japanese Patent Laid-Open No. 7-106605 Japanese Patent Laid-Open No. 11-233795 (FIG. 15)

As described above, a small reverse recovery current is required for a high voltage lateral diode mounted on a high voltage power IC. However, in the method of shortening the lifetime of Patent Document 1, the increase in Vf accompanying the decrease in the reverse recovery current is not sufficiently reduced, and He ion implantation is performed on the entire surface of the semiconductor substrate, so that a high breakdown voltage power IC is obtained. The characteristics of the circuit portion constituting the above are deteriorated, and the manufacturing cost is also increased. In the method of Patent Document 2, the parasitic thyristor operates and the reverse recovery tolerance becomes small.
An object of the present invention is to provide a semiconductor device that solves the above-mentioned problems, reduces the reverse recovery current while suppressing an increase in Vf, and can further improve the reverse recovery withstand and reduce the manufacturing cost. There is.

To achieve the above object, a first conductivity type semiconductor layer, a first conductivity type first diffusion region and a second conductivity type second diffusion region formed separately from a surface layer of the semiconductor layer, A third diffusion region of the first conductivity type and a fourth diffusion region of the second conductivity type formed in contact with the surface layer of the first diffusion region, and a second conductivity type formed in the surface layer of the second diffusion region. A first main electrode in contact with the third diffusion region and the fourth diffusion region, and a second main electrode in contact with the fifth diffusion region,
A distance between the third diffusion region and the fifth diffusion region is not more than a distance between the fourth diffusion region and the fifth diffusion region.
A first conductivity type semiconductor layer; a first conductivity type first diffusion region and a second conductivity type second diffusion region formed apart from a surface layer of the semiconductor layer; and a surface of the first diffusion region. A third diffusion region of the first conductivity type formed in the layer; a fifth diffusion region of the second conductivity type formed in contact with the surface layer of the second diffusion region; and a sixth diffusion region of the first conductivity type; A first main electrode in contact with the third diffusion region; and a second main electrode in contact with the fifth diffusion region and the sixth diffusion region;
A distance between the third diffusion region and the fifth diffusion region is not more than a distance between the third diffusion region and the sixth diffusion region.

A first conductivity type semiconductor layer; a first conductivity type first diffusion region and a second conductivity type second diffusion region formed separately from a surface layer of the semiconductor layer; and a surface of the first diffusion region. A third diffusion region of the first conductivity type and a fourth diffusion region of the second conductivity type formed in contact with each other; a fifth diffusion region of the second conductivity type formed on the surface layer of the second diffusion region; A sixth diffusion region of one conductivity type; a first main electrode in contact with the third diffusion region and the fourth diffusion region; a second main electrode in contact with the fifth diffusion region and the sixth diffusion region; Comprising
The distance between the third diffusion region and the fifth diffusion region is equal to or less than the distance between the fourth diffusion region and the fifth diffusion region, and the distance between the third diffusion region and the fifth diffusion region is the first distance. It may be less than or equal to the distance between 3 diffusion regions and the sixth diffusion region.
The third diffusion region may be disposed between the fourth diffusion region and the fifth diffusion region.

The fifth diffusion region may be disposed between the third diffusion region and the sixth diffusion region.
The third diffusion region and the fifth diffusion region may be disposed between the fourth diffusion region and the sixth diffusion region.
The third diffusion region may be disposed so as to face the sixth diffusion region, and the fourth diffusion region may face the fifth diffusion region.
The third diffusion region may be disposed to face the fifth diffusion region, and the fourth diffusion region may be disposed to face the sixth diffusion region.
A plurality of the third diffusion regions and a plurality of the fourth diffusion regions may be alternately arranged.

Furthermore, a control electrode provided on the surface of the first diffusion region sandwiched between the fourth diffusion region and the semiconductor layer may be provided via an insulating film.
A plurality of the fifth diffusion regions and the sixth diffusion regions may be alternately arranged.
Further, it is preferable that a control electrode provided via an insulating film is provided on the surface of the second diffusion region sandwiched between the sixth diffusion region and the semiconductor layer.
In the present invention, in a high breakdown voltage lateral diode mounted on a high breakdown voltage power IC, an n-type short region that contacts the anode electrode is formed in a p-type diffusion region that is a second diffusion region in which a p-type anode region is formed. Then, a p-type short region that contacts the cathode electrode is formed in the n-type diffusion region where the n-type cathode region is formed. By adjusting the proportion of the short layer, carrier injection during forward operation can be controlled. In addition, since the injected carriers are extracted by the short layer, the amount of accumulated carriers can be adjusted. The reverse recovery characteristic can be controlled by controlling the amount of accumulated carriers.

As described above, in the present invention, the short region is formed adjacent to the anode region and the cathode region, and the reverse recovery is performed while suppressing the increase in Vf as much as possible by adjusting the ratio of the short region (hereinafter referred to as the short rate). Current can be reduced. The short rate can be adjusted by the planar pattern of the short region. The short-circuit rate may be adjusted according to the desired Vf and reverse recovery current. This is possible by changing the mask pattern.
Further, the n-type short region formed in the p-type diffusion region is at a distance farther from the n-type cathode region than the p-type anode region, and the p-type short region formed in the n-type diffusion region is from the n-type cathode region. In addition, by disposing at a distance far from the p-type anode layer, the operation of the parasitic thyristor during the reverse recovery operation can be prevented, and the reverse recovery tolerance can be improved.
Further, when n-type short regions formed in the p-type diffusion region are alternately arranged with the p-type anode region, oxidation is performed on the surface of the p-type diffusion region sandwiched between the n-type short region and the n-type semiconductor layer. A control electrode is formed through the membrane. Then, a voltage at which an inversion layer is formed on the surface of the p-type diffusion region during forward operation of the diode is applied to the control electrode. Thereby, a low resistance layer is formed in the surface region directly under the control electrode, and the effect of extracting electrons into the n-type short region is increased. As a result, the amount of stored charge during forward operation is reduced, and the speed of the diode can be increased.

This method of forming the control electrode is applicable even when the p-type short region and the n-type cathode region formed in the n-type diffusion region are alternately formed.
In this case, a low resistance layer is formed in the surface region under the control electrode, and the effect of extracting holes into the p-type short region is increased. As a result, the amount of stored charge during forward operation is reduced, and the speed of the diode can be increased.
In this manner, the reverse recovery current of the diode can be reduced without the formation of a Schottky contact and the introduction of a lifetime killer as in the prior art. Moreover, reverse recovery tolerance can be improved.

According to the present invention, the cathode region and the anode region of the lateral diode are disposed so as to face each other, and the cathode-side short region (p-type short region) is formed so as to contact the cathode region end opposite to the anode region side, By forming a short region (n-type short region) on the anode side so as to be in contact with the anode region end opposite to the cathode region side, the reverse recovery current is reduced and the reverse recovery resistance is improved while suppressing an increase in Vf. Can be made.
In addition, a first location in which the cathode region and the short region on the cathode side are alternately in contact with each other and arranged in one direction, and a second location in which the anode region and the short region on the anode side are alternately in contact with each other in the same direction. Is disposed so as to face the direction orthogonal to the above direction, the reverse recovery current can be greatly reduced while suppressing an increase in Vf.
Further, when n-type short regions formed in the p-type diffusion region are alternately arranged with the p-type anode region, oxidation is performed on the surface of the p-type diffusion region sandwiched between the n-type short region and the n-type semiconductor layer. A control electrode is formed through the membrane. Then, a voltage at which an inversion layer is formed on the surface of the p-type diffusion region during forward operation of the diode is applied to the control electrode. Thereby, a low resistance layer is formed in the surface region directly under the control electrode, and the effect of extracting electrons into the n-type short region is increased. Thereby, a low resistance layer is formed in the surface region directly under the control electrode, and the effect of extracting electrons into the n-type short region is increased. As a result, the amount of stored charge during forward operation is reduced, and the speed of the diode can be increased.

This method of forming the control electrode is applicable even when the p-type short region and the n-type cathode region formed in the n-type diffusion region are alternately formed.
In this case, a low resistance layer is formed in the surface region under the control electrode, and the effect of extracting holes into the p-type short region is increased. As a result, the amount of stored charge during forward operation is reduced, and the speed of the diode can be increased.
In addition, a first location in which the cathode region and the short region on the cathode side are alternately in contact with each other and arranged in one direction, and a second location in which the anode region and the short region on the anode side are alternately in contact with each other in the same direction. Are arranged so as to face each other in a direction orthogonal to the above direction, and the minimum distance between the end of the cathode region and the end of the anode region facing each other is set to the end of the cathode region facing each other. Because the parasitic thyristor operation can be suppressed by making the distance smaller than the minimum distance between the end of the short circuit area on the anode side and the minimum distance between the end of the anode area and the short area on the cathode side. The reverse recovery tolerance can be improved. Of course, the reverse recovery current can be significantly reduced while suppressing the increase in Vf.

Further, the reverse recovery current can be reduced by changing the plane pattern, and the lifetime killer can be omitted, so that the manufacturing cost can be reduced.
Also, by mounting this diode on the high voltage power IC, the power loss of the high voltage power IC can be reduced.

  The best mode for carrying out the invention will be described in the following examples. Here, the first conductivity type may be n-type and the second conductivity type may be p-type.

FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) is a plan view of an essential part, and FIG. 1 (b) is cut along line XX in FIG. 1 (a). It is principal part sectional drawing. This semiconductor device is a high breakdown voltage lateral diode.
Using an SOI substrate 100 in which an n-type semiconductor layer 3 is formed on an n-type or p-type semiconductor substrate 1 with an oxide film 2 interposed, an n-type diffusion region 4 and this are formed on the surface layer of the n-type semiconductor layer 3. A p-type diffusion region 5 is formed apart from the n-type diffusion region 4. An n-type cathode region 6 and a p-type short region 8 are formed adjacent to the n-type cathode region 6 in the surface layer of the n-type diffusion region 4. A p-type anode region 7 and an n-type short region 9 are formed adjacent to the p-type anode region 7 in the surface layer of the p-type diffusion region 5. A cathode electrode 10 is formed from the n-type cathode region 6 to the p-type short region 8, and an anode electrode 11 is formed from the p-type anode region 7 to the n-type short region 9.

In the case of a high breakdown voltage lateral diode with a breakdown voltage of about 200 V, the thickness of the n-type semiconductor layer 3 is about 10 μm, the surface concentration of the n-type diffusion region 4 is about 5 × 10 ¹⁶ cm ⁻³ , and the diffusion depth is about 3 μm. The surface concentration of the p-type diffusion region 5 is about 2 × 10 ¹⁷ cm ⁻³ and the diffusion depth is about 3 μm. The surface concentration of the n-type cathode region 6 is about 5 × 10 ¹⁹ cm ⁻³ and the diffusion depth is 0.3 μm. The surface concentration of the p-type anode region 7 is about 5 × 10 ¹⁹ cm ⁻³ and the diffusion depth is about 0.5 μm. The surface concentration of the p-type short region 8 is about 5 × 10 ¹⁹ cm ⁻³ and the diffusion depth. Is 0.5 μm, the surface concentration of the n-type short region 9 is about 5 × 10 ¹⁹ cm ⁻³ , the diffusion depth is 0.3 μm, and the distance between the n-type diffusion region 4 and the p-type diffusion region 5 is about 15 μm. .
The planar pattern of the n-type diffusion region 4 and the p-type diffusion region 5 is a rectangle, and the n-type diffusion region 4 and the p-type diffusion region 5 are arranged to face each other. The planar pattern of the n-type cathode region 6 and the p-type anode region 7 is striped, and the n-type cathode region 6 and the p-type anode region 7 are arranged to face each other. The planar pattern of the p-type short region 8 and the n-type short region 5 is striped. The p-type short region 8 and the n-type short region 5 are n-type cathodes sandwiching the n-type cathode region 6 and the p-type anode region 7. Arranged so as to face the outside of region 6 and p-type anode region 7.

FIG. 2 is a diagram illustrating an ON state during forward operation of the diode of FIG. When a positive voltage of 0.6 V or more is applied to the anode electrode 11 with respect to the cathode electrode 10 (forward bias), the diode is turned on and passes from the p-type anode region 7 through the p-type diffusion region 5 to the n-type semiconductor layer 3. Holes 22 are injected, and electrons 21 are injected from the n-type cathode region 6 through the n-type diffusion region 4 and the n-type semiconductor layer 3 to the p-type diffusion region 5. These injected holes 24 and electrons 23 are accumulated as excess carriers (becomes accumulated carriers) in the n-type semiconductor layer 3, the n-type diffusion region 4 and the p-type diffusion region 5.
Among the accumulated holes 24, some holes 26 flow out to the cathode electrode 10 through the p-type short region 8, and some electrons 25 of the accumulated electrons 23 are anodes through the n-type short region 9. The excess carriers (electrons 23 and holes 24) accumulated in the n-type semiconductor layer 3, the n-type diffusion region 4 and the p-type diffusion region 5 flow out to the electrode 11. There are few compared.

Further, by increasing the areas of the p-type short region 8 and the n-type short region 9 and decreasing the areas of the n-type cathode region 6 and the p-type anode region 7, the accumulated excess carriers can be reduced.
FIG. 3 is a diagram illustrating a state during the reverse recovery operation of the diode of FIG. A negative voltage is applied to the anode electrode 11 with respect to the cathode electrode 10 (reverse bias), a reverse current is applied so as to cancel the forward current flowing in the ON state, and the diode is set in the blocking state. In this process, of the excess carriers accumulated in the ON state, the electrons 23 flow out from the n-type cathode region 6 to the cathode electrode 10, and the holes 24 flow out from the p-type anode region 7 to the anode electrode 11 to reversely recover the diode. It becomes current. If the accumulated excess carriers are small, the reverse recovery current is small.

When the excess carriers accumulated by pulling out from the short regions 8 and 9 are reduced, the increase in Vf can be reduced as compared with the case of reducing the excess carriers by introducing a lifetime killer. This is because, although not shown, the drop of excess carriers in the n-type semiconductor layer 3 is reduced in the distribution of excess carriers in the ON state.
Further, the reverse recovery current can be reduced by increasing the areas of the p-type short region 8 and the n-type short region 9 and decreasing the areas of the n-type cathode region 6 and the p-type anode region 7.
Further, since the reverse recovery current can flow into the p-type anode region 7 and the n-type cathode region 6 without flowing laterally immediately below the short regions 8 and 9, the parasitic thyristor does not operate like a conventional diode, Therefore, since the latch-up does not occur, the reverse recovery tolerance can be improved as compared with the conventional diode shown in Patent Document 2.

FIG. 4 is a graph showing the relationship between Vf and reverse recovery current of the diode of FIG. The horizontal axis is Vf when a forward current of 1000 A / cm ^{2 is} passed, and the vertical axis is a normalized reverse recovery current. Element A to element E in the figure have different short rates.
The definition of the short rate will be described. The short rate includes a short rate on the cathode side and a short rate on the anode side. The short-circuit rate on the cathode side is the area of the p-type short region / (the area of the n-type cathode region + the area of the p-type short region), and the short-circuit rate on the anode side is the area of the n-type short region / (area of the p-type anode region). + Area of n-type short region). Here, the cathode-side short-circuit rate and the anode-side short-circuit rate are made the same, and (area of n-type cathode region + area of p-type short region) and (area of p-type cathode region + area of n-type short region) are In the same manner, an element with the short rate changed from 0% to 70% is manufactured. The cathode-side short ratio is adjusted by the lateral width (short side length) in the planar pattern of the p-type short region and the n-type cathode region, and the anode-side short rate is adjusted in the planar pattern of the n-type short region and the p-type anode region. Adjust the width (short side length).

Element A is a conventional element and has a short-circuit rate of zero, and elements B to E are elements of the present invention. The short ratio of the element B is 20%, the short ratio of the element C is 30%, the short ratio of the element D is 50%, and the short ratio of the element E is 70%.
When the short-circuit rate is increased from the element B to the element E, Vf slightly increases and the reverse recovery current greatly decreases. In the case of the element E in which the short rate is 70%, the reverse recovery current can be reduced by about 40% by increasing about 0.2 V with respect to Vf of the element A having a short rate of zero. By reducing the reverse recovery current, the decay rate of the reverse recovery current (inclination when the reverse recovery current decreases from the peak value of the reverse recovery current: -di / dt) is reduced, and the reverse recovery operation (not shown) is performed. The reverse reverse voltage (-di / dt × L: L is the circuit inductance) is suppressed to a low level, the device voltage breakdown (including -dV / dt breakdown during reverse recovery) is prevented, and the reverse recovery loss is also reduced. Is done.

Further, when a small Vf is required, the element B or element C with a small short circuit rate can be used, and when a small reverse recovery current is required, the element D or element E with a large short circuit rate may be used. That is, the element of the present invention can meet a wide range of requirements by changing the short-circuit rate.
FIG. 5 is a diagram showing the relationship between Vf and the amount of reverse recovery charge of the diode of FIG. In this figure, the reverse recovery charge amount obtained by time integration of the reverse recovery current of FIG. 4 is normalized and shown on the vertical axis.
In the case of the element E, the reverse recovery charge amount can be significantly reduced to 80% with respect to the reverse recovery charge amount of the element A.
The only structural difference between the element A as the conventional element and the element B as the element of the present invention to the element E is only the short ratio, and this can be dealt with only by changing the pattern of the existing mask. Therefore, no additional process is required in manufacturing the high breakdown voltage lateral diode of the present invention, and the cost is not increased.

  In the stripe pattern of FIG. 1, the short regions 8 and 9 are formed in both the n-type diffusion region 4 and the p-type diffusion region 5, but the short region may be formed only in one of the diffusion regions. . This may be selected according to the desired characteristics.

6A and 6B are configuration diagrams of a semiconductor device according to a second embodiment of the present invention, in which FIG. 6A is a plan view of an essential part, and FIG. 6B is cut along line X1-X1 in FIG. The principal part sectional view and the figure (c) are principal part sectional views cut by the X2-X2 line of the figure (a). This semiconductor device is a high breakdown voltage lateral diode.
The difference from FIG. 1 is that elongated n-type cathode regions 6 and elongated p-type short regions 8 formed in the surface layer of the n-type diffusion region 4 are alternately arranged in a strip shape in the longitudinal direction of the n-type diffusion region 4. An elongated p-type anode region 7 and an elongated n-type short region 9 formed in the surface layer of the p-type diffusion region 5 are alternately arranged in the longitudinal direction of the p-type diffusion region 5 to form an n-type cathode. This is that the elongated direction of the region 6, the p-type short region 8 and the p-type anode region 7 and the n-type short region 9 and the longitudinal direction of the n-type diffusion region 4 and the p-type diffusion region 5 are arranged to be orthogonal to each other.

Also in this case, the reverse recovery current can be reduced by suppressing the increase in Vf as in the first embodiment.
6 shows the case where the n-type cathode region 6 and the p-type anode region 7 and the p-type short region 8 and the n-type short region 9 face each other, the n-type cathode region 6 and the n-type short region 9 and p The shape anode region 7 and the p-type short region 8 may be arranged to face each other. What is important in the formation of the two short regions is the short ratio, and there is no restriction on the opposing arrangement.
Further, the short ratio is adjusted by the elongated width (short side length) of each of the short regions 8, 9 and the n-type cathode region 6 and the p-type anode region 7.

FIGS. 7A and 7B are configuration diagrams of a semiconductor device according to a third embodiment of the present invention. FIG. 7A is a plan view of the main part, and FIG. 7B is cut along line X1-X1 in FIG. The principal part sectional view and the figure (c) are principal part sectional views cut by the X2-X2 line of the figure (a). This semiconductor device is a high breakdown voltage lateral diode.
The difference from FIG. 6 is that the end 8a of the p-type short region on the side facing the p-type diffusion region 5 is retreated from the end 6a of the n-type cathode region, and the n-type short region on the side facing the n-type diffusion region 4 By retracting the end portion 9a of the p-type anode region from the end portion 7a of the p-type anode region, the distance L1 between the end portion 8a of the p-type short region and the end portion 9a of the n-type short region is set to the end portion 6a of the n-type cathode region. This is a point that is wider than the interval L2 between the end portions 7a of the p-type anode region.
By making L1 wider than L2, the electrons 25 and the holes 26 accumulated in the n-type semiconductor layer 3, the n-type diffusion region 4 and the p-type diffusion region 5 are directly under the p-type short region 8 and n during the reverse recovery operation. Since it is swept to the n-type cathode region 6 and the p-type anode region 7 without passing directly under the short-shaped region 9, the parasitic thyristor operation is suppressed, and the reverse recovery tolerance can be improved.

Also in this case, the reverse recovery current can be reduced by suppressing the increase in Vf as in the first embodiment.
By the way, in the strip pattern of FIGS. 6 and 7, the short regions 8 and 9 are formed in both the n-type diffusion region 4 and the p-type diffusion region 5, but the short region is formed in one of the diffusion regions. Just fine.

8A and 8B are configuration diagrams of a semiconductor device according to a fourth embodiment of the present invention. FIG. 8A is a plan view of the main part, and FIG. 8B is cut along line X1-X1 in FIG. The principal part sectional view and the figure (c) are principal part sectional views cut by the X2-X2 line of the figure (a). This figure shows a case where the present invention is applied to the high voltage lateral diode of FIG.
The difference from FIG. 6 is that the n-type semiconductor layer extends across the p-type diffusion region 5 from the cathode electrode 10 side of the p-type anode region 7 and the n-type short region 9 arranged in a strip shape in the p-type diffusion region 5. 3 is that the control electrode 12 is disposed through the oxide film 13.
The effect of providing the control electrode 12 will be described with reference to FIG.
FIG. 9 shows the flow of electrons 23 and holes 24 during the forward operation of the diode shown in FIG. During forward operation, a voltage that forms an inversion layer on the surface of the p-type diffusion region 5 is applied to the control electrode 12. As a result, an inversion layer is formed on the surface layer of the p-type diffusion region 5 immediately below the control electrode 12, and a low resistance region 14 indicated by a cross can be formed in the surface region immediately below the control electrode 12.

Since the electrons 23 flow into the n-type short region 9 through the low resistance region 14, the electron extraction effect of the n-type short region 9 can be promoted. As a result, the amount of stored charge during the forward operation is reduced, and the speed of the diode can be increased.
In FIG. 8, the control electrode 12 is formed from the p-type anode region 7 to the n-type semiconductor layer 3 via the insulating film 13, but there is no adverse effect due to this. For this, the control electrode 12 between the p-type anode region 7 and the semiconductor layer 3 may be deleted by a photomask.
The voltage applied to the control electrode 12 may be a power supply inside the power IC on which this diode is mounted. Alternatively, a power source for application to the control electrode 12 may be formed inside the power IC.
In FIG. 8, the control electrode 12 is provided only on the p-type diffusion region 5 side, but a similar control electrode may be provided on the n-type diffusion region 4 side. Also in this case, a voltage is applied to the control electrode so that an inversion layer is formed on the surface layer of the n-type diffusion region 4 during forward operation.

  At this time, since the holes 24 flow into the p-type short region 9 through the low resistance region formed in the surface layer of the n-type diffusion region 4, the hole extraction effect of the p-type short region 9 can be promoted. As a result, the amount of stored charge during forward operation is reduced, and the speed of the diode can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of 1st Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). The figure which shows the ON state at the time of forward operation | movement of the diode of FIG. The figure which shows the state at the time of reverse recovery operation | movement of the diode of FIG. The figure which shows the relationship between Vf and reverse recovery current of the diode of FIG. The figure which shows the relationship between Vf of a diode of FIG. 1, and a reverse recovery charge amount It is a block diagram of the semiconductor device of 2nd Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the X1-X1 line | wire of (a), (c) is ( Sectional view of the principal part cut along line X2-X2 in a) It is a block diagram of the semiconductor device of 3rd Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the X1-X1 line | wire of (a), (c) is ( Sectional view of the principal part cut along line X2-X2 in a) It is a block diagram of the semiconductor device of 4th Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the X1-X1 line | wire of (a), (c) is ( Sectional view of the principal part cut along line X2-X2 in a) The figure which shows the ON state at the time of forward operation | movement of the diode of FIG. FIG. 2 is a configuration diagram of a conventional semiconductor device, where (a) is a plan view of the main part, and (b) is a cross-sectional view of the main part taken along line XX of (a). Sectional drawing of the principal part of another conventional semiconductor device

Explanation of symbols

1 semiconductor substrate 2 oxide film 3 n-type semiconductor layer 4 n-type diffusion region 5 p-type diffusion region 6 n-type cathode region 6a end of n-type cathode region 7 p-type anode region 7a end of p-type anode region 8 p-type Short region 8a End of p-type short region 9 n-type short region 9a End of n-type short region 10 Cathode electrode 11 Anode electrode 21, 23, 25 Electron 22, 24, 26 Hole 100 SOI substrate

Claims (12)

A first conductivity type semiconductor layer, a first conductivity type first diffusion region and a second conductivity type second diffusion region formed separately from a surface layer of the semiconductor layer, and a surface layer of the first diffusion region; A third diffusion region of the first conductivity type and a fourth diffusion region of the second conductivity type formed in contact with each other; a fifth diffusion region of the second conductivity type formed in a surface layer of the second diffusion region; A first main electrode in contact with three diffusion regions and the fourth diffusion region, and a second main electrode in contact with the fifth diffusion region;
A semiconductor device, wherein a distance between the third diffusion region and the fifth diffusion region is equal to or less than a distance between the fourth diffusion region and the fifth diffusion region. A first conductivity type semiconductor layer, a first conductivity type first diffusion region and a second conductivity type second diffusion region formed separately from a surface layer of the semiconductor layer, and a surface layer of the first diffusion region; A third diffusion region of the first conductivity type formed, a fifth diffusion region of the second conductivity type formed in contact with the surface layer of the second diffusion region, and a sixth diffusion region of the first conductivity type; A first main electrode in contact with three diffusion regions; a second main electrode in contact with the fifth diffusion region and the sixth diffusion region;
A semiconductor device, wherein a distance between the third diffusion region and the fifth diffusion region is equal to or less than a distance between the third diffusion region and the sixth diffusion region. A first conductivity type semiconductor layer, a first conductivity type first diffusion region and a second conductivity type second diffusion region formed separately from a surface layer of the semiconductor layer, and a surface layer of the first diffusion region; A third diffusion region of the first conductivity type and a fourth diffusion region of the second conductivity type formed in contact with each other, a fifth diffusion region of the second conductivity type and a first conductivity formed in the surface layer of the second diffusion region. A sixth diffusion region having a shape, a first main electrode in contact with the third diffusion region and the fourth diffusion region, and a second main electrode in contact with the fifth diffusion region and the sixth diffusion region. And
The distance between the third diffusion region and the fifth diffusion region is equal to or less than the distance between the fourth diffusion region and the fifth diffusion region, and the distance between the third diffusion region and the fifth diffusion region is the first distance. A semiconductor device having a distance equal to or shorter than a distance between three diffusion regions and the sixth diffusion region. The semiconductor device according to claim 1, wherein the third diffusion region is disposed between the fourth diffusion region and the fifth diffusion region. 4. The semiconductor device according to claim 2, wherein the fifth diffusion region is disposed between the third diffusion region and the sixth diffusion region. 5. The semiconductor device according to claim 3, wherein the third diffusion region and the fifth diffusion region are disposed between the fourth diffusion region and the sixth diffusion region. The semiconductor device according to claim 3, wherein the third diffusion region is disposed so as to face the sixth diffusion region, and the fourth diffusion region is opposed to the fifth diffusion region. The semiconductor device according to claim 3, wherein the third diffusion region is disposed so as to face the fifth diffusion region, and the fourth diffusion region is opposed to the sixth diffusion region. 9. The semiconductor device according to claim 1, wherein a plurality of the third diffusion regions and a plurality of the fourth diffusion regions are alternately arranged. 9. The semiconductor device according to claim 2, wherein a plurality of the fifth diffusion regions and a plurality of the sixth diffusion regions are alternately arranged. 10. The semiconductor device according to claim 9, further comprising a control electrode provided through an insulating film on a surface of the first diffusion region sandwiched between the fourth diffusion region and the semiconductor layer. . 11. The semiconductor device according to claim 10, further comprising a control electrode provided via an insulating film on a surface of the second diffusion region sandwiched between the sixth diffusion region and the semiconductor layer. .

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