CN103594377A - Manufacturing method of integrated Schottky split-gate type power MOS device - Google Patents
Manufacturing method of integrated Schottky split-gate type power MOS device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Abstract
The invention discloses a manufacturing method of an integrated Schottky split-gate type power MOS device. The integrated Schottky split-gate type power MOS device is manufactured by utilizing 6 mask templates. Compared with a traditional manufacturing process of a split-gate type channel power MOS device, the manufacturing method of the integrated Schottky split-gate type power MOS device can reduce process steps and process difficulty.
Description
Technical field
The present invention relates to semiconductor applications, particularly the manufacture method of a kind of integrated schottky splitting bar type power metal-oxide semiconductor (METAL-OXIDE-SEMICONDUCTOR, MOS) device.
Background technology
In 20th century the nineties, the development of power groove metal-oxide semiconductor (MOS) MOS field-effect transistor (Power Trench MOSFET) and the main direction of studying of industrialization technology, mainly minimizing the forward conduction resistance (Ron) of low voltage power devices.Today, the structure of power groove MOS device has been applicable to most of power metal oxide semiconductor field-effect transistors (METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR, MOSFET) in application, and the characteristic of device constantly approaches the one dimension restriction of silicon materials.Reduction surface field REduced SURface Field(RESURF) proposition of technology, can make puncture voltage is that the power groove MOS device of 600V is over the one dimension restriction of silicon materials.Then, according to the operation principle of RESURF, there is again splitting bar type groove (Split-Gate Trench) MOSFET device architecture, can under the low pressure of the 30V left and right of scaled down, surpass the one dimension restriction of silicon materials.Therefore, splitting bar type groove MOSFET device, in low, middle pressure (20～200V) scope, has lower forward conduction resistance, occupies obvious advantage.
But although the terminal structure of current splitting bar type groove MOSFET device can guarantee the withstand voltage of device, complicated structure needs too much technique and reticle to coordinate, therefore must increase the cost of device and reduce the functional reliability of device.When improving integrated level and reducing photoetching number of times, effectively reduce the most the method for cost.But the lifting that integrated level is high is limited to the capacity of equipment of Semiconductor enterprises and technological ability and is difficult to realize, or can bring negative impact to the switching characteristic of device.Therefore, optimised devices result, Optimization Technology manufacturing process, when having improved the reliability of splitting bar type groove MOSFET device, has reduced the cost of manufacture of device.
Publication number is U.S. Patent application < < integrated splitting bar power semiconductor transistor and the manufacture method > > (< < Power Semiconductor Devices With Trenched Shielded Split Gate Transistor And Methods Of Manufacture > >) of US20090008709A, a kind of splitting bar type groove MOSFET device and terminal structure thereof of 7 reticle are disclosed, as shown in Figure 1, 7 reticle used are respectively: channeled layer reticle 1, the reticle 2 of isolating when the polysilicon while forming terminal and oxide return etching, active area is with field oxide territory reticle 3, electrode contact hole, source reticle 4, gate electrode fairlead reticle 5, metal level reticle 6, surface passivation, photoetching pressure welding point 7.Specifically as shown in Figure 1.Be characterized in terminal homology electrode contact.But the gate electrode fairlead of device, in device inside active area, can take cellular active region area, thus the utilance of reduction wafer.
Publication number is the manufacture method > > (< < Method of Forming high density trench FET with Integrated Schottky Diode > >) of high density trench field effect transistor of the United States Patent (USP) < < integrated schottky diode of US7713822B2, a kind of zanjon groove MOSFET device and terminal structure thereof of 5 reticle are disclosed, as shown in Figure 2, 5 reticle used are respectively: deep plough groove etched reticle 1, barrier layer, N+ source reticle 2, electrode contact hole, source reticle 3, metal level reticle 4, surface passivation, photoetching pressure welding point 5.Specifically as shown in Figure 2.Its feature is: this splitting bar power MOS (Metal Oxide Semiconductor) device with groove is at the inner integrated schottky diode of cellular, and required reticle is less.But the processing step that this patent provides is comparatively complicated, and much technique is difficult to accurate control, such as techniques such as raceway groove CONCENTRATION DISTRIBUTION and source electrode hole etchings.In order to reserve Schottky contacts area proportion in the electrode of source, it is very little that the spacing of two grooves can not be done, and understands like this optimal design of display device.And this patent does not provide the terminal structure of device, so actual process manufacture may also need other mask plate.
Some shortcomings that exist in the technical process of above-mentioned 2 patents: in patent one US20090008709A, with splitting bar electrode as terminal structure, in manufacture process, need extra mask version, splitting bar electrode is covered, through returning after the techniques such as etching, oxidation, deposit of groove structure in active area, then carry out planarization, increased the complexity of technique.In patent two US7713822B2, pass through N-type Implantation for the second time, realize Schottky and the ohmic contact in cellular with electrode contact hole, source etching, so in technique, be difficult to control, if it is bad that N-type Implantation is controlled, be easy to increase the leakage current of device, thereby weaken device performance.
Summary of the invention
The present invention proposes a kind of manufacture method of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device, for solving the problem of prior art complex manufacturing technology.
On the one hand, provide a kind of manufacture method of integrated schottky splitting bar type power metal-oxide semiconductor MOS device, having comprised:
Use the first mask plate to carry out etching groove to silicon chip;
Use the second mask plate to carry out P-Implantation and P+ Implantation to described silicon chip, wherein, the below, region of covering when described the second mask plate carries out P-Implantation is Schottky contacts region;
Use the 3rd mask plate to carry out N+ Implantation to described silicon chip, wherein, N+ Implantation region and P+ Implantation region are along table top length direction alternative arrangement;
Use the 4th mask plate on described silicon chip, to make electrode contact hole;
Use the 5th mask plate in the separated etching of the enterprising row metal of described silicon chip;
Use the 6th mask plate on described silicon chip, to carry out photoetching pressure welding point.
In the present invention, by six reticle, realize a kind of domain and technological design of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device, also short circuit is drawn respectively to by ,P+ district, device source electrode Nei N+ district and Schottky contact region, Schottky contacts proportion in the electrode of source is not affected by groove pitch, can optimal design device performance.Whole operation needs six versions, the corresponding simplification of technique.When guaranteeing that device has ultralow conducting resistance, do not affect the puncture voltage of device, integrated schottky in device cellular, and improve devices switch speed, improved again the utilization rate of silicon chip.
Accompanying drawing explanation
Fig. 1 is US20090008709A disclosed splitting bar type power MOS (Metal Oxide Semiconductor) device with groove and terminal structure schematic diagram thereof;
Fig. 2 is the splitting bar power MOS (Metal Oxide Semiconductor) device with groove structural representation of the disclosed integrated schottky of US7713822B2;
Fig. 3 is integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device with groove process flow diagram disclosed by the invention;
Fig. 4 is a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device mask plate alignment stack schematic diagram disclosed by the invention;
Fig. 5 is the schematic diagram of the trench etching mask version of a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention;
Fig. 6 is the schematic diagram of the P-/P+ ion implantation mask version of a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention;
Fig. 7 is the schematic diagram of the N+ ion implantation mask version of a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention;
Fig. 8 is the schematic diagram of the electrode contact hole mask plate of a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention;
Fig. 9 is the schematic diagram of the metal separation mask plate of a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention;
Figure 10 is the schematic diagram of the metal crimp solder joint mask plate of a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention;
Figure 11-16th, a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention is with the schematic diagram of the structural change of different process step.
Embodiment
Below in conjunction with accompanying drawing, implementation of the present invention is described.
The embodiment of the present invention realizes a kind of domain and technological design of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device by six reticle, also short circuit is drawn respectively to by ,P+ district, device source electrode Nei N+ district and Schottky contact region, Schottky contacts proportion in the electrode of source is not affected by groove pitch, can optimal design device performance.Whole operation needs six versions, the corresponding simplification of technique.When guaranteeing that device has ultralow conducting resistance, do not affect the puncture voltage of device, integrated schottky in device cellular, and improve devices switch speed, improved again the utilization rate of silicon chip.
The embodiment of the present invention provides a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device with groove domain, comprise: trench etching mask version (once version), P-ion implantation mask version (secondary version), P+ ion implantation mask version (with secondary version), N+ ion implantation mask version (three versions), electrode contact hole mask plate (four versions), metal separation etch mask version (five versions), photoetching pressure welding point mask plate (six versions).P-Implantation and P+ Implantation share same mask plate; In domain, N+ Implantation and P+ ion are on domain, along table top length direction alternative arrangement, and Schottky contacts ratio, for Schottky contacts region, can be controlled by adjusting this edition size in P-ion implantation mask version (this region is etching reserve area) below.
Preferably, active area groove and termination environment groove be etching generation simultaneously in technique, and is realized and be communicated with short circuit by electrode contact hole (four versions) and metal separation etching (five versions), and gate electrode is drawn.By such scheme, can reduce processing step and reduce technology difficulty.
Preferably, in device active region, groove structure surrounds mesa structure, and mesa structure is regular list structure.By such scheme, can improve Electric Field Distribution concentration effect when table top is critical to be punctured, improve device electric breakdown strength.
The embodiment of the present invention also provides a kind of manufacture method of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device, below the method is elaborated.
Fig. 4 has provided six mask plate alignment stack schematic diagrames of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device with groove: wherein, 401 is gate groove etching mask version, 402 is P-/P+ ion implantation mask version, 403 is N+ ion implantation mask version, 404 is gate electrode fairlead mask plate, and 405 is source electrode or Schottky electrode fairlead etching mask version, and 406 is separating metal mask, 407 is gate electrode photoetching pressure welding point, and 408 is source electrode photoetching pressure welding point.In domain, process structure corresponding to AA` cross section will be introduced below.Below each mask plate is illustrated respectively.Fig. 5 is the schematic diagram of the trench etching mask version (once version, the first mask plate) of a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention; Wherein, 501 is mesa region, and 502 is trench region.Fig. 6 is the schematic diagram of the P-/P+ ion implantation mask version (secondary version, the second mask plate) of a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention; 601 is P-/P+ ion implantation mask region, and 602 is P-/P+ Implantation region.Fig. 7 is the schematic diagram of the N+ ion implantation mask version (three version, the 3rd mask plate) of a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention; 701 is N+ ion implantation mask region, and 702 is N+ Implantation region.Fig. 8 is the schematic diagram of the electrode contact hole mask plate (four version, the 4th mask plate) of a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention; 801 is gate electrode contact hole, and 802 is electrode contact hole, source.Fig. 9 is the schematic diagram of the metal separation mask plate (five version, the 5th mask plate) of a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention; 901 is metal gap; 902 is metallic region.Figure 10 is the schematic diagram of the metal crimp solder joint mask plate (six version, the 6th mask plate) of a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention; 1001 is gate electrode pressure welding point, and 1002 is source electrode pad, and 1003 is pressure welding point gap.
Fig. 3 has provided the technological process of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device with groove.Figure 11-16th, a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device disclosed by the invention is with the schematic diagram of the structural change of different process step.The line of cut in device AA` interface schematic diagram corresponding diagram 4 wherein.According to the traditional handicraft of groove MOSFET, epitaxial growth N-district 1103 on N+ substrate 1105, growth buffering silicon dioxide layer 1102, grown silicon nitride 1101 is sheltered dielectric layer.Silicon nitride can be grown by low pressure chemical vapor deposition method, spin coating photoresist on silicon nitride, utilizes trench etching mask version (once version), as shown in figure 11, through photo-mask process, define groove gate region, adopt dry etching (anisotropy) to form deep groove structure 1104.Difference LPCVD method deposit silicon dioxide, in-situ doped polysilicon 1204, and carry out chemical-mechanical planarization.Then return etch polysilicon and silicon dioxide, to designated depth, place stops, by dry method, generate grid oxygen, and on polysilicon top, bottom, generate isolating oxide layer simultaneously, then the in-situ doped polysilicon 1202/1203 of LPCVD method growth N-type, and carrying out chemical-mechanical planarization, corrosion polysilicon is to oxide layer surface, as shown in figure 12.Spin coating photoresist on silicon nitride, utilizes bis-versions of P-ion implantation mask version 1302() through photo-mask process, define P injection zone, inject B element, annealing generates behind p-body district (p tagma), carry out again a B element and inject, at silicon face, form P+ layer, as shown in figure 13.Remove after silicon nitride, spin coating photoresist, utilizes tri-versions of N+ ion implantation mask version 1401() through photo-mask process, define N+ injection zone, then inject P or As impurity, form N+ region, as shown in figure 14.Remove photoresist, deposit silicon dioxide, spin coating photoresist on silicon dioxide, utilize tetra-versions of electrode contact hole mask plate 1501() through photo-mask process, define contact hole region, adopt dry etching (anisotropy) to etch 1502 ,P+ districts 1504, N+ district, Schottky contact region 1503 and gate electrode contact zone 1505, as shown in figure 15.Deposited alloys, forms ohmic contact and Schottky contacts at source electrode.Spin coating photoresist on metal, utilizes metal separation mask plate (five versions), through photo-mask process, defines metal etch region, adopts dry etching (anisotropy) to etch away metal, and wherein top, active area is source electrode 1601.Terminal top is gate electrode 1602, as shown in figure 16.At top device growth dense oxide, by surface passivation, spin coating photoresist in passivation, utilize metal crimp solder joint mask plate (six versions), through photo-mask process, define passivation etch areas, adopt dry etching (anisotropy) to etch photoetching pressure welding point, then to device thinning back side, and metallization, finally carries out device cutting and encapsulation.
In the embodiment of the present invention, utilize 6 masks to complete a kind of integrated schottky splitting bar type power MOS device construction.Contrast traditional splitting bar type power MOS (Metal Oxide Semiconductor) device with groove manufacturing process, the integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device with groove that this patent proposes, reduces processing step and technology difficulty.(1), device terminal trenches structure, with groove structure in active area, forms, and is communicated with gate electrode by metal electrode in same processing step, and gate electrode is drawn.(2), P-/P+ ion implantation technology shares a mask plate.And Schottky contacts ratio is by P-mask plate size Control, and not limited by groove pitch.(3), in device active region, groove structure surrounds mesa structure, and mesa structure is regular list structure.Can improve Electric Field Distribution concentration effect when table top is critical to be punctured, improve device electric breakdown strength.
The embodiment of the present invention also provides a kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device, if design puncture voltage is 140V, Schottky contacts accounts for the more than 30% of the total contact of source electrode.According to splitting bar type power MOS (Metal Oxide Semiconductor) device with groove design principle, select N-drift region impurity to be defined as 1.0 * 10
16/ cm
3(0.497 Ω cm), after growth silicon dioxide and silicon nitride, etches after trench region by trench mask version, silicon body is carried out to etching, and groove pitch (table top) is 2.6 μ m, and groove width is 2.4 μ m, groove angle is vertical as far as possible, improves silicon chip utilance.Remove after silicon nitride deposit silicon dioxide and polysilicon, wherein thick silicon oxide approximately 0.8 μ m.Remove after unnecessary silicon nitride, by dry method, generate grid oxygen, thickness is 45～55nm, and on polysilicon top, bottom, generate isolating oxide layer simultaneously, thickness is greater than 100nm, then adopt the in-situ doped polysilicon of LPCVD method growth N-type, contact resistance is lower than polysilicon 20 Ω/ (20 Ω/square), and multi crystal silicon chemical machinery planarization is surperficial to oxide layer.By P-ion implantation mask carving eating away P-injection zone, B Implanted impurity also carries out rapid thermal annealing formation P tagma, and the reserved N+ source electrode degree of depth is 0.2 μ m, and channel length is 0.5-0.6 μ m.Then inject BF2, dosage is 1 * e
14/ cm
2, energy is 20Kev, forms P+ region.Remove after silicon nitride, utilize N+ to inject mask plate, inject P or As and form N+ source region, implantation dosage is 1.5 * e
14/ cm
2, energy is 25Kev, N+ injects the degree of depth and is about 200nm.Remove silicon nitride, deposit silicon dioxide, under the mask plate effect of electrode contact hole, etches the contact hole of gate electrode and source electrode.After surface sputtering metal, utilize metal separation mask plate, etching metal, makes Different electrodes separately, grill-protected electrode homology electrode short circuit now, gate electrode with the top polysilicon in terminal trenches by metal short circuit.And form gate electrode metal region at the left upper end of Fig. 4, and for gate electrode pressure welding point reserves sufficient space, after surface passivation, utilize photoetching pressure welding point mask plate, etching generates gate electrode pressure welding point and source electrode pad.Here two P-/P+ mask plate sizes have determined that Schottky contacts area accounts for the percentage of the source electrode contact gross area.
The embodiment of the present invention also provides another kind of integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device.Comprise trench etching mask version (once version), P-/P+ ion implantation mask version (secondary version), N+ ion implantation mask version (three versions), electrode contact hole mask plate (four versions), metal separation etch mask version (five versions), photoetching pressure welding point mask plate (six versions).P-Implantation and P+ Implantation share same mask plate; In domain, N+ Implantation and P+ ion are on domain, along table top length direction alternative arrangement, and Schottky contacts ratio, for Schottky contacts region, can be controlled by adjusting this edition size in P-ion implantation mask version (this region is etching reserve area) below.Active area groove and termination environment groove be etching generation simultaneously in technique, and is realized and be communicated with short circuit by electrode contact hole (four versions) and metal separation etching (five versions), and gate electrode is drawn.Reduce processing step and difficulty.In device active region, groove structure surrounds mesa structure, and mesa structure is regular list structure.Can improve Electric Field Distribution concentration effect when table top is critical to be punctured, improve device electric breakdown strength.
Above-mentioned for the present invention especially exemplified by embodiment, not in order to limit the present invention.Integrated schottky splitting bar type power MOS (Metal Oxide Semiconductor) device with groove domain provided by the invention and technological design are equally applicable to split longitudinally power semiconductor and their variant such as grid type groove power MOS or common groove MOS.Do not departing from the spirit and scope of the invention, can do a little adjustment and optimization, these adjustment and optimization also should be within protection scope of the present invention.
Claims (4)
1. a manufacture method for integrated schottky splitting bar type power metal-oxide semiconductor MOS device, is characterized in that, comprising:
Use the first mask plate to carry out etching groove to silicon chip;
Use the second mask plate to carry out P-Implantation and P+ Implantation to described silicon chip, wherein, the below, region of covering when described the second mask plate carries out P-Implantation is Schottky contacts region;
Use the 3rd mask plate to carry out N+ Implantation to described silicon chip, wherein, N+ Implantation region and P+ Implantation region are along table top length direction alternative arrangement;
Use the 4th mask plate on described silicon chip, to make electrode contact hole;
Use the 5th mask plate in the separated etching of the enterprising row metal of described silicon chip;
Use the 6th mask plate on described silicon chip, to carry out photoetching pressure welding point.
2. method according to claim 1, is characterized in that, uses the first mask plate to carry out etching groove to silicon chip and comprises:
Use described first to flood version and on described silicon chip, etch active area groove and termination environment groove simultaneously.
3. method according to claim 2, is characterized in that, the metal separation etching that described active area groove is made by described electrode contact hole and described the 5th mask plate with termination environment groove realizes and is communicated with short circuit.
4. according to the method in any one of claims 1 to 3, it is characterized in that, in the active area of described device, groove structure surrounds mesa structure, and described mesa structure is regular list structure.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106443401A (en) * | 2016-10-16 | 2017-02-22 | 北京工业大学 | Power MOS device temperature rise and thermal resistance component test device and method |
| CN111883527A (en) * | 2020-07-10 | 2020-11-03 | 安徽安芯电子科技股份有限公司 | Groove type Schottky barrier chip for manufacturing large-size wafer |
| WO2021082158A1 (en) * | 2019-10-28 | 2021-05-06 | 苏州东微半导体有限公司 | Semiconductor power device terminal structure |
| CN114597130A (en) * | 2022-04-02 | 2022-06-07 | 致瞻科技(上海)有限公司 | Silicon carbide MOSFET device based on split gate and manufacturing method thereof |
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| CN106443401A (en) * | 2016-10-16 | 2017-02-22 | 北京工业大学 | Power MOS device temperature rise and thermal resistance component test device and method |
| WO2021082158A1 (en) * | 2019-10-28 | 2021-05-06 | 苏州东微半导体有限公司 | Semiconductor power device terminal structure |
| CN111883527A (en) * | 2020-07-10 | 2020-11-03 | 安徽安芯电子科技股份有限公司 | Groove type Schottky barrier chip for manufacturing large-size wafer |
| CN114597130A (en) * | 2022-04-02 | 2022-06-07 | 致瞻科技(上海)有限公司 | Silicon carbide MOSFET device based on split gate and manufacturing method thereof |
| CN114597130B (en) * | 2022-04-02 | 2022-12-27 | 致瞻科技(上海)有限公司 | Silicon carbide MOSFET device based on split gate and manufacturing method thereof |
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