CN105280692A - Insulated gate bipolar transistor and method of manufacturing the same - Google Patents
Insulated gate bipolar transistor and method of manufacturing the same Download PDFInfo
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- CN105280692A CN105280692A CN201410383362.3A CN201410383362A CN105280692A CN 105280692 A CN105280692 A CN 105280692A CN 201410383362 A CN201410383362 A CN 201410383362A CN 105280692 A CN105280692 A CN 105280692A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
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- 238000000034 method Methods 0.000 claims description 41
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
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- 238000000576 coating method Methods 0.000 claims description 18
- 239000011248 coating agent Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
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- 239000000377 silicon dioxide Substances 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 230000000052 comparative effect Effects 0.000 description 25
- 239000003989 dielectric material Substances 0.000 description 21
- 238000005229 chemical vapour deposition Methods 0.000 description 19
- -1 boron ion Chemical class 0.000 description 17
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- 238000005468 ion implantation Methods 0.000 description 14
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- 239000002184 metal Substances 0.000 description 10
- 238000000059 patterning Methods 0.000 description 10
- 239000004020 conductor Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
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- 238000004458 analytical method Methods 0.000 description 6
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- 238000005137 deposition process Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
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- 239000010931 gold Substances 0.000 description 4
- 229910001449 indium ion Inorganic materials 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 229910052741 iridium Inorganic materials 0.000 description 4
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 229910052703 rhodium Inorganic materials 0.000 description 4
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- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 4
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- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
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- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
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- 229910005540 GaP Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
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- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 2
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- 229910001925 ruthenium oxide Inorganic materials 0.000 description 2
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- 238000004062 sedimentation Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
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- 229910017121 AlSiO Inorganic materials 0.000 description 1
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- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 150000004645 aluminates Chemical class 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
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- 150000001875 compounds Chemical class 0.000 description 1
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- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
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- 238000005498 polishing Methods 0.000 description 1
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- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
An embodiment of the present invention provides an insulated gate bipolar transistor, including: a substrate; the collector region is provided with a first conduction type collector region and an adjacent second conduction type collector region, and extends into the substrate from the lower surface of the substrate; a collector electrode electrically connected to the second conductive type collector region and electrically insulated from the first conductive type collector region by a collector insulating layer; a first emitter region, a second emitter region, and a base region of a first conductivity type; an emitter electrode, a gate dielectric layer, and a gate electrode disposed on the gate dielectric layer. The embodiment of the invention also provides a manufacturing method of the insulated gate bipolar transistor.
Description
Technical field
The embodiment of the present invention relates to semiconductor technology, and relates to Insulated Gate Bipolar transistor and manufacture method thereof especially.
Background technology
Power component is widely used in for driving and controlling high-power electrical article and vehicular applications etc.This power component comprises the power transistor of the large output carrying out switching manipulation.This kind of power transistor, except power metal oxide semiconductor field-effect transistor (MOSFET), Power bipolar transistor, also comprise Insulated Gate Bipolar transistor (insulatedgatebipolartransistor, IGBT).Insulated Gate Bipolar transistor has the high input impedance of mos field effect transistor and the low on-resistance of bipolar transistor concurrently.
Summary of the invention
The embodiment of the present invention provides a kind of Insulated Gate Bipolar transistor, comprising: substrate, has the first conductivity type, and has upper surface and lower surface; First conductive collector district and the second adjacent conductive collector district, extend in substrate from the lower surface of substrate, wherein the second conductivity type is different from the first conductivity type; Collector electrode, is electrically connected the second conductive collector district, and is electrically insulated by collector electrode insulating barrier and the first conductive collector district; First emitter region, has the second conductivity type, extends in substrate from the upper surface of substrate; Second emitter region, there is the first conductivity type, and extend in the first emitter region from the upper surface of substrate, wherein substrate be not formed the first emitter region, the second emitter region, the first conductive collector district and the second conductive collector district part be as the first conductivity type base region; Emitter electrode, is electrically connected with the first emitter region and the second emitter region; Gate dielectric, is located on the first emitter region, the second emitter region and substrate; And gate electrode, be located on gate dielectric.
The embodiment of the present invention also provides a kind of Insulated Gate Bipolar transistor, comprising: substrate, has the first conductivity type, and has upper surface and lower surface; First conductive collector district and the second adjacent conductive collector district, extend in substrate from the lower surface of substrate, wherein the second conductivity type is different from the first conductivity type; Collector electrode, is electrically connected the second conductive collector district, and is electrically insulated by collector electrode insulating barrier and the first conductive collector district; First emitter region, has the second conductivity type, and extends in substrate from the upper surface of substrate; Second emitter region, there is the first conductivity type, and extend in the first emitter region from the upper surface of substrate, wherein substrate be not formed the first emitter region, the second emitter region, the first conductive collector district and the second conductive collector district part be as the first conductivity type base region; Emitter electrode, is electrically connected with the first emitter region and the second emitter region; Groove (trench), extends from the upper surface of substrate and passes through the first emitter region and the second emitter region and enter in substrate; Gate dielectric, is inside lining in sidewall and the bottom of groove; Gate electrode, to be located on gate dielectric and to insert groove; And inter-electrode dielectric layer, be located between gate electrode and emitter electrode.
The embodiment of the present invention provides again a kind of manufacture method of Insulated Gate Bipolar transistor, comprising: provide substrate, has the first conductivity type, and has upper surface and lower surface; Form the first emitter region, there is the second conductivity type, extend in substrate from the upper surface of substrate, and the second conductivity type is different from the first conductivity type; Form gate dielectric on the first emitter region and substrate; Form gate electrode on gate dielectric; Form the second emitter region, the second emitter region has the first conductivity type, and extends in the first emitter region from the upper surface of substrate; Form emitter electrode, emitter electrode is electrically connected with the first emitter region and the second emitter region; Form the first conductive collector district, extend in substrate from the lower surface of substrate; Form collector electrode insulating barrier in the first conductive collector district; Form the second conductive collector district adjacent to the first conductive collector district, wherein substrate be not formed the first emitter region, the second emitter region, the first conductive collector district and the second conductive collector district part be as the first conductivity type base region; And formation collector electrode, collector electrode is electrically connected the second conductive collector district, and is electrically insulated by collector electrode insulating barrier and the first conductive collector district.
The embodiment of the present invention reoffers a kind of manufacture method of Insulated Gate Bipolar transistor, comprising: provide substrate, has the first conductivity type, and has upper surface and lower surface; Form the first emitter region, there is the second conductivity type, and extend in substrate from the upper surface of substrate, and the second conductivity type is different from the first conductivity type; Form groove (trench), extend from the upper surface of substrate and pass through the first emitter region in substrate; Compliance forms gate dielectric on the sidewall and bottom of groove; Form gate electrode and insert groove on gate dielectric; Form the second emitter region, the second emitter region has the first conductivity type, and extends in the first emitter region from the upper surface of substrate; Form inter-electrode dielectric layer on gate electrode; Form emitter electrode, emitter electrode is electrically connected with the first emitter region and the second emitter region, and inter-electrode dielectric layer is located between gate electrode and emitter electrode; Form the first conductive collector district, extend in substrate from the lower surface of substrate; Form collector electrode insulating barrier in the first conductive collector district; Form the second conductive collector district adjacent to the first conductive collector district, wherein substrate be not formed the first emitter region, the second emitter region, the first conductive collector district and the second conductive collector district part be as the first conductivity type base region; And formation collector electrode, collector electrode is electrically connected the second conductive collector district, and is electrically insulated by collector electrode insulating barrier and the first conductive collector district.
For the features and advantages of the present invention can be become apparent, cited below particularly go out preferred embodiment, and coordinate institute's accompanying drawings, be described in detail below.
Accompanying drawing explanation
Fig. 1-7 is the profiles in Insulated Gate Bipolar transistor each stage in its manufacture method of the embodiment of the present invention;
Fig. 8-17 is the profiles in Insulated Gate Bipolar transistor each stage in its manufacture method of another embodiment of the present invention;
Figure 18 is the switch performance analysis chart of Insulated Gate Bipolar transistor; And
Figure 19 is the puncture voltage analysis chart of Insulated Gate Bipolar transistor.
Symbol description:
100 Insulated Gate Bipolar transistors;
110 substrates;
110A upper surface;
110B lower surface;
120 first emitter regions;
130a gate dielectric;
130b inter-electrode dielectric layer;
140 gate electrodes;
150 second emitter regions;
160 the 3rd emitter regions;
170 emitter electrodes;
180 collector electrode fates;
190 base stage fates;
190 ' first conductivity type base region;
200 heavy doping resilient coatings;
210 patterned mask layer;
220 openings;
230 first conductive collector districts;
240 insulation material layers;
250 patterned mask layer;
260 second conductive collector districts;
270 collector electrode insulating barriers;
280 collector electrodes;
300 Insulated Gate Bipolar transistors;
310 substrates;
310A upper surface;
310B lower surface;
320 first emitter regions;
330 grooves;
340 gate dielectrics;
350 gate electrodes;
360 second emitter regions;
370 inter-electrode dielectric layer;
380 openings;
390 the 3rd emitter regions;
400 emitter electrodes;
410 collector electrode fates;
420 base stage fates;
420 ' first conductivity type base region;
430 heavy doping resilient coatings;
440 patterned mask layer;
450 openings;
460 first conductive collector districts;
470 insulation material layers;
480 patterned mask layer;
490 second conductive collector districts;
500 collector electrode insulating barriers;
510 collector electrodes;
T1-T6 thickness;
W1-W8 width.
Embodiment
Insulated Gate Bipolar transistor below for the embodiment of the present invention elaborates.Describing it is to be understood that provides many different embodiments or example, in order to implement different pattern of the present invention.The specific element of the following stated and arrangement mode are to the greatest extent for simply to describe the present invention.Certainly, these are only in order to illustrate but not restriction of the present invention.In addition, label or the sign of repetition may be used in different embodiments.These repeat only clearly to describe the present invention in order to simple, do not represent between discussed different embodiment and/or structure and have any relevance.Moreover, when address one first material layer to be positioned on one second material layer or on time, comprise the situation that the first material layer directly contacts with the second material layer.Or, be also separated with the situation of other material layer one or more between possibility, in this case, may not directly contact between the first material layer with the second material layer.
Must it is to be understood that to describe or illustrated element can exist by the various forms known by this technology personage for special.In addition, when certain layer other layer or substrate " on " time, likely refer to that " directly " is on other layer or substrate, or refer to that certain layer is on other layer or substrate, or refer to other layer of sandwiched between other layer or substrate.
In addition, the term of relativity may in embodiment, be used, such as " lower " or " bottom " and " higher " or " top ", to describe the relativeness of an illustrated element for another element.Accessible, if make it turn upside down the upset of illustrated device, then be described in " lower " side element will become element in " higher " side.
At this, the term ordinary representation of " about ", " approximately ", within 20% or other numerical value of a set-point or scope, is preferably within 10%, and better be within 5%.Be about quantity in this given quantity, meaning, namely when not having certain illustrated, still can imply the implication of " about ", " approximately ".
The embodiment of the present invention utilizes one first conductive collector district and collector electrode insulating barrier formed thereon to reduce closedown loss (turn-offloss) of this Insulated Gate Bipolar transistor and to maintain its conducting voltage (onvoltage) simultaneously.
See Fig. 1, first provide a substrate 110.This substrate 110 can comprise: the silicon of crystalline texture, polycrystalline structure or non crystalline structure or the elemental semiconductor of germanium; The compound semiconductors such as gallium nitride (GaN), carborundum (siliconcarbide), GaAs (galliumarsenic), gallium phosphide (galliumphosphide), indium phosphide (indiumphosphide), indium arsenide (indiumarsenide) or indium antimonide (indiumantimonide); The alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP or GaInAsP or other material be applicable to and/or combinations thereof.In one embodiment, this substrate 110 has the first conductivity type.Such as, when the first conductivity type is N-type, this substrate 110 can be lightly doped n-type substrate.In addition, substrate 110 has upper surface 110A and lower surface 110B.
Then, in substrate 110, the first emitter region 120 is formed.This first emitter region 120 extends in substrate 110 from the portion of upper surface 110A of substrate 110, and as shown in Figure 1, the width W 2 of the first emitter region 120 is less than the width W 1 of substrate 110.In embodiments of the present invention, the first emitter region 120 only extends into the partial depth of substrate 110, that is the thickness T2 of this first emitter region 120 is less than the thickness T1 of substrate 110.This first emitter region 120 has the second conductivity type, and this second conductivity type is different from the first conductivity type.Such as, this first emitter region 120 is formed by ion implantation step.In one embodiment, when this second conductivity type is P type, boron ion, indium ion or boron difluoride ion (BF can be injected in the region of this first emitter region 120 of predetermined formation
2 +).
Then, see Fig. 2, form gate dielectric 130a in the first emitter region 120 with on substrate 110, and form gate electrode 140 on gate dielectric 130a.In one embodiment, can first sequentially the blanket property covered deposit a dielectric materials layer (not illustrating) and the conductive material layer (not illustrating) that is located thereon on the upper surface 110A of substrate 110, then by this dielectric materials layer and conductive material layer through photoetching and etching manufacturing process respectively patterning to form gate dielectric 130a and gate electrode 140.
Above-mentioned dielectric materials layer (in order to form gate dielectric 130a) can be silica, silicon nitride, silicon oxynitride, high-k (high-k) dielectric material or other any applicable dielectric material or above-mentioned combination.This high-k (high-k) dielectric material can be metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, the nitrogen oxide of metal, metal aluminate, zirconium silicate, zircoaluminate.Such as, this high-k (high-k) dielectric material can be LaO, AlO, ZrO, TiO, Ta
2o
5, Y
2o
3, SrTiO
3(STO), BaTiO
3(BTO), BaZrO, HfO
2, HfO
3, HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr) TiO
3(BST), Al
2o
3, other high-k dielectric materials of other suitable material or combinations thereof.This dielectric materials layer is formed by chemical vapour deposition technique (CVD) or method of spin coating, this chemical vapour deposition technique such as can be Low Pressure Chemical Vapor Deposition (lowpressurechemicalvapordeposition, LPCVD), low temperature chemical vapor deposition method (lowtemperaturechemicalvapordeposition, LTCVD), be rapidly heated chemical vapour deposition technique (rapidthermalchemicalvapordeposition, RTCVD), plasma enhanced chemical vapor deposition method (plasmaenhancedchemicalvapordeposition, PECVD), atomic layer deposition method (the atomiclayerdeposition of atomic layer chemical vapor deposition method, or other conventional method ALD).
The material (that is material of gate electrode 140) of aforesaid conductive material layer can be amorphous silicon, polysilicon, one or more metal, metal nitride, conducting metal oxide or above-mentioned combination.Above-mentioned metal can include but not limited to molybdenum (molybdenum), tungsten (tungsten), titanium (titanium), tantalum (tantalum), platinum (platinum) or hafnium (hafnium).Above-mentioned metal nitride can include but not limited to molybdenum nitride (molybdenumnitride), tungsten nitride (tungstennitride), titanium nitride (titaniumnitride) and tantalum nitride (tantalumnitride).Above-mentioned conducting metal oxide can include but not limited to Ruthenium oxide (rutheniumoxide) and indium tin metal oxide (indiumtinoxide).The material of this conductive material layer is formed by aforesaid chemical vapour deposition technique (CVD), sputtering method, resistive heating evaporation, e-beam evaporation or other any applicable depositional mode, such as, in one embodiment, available Low Pressure Chemical Vapor Deposition (LPCVD) deposits and obtained amorphous silicon conductive material layer or polycrystalline silicon material layer between 525 ~ 650 DEG C, and its thickness range can be about
extremely about
In addition, the top of gate electrode 140 also can comprise a metal silicide layer, and this metal silicide can include but not limited to nickle silicide (nickelsilicide), cobalt silicide (cobaltsilicide), tungsten silicide (tungstensilicide), titanium silicide (titaniumsilicide), tantalum silicide (tantalumsilicide), platinum silicide (platinumsilicide) and silication erbium (erbiumsilicide).
As shown in Figure 2, gate electrode 140 is located on gate dielectric 130a.Specifically, gate dielectric 130a and gate electrode 140 are all located at the first emitter region 120 with on substrate 110, and gate dielectric 130a makes gate electrode 140 and the first emitter region 120 and substrate 110 be electrically insulated.
Then, continue see Fig. 2, in the first emitter region 120, form second emitter region 150 with the first conductivity type.Such as, in one embodiment, this second emitter region 150 is heavy doping first conductivity type, and in addition, this second emitter region 150 extends in the first emitter region 120 from the portion of upper surface 110A of substrate 110, as shown in Figure 2.In embodiments of the present invention, the second emitter region 150 only extends into the partial depth of the first emitter region 120, that is the thickness T3 of this second emitter region 150 is less than the thickness T2 of the first emitter region 120.This second emitter region 150 is formed by ion implantation step.Such as, when this first conductivity type is N-type, phosphonium ion or arsenic ion can be injected in the region of this second emitter region 150 of predetermined formation.
Then, alternative (optionally) carries out an ion implantation step to form one the 3rd emitter region 160 in the second emitter region 150.This 3rd emitter region 160 also extends in the first emitter region 120 from the portion of upper surface 110A of substrate 110, and thickness can equal or be not equal to T3.In general, the thickness of the 3rd emitter region 160 is deeper than T3.3rd adjacent second emitter region 150, emitter region 160.This 3rd emitter region 160 can be heavy doping second conductivity type.The overall width W3 of the second emitter region 150 and the 3rd emitter region 160 is less than the width W 2 of the first emitter region 120.Then, the top of its cover gate electrode 140 of inter-electrode dielectric layer 130b and sidewall and the second emitter region 150 (figure does not illustrate) is formed at upper surface 110A.
Then, etching covers the inter-electrode dielectric layer 130b (figure does not illustrate) of the second emitter region 150 of part.See Fig. 3, finally form top and the sidewall of inter-electrode dielectric layer 130b cover gate electrode 140.This inter-electrode dielectric layer 130b is in order to be electrically insulated by the emitter electrode of gate electrode 140 with follow-up formation.Inter-electrode dielectric layer 130b can be silica, silicon nitride, silicon oxynitride, boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), spin-on glasses (SOG), highdensity plasma (highdensityplasma, HDP) deposition or other any applicable dielectric material or above-mentioned combination.Inter-electrode dielectric layer 130b is formed by aforesaid chemical vapour deposition technique (CVD) or method of spin coating and patterning step.
Then, emitter electrode 170 is formed.This emitter electrode 170 is electrically connected with the second emitter region 150 and the 3rd emitter region 160.This emitter electrode 170 is coupled to the first emitter region 120 by the 3rd emitter region 160 again.Emitter electrode 170 can be the good metal material (such as aluminium copper (AlCu), Al-Si-Cu alloy (AlSiCu)) of the gold of single or multiple lift, chromium, nickel, platinum, titanium, aluminium, iridium, rhodium, copper, above-mentioned combination or other conductivity.This emitter electrode 170 is by being such as sputtering method, galvanoplastic, resistive heating evaporation, e-beam evaporation or other any applicable deposition process formation.
Then, after emitter electrode 170, alternative (optionally) thin substrate 110 (graphic do not illustrate the substrate after this thinning).The thickness of the substrate 110 after this thinning can be different according to operating voltage and component structure.
As shown in Figure 3, the bottom of substrate 110 is collector electrode fate 180, and the region in substrate 110 except the first emitter region 150, emitter region 120, second, the 3rd emitter region 160 and collector electrode fate 180 is as base stage fate 190.And after thin substrate 110, alternative (optionally) forms heavy doping resilient coating 200 in base stage fate 190 (that is being formed in the first follow-up conductivity type base region).This heavy doping resilient coating 200 has the first conductivity type, and can in order to reduce the size of the final Insulated Gate Bipolar transistor formed further.This heavy doping resilient coating 200 is formed by ion implantation step.Such as, when this first conductivity type is N-type, phosphonium ion or arsenic ion can be injected in the region of this heavy doping resilient coating 200 of predetermined formation.
Then, see Fig. 4, patterned mask layer 210 is formed on the lower surface 110B of substrate 110.This patterned mask layer 210 can be patterning photoresistance or is such as the patterned hard mask layer of silicon dioxide, silicon nitride or silicon oxynitride.This patterned mask layer 210 has the substrate 110 that opening 220 exposes predetermined formation first conductive collector district.
Then, carry out an ion implantation step to form the first conductive collector district 230 among substrate 110 via opening 220, this first conductive collector district 230 extends in substrate 110 from the lower surface 110B of substrate 110.This first conductive collector district 230 can reduce the carrier quantity corresponding with the second conductivity type in substrate 110.Such as, when the second conductivity type is P type, the quantity in hole in substrate 110 can be reduced.Therefore, this the first conductive collector district 230 can reduce closedown loss (turn-offloss), and does not affect conducting voltage (onvoltage), puncture voltage and latch-up current density (latchupcurrentdensity) simultaneously.In addition, owing to closing the reduction of loss, after device is closed, the carrier of flowing can reduce fast, therefore further can shorten the switching time (switchingtime) of device, the significantly performance of enhanced device.
In one embodiment, when this first conductivity type is N-type, phosphonium ion or arsenic ion can be injected to form the first conductive collector district 230 in the substrate 110 in predetermined formation first conductive collector district.The width W 4 in this first conductive collector district 230 can be the about 0.2-0.8 of substrate 110 width W 1 doubly, such as, be about 0.3-0.6 times.In this embodiment, if the width W 4 in this first conductive collector district 230 is wide, such as, wider than 0.8 times of substrate 110 width W 1, then corresponding with the second conductivity type in substrate 110 carrier quantity can be too low, and conducting voltage is increased.Such as, but if the width W 4 in this first conductive collector district 230 is narrow, be narrower than 0.2 times of substrate 110 width W 1, then it effectively cannot reduce carrier quantity corresponding with the second conductivity type in substrate 110, the closedown loss causing it effectively cannot reduce device.
See Fig. 5, after removing patterned mask layer 210, the blanket property covered forms insulation material layer 240 on the lower surface 110B of substrate 110.This insulation material layer 240 can be silica, silicon nitride, silicon oxynitride, boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), spin-on glasses (SOG) or other any applicable dielectric material or above-mentioned combination.Insulation material layer 240 is formed by aforesaid chemical vapour deposition technique (CVD) or method of spin coating and aforesaid patterning step.In one embodiment, tetraethoxysilane (TEOS can be used, tetraethyl-ortho-silicate) be reacting gas, coordinate patterning step to form insulation material layer 240 with the mode sedimentation of plasma enhancing (plasmaenhanced).In another embodiment, insulation material layer 240 is formed on the lower surface 110B of substrate 110 by the direct blanket property covered of thermal oxidation method.
Then, patterned mask layer 250 is formed on the lower surface 110B of substrate 110 to cover the first conductive collector district 230 and to expose the substrate 110 in predetermined formation second conductive collector district.This patterned mask layer 250 can be patterning photoresistance or is such as the patterned hard mask layer of silicon dioxide, silicon nitride or silicon oxynitride.
Then, as shown in Figure 6, another ion implantation step is carried out using patterned mask layer 250 as mask to form the second conductive collector district 260 among substrate 110.This second conductive collector district 260 also extends in substrate 110 from the lower surface 110B of substrate 110.This second conductive collector district 260 is adjacent to the first conductive collector district 230.In one embodiment, when this second conductivity type is P type, boron ion, indium ion or boron difluoride ion (BF can be injected in the region in this second conductive collector district 260 of predetermined formation
2 +).And substrate 110 is not formed with the first emitter region 150, emitter region 120, second, the part in the 3rd conductive collector district, emitter region 160, first 230 and the second conductive collector district 260 is as the first conductivity type base region 190 '.
Then, remove the portions of insulating material layer 240 not being patterned mask layer 250 and covering, remaining insulation material layer 240 is as collector electrode insulating barrier 270, and this collector electrode insulating barrier 270 is located in the first conductive collector district 230.
It should be noted, although abovementioned steps is for first to form the second conductive collector district 260, then form collector electrode insulating barrier 270.But above-mentioned steps also can be exchanged front and back, also first can remove and not be patterned portions of insulating material layer 240 that mask layer 250 covers to form collector electrode insulating barrier 270, then carry out ion implantation step to form the second conductive collector district 260 among substrate 110.
As long as the thickness of this collector electrode insulating barrier 270 can allow between subsequent set electrodes 280 and the first conductive collector district 230 and be electrically insulated, such as thickness is greater than 10nm.In addition, the width W 5 of collector electrode insulating barrier 270 can be the about 0.2-0.8 of substrate 110 width W 1 doubly, such as, be about 0.3-0.6 times.In one embodiment, the width W 5 of collector electrode insulating barrier 270 can be identical with the width W 4 in the first conductive collector district 230.In another embodiment, the width W 5 of collector electrode insulating barrier 270 can be greater than the width W 4 in the first conductive collector district 230.It should be noted, the width W 5 of this collector electrode insulating barrier 270 should be not less than the width W 4 in the first conductive collector district 230, otherwise the collector electrode 280 of the first conductive collector district 230 and follow-up formation cannot be electrically insulated by it.
Then, see Fig. 7, remove patterned mask layer 250, then form collector electrode 280 to complete the making of Insulated Gate Bipolar transistor 100.This collector electrode 280 is electrically connected the second conductive collector district 260, and is electrically insulated by collector electrode insulating barrier 270 and the first conductive collector district 230.Collector electrode 280 can be the good metal material (such as aluminium copper (AlCu), Al-Si-Cu alloy (AlSiCu)) of the gold of single or multiple lift, chromium, nickel, platinum, titanium, aluminium, iridium, rhodium, copper, above-mentioned combination or other conductivity.This collector electrode 280 is by being such as sputtering method, galvanoplastic, resistive heating evaporation, e-beam evaporation or other any applicable deposition process formation.
The Insulated Gate Bipolar transistor 100 of the embodiment of the present invention comprises substrate 110, has the first conductivity type, and has upper surface 110A and lower surface 110B.First conductive collector district 230 and the second adjacent conductive collector district 260, extend in substrate 110 from the lower surface 110B of substrate 110, this second conductivity type is different from the first conductivity type.Collector electrode 280, is electrically connected the second conductive collector district 260, and is electrically insulated by collector electrode insulating barrier 270 and the first conductive collector district 230.First emitter region 120, has the second conductivity type, extends in substrate 110 from the upper surface 110A of substrate 110.Second emitter region 150, has the first conductivity type, and extends in the first emitter region 120 from the upper surface 110A of substrate 110.Substrate 110 is not formed with the part system in the first conductive collector district, emitter region 150, first, emitter region 120, second 230 and the second conductive collector district 260 as the first conductivity type base region 190 '.Emitter electrode 170, is electrically connected with the first emitter region 120 and the second emitter region 150.Gate dielectric 130a, is located at the first emitter region, emitter region 120, second 150 with on substrate 110.Gate electrode 140, is located on gate dielectric 130a.Insulated Gate Bipolar transistor 100 can also comprise heavy doping resilient coating 200, has the first conductivity type and is located in the first conductivity type base region 190 '.
Fig. 8-17 shows the manufacturing step of the Insulated Gate Bipolar transistor 300 of another embodiment of the present invention.Be different from gate dielectric shown in Fig. 1-7 and gate electrode is formed on the second emitter region, the first emitter region and substrate, in the present embodiment, gate dielectric and gate electrode are formed in the groove (trench) of substrate.It should be noted, hereinafter as hereinbefore or similar element or rete will represent with same or analogous label, its material, manufacture method and function are all with aforementioned described same or similar, so part will repeat no more below.
See Fig. 8, first provide a substrate 310.The material of this substrate 310 can be identical with the material of aforesaid base plate 110.In one embodiment, this substrate 310 can have the first conductivity type.In one embodiment, this substrate 310 has the first conductivity type.Such as, when the first conductivity type is N-type, this substrate 310 can be lightly doped n-type substrate.In addition, substrate 310 has upper surface 310A and lower surface 310B.
Then, in substrate 310, the first emitter region 320 is formed.This first emitter region 320 has the second conductivity type, and this second conductivity type is different from the first conductivity type.This first emitter region 320 extends in substrate 310 from the upper surface 310A of substrate 310, as shown in Figure 8.In embodiments of the present invention, the first emitter region 320 only extends into the partial depth of substrate 310, that is the thickness T5 of this first emitter region 320 is less than the thickness T4 of substrate 310.This first emitter region 320 is formed by ion implantation step.Such as, when this second conductivity type is P type, boron ion, indium ion or boron difluoride ion (BF can be injected in the region of this first emitter region 320 of predetermined formation
2 +).
See Fig. 9, form groove (trench) 330.This groove 330 passes through in the first emitter region 320 to substrate 310 from the upper surface 310A extension of substrate 310.
See Figure 10, compliance forms gate dielectric 340 on the sidewall and bottom of groove 330, and forms gate electrode 350 on gate dielectric 340 and insert groove 330.In one embodiment, first compliance can deposit a dielectric materials layer on the sidewall and bottom of groove 330 and on the upper surface 310A of substrate 310, then the blanket property covered deposits a conductive material layer on the upper surface 310A of substrate 310 and inserts groove 330.Then, dielectric materials layer outside groove 330 and conductive material layer is removed to form gate dielectric 340 and gate electrode 350 respectively.Such as, dielectric materials layer outside groove 330 and conductive material layer is removed by returning etch step or chemical-mechanical polishing step.
Above-mentioned dielectric materials layer (in order to form gate dielectric 340) can be silica, silicon nitride, silicon oxynitride, high-k (high-k) dielectric material or other any applicable dielectric material or above-mentioned combination.This dielectric materials layer is formed by chemical vapour deposition technique (CVD) or method of spin coating.
The material (that is material of gate electrode 350) of aforesaid conductive material layer can be amorphous silicon, polysilicon or above-mentioned combination.And formed by chemical vapour deposition technique (CVD), sputtering method, resistive heating evaporation, e-beam evaporation or other any applicable depositional mode.
As shown in Figure 10, gate dielectric 340 directly contacts the first emitter region 320 and substrate 310, and gate electrode 350 inserts groove 330 on gate dielectric 340.This gate dielectric 340 makes gate electrode 350 and the first emitter region 320, the second emitter region of substrate 310 and follow-up formation is electrically insulated.
Then, as shown in figure 11, in the first emitter region 320, the second emitter region 360 is formed.This second emitter region 360 has the first conductivity type, and such as, in one embodiment, this second emitter region 360 is heavy doping first conductivity type.In addition, this second emitter region 360 extends in the first emitter region 320 from the upper surface 310A of substrate 310.In embodiments of the present invention, the second emitter region 360 only extends into the partial depth of the first emitter region 320, that is the thickness T6 of this second emitter region 360 is less than the thickness T5 of the first emitter region 320.In one embodiment, this second emitter region 360 is formed by ion implantation step.Such as, when this first conductivity type is N-type, phosphonium ion or arsenic ion can be injected in the region of this second emitter region 360 of predetermined formation.
Then, form inter-electrode dielectric layer 370 on gate electrode 350, this inter-electrode dielectric layer 370 is in order to be electrically insulated by the emitter electrode of gate electrode 350 with follow-up formation.Inter-electrode dielectric layer 370 can be silica, silicon nitride, silicon oxynitride, boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), spin-on glasses (SOG), highdensity plasma (highdensityplasma, HDP) deposition or other any applicable dielectric material or above-mentioned combination.Gate dielectric 340 is formed by aforesaid chemical vapour deposition technique (CVD) or method of spin coating.
Then, see Figure 12, a contact etch step eating thrown inter-electrode dielectric layer 370 and the second emitter region 360 is carried out to form contact opening 380.This etch step can comprise reactive ion etching (reactiveionetch, RIE), plasma etching or other suitable etch step.Then, alternative (optionally) carries out an ion implantation step to form one the 3rd emitter region 390 in the first emitter region 320.3rd emitter region 390 can be heavy doping second conductivity type.In addition, the step forming the 3rd emitter region 390 in the embodiment of the present invention does not use extra mask, therefore can reduce production cost.
Then, see Figure 13, emitter electrode 400 is formed.This emitter electrode 400 is electrically connected with the second emitter region 360 and the 3rd emitter region 390, and this emitter electrode 400 is coupled to the first emitter region 320 by the 3rd emitter region 390 again.And inter-electrode dielectric layer 370 is located between gate electrode 350 and emitter electrode 400.Inter-electrode dielectric layer 370 makes gate electrode 350 and emitter electrode 400 be electrically insulated.Emitter electrode 400 can be the good metal material (such as aluminium copper (AlCu), Al-Si-Cu alloy (AlSiCu)) of the gold of single or multiple lift, chromium, nickel, platinum, titanium, aluminium, iridium, rhodium, copper, above-mentioned combination or other conductivity.This emitter electrode 400 is by being such as sputtering method, galvanoplastic, resistive heating evaporation, e-beam evaporation or other any applicable deposition process formation.
Then, after emitter electrode 400, alternative (optionally) thin substrate 310 (graphic do not illustrate the substrate after thinning).The thickness of the substrate 310 after this thinning can be different according to operating voltage and component structure.
As shown in figure 13, the bottom of substrate 310 is collector electrode fate 410, and the region in substrate 310 except the first emitter region 360, emitter region 320, second, the 3rd emitter region 390 and collector electrode fate 410 is as base stage fate 420.And after thin substrate 310, alternative (optionally) forms heavy doping resilient coating 430 in base stage fate 420 (that is being formed in the first follow-up conductivity type base region).This heavy doping resilient coating 430 has the first conductivity type, and can in order to reduce the size of the final Insulated Gate Bipolar transistor formed further.This heavy doping resilient coating 430 is formed by ion implantation step.Such as, when this first conductivity type is N-type, phosphonium ion or arsenic ion can be injected in the region of this heavy doping resilient coating 430 of predetermined formation.
Then, see Figure 14, patterned mask layer 440 is formed on the lower surface 310B of substrate 310.This patterned mask layer 440 can be patterning photoresistance or is such as the patterned hard mask layer of silicon dioxide, silicon nitride or silicon oxynitride.This patterned mask layer 440 has the substrate 310 that opening 450 exposes predetermined formation first conductive collector district.
Then, carry out an ion implantation step to form the first conductive collector district 460 among substrate 310 via opening 450, this first conductive collector district 460 extends in substrate 310 from the lower surface 310B of substrate 310.This first conductive collector district 460 can reduce the carrier quantity corresponding with the second conductivity type in substrate 310.Such as, when the second conductivity type is P type, the quantity in hole in substrate 310 can be reduced.
In one embodiment, when this first conductivity type is N-type, phosphonium ion or arsenic ion can be injected to form the first conductive collector district 460 in the substrate 310 in predetermined formation first conductive collector district.The width W 6 in this first conductive collector district 460 can be the about 0.2-0.8 of substrate 310 width W 7 doubly, such as, be about 0.3-0.6 times.It should be noted, if the width W 6 in this first conductive collector district 460 is wide, such as, wider than 0.8 times of substrate 310 width W 7, then corresponding with the second conductivity type in substrate 310 carrier quantity can be too low, and conducting voltage is increased.Such as, but if the width W 6 in this first conductive collector district 460 is narrow, be narrower than 0.2 times of substrate 310 width W 7, then it effectively cannot reduce carrier quantity corresponding with the second conductivity type in substrate 310, the closedown loss causing it effectively cannot reduce device.
See Figure 15, after removing patterned mask layer 440, the blanket property covered forms insulation material layer 470 on the lower surface 310B of substrate 310.This insulation material layer 470 can be silica, silicon nitride, silicon oxynitride, boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), spin-on glasses (SOG) or other any applicable dielectric material or above-mentioned combination.Insulation material layer 470 is formed by aforesaid chemical vapour deposition technique (CVD) or method of spin coating and aforesaid patterning step.In one embodiment, tetraethoxysilane (TEOS can be used, tetraethyl-ortho-silicate) be reacting gas, coordinate patterning step to form insulation material layer 470 with the mode sedimentation of plasma enhancing (plasmaenhanced).In another embodiment, insulation material layer 470 is formed on the lower surface 310B of substrate 310 by the direct blanket property covered of thermal oxidation method.
Then, patterned mask layer 480 is formed on the lower surface 310B of substrate 310 to cover the first conductive collector district 460 and to expose the substrate 310 in predetermined formation second conductive collector district.This patterned mask layer 480 can be patterning photoresistance or is such as the patterned hard mask layer of silicon dioxide, silicon nitride or silicon oxynitride.
Then, as shown in figure 16, another ion implantation step is carried out using patterned mask layer 480 as mask to form the second conductive collector district 490 among substrate 310.This second conductive collector district 490 also extends in substrate 310 from the lower surface 310B of substrate 310.This second conductive collector district 490 is adjacent to the first conductive collector district 460.In one embodiment, when this second conductivity type is P type, boron ion, indium ion or boron difluoride ion (BF can be injected in the region in this second conductive collector district 490 of predetermined formation
2 +).And substrate 310 is not formed with the first emitter region 360, emitter region 320, second, the part in the 3rd conductive collector district, emitter region 390, first 460 and the second conductive collector district 490 is as the first conductivity type base region 420 '.
Then, remove the portions of insulating material layer 470 not being patterned mask layer 480 and covering, remaining insulation material layer 470 is as collector electrode insulating barrier 500, and this collector electrode insulating barrier 500 is located in the first conductive collector district 460.
It should be noted, although abovementioned steps is for first to form the second conductive collector district 490, then form collector electrode insulating barrier 500.But above-mentioned steps also can be exchanged front and back, also first can remove and not be patterned portions of insulating material layer 470 that mask layer 480 covers to form collector electrode insulating barrier 500, then carry out ion implantation step to form the second conductive collector district 490 among substrate 310.
As long as the thickness of this collector electrode insulating barrier 500 can allow between collector electrode 510 and the first conductive collector district 420 ' and be electrically insulated, such as thickness is greater than 10nm.In addition, the width W 8 of collector electrode insulating barrier 500 can be the about 0.2-0.8 of substrate 310 width W 7 doubly, such as, be about 0.3-0.6 times.In one embodiment, the width W 8 of collector electrode insulating barrier 500 can be identical with the width W 6 in the first conductive collector district 460.In another embodiment, the width W 8 of collector electrode insulating barrier 500 can be greater than the width W 6 in the first conductive collector district 460.In this embodiment, the width W 8 of this collector electrode insulating barrier 500 should be not less than the width W 6 in the first conductive collector district 460, otherwise the collector electrode of the first conductive collector district 460 and follow-up formation cannot be electrically insulated by it.
Then, see Figure 17, remove patterned mask layer 480, then form collector electrode 510 to complete the making of Insulated Gate Bipolar transistor 300.This collector electrode 510 is electrically connected the second conductive collector district 490, and is electrically insulated by collector electrode insulating barrier 500 and the first conductive collector district 460.Collector electrode 510 can be the good metal material (such as aluminium copper (AlCu), Al-Si-Cu alloy (AlSiCu)) of the gold of single or multiple lift, chromium, nickel, platinum, titanium, aluminium, iridium, rhodium, copper, above-mentioned combination or other conductivity.This collector electrode 510 is by being such as sputtering method, galvanoplastic, resistive heating evaporation, e-beam evaporation or other any applicable deposition process formation.
The Insulated Gate Bipolar transistor 300 of the embodiment of the present invention comprises substrate 310, has the first conductivity type, and has upper surface 310A and lower surface 310B.First conductive collector district 460 and the second adjacent conductive collector district 490, extend in substrate 310 from the lower surface 310B of substrate 310, this second conductivity type is different from the first conductivity type.Collector electrode 510, is electrically connected the second conductive collector district 490, and is electrically insulated by collector electrode insulating barrier and the first conductive collector district 460.First emitter region 320, has the second conductivity type, and extends in substrate 310 from the upper surface 310A of substrate 310.Second emitter region 360, has the first conductivity type, and extends in the first emitter region 320 from the upper surface 310A of substrate 310.And the part that substrate 310 is not formed with the first conductive collector district, emitter region 360, first, emitter region 320, second 460 and the second conductive collector district 490 is as the first conductivity type base region 420 '.Emitter electrode 400, is electrically connected with the first emitter region 320 and the second emitter region 360.Groove 330, extends from the upper surface 310A of substrate 310 and passes through the first emitter region 320 and the second emitter region 360 and enter in substrate 310.Gate dielectric 340, is inside lining in sidewall and the bottom of groove 330.Gate electrode 350, to be located on gate dielectric 340 and to insert groove 330.Inter-electrode dielectric layer 370, is located between gate electrode 350 and emitter electrode 400.Insulated Gate Bipolar transistor 300 can also comprise heavy doping resilient coating 430, has the first conductivity type and is located in the first conductivity type base region 420 '.
It should be noted, although in above embodiment, all with the first conductivity type for N-type, the second conductivity type is that P type illustrates, but in any art, technical staff's this first conductivity type known also can be P type, and the second conductivity type can be N-type.
Table 1
Table 1 shows the Performance comparision of the Insulated Gate Bipolar transistor of the embodiment of the present invention and comparative example, and Figure 18 is the switch performance analysis chart of the Insulated Gate Bipolar transistor of one embodiment of the invention and comparative example.This analysis simulates gained by computer software (TechnologyComputerAidedDesign, TCAD).With the difference of the Insulated Gate Bipolar transistor of the embodiment of the present invention, the Insulated Gate Bipolar transistor (IGBT of comparative example 1) of comparative example 1 is that it does not have the first conductive collector district and collector electrode insulating barrier, and with the difference of the Insulated Gate Bipolar transistor of the embodiment of the present invention, reverse-conducting insulated gate pole bipolar transistor (reverseconductingIGBT, RC-IGBT) of comparative example 2 is that it does not have collector electrode insulating barrier.Figure 18 display is by the Insulated Gate Bipolar transistor (IGBT of one embodiment of the invention) of one embodiment of the invention, the Insulated Gate Bipolar transistor (IGBT of comparative example 1) of comparative example 1 and the reverse-conducting insulated gate pole bipolar transistor (reverseconductingIGBT of comparative example 2, RC-IGBT) identical voltage is bestowed, and when closing voltage simultaneously, the shut-in time of the electric current of the Insulated Gate Bipolar transistor of the embodiment of the present invention is 180ns, and the shut-in time of the reverse-conducting insulated gate pole bipolar transistor (RC-IGBT of comparative example 2) of comparative example 2 is 370ns, the shut-in time of the Insulated Gate Bipolar transistor (IGBT of comparative example 1) of comparative example 1 is 435ns.It can thus be appreciated that the collector structure of the Insulated Gate Bipolar transistor of one embodiment of the invention significantly can reduce the shut-in time of device.
Figure 19 be the embodiment of the present invention and comparative example Insulated Gate Bipolar transistor in off position under puncture voltage analysis chart.This analysis simulates gained by computer software (TechnologyComputerAidedDesign, TCAD).The puncture voltage that Figure 19 shows the electric current of the Insulated Gate Bipolar transistor of the embodiment of the present invention is 1375V, and the puncture voltage of the reverse-conducting insulated gate pole bipolar transistor (RC-IGBT of comparative example 2) of comparative example 2 is 1375V, the puncture voltage of the Insulated Gate Bipolar transistor (IGBT of comparative example 1) of comparative example 1 is 1250V.It can thus be appreciated that the Insulated Gate Bipolar transistor of one embodiment of the invention can not affect its puncture voltage while the shut-in time of reducing device.
Moreover, as shown in Table 1, the conducting voltage of the electric current of the Insulated Gate Bipolar transistor of the embodiment of the present invention is 2.5V, and the conducting voltage of the reverse-conducting insulated gate pole bipolar transistor (RC-IGBT of comparative example 2) of comparative example 2 is 2.5V, the conducting voltage of the Insulated Gate Bipolar transistor (IGBT of comparative example 1) of comparative example 1 is 2.65V.In addition, the latch-up current density (latchupcurrentdensity) of the electric current of the Insulated Gate Bipolar transistor of the embodiment of the present invention is 1600A/cm
2, and the latch-up current density of the reverse-conducting insulated gate pole bipolar transistor (RC-IGBT of comparative example 2) of comparative example 2 is 1600A/cm
2, the latch-up current density of the Insulated Gate Bipolar transistor (IGBT of comparative example 1) of comparative example 1 is 1500A/cm
2.It can thus be appreciated that the Insulated Gate Bipolar transistor of one embodiment of the invention can not affect its conducting voltage (onvoltage) and latch-up current density (latchupcurrentdensity) while the shut-in time of reducing device.
In sum, the Insulated Gate Bipolar transistor of the embodiment of the present invention can reduce closes loss (turn-offloss), and does not affect conducting voltage (onvoltage), puncture voltage and latch-up current density (latchupcurrentdensity) simultaneously.In addition, owing to closing the reduction of loss, after device is closed, the carrier of flowing can reduce fast, therefore further can shorten the switching time (switchingtime) of device, the significantly performance of enhanced device.
Although embodiments of the invention and advantage thereof have disclosed as above, will be appreciated that technical staff in any art, without departing from the spirit and scope of the present invention, when changing, substitute and retouching.In addition; protection scope of the present invention is not confined to manufacturing process in specification in described specific embodiment, machine, manufacture, material composition, device, method and step; in any art, technical staff can understand existing or following developed manufacturing process, machine, manufacture, material composition, device, method and step from disclosure of the present invention, all can be used according to the invention as long as can implement more or less the same function or obtain more or less the same result in described embodiment herein.Therefore, protection scope of the present invention comprises above-mentioned manufacturing process, machine, manufacture, material composition, device, method and step.In addition, each claim forms other embodiment, and protection scope of the present invention also comprises the combination of each claim and embodiment.
Claims (14)
1. an Insulated Gate Bipolar transistor, is characterized in that, this Insulated Gate Bipolar transistor comprises:
One substrate, has one first conductivity type, and has a upper surface and a lower surface;
One first conductive collector district and one second adjacent conductive collector district, extend in this substrate from the lower surface of this substrate, wherein this second conductivity type is different from this first conductivity type;
One collector electrode, is electrically connected this second conductive collector district, and is electrically insulated by a collector electrode insulating barrier and this first conductive collector district;
One first emitter region, has this second conductivity type, extends in this substrate from the upper surface of this substrate;
One second emitter region, there is this first conductivity type, and extend in this first emitter region from the upper surface of this substrate, wherein this substrate be not formed this first emitter region, this second emitter region, this first conductive collector district and this second conductive collector district part be as one first conductivity type base region;
One emitter electrode, is electrically connected with this first emitter region and this second emitter region;
One gate dielectric, is located on this first emitter region, this second emitter region and this substrate; And
One gate electrode, is located on this gate dielectric.
2. Insulated Gate Bipolar transistor as claimed in claim 1, it is characterized in that, the material of this collector electrode insulating barrier comprises silica, silicon nitride or silicon oxynitride.
3. Insulated Gate Bipolar transistor as claimed in claim 1, it is characterized in that, the thickness of this collector electrode insulating barrier is greater than 10nm.
4. Insulated Gate Bipolar transistor as claimed in claim 1, is characterized in that, the width of this collector electrode insulating barrier is 0.2-0.8 times of this substrate width.
5. Insulated Gate Bipolar transistor as claimed in claim 1, is characterized in that, also comprise a heavy doping resilient coating have this first conductivity type and be located in this first conductivity type base region.
6. an Insulated Gate Bipolar transistor, is characterized in that, this Insulated Gate Bipolar transistor comprises:
One substrate, has one first conductivity type, and has a upper surface and a lower surface;
One first conductive collector district and one second adjacent conductive collector district, extend in this substrate from the lower surface of this substrate, wherein this second conductivity type is different from this first conductivity type;
One collector electrode, is electrically connected this second conductive collector district, and is electrically insulated by a collector electrode insulating barrier and this first conductive collector district;
One first emitter region, has this second conductivity type, and extends in this substrate from the upper surface of this substrate;
One second emitter region, there is this first conductivity type, and extend in this first emitter region from the upper surface of this substrate, wherein this substrate be not formed this first emitter region, this second emitter region, this first conductive collector district and this second conductive collector district part be as one first conductivity type base region;
One emitter electrode, is electrically connected with this first emitter region and this second emitter region;
One groove, extends from the upper surface of this substrate and passes through this first emitter region and this second emitter region and enter in this substrate;
One gate dielectric, is inside lining in sidewall and the bottom of this groove;
One gate electrode, to be located on this gate dielectric and to insert this groove; And
One inter-electrode dielectric layer, is located between this gate electrode and this emitter electrode.
7. Insulated Gate Bipolar transistor as claimed in claim 6, is characterized in that, also comprise a heavy doping resilient coating have this first conductivity type and be located in this first conductivity type base region.
8. a manufacture method for Insulated Gate Bipolar transistor, is characterized in that, the manufacture method of this Insulated Gate Bipolar transistor comprises:
One substrate is provided, there is one first conductivity type, and there is a upper surface and a lower surface;
Form one first emitter region, there is one second conductivity type, extend in this substrate from the upper surface of this substrate, and this second conductivity type is different from this first conductivity type;
Form a gate dielectric on this first emitter region and this substrate;
Form a gate electrode on this gate dielectric;
Form one second emitter region, this second emitter region has this first conductivity type, and extends in this first emitter region from the upper surface of this substrate;
Form an emitter electrode, this emitter electrode is electrically connected with this first emitter region and this second emitter region;
Form one first conductive collector district, extend in this substrate from the lower surface of this substrate;
Form a collector electrode insulating barrier in this first conductive collector district;
Form one second conductive collector district adjacent to this first conductive collector district, wherein this substrate be not formed this first emitter region, this second emitter region, this first conductive collector district and this second conductive collector district part be as one first conductivity type base region; And
Form a collector electrode, this collector electrode is electrically connected this second conductive collector district, and is electrically insulated by this collector electrode insulating barrier and this first conductive collector district.
9. the manufacture method of Insulated Gate Bipolar transistor as claimed in claim 8, it is characterized in that, the material of this collector electrode insulating barrier comprises silica, silicon nitride or silicon oxynitride.
10. the manufacture method of Insulated Gate Bipolar transistor as claimed in claim 8, it is characterized in that, the thickness of this collector electrode insulating barrier is greater than 10nm.
The manufacture method of 11. Insulated Gate Bipolar transistors as claimed in claim 8, is characterized in that, the width of this collector electrode insulating barrier is 0.2-0.8 times of this substrate width.
The manufacture method of 12. Insulated Gate Bipolar transistors as claimed in claim 8, is characterized in that, also comprise formation one heavy doping resilient coating in this first conductivity type base region, wherein this heavy doping resilient coating has the first conductivity type.
The manufacture method of 13. 1 kinds of Insulated Gate Bipolar transistors, is characterized in that, the manufacture method of this Insulated Gate Bipolar transistor comprises:
One substrate is provided, there is one first conductivity type, and there is a upper surface and a lower surface;
Form one first emitter region, there is one second conductivity type, and extend in this substrate from the upper surface of this substrate, and this second conductivity type is different from this first conductivity type;
Form a groove, extend from the upper surface of this substrate and pass through this first emitter region in this substrate;
Compliance forms a gate dielectric on the sidewall and bottom of this groove;
Forming a gate electrode on this gate dielectric inserts this groove;
Form one second emitter region, this second emitter region has this first conductivity type, and extends in this first emitter region from the upper surface of this substrate;
Form an inter-electrode dielectric layer on this gate electrode;
Form an emitter electrode, this emitter electrode is electrically connected with this first emitter region and this second emitter region, and this inter-electrode dielectric layer is located between this gate electrode and this emitter electrode;
Form one first conductive collector district, extend in this substrate from the lower surface of this substrate;
Form a collector electrode insulating barrier in this first conductive collector district;
Form one second conductive collector district adjacent to this first conductive collector district, wherein this substrate be not formed this first emitter region, this second emitter region, this first conductive collector district and this second conductive collector district part be as one first conductivity type base region; And
Form a collector electrode, this collector electrode is electrically connected this second conductive collector district, and is electrically insulated by this collector electrode insulating barrier and this first conductive collector district.
The manufacture method of 14. Insulated Gate Bipolar transistors as claimed in claim 13, is characterized in that, be also included in formation one heavy doping resilient coating in this first conductivity type base region, wherein this heavy doping resilient coating has this first conductivity type.
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| TW103119994 | 2014-06-10 | ||
| TW103119994A TWI544627B (en) | 2014-06-10 | 2014-06-10 | Insulated gate bipolar transistor and method of manufacturing the same |
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| CN105280692A true CN105280692A (en) | 2016-01-27 |
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Cited By (2)
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| CN108010964A (en) * | 2017-11-29 | 2018-05-08 | 吉林华微电子股份有限公司 | A kind of IGBT device and manufacture method |
| CN111627924A (en) * | 2016-06-14 | 2020-09-04 | 群创光电股份有限公司 | Display device and method for manufacturing display device |
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| JP2005333055A (en) * | 2004-05-21 | 2005-12-02 | Toyota Central Res & Dev Lab Inc | Semiconductor apparatus |
| CN102412288A (en) * | 2010-09-21 | 2012-04-11 | 株式会社东芝 | Reverse conducting-insulated gate bipolar transistor |
| CN103311242A (en) * | 2012-03-15 | 2013-09-18 | 株式会社东芝 | Semiconductor device |
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- 2014-06-10 TW TW103119994A patent/TWI544627B/en active
- 2014-08-06 CN CN201410383362.3A patent/CN105280692A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005333055A (en) * | 2004-05-21 | 2005-12-02 | Toyota Central Res & Dev Lab Inc | Semiconductor apparatus |
| CN102412288A (en) * | 2010-09-21 | 2012-04-11 | 株式会社东芝 | Reverse conducting-insulated gate bipolar transistor |
| CN103311242A (en) * | 2012-03-15 | 2013-09-18 | 株式会社东芝 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111627924A (en) * | 2016-06-14 | 2020-09-04 | 群创光电股份有限公司 | Display device and method for manufacturing display device |
| CN111627924B (en) * | 2016-06-14 | 2023-05-16 | 群创光电股份有限公司 | Display device and method for manufacturing display device |
| CN108010964A (en) * | 2017-11-29 | 2018-05-08 | 吉林华微电子股份有限公司 | A kind of IGBT device and manufacture method |
| CN108010964B (en) * | 2017-11-29 | 2020-09-08 | 吉林华微电子股份有限公司 | IGBT device and manufacturing method thereof |
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| TWI544627B (en) | 2016-08-01 |
| TW201547020A (en) | 2015-12-16 |
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