TWI544627B - Insulated gate bipolar transistor and method of manufacturing the same - Google Patents

Description

Insulated gate bipolar transistor and manufacturing method thereof

Embodiments of the present invention relate to semiconductor technology, and in particular to insulated gate bipolar transistors and methods of fabricating the same.

Power components are widely used in home appliances and automotive applications for driving and controlling high power. This power component includes a power transistor that performs a large output of the switching operation. The power transistor includes an insulated gate bipolar transistor (IGBT) in addition to a power MOS field-effect transistor (MOSFET) and a power bipolar transistor. The insulated gate bipolar transistor has both the high input impedance of the gold oxide half field effect transistor and the low on resistance of the bipolar transistor.

An embodiment of the present invention provides an insulated gate bipolar transistor, comprising: a substrate having a first conductivity type and having an upper surface and a lower surface; a first conductive type collector region and an adjacent second conductive type collector region And extending from the lower surface of the substrate into the substrate, wherein the second conductive type is different from the first conductive type; the collector electrode is electrically connected to the second conductive type collector region, and is formed by the collector insulating layer and the first conductive type The collector region is electrically insulated; the first emitter region has a second conductivity type extending from the upper surface of the substrate into the substrate; and the second emitter region has a first conductivity type and extends from the upper surface of the substrate In an emitter region, wherein the substrate is not formed with a first emitter region, a portion of the second emitter region, the first conductive type collector region and the second conductive type collector region is used as the first conductive type base region; the emitter electrode is electrically connected to the first emitter region and the second emitter region The gate electrode layer is disposed on the first emitter region, the second emitter region and the substrate; and the gate electrode is disposed on the gate dielectric layer.

The embodiment of the invention further provides an insulated gate bipolar transistor, The method includes: a substrate having a first conductivity type and having an upper surface and a lower surface; the first conductive type collector region and the adjacent second conductive type collector region extending from the lower surface of the substrate into the substrate, wherein the second The conductive type is different from the first conductive type; the collector electrode is electrically connected to the second conductive type collector region, and is electrically insulated from the first conductive type collector region by the collector insulating layer; the first emitter region has a second conductivity type extending from the upper surface of the substrate into the substrate; the second emitter region having the first conductivity type and extending from the upper surface of the substrate into the first emitter region, wherein the substrate is not formed with the first The emitter region, the second emitter region, the first conductive type collector region and the second conductive type collector region are used as the first conductive type base region; the emitter electrode, and the first emitter region and the second portion The emitter region is electrically connected; a trench extends from the upper surface of the substrate through the first emitter region and the second emitter region and enters the substrate; the gate dielectric layer is lined with the sidewall of the trench and a bottom electrode; a gate electrode disposed on the gate dielectric layer and filled with a trench; and an inter-electrode dielectric layer disposed on Between the electrode and the emitter electrode.

The embodiment of the invention further provides an insulated gate bipolar transistor The manufacturing method includes: providing a substrate having a first conductivity type and having an upper surface and a lower surface; forming a first emitter region having a second conductivity type extending from the upper surface of the substrate into the substrate, and the second conductive The type is different from the first conductivity type; forming a gate dielectric layer on the first emitter region and the substrate; forming a gate electrode on the gate dielectric layer; forming a second emitter region, the second emitter region having the first One conductivity type and from the substrate The upper surface extends into the first emitter region; the emitter electrode is formed, and the emitter electrode is electrically connected to the first emitter region and the second emitter region; forming a first conductive type collector region from the lower surface of the substrate Extending into the substrate; forming a collector insulating layer on the first conductive type collector region; forming a second conductive type collector region adjacent to the first conductive type collector region, wherein the substrate is not formed with the first emitter region, a portion of the second emitter region, the first conductive type collector region and the second conductive type collector region is used as a first conductive type base region; and a collector electrode is formed, and the collector electrode is electrically connected to the second conductive type set The polar region is electrically insulated from the first conductive type collector region by the collector insulating layer.

An embodiment of the invention further provides an insulated gate bipolar transistor The manufacturing method includes: providing a substrate having a first conductivity type and having an upper surface and a lower surface; forming a first emitter region having a second conductivity type, extending from the upper surface of the substrate into the substrate, and second The conductive type is different from the first conductive type; forming a trench extending from the upper surface of the substrate through the first emitter region to the substrate; compliant forming a gate dielectric layer on the sidewall and the bottom of the trench; forming a gate electrode is formed on the gate dielectric layer and filled with a trench; a second emitter region is formed, the second emitter region has a first conductivity type, and extends from the upper surface of the substrate into the first emitter region; The inter-electrode dielectric layer is on the gate electrode; the emitter electrode is formed, the emitter electrode is electrically connected to the first emitter region and the second emitter region, and the inter-electrode dielectric layer is disposed on the gate electrode and the emitter electrode Forming a first conductive type collector region extending from the lower surface of the substrate into the substrate; forming a collector insulating layer on the first conductive type collector region; forming a second conductive type collector region adjacent to the first a conductive collector region in which the substrate is not formed with a first emitter region and a second shot a portion of the first conductive type collector region and the second conductive type collector region is used as a first conductive type base region; and a collector electrode is formed, and the collector electrode is electrically connected to the second conductive type collector region, and By collector insulating layer and first The conductive collector region is electrically insulated.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments of the present invention are described in detail below.

100‧‧‧Insulated gate bipolar transistor

110‧‧‧Substrate

110A‧‧‧Upper surface

110B‧‧‧ lower surface

120‧‧‧first emitter area

130a‧‧‧gate dielectric layer

130b‧‧‧Interelectrode dielectric layer

140‧‧‧gate electrode

150‧‧‧second emitter area

160‧‧‧third emitter area

170‧‧ ‧ emitter electrode

180‧‧‧Positive reservation area

190‧‧‧base reservation area

190'‧‧‧First Conductive Base Region

200‧‧‧ heavily doped buffer layer

210‧‧‧ patterned mask layer

220‧‧‧ openings

230‧‧‧First Conductive Collector Region

240‧‧‧Insulation layer

250‧‧‧ patterned mask layer

260‧‧‧Second Conductive Collector Region

270‧‧‧ collector insulation

280‧‧ ‧ collector electrode

300‧‧‧Insulated gate bipolar transistor

310‧‧‧Substrate

310A‧‧‧ upper surface

310B‧‧‧ lower surface

320‧‧‧First Polar Region

330‧‧‧ trench

340‧‧‧gate dielectric layer

350‧‧‧gate electrode

360‧‧‧second emitter area

370‧‧‧Interelectrode dielectric layer

380‧‧‧ openings

390‧‧‧The third emitter area

400‧‧ ‧ emitter electrode

410‧‧‧Positive reservation area

420‧‧‧base reservation area

420'‧‧‧First Conductive Base Region

430‧‧‧ heavily doped buffer layer

440‧‧‧ patterned mask layer

450‧‧‧ openings

460‧‧‧First Conductive Collector Region

470‧‧‧Insulation layer

480‧‧‧ patterned mask layer

490‧‧‧Second Conductive Collector Region

500‧‧‧ collector insulation

510‧‧‧ Collector electrode

T1-T6‧‧‧ thickness

W1-W8‧‧‧Width

1-7 are cross-sectional views showing stages of an insulating gate bipolar transistor of an embodiment of the present invention in a method of manufacturing the same; and FIGS. 8-17 are diagrams showing an insulating gate bipolar transistor according to another embodiment of the present invention. A cross-sectional view of each stage of the manufacturing method; Fig. 18 is a graph showing the switching performance of the insulated gate bipolar transistor; and Fig. 19 is a graph of the breakdown voltage of the insulated gate bipolar transistor.

The insulated gate bipolar transistor of the embodiment of the present invention will be described in detail below. It will be appreciated that the following description provides many different embodiments or examples for implementing the invention. The specific elements and arrangements described below are intended to provide a brief description of the invention. Of course, these are by way of example only and not as a limitation of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the invention and are not to be construed as a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is on or above a second material layer, the first material layer is in direct contact with the second material layer. Alternatively, it is also possible to have one or more layers of other materials interposed, in which case there may be no direct contact between the first layer of material and the second layer of material.

It must be understood that components that are specifically described or illustrated may be Various forms are known to the skilled person. In addition, when a layer is "on" another layer or substrate, it may mean "directly" on another layer or substrate, or a layer on another layer or substrate, or between other layers or substrates. Other layers.

In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element to another. It will be understood that if the illustrated device is flipped upside down, the component described on the "lower" side will be the component on the "higher" side.

Here, the terms "about" and "about" are usually expressed within 20% or other values of a given value or range, preferably within 10%, and more preferably within 5%. The quantity given here is an approximate quantity, meaning that the meaning of "about" or "about" may be implied without specific explanation.

Embodiments of the present invention utilize a first conductive type collector region and a collector insulating layer formed thereon to reduce turn-off loss of the insulated gate bipolar transistor while maintaining its turn-on voltage ( On voltage).

Referring to Figure 1, a substrate 110 is first provided. The substrate 110 may include: a crystalline structure, a polycrystalline structure or an amorphous structure of germanium or germanium elemental semiconductor; gallium nitride (GaN), silicon carbide, gallium arsenic, gallium phosphide ( Alloy semiconductor such as gallium phosphide, indium phosphide, indium arsenide or indium antimonide; alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP or GaInAsP or other suitable Materials and / or combinations of the above. In an embodiment, the substrate 110 has a first conductivity type. For example, when the first conductivity type is an N-type, the substrate 110 may be a lightly doped N-type substrate. In addition, the substrate 110 has an upper surface 110A And lower surface 110B.

Next, a first emitter region 120 is formed in the substrate 110. The first emitter region 120 extends from the upper surface 110A of the substrate 110 into the substrate 110. As shown in FIG. 1, the width W2 of the first emitter region 120 is smaller than the width W1 of the substrate 110. In the embodiment of the present invention, the first emitter region 120 extends only a portion of the depth of the substrate 110, that is, the thickness T2 of the first emitter region 120 is smaller than the thickness T1 of the substrate 110. The first emitter region 120 has a second conductivity type, and the second conductivity type is different from the first conductivity type. For example, the first emitter region 120 can be formed by an ion implantation step. In one embodiment, when the second conductivity type is a P-type, boron ions, indium ions, or boron difluoride ions (BF ₂ ⁺ ) may be implanted in a region where the first emitter region 120 is predetermined to be formed.

Next, referring to FIG. 2, a gate dielectric layer 130a is formed on the first emitter region 120 and the substrate 110, and a gate electrode 140 is formed on the gate dielectric layer 130a. In an embodiment, a dielectric material layer (not shown) and a conductive material layer (not shown) on the upper surface 110A of the substrate 110 may be sequentially deposited on the substrate 110. The electrical material layer and the conductive material layer are respectively patterned by a lithography and etching process to form a gate dielectric layer 130a and a gate electrode 140.

The dielectric material layer (to form the gate dielectric layer 130a) may be tantalum oxide, tantalum nitride, hafnium oxynitride, high-k dielectric material, or any other suitable dielectric material. Or a combination of the above. The high-k dielectric material can be a metal oxide, a metal nitride, a metal halide, a transition metal oxide, a transition metal nitride, a transition metal halide, a metal oxynitride, or a metal aluminum. Acid salt, zirconium silicate, zirconium aluminate. For example, the high-k dielectric material may be LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO. ₂ , HfO ₃ , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr)TiO ₃ (BST), Al ₂ O ₃ , other high dielectric constants of other suitable materials Dielectric material, or a combination of the above. The dielectric material layer can be formed by chemical vapor deposition (CVD) or spin coating. The chemical vapor deposition method can be, for example, low pressure chemical vapor deposition (LPCVD), low temperature chemistry. Low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), atom Atomic layer deposition (ALD) or other commonly used methods of layer chemical vapor deposition.

The material of the foregoing conductive material layer (that is, the material of the gate electrode 140) It may be an amorphous germanium, a germanium germanium, one or more metals, a metal nitride, a conductive metal oxide, or a combination thereof. The above metals may include, but are not limited to, molybdenum, tungsten, titanium, tantalum, platinum or hafnium. The above metal nitrides may include, but are not limited to, molybdenum nitride, tungsten nitride, titanium nitride, and tantalum nitride. The above conductive metal oxide may include, but is not limited to, ruthenium oxide and indium tin oxide. The material of the conductive material layer can be formed by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method, for example, in an implementation. In the case, low pressure chemical vapor deposition (LPCVD) can be used between 525 and 650 °C. A layer of amorphous germanium conductive material or a layer of polycrystalline germanium conductive material is deposited to a thickness ranging from about 1000 Å to about 10000 Å.

In addition, the top of the gate electrode 140 may further include a metal telluride layer, which may include, but is not limited to, nickel silicide, cobalt silicide, tungsten tungsten, titanium telluride (titanium telluride). Titanium silicide, tantalum silicide, platinum silicide, and erbium silicide.

As shown in FIG. 2, the gate electrode 140 is provided on the gate dielectric layer 130a. In detail, the gate dielectric layer 130a and the gate electrode 140 are disposed on the first emitter region 120 and the substrate 110, and the gate dielectric layer 130a causes the gate electrode 140 and the first emitter region 120 and the substrate. 110 electrical insulation.

Next, referring to FIG. 2, a second emitter region 150 having a first conductivity type is formed in the first emitter region 120. For example, in an embodiment, the second emitter region 150 is heavily doped with a first conductivity type. Further, the second emitter region 150 extends from a portion of the upper surface 110A of the substrate 110 into the first emitter region 120. As shown in Figure 2. In the embodiment of the present invention, the second emitter region 150 extends only a portion of the depth of the first emitter region 120, that is, the thickness T3 of the second emitter region 150 is smaller than the thickness T2 of the first emitter region 120. This second emitter region 150 can be formed by an ion implantation step. For example, when the first conductivity type is an N-type, phosphorus ions or arsenic ions may be implanted in a region where the second emitter region 150 is predetermined to be formed.

Next, an ion implantation step can be performed selectively to form a third emitter region 160 in the second emitter region 150. The third emitter region 160 also extends from a portion of the upper surface 110A of the substrate 110 into the first emitter region 120 and may have a thickness equal to or not equal to T3. Generally, the thickness of the third emitter region 160 Deeper than T3. The third emitter region 160 is adjacent to the second emitter region 150. The third emitter region 160 can be heavily doped second conductivity type. The total width W3 of the second emitter region 150 and the third emitter region 160 is smaller than the width W2 of the first emitter region 120. Next, an inter-electrode dielectric layer 130b is formed on the upper surface 110A to cover the top and sidewalls of the gate electrode 140 and the second emitter region 150 (not shown).

Next, the inter-electrode dielectric layer 130b (not shown) covering a portion of the second emitter region 150 is etched. Referring to FIG. 3, the inter-electrode dielectric layer 130b is formed to cover the top and sidewalls of the gate electrode 140. The inter-electrode dielectric layer 130b is used to electrically insulate the gate electrode 140 from the subsequently formed emitter electrode. The interelectrode dielectric layer 130b may be yttrium oxide, tantalum nitride, hafnium oxynitride, borophosphoquinone glass (BPSG), phosphorous bismuth glass (PSG), spin-on glass (SOG), high density plasma (high density). Plasma, HDP) deposition or any other suitable dielectric material, or a combination of the above. The interelectrode dielectric layer 130b can be formed by the aforementioned chemical vapor deposition (CVD) or spin coating method and a patterning step.

Next, the emitter electrode 170 is formed. The emitter electrode 170 is electrically connected to the second emitter region 150 and the third emitter region 160. The emitter electrode 170 is coupled to the first emitter region 120 through the third emitter region 160. The emitter electrode 170 may be a single layer or a plurality of layers of gold, chromium, nickel, platinum, titanium, aluminum, tantalum, niobium, copper, a combination of the above or other conductive metal materials (for example, aluminum-copper alloy (AlCu), aluminum. Beryllium copper alloy (AlSiCu)). The emitter electrode 170 can be formed by, for example, sputtering, electroplating, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process.

Next, after the emitter electrode 170, the substrate 110 can be selectively thinned (the thinned substrate is not shown in the drawings). Thinned substrate The thickness of 110 will vary depending on the operating voltage and component structure.

As shown in FIG. 3, the bottom of the substrate 110 is a collector predetermined area 180. The region of the substrate 110 other than the first emitter region 120, the second emitter region 150, the third emitter region 160, and the collector predetermined region 180 serves as a base predetermined region 190. After thinning the substrate 110, the heavily doped buffer layer 200 may be selectively formed in the base predetermined region 190 (ie, formed in the subsequent first conductive type base region). The heavily doped buffer layer 200 has a first conductivity type and can be used to further reduce the size of the finally formed insulating gate bipolar transistor. The heavily doped buffer layer 200 can be formed by an ion implantation step. For example, when the first conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the heavily doped buffer layer 200 is to be formed.

Next, referring to FIG. 4, a patterned mask layer 210 is formed on the substrate. 110 is below the surface 110B. The patterned mask layer 210 can be a patterned photoresist or a patterned hard mask layer such as hafnium oxide, tantalum nitride or hafnium oxynitride. The patterned mask layer 210 has an opening 220 exposing the substrate 110 that is intended to form a first conductive type collector region.

Next, an ion implantation step is performed through the opening 220 to form the first A conductive type collector region 230 is embedded in the substrate 110. The first conductive type collector region 230 extends from the lower surface 110B of the substrate 110 into the substrate 110. The first conductive type collector region 230 can reduce the number of carriers in the substrate 110 corresponding to the second conductivity type. For example, when the second conductivity type is a P type, the number of holes in the substrate 110 can be reduced. Therefore, the first conductive type collector region 230 can reduce the turn-off loss without affecting the on voltage, the breakdown voltage, and the latch up current density. In addition, due to the reduction in closing loss, when installed When the switch is turned off, the flow carrier can be quickly reduced, thereby further shortening the switching time of the device and greatly improving the performance of the device.

In an embodiment, when the first conductivity type is N-type, The substrate 110 forming the first conductive type collector region is implanted with phosphorus ions or arsenic ions to form the first conductive type collector region 230. The width W4 of the first conductive type collector region 230 may be about 0.2-0.8 times the width W1 of the substrate 110, for example, about 0.3-0.6 times. In this embodiment, if the width W4 of the first conductive type collector region 230 is too wide, for example, 0.8 times wider than the width W1 of the substrate 110, the number of carriers corresponding to the second conductivity type in the substrate 110 may be too low. To increase the turn-on voltage. However, if the width W4 of the first conductive type collector region 230 is too narrow, for example, 0.2 times wider than the width W1 of the substrate 110, it cannot effectively reduce the number of carriers corresponding to the second conductivity type in the substrate 110, resulting in It is not possible to effectively reduce the shutdown loss of the device.

Referring to Figure 5, after removing the patterned mask layer 210, the blanket is A layer of insulating material 240 is formed on the lower surface 110B of the substrate 110. The insulating material layer 240 may be tantalum oxide, tantalum nitride, hafnium oxynitride, borophosphoquinone glass (BPSG), phosphoric bismuth glass (PSG), spin-on glass (SOG), or any other suitable dielectric material, Or a combination of the above. The insulating material layer 240 can be formed by the aforementioned chemical vapor deposition (CVD) or spin coating method and the aforementioned patterning step. In one embodiment, tetraethoxy-ortho-silicate (TEOS) can be used as a reactive gas, deposited in a plasma enhanced manner, and patterned to form an insulating material layer 240. In another embodiment, the insulating material layer 240 can be directly formed on the lower surface 110B of the substrate 110 by thermal oxidation.

Next, a patterned mask layer 250 is formed on the lower surface of the substrate 110. The first conductive type collector region 230 is shielded on the 110B to expose the substrate 110 which is intended to form the second conductive type collector region. The patterned mask layer 250 can be a patterned photoresist or a patterned hard mask layer such as hafnium oxide, tantalum nitride or hafnium oxynitride.

Next, as shown in FIG. 6, another ion implantation step is performed with the patterned mask layer 250 as a mask to form a second conductive type collector region 260 in the substrate 110. The second conductive type collector region 260 also extends into the substrate 110 from the lower surface 110B of the substrate 110. The second conductive type collector region 260 is adjacent to the first conductive type collector region 230. In an embodiment, when the second conductivity type is P-type, boron ions, indium ions or boron difluoride ions (BF ₂ ⁺ ) may be implanted in a region where the second conductivity type collector region 260 is to be formed. . The portion of the substrate 110 that is not formed with the first emitter region 120, the second emitter region 150, the third emitter region 160, the first conductive type collector region 230, and the second conductive type collector region 260 is first. Conductive base region 190'.

Next, the partial insulation that is not masked by the patterned mask layer 250 is removed. The material layer 240, the remaining insulating material layer 240 is used as the collector insulating layer 270, and the collector insulating layer 270 is disposed on the first conductive type collector region 230.

It should be noted that although the foregoing steps are to form the second conductivity type first The collector region 260 is further formed with a collector insulating layer 270. However, the above steps may also be interchanged before and after, or a portion of the insulating material layer 240 that is not shielded by the patterned mask layer 250 may be removed to form the collector insulating layer 270, and then an ion implantation step is performed to form a second conductive type set. The polar region 260 is in the substrate 110.

The thickness of the collector insulating layer 270 may be such that the collector electrode 280 and the first conductive type collector region 230 are electrically insulated from each other, for example, having a thickness greater than 10 nm. In addition, the width W5 of the collector insulating layer 270 may be about 0.2-0.8 times the width W1 of the substrate 110, for example, about 0.3-0.6 times. In an embodiment, the collector insulating layer 270 The width W5 may be the same as the width W4 of the first conductive type collector region 230. In another embodiment, the width W5 of the collector insulating layer 270 may be greater than the width W4 of the first conductive type collector region 230. It should be noted that the width W5 of the collector insulating layer 270 should be not less than the width W4 of the first conductive type collector region 230, otherwise the first conductive type collector region 230 and the subsequent collector electrode electrical properties cannot be formed. insulation.

Next, referring to Figure 7, the patterned mask layer 250 is removed, followed by Collector electrode 280 is formed to complete the fabrication of insulated gate bipolar transistor 100. The collector electrode 280 is electrically connected to the second conductive type collector region 260 and electrically insulated from the first conductive type collector region 230 by the collector insulating layer 270. The collector electrode 280 can be a single layer or a plurality of layers of gold, chromium, nickel, platinum, titanium, aluminum, tantalum, niobium, copper, combinations of the above or other conductive metal materials (such as aluminum-copper alloy (AlCu), aluminum. Beryllium copper alloy (AlSiCu)). The collector electrode 280 can be formed by, for example, sputtering, electroplating, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process.

The insulated gate bipolar transistor 100 of the embodiment of the present invention includes The substrate 110 has a first conductivity type and has an upper surface 110A and a lower surface 110B. The first conductive type collector region 230 and the adjacent second conductive type collector region 260 extend from the lower surface 110B of the substrate 110 into the substrate 110. The second conductive type is different from the first conductive type. The collector electrode 280 is electrically connected to the second conductive type collector region 260 and electrically insulated from the first conductive type collector region 230 by the collector insulating layer 270. The first emitter region 120, having a second conductivity type, extends into the substrate 110 from the upper surface 110A of the substrate 110. The second emitter region 150 has a first conductivity type and extends into the first emitter region 120 from the upper surface 110A of the substrate 110. The substrate 110 is not formed with the first emitter region 120, the second emitter region 150, the first conductive type collector region 230, and the second conductivity type. A portion of the collector region 260 serves as a first conductive type base region 190'. The emitter electrode 170 is electrically connected to the first emitter region 120 and the second emitter region 150. The gate dielectric layer 130a is disposed on the first emitter region 120, the second emitter region 150, and the substrate 110. The gate electrode 140 is disposed on the gate dielectric layer 130a. The insulated gate bipolar transistor 100 may further include a heavily doped buffer layer 200 having a first conductivity type and disposed in the first conductivity type base region 190'.

8-17 show an insulated gate bipolar according to another embodiment of the present invention Manufacturing steps of the transistor 300. Different from the gate dielectric layer and the gate electrode shown in FIG. 1-7, the gate electrode layer and the gate electrode are formed on the second emitter region, the first emitter region and the substrate. In this embodiment, the gate dielectric layer and the gate electrode system are different. Formed in a trench of the substrate. It should be noted that the same or similar elements or layers as those described above will be denoted by the same or similar reference numerals, and the materials, manufacturing methods and functions thereof are the same as or similar to those described above, and therefore will not be described later. Narration.

Referring to Figure 8, a substrate 310 is first provided. The material of the substrate 310 may be the same as the material of the substrate 110 described above. In an embodiment, the substrate 310 can have a first conductivity type. In an embodiment, the substrate 310 has a first conductivity type. For example, when the first conductivity type is an N-type, the substrate 310 may be a lightly doped N-type substrate. Further, the substrate 310 has an upper surface 310A and a lower surface 310B.

Next, a first emitter region 320 is formed in the substrate 310. The first emitter region 320 has a second conductivity type, and the second conductivity type is different from the first conductivity type. The first emitter region 320 extends from the upper surface 310A of the substrate 310 into the substrate 310 as shown in FIG. In the embodiment of the present invention, the first emitter region 320 extends only a portion of the depth of the substrate 310, that is, the thickness T5 of the first emitter region 320 is less than the thickness T4 of the substrate 310. This first emitter region 320 can be formed by an ion implantation step. For example, when the second conductivity type is a P-type, boron ions, indium ions, or boron difluoride ions (BF ₂ ⁺ ) may be implanted in a region where the first emitter region 320 is to be formed.

Referring to Figure 9, a trench 330 is formed. This trench 330 extends from the upper surface 310A of the substrate 310 through the first emitter region 320 into the substrate 310.

Referring to FIG. 10, the gate dielectric layer 340 is formed on the sidewalls and the bottom of the trench 330, and the gate electrode 350 is formed on the gate dielectric layer 340 and filled in the trench 330. In one embodiment, a dielectric material layer may be deposited on the sidewalls and the bottom of the trench 330 and the upper surface 310A of the substrate 310, and then a conductive material layer is blanket deposited on the upper surface 310A of the substrate 310. The trench 330 is filled in and filled. Next, the dielectric material layer and the conductive material layer outside the trench 330 are removed to form the gate dielectric layer 340 and the gate electrode 350, respectively. For example, the dielectric material layer and the conductive material layer outside the trench 330 may be removed by an etch back step or a chemical mechanical polishing step.

The dielectric material layer (to form the gate dielectric layer 340) may be tantalum oxide, tantalum nitride, hafnium oxynitride, high-k dielectric material, or any other suitable dielectric material. Or a combination of the above. This dielectric material layer can be formed by chemical vapor deposition (CVD) or spin coating.

The material of the foregoing conductive material layer (that is, the material of the gate electrode 350) may be amorphous germanium, polycrystalline germanium or a combination thereof. And it can be formed by chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method.

As shown in FIG. 10, the gate dielectric layer 340 directly contacts the first emitter region 320 and the substrate 310, and the gate electrode 350 is on the gate dielectric layer 340 and fills the trench 330. The gate dielectric layer 340 causes the gate electrode 350 and the first emitter region 320, the base The board 310 and the subsequently formed second emitter region are electrically insulated.

Next, as shown in FIG. 11, the first emitter region 320 is formed The second emitter region 360. The second emitter region 360 has a first conductivity type. For example, in one embodiment, the second emitter region 360 is heavily doped with a first conductivity type. In addition, the second emitter region 360 extends from the upper surface 310A of the substrate 310 into the first emitter region 320. In the embodiment of the present invention, the second emitter region 360 extends only a portion of the depth of the first emitter region 320, that is, the thickness T6 of the second emitter region 360 is smaller than the thickness T5 of the first emitter region 320. In an embodiment, the second emitter region 360 can be formed by an ion implantation step. For example, when the first conductivity type is an N-type, phosphorus ions or arsenic ions may be implanted in a region where the second emitter region 360 is predetermined to be formed.

Next, an inter-electrode dielectric layer 370 is formed on the gate electrode 350. The inter-electrode dielectric layer 370 is used to electrically insulate the gate electrode 350 from the subsequently formed emitter electrode. The interelectrode dielectric layer 370 may be yttrium oxide, tantalum nitride, hafnium oxynitride, borophosphorus bismuth (BPSG), phosphorous bismuth (PSG), spin-on glass (SOG), high density plasma (high density). Plasma, HDP) deposition or any other suitable dielectric material, or a combination of the above. The gate dielectric layer 340 can be formed by the aforementioned chemical vapor deposition (CVD) or spin coating method.

Next, referring to Figure 12, a contact etching step is performed to etch through the electricity. The inter-electrode dielectric layer 370 and the second emitter region 360 form a contact opening 380. This etching step can include reactive ion etch (RIE), plasma etching, or other suitable etching steps. Next, an ion implantation step can be selectively performed to form a third emitter region 390 in the first emitter region 320. The third emitter region 390 can be heavily doped second conductivity type. In addition, the step of forming the third emitter region 390 in the embodiment of the present invention does not use an additional mask, thereby reducing the Production cost.

Next, referring to Fig. 13, an emitter electrode 400 is formed. This shot The pole 400 is electrically coupled to the second emitter region 360 and the third emitter region 390. The emitter electrode 400 is coupled to the first emitter region 320 through the third emitter region 390. The inter-electrode dielectric layer 370 is disposed between the gate electrode 350 and the emitter electrode 400. The inter-electrode dielectric layer 370 electrically insulates the gate electrode 350 from the emitter electrode 400. The emitter electrode 400 can be a single layer or a plurality of layers of gold, chromium, nickel, platinum, titanium, aluminum, tantalum, niobium, copper, combinations of the above or other conductive metal materials (such as aluminum-copper alloy (AlCu), aluminum. Beryllium copper alloy (AlSiCu)). The emitter electrode 400 can be formed by, for example, sputtering, electroplating, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process.

Then, after the emitter electrode 400, it is selectively thin The substrate 310 is not shown (the thinned substrate is not shown). The thickness of the thinned substrate 310 will vary depending on the operating voltage and component structure.

As shown in FIG. 13, the bottom of the substrate 310 is a collector predetermined area 410. The area of the substrate 310 other than the first emitter region 320, the second emitter region 360, the third emitter region 390, and the collector predetermined region 410 serves as the base predetermined region 420. After thinning the substrate 310, the heavily doped buffer layer 430 may be selectively formed in the base predetermined region 420 (ie, formed in the subsequent first conductive type base region). The heavily doped buffer layer 430 has a first conductivity type and can be used to further reduce the size of the finally formed insulating gate bipolar transistor. This heavily doped buffer layer 430 can be formed by an ion implantation step. For example, when the first conductivity type is an N-type, phosphorus ions or arsenic ions may be implanted in a region where the heavily doped buffer layer 430 is to be formed.

Next, referring to FIG. 14, a patterned mask layer 440 is formed on the substrate. 310 is below surface 310B. The patterned mask layer 440 can be a patterned photoresist or a patterned hard mask layer such as hafnium oxide, tantalum nitride or hafnium oxynitride. The patterned mask layer 440 has an opening 450 to expose the substrate 310 that is intended to form the first conductive type collector region.

Next, an ion implantation step is performed through the opening 450 to form a A conductive collector region 460 is embedded in the substrate 310. The first conductive type collector region 460 extends from the lower surface 310B of the substrate 310 into the substrate 310. The first conductive type collector region 460 can reduce the number of carriers in the substrate 310 corresponding to the second conductivity type. For example, when the second conductivity type is a P type, the number of holes in the substrate 310 can be reduced.

In an embodiment, when the first conductivity type is N-type, The substrate 310 forming the first conductive type collector region is implanted with phosphorus ions or arsenic ions to form a first conductive type collector region 460. The width W6 of the first conductive type collector region 460 may be about 0.2-0.8 times the width W7 of the substrate 310, for example, about 0.3-0.6 times. It should be noted that if the width W6 of the first conductive type collector region 460 is too wide, for example, 0.8 times wider than the width W7 of the substrate 310, the number of carriers corresponding to the second conductivity type in the substrate 310 may be too low. Increase the turn-on voltage. However, if the width W6 of the first conductive type collector region 460 is too narrow, for example, 0.2 times wider than the width W7 of the substrate 310, it cannot effectively reduce the number of carriers corresponding to the second conductivity type in the substrate 310, resulting in It is not possible to effectively reduce the shutdown loss of the device.

Referring to Figure 15, after removing the patterned mask layer 440, the blanket is A layer of insulating material 470 is formed on the lower surface 310B of the substrate 310. The insulating material layer 470 can be tantalum oxide, tantalum nitride, hafnium oxynitride, borophosphoquinone glass (BPSG), phosphoric bismuth glass (PSG), spin-on glass (SOG), or any other suitable dielectric material, Or a combination of the above. The insulating material layer 470 can be formed by the aforementioned chemical vapor deposition (CVD) or spin coating method and the aforementioned patterning step. In one embodiment, tetraethoxy-ortho-silicate (TEOS) can be used as a reactive gas, deposited in a plasma enhanced manner, and patterned to form an insulating material layer 470. In another embodiment, the insulating material layer 470 can be directly blanket formed on the lower surface 310B of the substrate 310 by thermal oxidation.

Next, a patterned mask layer 480 is formed on the lower surface of the substrate 310. The substrate 310 is shielded from the first conductive type collector region 460 and exposed to form a substrate 310 of a second conductive type collector region. The patterned mask layer 480 can be a patterned photoresist or a patterned hard mask layer such as hafnium oxide, tantalum nitride or hafnium oxynitride.

Next, as shown in FIG. 16, another ion implantation step is performed with the patterned mask layer 480 as a mask to form a second conductive type collector region 490 in the substrate 310. The second conductive type collector region 490 also extends into the substrate 310 from the lower surface 310B of the substrate 310. The second conductive type collector region 490 is adjacent to the first conductive type collector region 460. In an embodiment, when the second conductivity type is P-type, boron ions, indium ions or boron difluoride ions (BF ₂ ⁺ ) may be implanted in a region where the second conductive type collector region 490 is to be formed. . The substrate 310 is not formed with the first emitter region 320, the second emitter region 360, the third emitter region 390, the first conductive type collector region 460, and the second conductive type collector region 490 as the first portion. Conductive base region 420'.

Next, the partial insulation that is not masked by the patterned mask layer 480 is removed. The material layer 470, the remaining insulating material layer 470 is used as the collector insulating layer 500, and the collector insulating layer 500 is disposed on the first conductive type collector region 460.

It should be noted that although the foregoing steps are to form the second conductivity type first The collector region 490 is further formed with a collector insulating layer 500. However, the above steps may also be interchanged before and after, or a portion of the insulating material layer 470 not shielded by the patterned mask layer 480 may be removed to form the collector insulating layer 500, and then an ion implantation step is performed to form a second conductive type set. The polar region 490 is in the substrate 310.

The thickness of the collector insulating layer 500 may be such that the collector electrode 510 and the first conductive type collector region 420' are electrically insulated from each other, for example, having a thickness greater than 10 nm. In addition, the width W8 of the collector insulating layer 500 may be about 0.2-0.8 times the width W7 of the substrate 310, for example, about 0.3-0.6 times. In an embodiment, the width W8 of the collector insulating layer 500 may be the same as the width W6 of the first conductive type collector region 460. In another embodiment, the width W8 of the collector insulating layer 500 may be greater than the width W6 of the first conductive type collector region 460. In this embodiment, the width W8 of the collector insulating layer 500 should be not less than the width W6 of the first conductive type collector region 460. Otherwise, the first conductive type collector region 460 and the subsequently formed collector electrode cannot be electrically charged. Sexual insulation.

Next, referring to FIG. 17, the patterned mask layer 480 is removed, and then the collector electrode 510 is formed to complete the fabrication of the insulated gate bipolar transistor 300. The collector electrode 510 is electrically connected to the second conductive type collector region 490 and electrically insulated from the first conductive type collector region 460 by the collector insulating layer 500. The collector electrode 510 may be a single layer or a plurality of layers of gold, chromium, nickel, platinum, titanium, aluminum, tantalum, niobium, copper, a combination of the above or other conductive metal materials (for example, aluminum-copper alloy (AlCu), aluminum. Beryllium copper alloy (AlSiCu)). The collector electrode 510 can be formed by, for example, sputtering, electroplating, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process.

The insulated gate bipolar transistor 300 of the embodiment of the present invention includes a substrate 310 having a first conductivity type and having an upper surface 310A and a lower surface 310B. The first conductive type collector region 460 and the adjacent second conductive type collector region 490 extend from the lower surface 310B of the substrate 310 into the substrate 310. The second conductive type is different from the first conductive type. The collector electrode 510 electrically connects the second conductive type collector region 490 and is electrically insulated from the first conductive type collector region 460 by the collector insulating layer. The first emitter region 320 has a second conductivity type and extends into the substrate 310 from the upper surface 310A of the substrate 310. The second emitter region 360 has a first conductivity type and extends into the first emitter region 320 from the upper surface 310A of the substrate 310. The portion of the substrate 310 that is not formed with the first emitter region 320, the second emitter region 360, the first conductive type collector region 460, and the second conductive type collector region 490 is used as the first conductive type base region 420'. . The emitter electrode 400 is electrically connected to the first emitter region 320 and the second emitter region 360. The trench 330 extends from the upper surface 310A of the substrate 310 through the first emitter region 320 and the second emitter region 360 and into the substrate 310. The gate dielectric layer 340 is lined with the sidewalls and the bottom of the trench 330. The gate electrode 350 is disposed on the gate dielectric layer 340 and filled in the trench 330. The inter-electrode dielectric layer 370 is disposed between the gate electrode 350 and the emitter electrode 400. The insulated gate bipolar transistor 300 may further include a heavily doped buffer layer 430 having a first conductivity type and disposed in the first conductivity type base region 420'.

It should be noted that although in the above embodiments, the first The conductivity type is N type, and the second conductivity type is P type description. However, any one of ordinary skill in the art may know that the first conductivity type may also be a P type, and the second conductivity type may be an N type.

Table 1 shows the insulated gate bipolar of the embodiment and the comparative example of the present invention. The performance comparison of the transistor is shown in Fig. 18, and the switching performance analysis diagram of the insulated gate bipolar transistor of an embodiment and a comparative example of the present invention is shown. This analysis was simulated by Computer Computer Aided Design (TCAD). The insulated gate bipolar transistor of Comparative Example 1 (the IGBT of Comparative Example 1) differs from the insulated gate bipolar transistor of the embodiment of the present invention in that it does not have the first conductive type collector region and the collector insulating layer. The reverse conducting IGBT (RC-IGBT) of Comparative Example 2 differs from the insulated gate bipolar transistor of the embodiment of the present invention in that it does not have a collector insulating layer. Fig. 18 is a view showing an insulating gate bipolar transistor (an IGBT according to an embodiment of the present invention) according to an embodiment of the present invention, an insulated gate bipolar transistor of Comparative Example 1 (an IGBT of Comparative Example 1), and Comparative Example 2; When the reverse conducting IGBT (RC-IGBT) is applied with the same voltage and the voltage is turned off at the same time, the closing time of the current of the insulated gate bipolar transistor of the embodiment of the present invention is 180 ns. And the reverse conducting insulated gate bipolar transistor of Comparative Example 2 (comparison The turn-off time of the RC-IGBT of Example 2 was 370 ns, and the turn-off time of the insulated gate bipolar transistor of Comparative Example 1 (IGBT of Comparative Example 1) was 435 ns. It can be seen that the collector structure of the insulated gate bipolar transistor according to an embodiment of the present invention can greatly reduce the off time of the device.

Figure 19 is an insulated gate bipolar of an embodiment of the present invention and a comparative example. A breakdown voltage analysis diagram of a transistor in a closed state. This analysis was simulated by Computer Computer Aided Design (TCAD). Fig. 19 is a view showing that the breakdown voltage of the current of the insulated gate bipolar transistor of the embodiment of the present invention is 1375 V, and the breakdown of the reverse conducting insulated gate bipolar transistor of Comparative Example 2 (RC-IGBT of Comparative Example 2) The voltage was 1375 V, and the breakdown voltage of the insulated gate bipolar transistor of Comparative Example 1 (IGBT of Comparative Example 1) was 1250V. It can be seen that the insulated gate bipolar transistor of one embodiment of the present invention does not affect the breakdown voltage of the device while reducing the turn-off time of the device.

Furthermore, as shown in Table 1, the on-state voltage of the insulated gate bipolar transistor of the embodiment of the present invention is 2.5 V, and the reverse conducting insulated gate bipolar transistor of Comparative Example 2 (RC of Comparative Example 2) The on-voltage of -IGBT) was 2.5 V, and the on-voltage of the insulated gate bipolar transistor of Comparative Example 1 (IGBT of Comparative Example 1) was 2.65 V. In addition, the latch-up current density of the current of the insulated gate bipolar transistor of the embodiment of the present invention is 1600 A/cm ² , and the reverse conducting insulated gate bipolar transistor of Comparative Example 2 (Comparative) The latch current density of the RC-IGBT of Example 2 was 1600 A/cm ² , and the latching current density of the insulated gate bipolar transistor of Comparative Example 1 (IGBT of Comparative Example 1) was 1500 A/cm ² . It can be seen that the insulated gate bipolar transistor of one embodiment of the present invention does not affect its on voltage and latch up current density while reducing the turn-off time of the device.

In summary, the insulated gate bipolar electric crystal of the embodiment of the invention The body can reduce the turn-off loss without affecting the on voltage, the breakdown voltage, and the latch up current density. In addition, due to the reduction in the closing loss, the flow carrier can be quickly reduced when the device is turned off, so that the switching time of the device can be further shortened, and the performance of the device is greatly improved.

Although the embodiments of the present invention and its advantages are disclosed above, it should be understood that those skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of the invention. In addition, the scope of the present invention is not limited to the processes, machines, manufacture, compositions, devices, methods, and steps in the specific embodiments described in the specification. Any one of ordinary skill in the art can. The processes, machines, fabrications, compositions, devices, methods, and procedures that are presently or in the future are understood to be used in accordance with the present invention as long as they can perform substantially the same function or achieve substantially the same results in the embodiments described herein. Accordingly, the scope of the invention includes the above-described processes, machines, manufactures, compositions, devices, methods, and steps. In addition, the scope of each of the claims constitutes an individual embodiment, and the scope of the invention also includes the combination of the scope of the application and the embodiments.

100‧‧‧Insulated gate bipolar transistor

110‧‧‧Substrate

120‧‧‧first emitter area

130a‧‧‧gate dielectric layer

130b‧‧‧Interelectrode dielectric layer

140‧‧‧gate electrode

150‧‧‧second emitter area

160‧‧‧third emitter area

170‧‧ ‧ emitter electrode

190'‧‧‧First Conductive Base Region

200‧‧‧ heavily doped buffer layer

230‧‧‧First Conductive Collector Region

260‧‧‧Second Conductive Collector Region

270‧‧‧ collector insulation

280‧‧ ‧ collector electrode

Claims (14)

An insulated gate bipolar transistor comprises: a substrate having a first conductivity type and having an upper surface and a lower surface; a first conductivity type collector region and an adjacent one of the second conductivity type collector regions Extending from the lower surface of the substrate into the substrate, wherein the second conductivity type is different from the first conductivity type; a collector electrode electrically connecting the second conductivity type collector region and having a collector The insulating layer is electrically insulated from the first conductive type collector region; a first emitter region having the second conductivity type extending from the upper surface of the substrate into the substrate; and a second emitter region having the a first conductivity type extending from the upper surface of the substrate into the first emitter region, wherein the substrate is not formed with the first emitter region, the second emitter region, and the first conductive type collector region And a portion of the second conductive type collector region is a first conductive type base region; an emitter electrode electrically connected to the first emitter region and the second emitter region; and a gate dielectric a layer disposed on the first emitter region, the second emitter region and the substrate; and a gate electrode disposed on the gate Dielectric layer. The insulated gate bipolar transistor according to claim 1, wherein the material of the collector insulating layer comprises cerium oxide, cerium nitride or cerium oxynitride. The insulated gate bipolar transistor of claim 1, wherein the collector insulating layer has a thickness greater than 10 nm. The insulated gate bipolar transistor according to claim 1, wherein the collector insulating layer has a width of 0.2-0.8 times the width of the substrate. The insulated gate bipolar transistor according to claim 1, further comprising a heavily doped buffer layer having a first conductivity type and disposed in the first conductivity type base region. An insulated gate bipolar transistor comprises: a substrate having a first conductivity type and having an upper surface and a lower surface; a first conductivity type collector region and an adjacent one of the second conductivity type collector regions Extending from the lower surface of the substrate into the substrate, wherein the second conductivity type is different from the first conductivity type; a collector electrode electrically connecting the second conductivity type collector region and having a collector The insulating layer is electrically insulated from the first conductive type collector region; a first emitter region having the second conductivity type and extending from the upper surface of the substrate into the substrate; and a second emitter region having The first conductivity type extends from the upper surface of the substrate into the first emitter region, wherein the substrate is not formed with the first emitter region, the second emitter region, and the first conductive collector And a portion of the second conductive type collector region serves as a first conductive type base region; an emitter electrode electrically connected to the first emitter region and the second emitter region; and a trench a trench extending from the upper surface of the substrate through the first emitter region and the second emitter region and into the substrate a gate dielectric layer lining the sidewalls and the bottom of the trench; a gate electrode disposed on the gate dielectric layer and filling the trench; and an inter-electrode dielectric layer disposed on the gate The gate electrode is between the emitter electrode and the emitter electrode. The insulated gate bipolar transistor according to claim 6, further comprising a heavily doped buffer layer having a first conductivity type and disposed on the first conductive In the base region. A method for manufacturing an insulated gate bipolar transistor includes: providing a substrate having a first conductivity type and having an upper surface and a lower surface; forming a first emitter region having a second conductivity type The upper surface of the substrate extends into the substrate, and the second conductivity type is different from the first conductivity type; forming a gate dielectric layer on the first emitter region and the substrate; forming a gate electrode Forming a second emitter region, the second emitter region having the first conductivity type, and extending from the upper surface of the substrate into the first emitter region; forming an emitter An electrode, the emitter electrode is electrically connected to the first emitter region and the second emitter region; forming a first conductive type collector region extending from the lower surface of the substrate into the substrate; forming a collector An insulating layer is disposed on the first conductive type collector region; a second conductive type collector region is formed adjacent to the first conductive type collector region, wherein the substrate is not formed with the first emitter region, the second portion The emitter region, the first conductive type collector region, and the portion of the second conductive type collector region are a first conductive type base region; and a collector electrode electrically connected to the second conductive type collector region, and the collector conductive layer and the first conductive type collector region are electrically connected insulation. The system for insulating gate bipolar transistors as described in claim 8 The method, wherein the material of the collector insulating layer comprises cerium oxide, cerium nitride or cerium oxynitride. The method for manufacturing an insulated gate bipolar transistor according to claim 8, wherein the collector insulating layer has a thickness greater than 10 nm. The method for manufacturing an insulated gate bipolar transistor according to claim 8, wherein the collector insulating layer has a width of 0.2 to 0.8 times the width of the substrate. The method for manufacturing an insulated gate bipolar transistor according to claim 8 , further comprising forming a heavily doped buffer layer in the first conductive type base region, wherein the heavily doped buffer layer has a first Conductive type. A method for manufacturing an insulated gate bipolar transistor, comprising: providing a substrate having a first conductivity type and having an upper surface and a lower surface; forming a first emitter region having a second conductivity type, and Extending from the upper surface of the substrate into the substrate, and the second conductivity type is different from the first conductivity type; forming a trench extending from the upper surface of the substrate through the first emitter region to the In the substrate, a gate dielectric layer is formed on the sidewalls and the bottom of the trench; a gate electrode is formed on the gate dielectric layer and fills the trench; and a second emitter region is formed. The second emitter region has the first conductivity type and extends from the upper surface of the substrate into the first emitter region; an inter-electrode dielectric layer is formed on the gate electrode; and an emitter electrode is formed. The emitter electrode and the first emitter region and the second shot The pole region is electrically connected, and the inter-electrode dielectric layer is disposed between the gate electrode and the emitter electrode; forming a first conductive type collector region extending from the lower surface of the substrate into the substrate; forming a collector insulating layer is disposed on the first conductive type collector region; a second conductive type collector region is formed adjacent to the first conductive type collector region, wherein the substrate is not formed with the first emitter region, The second emitter region, the first conductive type collector region and a portion of the second conductive type collector region are used as a first conductive type base region; and a collector electrode is formed, the collector electrode electrical The second conductive type collector region is connected, and is electrically insulated from the first conductive type collector region by the collector insulating layer. The method for manufacturing an insulated gate bipolar transistor according to claim 13 , further comprising forming a heavily doped buffer layer in the first conductive type base region, wherein the heavily doped buffer layer has a first A conductive type.