TWI805524B - Semiconductor device and the method for forming the same - Google Patents

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate, an epitaxy layer, an electrode structure, a first sidewall doping region and a second sidewall doping region, and a bottom doping region. The substrate has a first conductive type. The epitaxy layer has a first conductive type and is disposed on the substrate. The electrode structure is disposed in the epitaxy layer. The electrode structure extends along a first direction. The first sidewall doping region has the first conductive type and is disposed on a side of the electrode structure. The second sidewall doping region has a second conductive type different than the first conductive type and is disposed on another side of the electrode structure. The bottom doping region has the second conductive type and is disposed under the electrode structure. The second sidewall doping region is connected with the bottom doping region.

Description

Semiconductor device and method of forming the same

The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having vertical reduced surface field (RESURF) and asymmetric doped regions and a method for forming the same.

High-voltage component technology is generally used in high-voltage and high-power circuits or drive circuits. In order to meet the performance requirements of high withstand voltage, high current and high power density for traditional power transistors, the structure of power components has developed from a plane direction to a vertical direction. At present, structures such as vertical trench gate metal oxide semiconductor field effect transistors have been developed.

However, because the power element easily generates an excessive electric field at the corner of the bottom, which leads to current concentration, which in turn causes problems such as thermal runaway and high resistance of the channel area due to temperature rise of the power element. Existing high-voltage semiconductor devices are not satisfactory in all aspects, and further improvements are still needed to meet practical requirements.

Therefore, it is necessary to find a novel metal oxide semiconductor field effect transistor and its forming method to solve or improve the above-mentioned problems.

An embodiment of the present invention provides a semiconductor device, including a substrate, an epitaxial layer, an electrode structure, a first sidewall doped region, a second sidewall doped region, and a bottom doped region. The substrate has a first conductivity type. The epitaxial layer has a first conductivity type and is disposed on the substrate. The electrode structure is disposed in the epitaxial layer. The electrode structure extends along a first direction. The first sidewall doped region has a first conductivity type and is disposed on one side of the electrode structure. The second sidewall doped region has a second conductivity type different from the first conductivity type and is disposed on the other side of the electrode structure. The bottom doped region has the second conductivity type and is disposed under the electrode structure. The second side wall doped region is connected with the bottom doped region.

An embodiment of the present invention provides a method for forming a semiconductor device, including providing a substrate, wherein the substrate has a first conductivity type; forming an epitaxial layer on the substrate, wherein the epitaxial layer has a first conductivity type; forming a trench along a first direction on the substrate. In the epitaxial layer; forming a doped region around the trench. Forming the doped region includes: respectively performing first ion implantation and second ion implantation on two sidewalls of the trench to form a first sidewall doped region and a second sidewall doped region. The first sidewall doped region and the second sidewall doped region have different conductivity types respectively. The first ion implantation and the second ion implantation are not perpendicular to the substrate. The forming method further includes: forming an electrode structure in the trench.

The following disclosure provides many different embodiments or examples for implementing different components of the provided semiconductor devices. Specific examples of each component and its configuration are described below to simplify the embodiments of the present disclosure. Of course, these are just examples, not intended to limit the present disclosure. For example, if it is mentioned in the description that the first component is formed on the second component, it may include an embodiment in which the first component and the second component are in direct contact, and may also include an additional component formed on the first component and the second component between them so that they are not in direct contact with each other. In addition, the embodiments of the present disclosure may repeat element symbols and/or characters in different examples. This repetition is for brevity and clarity and is not intended to represent a relationship between the different embodiments and/or aspects discussed.

Some variations of the embodiment are described below. In the different drawings and described embodiments, similar reference numerals are used to designate similar components. It can be understood that additional operations may be provided before, during, and after the method, and some described operations may be replaced or deleted for other embodiments of the foregoing method.

Furthermore, terms related to space, such as "on", "under", "above", "below" and similar expressions, in addition to including the orientation shown in the diagram, also include Including different orientations of the device in use or operation. When the device is turned to another orientation (rotated 90 degrees or otherwise), the spatially relative descriptions used herein can also be read in terms of the rotated orientation.

In the embodiment of the present invention, the doped regions on both side walls surrounding the electrode structure have different conductivity types, which can reduce the surface electric field and reduce the drain-to-source on-resistance (Rdson) (hereinafter also referred to as conduction) without affecting the breakdown voltage. resistance). Specifically, the sidewall doped region with n-type conductivity can reduce the resistance caused by the parasitic junction gate field-effect transistor (JFET), and the sidewall doped region with p-type conductivity can be in The surface electric field at the superjunction is reduced when the device is turned off.

In addition, the embodiments of the present invention can further reduce the electric field and increase the breakdown voltage through the bottom doped region covering the bottom of the electrode structure. Moreover, the gate-to-source capacitance (Cgs) and the drain-to-source capacitance (Cds) can be further reduced by the bottom doped region and the sidewall doped region having p-type conductivity.

In addition, the embodiment of the present invention replaces the traditional electrode structure with the separated trench electrode structure, which can further reduce the contact area between the gate electrode and the drift region, and more effectively reduce the gate-to-drain capacitance (Cgd).

Some variations of the embodiment are described below. In the different drawings and described embodiments, like reference numerals have been used to designate like elements.

1-17 are schematic cross-sectional views illustrating different stages of forming a semiconductor device according to some embodiments of the present invention. Additional operations may be provided before, during, and/or after the stages described in FIGS. 1-17. In various embodiments, some of the aforementioned operations may be moved, deleted or replaced. Additional components may be added to the semiconductor device. In various embodiments, some of the components described below may be removed, deleted or substituted.

It should be noted that the structure of forming a single transistor (including a single electrode structure) is described below, however, multiple transistors (including a plurality of electrode structures) can also be formed simultaneously as shown in the figure.

Referring to FIG. 1 , a substrate 100 having a first conductivity type is provided. Here, the substrate 100 is defined as extending along the plane formed by the direction X and the direction Y, and a film layer is formed on the substrate 100 along the Z direction. The cross-sectional views shown in this document are all shown as the plane formed by the direction X and the direction Z.

In some embodiments, the substrate 100 may be made of silicon or other semiconductor materials, such as silicon wafers, bulk semiconductors or wide-gap semiconductors. In some embodiments, the substrate 100 can be an elemental semiconductor, such as a silicon substrate; the substrate 100 can also be a compound semiconductor, such as silicon carbide or gallium nitride. In some embodiments, the substrate 100 may also include silicon on insulator (SOI) or other suitable substrates. In the embodiment of the present invention, the substrate 100 is, for example, silicon carbide doped with the first conductivity type. In the application of a vertical trench-gate MOSFET, the substrate 100 with the first conductivity type can be used as a drain region of the semiconductor device. In the embodiment of the present invention, the first conductivity type is n-type, but it is not limited thereto. In some other embodiments, the first conductivity type may also be p-type.

Continuing to refer to FIG. 1 , an epitaxial layer 200 of the first conductivity type is formed on the substrate 100 . That is, the substrate 100 and the epitaxial layer 200 have the same conductivity type. In this embodiment, the epitaxial layer 200 is, for example, n-type. In some embodiments, the doping concentration of the epitaxial layer 200 (eg, about 10 ¹⁵ -10 ¹⁶ atoms/cm ³ ) is smaller than that of the substrate 100 (10 ¹⁹ -10 ²¹ atoms/cm ³ ). In some embodiments, the formation of the epitaxial layer 200 may include epitaxial growth processes, such as metal organic chemical vapor deposition (metal organic chemical vapor deposition, MOCVD), plasma-enhanced chemical vapor deposition (plasma-enhanced CVD, PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl -VPE), other suitable process methods, or a combination of the foregoing. In the application of the vertical trench gate MOSFET, the epitaxial layer 200 having the first conductivity type can be used as a drift region of the semiconductor device.

Next, referring to FIG. 2 , a well region 300 having a second conductivity type is formed in the epitaxial layer 200 . That is, the well region 300 and the epitaxial layer 200 have different conductivity types. In the embodiment of the present invention, the well region 300 is p-type, and its dopant is, for example, aluminum (Al), boron (B) or other suitable dopant. In some embodiments, the doping concentration of the well region 300 (eg, about 10 ¹⁷ -10 ¹⁸ atoms/cm ³ ) is greater than that of the epitaxial layer 200 . In some embodiments, the formation of the well region 300 may include an ion implantation process, such as blanketing the epitaxial layer 200 along the Z direction (eg, a direction at 90° to the substrate 100 ). ) ion implantation process. In the application of the vertical trench gate MOSFET, the well region 300 with the second conductivity type can be used as a channel region of the semiconductor device.

Next, referring to FIGS. 3-4 , a doped contact region 400 is formed in the well region 300 . The contact doped region 400 includes a first contact doped region 410 and a second contact doped region 420 adjacent to each other and having different conductivity types, so that the well region 300 can be subsequently connected to the source through a good ohmic contact. , to reduce the body effect (body effect) and stabilize the initial voltage. Its formation is detailed as follows.

As shown in FIG. 3 , a mask M1 is set at the non-predetermined doping position, and ion implantation is performed on the well region 300 by ion implantation to form a first hole in the well region 300 between the masks M1. A contact doped region 410 . Next, the mask M1 is removed. In some embodiments, the ion implantation can be straight ion implantation or oblique ion implantation, etc., but the invention is not limited thereto.

The depth of the doped region 410 of the first contact can be controlled by adjusting the implantation energy or other suitable methods. In the embodiment of the present invention, the depth of the first contact doped region 410 does not exceed the depth of the well region 300 (that is, the well region 300 covers the bottom surface of the first contact doped region 410), so as to reduce the body effect ( body effect). The removal of the mask M1 may include an ashing process, a wet etching process (such as acid etching), or other suitable processes.

As shown in FIG. 4, a mask M2 is set at a non-predetermined doping position (for example, directly above the first contact doped region 410), and ion implantation is performed on the well region 300 through ion implantation, The second contact doped region 420 is formed in the well region 300 between the masks M2. Next, the mask M2 is removed. In some embodiments, the ion implantation can be straight ion implantation or oblique ion implantation, etc., but the invention is not limited thereto.

Similarly, the depth of the second contact doped region 420 can also be controlled by adjusting the implantation energy or other suitable methods. In the embodiment of the present invention, the depth of the second contact doped region 420 generally does not exceed the depth of the well region 300 (that is, the well region 300 covers the bottom surface of the second contact doped region 420 ). The removal of the mask M2 is similar to the above, and will not be repeated here.

In some embodiments, the positions and shapes of the mask M1 and the mask M2 can be appropriately adjusted according to design requirements. For example, the mask M1 and the mask M2 can be set in a complementary manner (the positions are not repeated at all). , or, the mask M1 and the mask M2 can be set in a manner of partially overlapping positions, and so on.

The order of forming the first contact doped region 410 and the second contact doped region 420 is not particularly limited, and the first contact doped region may also be formed after the second contact doped region 420 is formed. As long as the conductivity types of the first contact doped region 410 and the second contact doped region 420 are different, there is no particular limitation. For example, in the embodiment of the present invention, the first contact doped region 410 and the second contact doped region 420 The impurity region 420 may be of the second conductivity type and the first conductivity type, ie, p-type and n-type, and the dopants thereof are, for example, aluminum (Al) and nitrogen (N), respectively. In some embodiments, the doping concentration of the first contact doped region 410 and the second contact doped region 420 (about 10 ¹⁹ -10 ²⁰ atoms/cm ³ ) is greater than that of the well region 300 to reduce The contact resistance thus reduces the on-resistance (Rdson).

Next, referring to FIG. 5 , a trench O is formed in the epitaxial layer 200 . Specifically, using the mask M3 as an etching mask, the trench O is formed by etching through the contact doped region 400, the well region 300 and the contact epitaxial layer 200 by an etching process along the direction Z, and the remaining first A contact doped region 410 and a second contact doped region 420 are respectively denoted as a first contact doped region 410 ′ and a second contact doped region 420 ′. In some embodiments, trench O extends along direction Y.

In some embodiments, a mask M3 is provided at a non-predetermined etching position to protect the underlying film layer and/or the doped region. In some embodiments, as long as the mask M3 is disposed (covered) on the first contact doped region 410 ′ and the second contact doped region 420 ′ at the same time to form a good ohmic contact later, there is no special limitation on the two. For example, in the embodiment of the present invention, the top surface areas of the first contact doped region 410' and the second contact doped region 420' occupy approximately 50% of the bottom surface area of the mask M3 respectively, However, the present invention is not limited thereto.

In the application of the vertical trench gate metal oxide semiconductor field effect transistor, the first contact doped region 410 ′ having the second conductivity type and the second contact doped region 420 having the first conductivity type 'Can be used as a source contact and a body contact of a semiconductor device respectively, and both are ohmic contacts.

In some embodiments, the etching process may include a dry etching process, a wet etching process, or other suitable etching processes. Dry etching may include plasma etching, plasma-free gas etching, sputter etching, ion milling, reactive ion etching (RIE), neutral beam etching (neutral beam etch, NBE), inductive coupled plasma etch (inductive coupled plasma etch). Wet etching may include using an acidic solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed. In addition, the etching process can also be pure chemical etching, pure physical etching, or any combination thereof.

Next, referring to FIGS. 6-8 , a doped region 500 is formed around the trench O. Referring to FIGS. The doped region 500 includes a first sidewall doped region 510 and a second sidewall doped region 520 of different conductivity types on both sides of the trench O, and a bottom doped region 530 at the bottom of the trench O, thereby reducing the surface electric field and reduces the gate-to-drain capacitance (Cgd). Its formation is detailed as follows.

As shown in Figures 6-7, ion implantation is performed on one side of the trench O by the first ion implantation im1, and then ion implantation is performed on the other side of the trench O by the second ion implantation im2 , so as to respectively form the sidewall doped region 510 and the sidewall doped region 520 having different conductivity types.

In some embodiments, the first ion implantation im1 and the second ion implantation im2 include performing ion implantation on the sidewall of the trench O in a manner that is not perpendicular to the substrate 100 (not along the direction Z), but not on the trench O ion implantation at the bottom. That is, as long as the implantation angles of the first ion implantation process im1 and the second ion implantation process im2 are not parallel to the normal of the substrate 100 and can be implanted on the sidewall of the trench O, there is no particular limitation. In some embodiments, the first ion implantation im1 and the second ion implantation im2 may be oblique ion implantation, for example.

In some embodiments, as long as the dopant conductivity types of the first ion implantation im1 and the second ion implantation im2 are different, there is no particular limitation. For example, in the embodiment of the present invention, the first ion implantation im1 and the second ion implantation im1 The implant im2 can use dopants of the first conductivity type and the second conductivity type respectively, that is, n-type and p-type, so the sidewall doped region 510 and the sidewall doped region 520 can be respectively the first conductivity type and the second conductivity type. The dopants of the conductivity type, ie n-type and p-type, are respectively nitrogen (N) and aluminum (Al), but the present invention is not limited thereto.

In some embodiments, the sidewall doped region 510 is separated from the contact doped region 400 by the well region 300 , and the sidewall doped region 520 contacts the contact doped region 400 through the well region 300 . In detail, the sidewall doped region 520 is in contact with the second contact doped region 420'.

In the embodiment of the present invention, after the first ion implantation im1 of dopants of the first conductivity type and the second ion implantation im2 of dopants of the second conductivity type, the two sides of the well region 300 have different doping concentrations . In detail, one side of the well region 300 has a concentration of the second conductivity type that is thicker than the middle portion of the well region 300, and the other side of the well region 300 has a concentration of the second conductivity type that is lighter than the middle portion of the well region 300, thus A doping concentration gradient of the second conductivity type from light to rich is formed in the direction X. Thereby, the situation of punch through can be prevented at the higher doping concentration, and the threshold voltage can be lowered at the lower doping concentration.

As shown in FIG. 8 , a third ion implantation im3 is performed on the bottom of the trench O to form a bottom doped region 530 . That is, the bottom doped region 530 covers the entire bottom of the trench O. As shown in FIG. Thereby, the electric field at the corner of the trench O can be effectively reduced.

In some embodiments, the third ion implantation im3 performs ion implantation on the bottom of the trench O in a manner perpendicular to the substrate 100 (along the direction Z). In some embodiments, the third ion implantation im3 may be, for example, straight ion implantation, but the invention is not limited thereto. In some embodiments, the third ion implantation im3 uses dopants of the second conductivity type, that is, p-type, so the bottom doped region 530 can be of the second conductivity type, that is, p-type, and its dopant is, for example, aluminum (Al).

In some embodiments, the doping concentration of the bottom doped region 530 (about 10 ¹⁶ -10 ¹⁹ atoms/cm ³ ) is greater than or equal to the doping concentration of the sidewall doped region 510 or the sidewall doped region 520 (about 10 ¹⁵ - 10 ¹⁸ atoms/cm ³ ). Thereby, the electric field at the bottom and corner of the trench O can be further reduced while reducing the impact on the channel region.

It should be noted that the first contact doped region 410 ′, the sidewall doped region 520 and the bottom doped region 530 shown in FIG. 8 of this application only represent the same conductivity type, so there is no clear boundary between the three. However, actual doping levels may vary depending on product requirements.

It should be noted that during the ion implantation as shown in FIGS. 6-8 , the mask M3 remains disposed on the contact doped region 400 to prevent the contact doped region 400 from being affected and changing its conductivity type. And, after the implantation process is completed, the mask M3 is removed. The method for removing the mask M3 is similar to that described above, and will not be repeated here.

It should be noted that although the embodiment of the present invention illustrates the formation of the doped region 500 in the order of FIGS. After the bottom doped region is formed by the third ion implantation process, the first and second ion implantation processes are performed to form the side wall doped region.

In the embodiment of the present invention, by forming a doped region to surround the trench, the subsequently formed electrode structure can be prevented from directly contacting the epitaxial layer, thereby reducing the gate-to-drain capacitance (Cgd) and the drain-to-source capacitance (Cds). Moreover, the embodiment of the present invention can further reduce the surface electric field and increase the breakdown voltage by using the bottom doped region.

Next, referring to FIG. 9 , after removing the mask M3 , the contact doped region 400 and the doped region 500 are activated.

In some embodiments, the activation can be performed before or after forming the electrode structure depending on the substrate material. For example, in the case where the substrate material is silicon, since the activation (or annealing) temperature is, for example, 900ﾟC, activation can be performed after the electrode structure is formed without affecting the electrode structure; in the case of the substrate material being silicon carbide In this case, since the activation temperature is, for example, 1800ﾟC, the elements of the electrode structure to be formed later may melt away, so activation must be performed before forming the electrode structure. In addition, if the substrate material is SiC, a graphite cap can be formed before activation and removed after activation to maintain the surface roughness of SiC during activation.

Next, referring to FIGS. 10-14 , an electrode structure 600 is formed in the trench O. Referring to FIGS. The electrode structure 600 may be a general gate trench structure or a split gate trench structure. In an embodiment of the present invention, the electrode structure 600 is a split-gate trench structure, which includes a top electrode, a bottom electrode, and a dielectric layer surrounding the top electrode and surrounding the bottom electrode. In some embodiments, the electrode structure 600 extends along the direction Y. The details of the electrode structure 600 will be explained as follows.

As shown in FIG. 10 , a shielding dielectric layer 610 is formed on the epitaxial layer 200 entirely. In detail, a shielding dielectric layer 610 is formed on the bottom and sidewalls of the trench O. Referring to FIG. In some embodiments, the shielding dielectric layer 610 can be silicon oxide, other suitable semiconductor oxide materials, or a combination of the aforementioned materials. In some embodiments, the formation of the masking dielectric layer 610 includes a conformably deposition process, an oxidation process, other suitable formation processes, and the like.

In some embodiments, the oxidation process may be thermal oxidation, or other suitable processes. In some embodiments, the deposition process may be a physical vapor deposition (physical vapor deposition; PVD) process, a chemical vapor deposition (CVD) process, a plasma-assisted chemical vapor deposition (PECVD), other suitable processes, or It is a combination of the aforementioned processes.

In some embodiments, a thermal process may be optionally performed on the shielding dielectric layer 610 to increase the density of the shielding dielectric layer 610 . In some embodiments, the thermal process may be a rapid thermal annealing (RTA) process.

As shown in FIG. 11 , a bottom gate 620 is formed in trench O. As shown in FIG. In some embodiments, the bottom electrode 620 is formed on the shielding dielectric layer 610 . In some embodiments, the top surface of the bottom electrode 620 is lower than the bottom surface of the well region 300 . The bottom electrode 620 is separated from the epitaxial layer 200 by a shielding dielectric layer 610 .

In some embodiments, the bottom electrode 620 can be a single-layer or multi-layer structure formed of amorphous silicon, polysilicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or a combination of the foregoing materials. . In some embodiments, metals may include, but are not limited to, tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt). In some embodiments, metal nitrides may include, but are not limited to, titanium nitride (TiN) and tantalum nitride (TaN). In some embodiments, the metal silicide may include, but is not limited to, tungsten silicide ( _WSix ). In some embodiments, the bottom electrode 620 may optionally contain dopants of the second conductivity type, ie, p-type, which may be aluminum (Al), boron (B), boron difluoride (BF ₂ ) or other suitable doping.

In some embodiments, the formation of the bottom electrode 620 includes depositing a bottom electrode material (not shown) on the masking dielectric layer 610 and the epitaxial layer 200 by a deposition process, and selectively performing a thermal process (such as annealing) on the bottom electrode material. process), and then a part of the bottom electrode material is removed by a removal process, so that the bottom electrode 620 does not fill the entire trench O (or the bottom electrode is recessed to a specific depth). In some embodiments, the above-mentioned deposition process may include metal organic chemical vapor deposition (MOCVD), sputtering, resistance heating evaporation, electron beam evaporation, suitable methods, and the like. In some embodiments, the removal process may include a planarization process, an etching process, etc., such as a chemical mechanical polishing (CMP) process, a dry etching process, and the like.

In some embodiments, the bottom electrode 620 can reduce the gate-to-drain capacitance (Cgd) to improve the switching characteristics of the semiconductor device, and it has a field plate (Field Plate) function to further enhance the reduction of the surface electric field (RESURF) Effect.

As shown in FIG. 12, a portion of the masking dielectric layer 610 is removed. Specifically, the portion of the shielding dielectric layer 610 not covered by the bottom electrode 620 is removed by a wet etching process, and the remaining shielding dielectric layer 610 is denoted as a shielding dielectric layer 610'. A shielding dielectric layer 610' is located on the sidewalls and bottom of the trench O lower portion. In some embodiments, the top surface of the masking dielectric layer 610' may be above (not shown), below, or substantially coplanar with the top surface of the bottom electrode 620. In the embodiment of FIG. 12, the top surface of the masking dielectric layer 610' is substantially coplanar with the top surface of the bottom electrode 620 and is slightly dished.

As shown in FIG. 13 , a dielectric layer 630 is formed on the epitaxial layer 200 , the masking dielectric layer 610 ′, and the bottom electrode 620 . The dielectric layer 630 may serve as a gate dielectric layer for a subsequently formed top electrode.

In some embodiments, the dielectric layer 630 extends from the top surface of the epitaxial layer 200 into the trench O and covers the top surface of the shielding dielectric layer 610' and the top surface of the bottom electrode 630. In the embodiment of the present invention, the dielectric layer 630 does not fill the trench O. That is, there is a space on the dielectric layer 630 in the trench O after the dielectric layer 630 is formed. Furthermore, in some embodiments, the thickness of the dielectric layer 630 in the trench O is less than the thickness of the shielding dielectric layer 610' in the trench O.

In some embodiments, the dielectric layer 630 can be silicon oxide, other suitable dielectric materials, or a combination of the aforementioned materials. In some embodiments, the material of the dielectric layer 630 that is the same as or different from the material of the shielding dielectric layer 610' can be selected according to actual requirements.

In some embodiments, the formation of the dielectric layer 630 may include an oxidation process similar to that described above, which will not be repeated here. It should be noted that during the formation of the dielectric layer 630 , since the bottom electrode 620 is also oxidized, a thicker insulating portion 640 is formed above the bottom electrode 630 . The insulating portion 640 is located between the bottom electrode 620 and a subsequently formed top electrode (not shown), and can be used for electrical isolation. The insulating portion 640 may also include materials similar to the dielectric layer 630 , which will not be repeated here.

As shown in FIG. 14 , a top gate 650 is formed in the trench O . In some embodiments, the top electrode 650 is located on the dielectric layer 630 and separated from the bottom electrode 620 by the insulating portion 640 . In some embodiments, the top surface of top electrode 650 is coplanar with the top surface of dielectric layer 630 . In some embodiments, the sidewall doped region 520 of the second conductivity type covers the entire sidewall of the bottom electrode 620 .

In some embodiments, the top electrode 650 can be a single-layer or multi-layer structure, and can be selected from materials similar to the bottom electrode 620, so details will not be repeated here. In some embodiments, the material of the top electrode 650 that is the same as or different from that of the bottom electrode 620 can be selected according to actual needs. In some embodiments, the top electrode 650 may optionally contain dopants of the second conductivity type, ie, p-type, which may be boron (B), boron difluoride (BF ₂ ) or other suitable dopants.

In some embodiments, the formation of the top electrode 650 includes depositing a top electrode material (not shown) on the dielectric layer 630 and the insulating portion 640 by a deposition process, selectively performing a thermal process on the top electrode material, and then removing The process removes a portion of the top electrode material such that the top surface of the top electrode 650 is substantially coplanar with the dielectric layer 630 . The relevant manufacturing process is similar to the above, and will not be repeated here.

In some embodiments, the top electrode 650 and the bottom electrode 620 can be electrically connected to the gate and the source respectively, which can more effectively reduce the contact area between the gate and the drift region (such as the epitaxial layer), thus reducing the gate pair. Drain capacitance (Cgd) and improve switching characteristics of semiconductor devices.

In some embodiments, the doped region 500 surrounds the electrode structure 600 . In some embodiments, sidewall doped regions 510 and 520 of the first conductivity type and the second conductivity type are provided on both sides of the electrode structure 600 respectively, and a bottom doped region 530 of the second conductivity type is provided at the bottom of the electrode structure. . Moreover, the sidewall doped regions 510 and 520 are connected by the bottom doped region 530 .

In the case where a plurality of transistors are to be formed, another trench can be formed on one side of the trench O (or in the X direction of the trench O) while forming the trench O (as shown in Figure 5); While forming the doped region 500, another doped region is formed around another trench (as shown in Figures 6-8); while the electrode structure 600 is formed, another electrode structure is formed in another trench (as in Figures 10-14). In some embodiments, the electrode structure 600 is separated from another electrode structure by the epitaxial layer 200 .

In some embodiments, another doped region is disposed in the epitaxial layer 200 and surrounds another electrode structure. In some embodiments, the other doped region is similar to the doped region 500, including another first sidewall doped region with the first conductivity type, another second sidewall doped region with the second conductivity type, and another doped sidewall region with the second conductivity type. Another bottom doped region of the second conductivity type, wherein another first sidewall doped region is connected to another second sidewall doped region through another bottom doped region. In some embodiments, the sidewall doped region 510 of the electrode structure 600 with different conductivity types is separated from the other sidewall doped region of another electrode structure by the epitaxial layer 200 . Furthermore, the doped sidewall region of the electrode structure 600 with different conductivity types and the doped sidewall region of another electrode structure and the epitaxial layer 200 therebetween can be regarded as a super junction. Thereby, the dopant concentration of the first conductivity type can be increased without affecting the breakdown voltage.

Next, referring to FIGS. 15-17 , a source contact 800 , a source electrode 900 and a passivation layer 1000 are formed on the electrode structure 600 .

As shown in FIG. 15 , an interlayer dielectric layer 700 is formed on the top electrode 650 and the dielectric layer 630 . In some embodiments, the interlayer dielectric layer 700 may include materials similar to the dielectric layer 630 , which will not be repeated here. In some embodiments, the formation of the interlayer dielectric layer 700 may include a deposition process similar to that described above, which will not be repeated here.

As shown in FIG. 16 , a contact hole H is formed in the interlayer dielectric layer 700 . In some embodiments, the formation of the contact hole H may include using a mask (or photoresist) as an etching mask, and etching a part of the interlayer dielectric layer 700 by one or more etching processes, and then removing the mask. (or photoresist).

As shown in FIG. 17, a contact 800 is formed in the contact hole H. Referring to FIG. In some embodiments, the contact 800 may include a contact metal silicide, a contact metal (not shown), a barrier layer, and the like. The barrier layer may serve to prevent the subsequently formed contact metal from diffusing into the interlayer dielectric layer 700 . Silicides can be used to reduce contact resistance.

In some embodiments, the contact 800 may comprise a conductive material comprising metal, metal nitride, etc., such as copper, silver, gold, aluminum, tungsten, titanium (Ti), titanium nitride (TiN), tantalum (Ta) , tantalum nitride (TaN), cobalt (Co), nickel silicide (nickel silicide; NiSi), cobalt silicide (cobalt silicide; CoSi), other suitable materials, or a combination of the aforementioned materials.

In some embodiments, the formation of the contact 800 may include a deposition process, a silicidation process (such as a rapid thermal processing (Rapid Thermal Processing, RTP)), a removal process (such as an etching process or a planarization process), and the like, and the related processes are similar to those described above. , which will not be repeated here.

As shown in FIG. 17 , a source electrode 900 and a passivation layer 1000 are formed on the contact 800 and the interlayer dielectric layer 700 . In some embodiments, the passivation layer 1000 is used to protect and isolate surface metals (such as source and gate metals) connected to external circuits.

In some embodiments, the source electrode 900 may comprise a conductive material comprising metal, metal alloy, etc., such as copper, silver, gold, aluminum, tungsten, aluminum copper, other suitable materials, or combinations thereof. In some embodiments, the source electrode 900 and the passivation layer 1000 can be formed respectively by a deposition process similar to the above, which will not be repeated here.

Next, referring to Fig. 18, it is a top view corresponding to the section line A-A' in Fig. 17 viewed from top to bottom. It can be seen from FIG. 18 that the sidewall doped region 510 of the first conductivity type and the sidewall doped region 520 of the second conductivity type extend continuously along two sides of the electrode structure 600 respectively. That is, both the sidewall doped region 510 and the sidewall doped region 520 extend along the direction Y.

19-32 are schematic diagrams according to other embodiments of the present invention.

Fig. 19 and Fig. 20 are a kind of aspect in some other embodiments, and both of them respectively depict the top view viewed from top to bottom and the top view from bottom to top. It should be noted that the top-down view refers to the viewing angle along the direction Z toward the substrate 100 ; the bottom-up viewing refers to the viewing angle along the direction Z from the substrate 100 .

FIG. 19 is similar to FIG. 18 , the difference is that there are sidewall doped regions of different conductivity types alternately arranged on both sides of the electrode structure 600 . Specifically, the sidewall doped region 5101 with the first conductivity type and the sidewall doped region 5201 with the second conductivity type respectively extend along both sides of the electrode structure 600 and are respectively connected to the sidewall doped regions with the second conductivity type. The region 5202 and the sidewall doped region 5102 of the first conductivity type. That is, the sidewall doped region 5101 is connected to the sidewall doped region 5202 ; the sidewall doped region 5201 is connected to the sidewall doped region 5102 . In FIG. 20, it can be seen that the bottom doped regions 5301 and 5302 of the second conductivity type extend along the direction Y and completely cover the electrode structure. Moreover, in FIG. 20 , the sidewall doped regions 5101 and 5102 of the first conductivity type do not overlap in the direction Y.

Fig. 21 and Fig. 22 are another form in some other embodiments, and both of them respectively depict the top view from top to bottom and bottom to top. Fig. 21 is similar to Fig. 19, the difference is that along one side of the electrode structure 600, a plurality of sidewall doped regions 5101 of the first conductivity type are interlaced with a plurality of sidewall doped regions 5202 of the second conductivity type Arrangement: Along the other side of the electrode structure 600 , a plurality of sidewall doped regions 5201 of the second conductivity type and sidewall doped regions 5102 of the first conductivity type are alternately arranged. That is, one sidewall doped region 5101 is connected to two sidewall doped regions 5202 along its Y direction (upper and lower directions in the drawing); one sidewall doped region 5201 is connected along its Y direction (upper and lower directions in the drawing) The two sidewall doped regions 5102 are connected. In FIG. 22, it can be seen that the bottom doped regions 5301 and 5302 of the second conductivity type are connected to each other, extend along the direction Y, and completely cover the electrode structure. Moreover, in FIG. 22 , the sidewall doped regions 5102 and 5101 of the first conductivity type do not overlap in the direction Y.

For the convenience of explaining the subsequent forming process, the enlarged schematic diagram of the box in FIG. 19 or FIG. 21 is shown as FIG. 23 . In FIG. 23 , the doped region 500 and the electrode structure 600 are divided into a first region R1 and a second region R2 along the extension direction (or direction Y) of the electrode structure 600 . That is, the first region R1 has sidewall doped regions 5101 and 5201 of the first conductivity type and the second conductivity type respectively; The sidewall doped regions 5102 and 5202 of the first conductivity type and the second conductivity type. In other words, in FIG. 23 , sidewall doped regions 5101 and 5201 with different conductivity types extend along two sides of the same electrode structure 600 . In FIG. 23 , the sidewall doped region 5101 is connected to the sidewall doped region 5202 ; the sidewall doped region 5201 is connected to the sidewall doped region 5102 .

Refer to Figures 24-32, which are schematic cross-sectional views at different stages for the section line A1-A1' (first region R1) and section line BB' (second region R2) corresponding to Fig. 23 . Additional operations may be provided before, during, and/or after the stages described in FIGS. 24-32. In various embodiments, some of the aforementioned operations may be moved, deleted or replaced. Additional components may be added to the semiconductor device. In various embodiments, some of the components described below may be removed, deleted or substituted.

It should be noted that, in this embodiment, in order to simplify the diagram, the structure of a single transistor (including a single electrode structure) will be shown later for description. Moreover, the structure of the first region R1 is similar to the embodiment shown in FIGS. 1-17 , so the description will focus on the structure of the second region R2 later.

Referring to Fig. 24, it is similar to Fig. 3, the difference is that in the second region R2, a mask M1 is set at an unintended doping position, and the well region 300 is fully ionized by an ion implantation process. implanted to form a first contact doped region 410 in the well region 300 not covered by the mask M1. Next, the mask M1 is removed. In the embodiment of FIG. 24 , the ion implantation includes dopants of the second conductivity type, ie, p-type dopants (such as aluminum), so the first contact doped region 410 has the second conductivity type.

Referring to FIG. 25, which is similar to FIG. 4, the difference is that in the second region R2, a mask M2 is set at a non-predetermined doping position (for example, directly above the first contact doping region 410), and Full-scale ion implantation is performed on the well region 300 by ion implantation, so as to form the second contact doped region 420 in the well region 300 not covered by M2. Next, the mask M2 is removed. In the embodiment of FIG. 25 , the ion implantation includes dopants of the first conductivity type, ie, n-type dopants (such as nitrogen), so the second contact doped region 420 has the first conductivity type.

Referring to FIG. 26 , which is similar to FIG. 5 , the difference is that: in the first region R1 and the second region R2 , trenches O are formed in the epitaxial layer 200 . It should be noted that although the cross-sectional view is divided into two cross-sectional views by the A1-A1' section line and the BB' section line, the trench O extends along the direction Y in the first region R1 and the second region R2 the same groove.

Referring to FIGS. 27-31, a doped region 500 is formed. As shown in FIG. 27, the photoresist P is overfilled in the trench O in the second region R2, and the first ion implantation im11 is performed on one side wall of the trench O in the first region R1 so that the first ion implantation im11 is performed in the first region R2. A sidewall doped region 5101 is formed in R1, and then the photoresist P in the second region R2 is removed. In some embodiments, the photoresist P can protect the underlying layer from further doping during the ion implantation, and is removed after the ion implantation is completed. In the embodiment shown in FIG. 27 , the first ion implantation im11 contains dopants of the first conductivity type, ie, n-type (such as nitrogen), so the sidewall doped region 5101 has the first conductivity type.

As shown in FIG. 28, the photoresist P is overfilled in the trench O in the first region R1, and another first ion implantation im12 is performed on one side wall of the trench O in the second region R2 so that in the second region R2 The sidewall doped region 5102 is formed in the second region R2, and then the photoresist P in the first region R1 is removed. In the embodiment of FIG. 28 , another first ion implantation im12 contains dopants of the first conductivity type, ie, n-type (eg, nitrogen), so the sidewall doped region 5102 has the first conductivity type.

As shown in FIG. 29, the photoresist P is overfilled in the trench O in the second region R2, and the second ion implantation im21 is performed on the other side wall of the trench O in the first region R1 so as to be in the first region R1. A sidewall doped region 5201 is formed in the region R1, and then the photoresist P in the second region R2 is removed. In the embodiment of FIG. 29 , the second ion implantation im21 contains dopants of the second conductivity type, ie, p-type (such as aluminum), so the sidewall doped region 5201 has the second conductivity type.

As shown in FIG. 30, the photoresist P is overfilled in the trench O in the first region R1, and another second ion implantation im22 is performed on the other side wall of the trench O in the second region R2 to The sidewall doped region 5202 is formed in the second region R2, and then the photoresist P in the first region R1 is removed. In an embodiment of the present invention, another second ion implantation im22 includes dopants of the second conductivity type, ie, p-type (such as aluminum), so the sidewall doped region 5202 has the second conductivity type.

As shown in FIG. 31, which is similar to FIG. 8, the third ion implantation im3 is performed on the bottom of the trench O in the first region R1 and the second region R2 at the same time so that in the first region R1 and the second region R2 Bottom doped regions 5301 and 5302 (or collectively referred to as 530 in FIG. 8 ) are formed. In the embodiment of FIG. 31 , the third ion implantation im3 includes dopants of the second conductivity type, ie, p-type (such as aluminum), so the bottom doped regions 5301 and 5302 have the second conductivity type. In some embodiments, the sidewall doped region 5102 is connected to the sidewall doped region 5202 through the bottom doped region 5302 .

It should be noted that although the embodiment of the present invention illustrates the formation of the doped region 500 in the order of FIGS. After the bottom doped region is formed in the third ion implantation process, the sidewall doped region in the first region R1 is formed, and finally the sidewall doped region in the second region R2 is formed.

As above, by forming sidewall doped regions of different conductivity types on one side of the trench (that is, the conductivity type of the sidewall doped regions in the second region is opposite to that of the sidewall doped regions in the first region), It can prevent the current from concentrating on the same side, prevent the temperature rise on one side, and effectively avoid the overheating (thermal runaway) of the parasitic bipolar junction transistor (BJT).

Next, referring to FIG. 32 , an electrode structure 600 , an interlayer dielectric layer 700 , a contact member 800 , a source electrode 900 , and a passivation layer 1000 are formed, which are similar to those described above, and thus will not be repeated here. In some embodiments, sidewall doped regions 5101 and 5201 are respectively provided on both sides of the electrode structure 600 in the first region R1 (section line A1-A1'), and in the second region R2 (section line BB'). Sidewall doped regions 5102 and 5202 are respectively provided on the sidewalls of both sides. That is, the doped region 500 of the first region R1 surrounds the electrode structure 600 of the first region R1, and the doped region 500 of the second region R2 surrounds the electrode structure 600 of the second region R2.

33-43 are schematic diagrams according to still other embodiments of the present invention.

Fig. 33 and Fig. 34 are still other embodiments, showing top views from top to bottom and bottom to top, respectively. Fig. 33 is similar to Fig. 19, the difference is that on one side of the electrode structure 600 there are sidewall doped regions of different conductivity types staggered, and on the other side of the electrode structure 600 there are sidewall doping regions of the same conductivity type extending continuously. district. In Fig. 34, it can be seen that the bottom doped region 5301 of the second conductivity type extends discontinuously along the direction Y and does not completely cover the electrode structure. That is, two bottom doped regions 5301 are spaced apart from each other.

To facilitate the description of the subsequent forming process, the enlarged schematic diagram of the box in FIG. 33 is shown in FIG. 35 . In FIG. 35 , the doped region is divided into a first region R1 and a third region R3 along the extension direction (or direction Y) of the electrode structure 600 . That is, the first region R1 has sidewall doped regions 5101 and 5201 of the first conductivity type and the second conductivity type respectively; the third region R3 has sidewall doped regions 5103 and 5203 of the second conductivity type. In other words, in FIG. 35 , sidewall doped regions with different conductivity types extend along one side of the same electrode structure 600 , and sidewall doped regions with the same conductivity type extend along the other side of the same electrode structure 600 . In FIG. 35 , the sidewall doped region 5101 is connected to the sidewall doped region 5103 . It should be noted that the boundary between the sidewall doped regions 5201 and 5203 with different conductivity types is divided into the first region R1 and the third region R3.

Refer to Figures 36-43, which are schematic cross-sectional views at different stages for the section line A2-A2' (first area R1) and section line CC' (second area R2) corresponding to Figure 35 . Additional operations may be provided before, during, and/or after the stages described in Figures 36-43. In various embodiments, some of the aforementioned operations may be moved, deleted or replaced. Additional components may be added to the semiconductor device. In various embodiments, some of the components described below may be removed, deleted or substituted.

It should be noted that in this embodiment, in order to simplify the diagram, the structure of a single transistor (including a single electrode structure) will be shown later for description. Moreover, the structure of the first region R1 is similar to the embodiment in FIGS. 1-17 (or the structure of the first region R1 in FIGS. 24-32 ), so the description will focus on the structure of the third region R3 later.

Referring to Fig. 36, it is similar to Fig. 3, and the difference is that in the third region R3, a mask M1 is set at non-predetermined doping positions (for example, the entire area of the third region R3) to avoid ion implantation The process is affected to the well region 300 of the third region R3. Next, the mask M1 is removed.

Referring to Fig. 37, it is similar to Fig. 4, and the difference is that the mask M2 is not set in the third region R3, and the well region 300 is fully ion-implanted by ion implantation, so that in the third region R3 A second contact doping region 420 is formed in the well region 300 of R3. In the embodiment of FIG. 37 , the ion implantation includes dopants of the first conductivity type, ie, n-type dopants (such as nitrogen), so the second contact doped region 420 has the first conductivity type. It should be noted that in the third region R3, the doped contact region 400 only includes the second doped contact region 420 of the first conductivity type.

Referring to FIG. 38 , which is similar to FIG. 5 , the difference is that: in the first region R1 and the third region R3 , trenches O are formed in the epitaxial layer 200 . It should be noted that although the cross-sectional view is divided into two cross-sectional views by the A2-A2' line and the CC' line, the groove O extends along the Y direction in the first region R1 and the third region R3 the same groove.

Referring to FIGS. 39-42, a doped region 500 is formed. As shown in FIG. 39, the first ion implantation im1 is performed on one side wall of the trench O in the first region R1 and the third region R3 at the same time to form sidewall doping in the first region R1 and the third region R3 respectively. Districts 5101 and 5103. In the embodiment of FIG. 39, ion implantation im1 comprises The dopant of one conductivity type is n-type (such as nitrogen), so the sidewall doped regions 5101 and 5103 both have the first conductivity type.

As shown in FIG. 40, the photoresist P is overfilled in the trench O in the first region R1, and the second ion implantation im22 is performed on the other side wall of the trench O in the third region R3 so that the second ion implantation im22 is performed in the third region R1. A sidewall doped region 5203 is formed in R3, and then the photoresist P in the first region R1 is removed. In the embodiment of FIG. 40 , the second ion implantation im22 contains dopants of the first conductivity type, ie, n-type (for example, nitrogen), so the sidewall doped region 5203 has the first conductivity type.

As shown in FIG. 41, the photoresist P is overfilled in the trench O in the third region R3, and another second ion implantation im21 is performed on the other side wall of the trench O in the first region R1 so as to be in the first region R3. A sidewall doped region 5201 is formed in the region R1. In the embodiment of FIG. 41 , another second ion implantation im21 includes dopants of the second conductivity type, ie, p-type (such as aluminum), so the sidewall doped region 5201 has the second conductivity type.

As shown in FIG. 42, while maintaining the photoresist P in the trench O in the third region R3 in FIG. 41, a third ion implantation im3 is performed on the bottom of the trench O in the first region R1 to A bottom doped region 5301 is formed in the first region R1, and then the photoresist P in the third region R3 is removed. In the embodiment of FIG. 42, the third ion implantation im3 contains dopants of the second conductivity type, ie, p-type (such as aluminum), so the bottom doped region 5301 has the second conductivity type.

It should be noted that although the embodiment of the present invention illustrates the formation of the doped region 500 in the order of FIGS. The third ion cloth After forming the bottom doped region in the implant process, the sidewall doped region in the first region R1 is formed, and finally the sidewall doped region in the third region R3 is formed.

Based on the above, by forming continuously extending sidewall doped regions of the first conductivity type on one side of the trench O and forming sidewall doped regions of the first conductivity type and the second conductivity type alternately arranged on the other side , can increase the channel area, thereby reducing the channel resistance and reducing the switch resistance. Moreover, the surface electric field at the corner of the bottom can be effectively reduced by the discontinuously extending bottom doped region.

Next, referring to FIG. 43 , an electrode structure 600 , an interlayer dielectric layer 700 , a contact member 800 , a source electrode 900 , and a passivation layer 1000 are formed, which are similar to those described above, so details are omitted. In the embodiment of FIG. 43 , in the third region R3 , the bottom of the electrode structure 600 directly contacts the epitaxial layer 200 . In some embodiments, sidewall doped regions 5101 and 5201 are respectively provided on both sides of the electrode structure 600 in the first region R1 (cross-section line A2-A2'), and in the third region R3 (cross-section line CC'). Sidewall doped regions 5103 and 5203 are respectively provided on the sidewalls of both sides. That is, the doped region 500 of the first region R1 surrounds the electrode structure 600 of the first region R1, and the doped region 500 of the third region R3 surrounds the electrode structure 600 of the third region R3.

In summary, the embodiments of the present invention can reduce the surface electric field and reduce the on-resistance (Rdson) by using the doped regions on both side walls of the electrode structure to have different conductivity types. In the embodiment of the present invention, the electric field can be reduced and the breakdown voltage can be increased by the bottom doped region covering the bottom of the electrode structure. In the embodiment of the present invention, by separating the trench electrode structure, the contact area between the gate electrode and the drift region can be further reduced, and the gate-to-drain capacitance (Cgd) can be reduced more effectively.

In addition, in the embodiment of the present invention, the sidewall doped regions of the first conductivity type (or the second conductivity type) are evenly distributed on both sides of the electrode structure, which can avoid current concentration on the same side and prevent overheating. In addition, in the embodiment of the present invention, the sidewall doped regions of the first conductivity type are continuously arranged on one side of the electrode structure, and the sidewall doped regions of the second conductivity type and the first conductivity type are arranged alternately on the other side of the electrode structure. On one side, the channel resistance can be reduced. Moreover, the surface electric field is more effectively reduced by the discontinuous bottom doped regions.

The protection scope of the present disclosure is not limited to the process, machine, manufacture, material composition, device, method and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the technical field can learn from some embodiments of the present disclosure In the content of the disclosure, it is understood that the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps can be used in accordance with this disclosure as long as they can perform substantially the same functions or obtain substantially the same results in the embodiments described here. Some examples use . Therefore, the protection scope of the present disclosure includes the aforementioned process, machine, manufacture, composition of matter, device, method and steps. In addition, each patent application scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes combinations of various patent application scopes and embodiments.

Several embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art should understand that they can design or modify other processes and structures based on the disclosed embodiments, so as to achieve the same purpose and/or advantages as the disclosed embodiments. Those with ordinary knowledge in the technical field should also understand that such equivalent processes and structures do not deviate from the spirit and scope of this disclosure, and they can be made in various ways without departing from the spirit and scope of this disclosure. Various changes, substitutions and substitutions.

100: Substrate 200: epitaxial layer 300: well area 400: contact doped area 410, 410': first contact doped region 420, 420': second contact doped region 500: doped area 510,520: sidewall doped region 5101, 5102, 5103, 5201, 5202, 5203: side wall doped regions 530: bottom doped region 5301,5302: bottom doped region 600: electrode structure 610,610': masking dielectric layer 620: bottom electrode 630: dielectric layer 640: insulation part 650: top electrode 700,700': interlayer dielectric layer 800: contact piece 900: source electrode 1000: passivation layer im1: first ion implantation im2: Second ion implantation im11, im12: (another) first ion implantation im21, im22: (another) second ion implantation im3: the third ion implantation A-A', A1-A1', A2-A2', B-B', C-C': broken line M1,M2,M3: mask H: contact hole O: Groove P: photoresist R1: Region 1 R2: second area R3: the third area X, Y, Z: direction

The viewpoints of the embodiments of the present disclosure can be better understood through the following detailed description combined with the accompanying drawings. It is worth noting that, in accordance with the standard practice in the industry, some features may not be drawn to scale. In fact, the dimensions of the various components may have been increased or decreased for clarity of discussion. 1-17 are schematic cross-sectional views illustrating different stages of forming a semiconductor device according to some embodiments of the present invention. FIG. 18 is a top view showing some components of a semiconductor device viewed from top to bottom according to some embodiments of the present invention. FIG. 19 is a top view showing some components of a semiconductor device viewed from top to bottom according to another aspect of some embodiments of the present invention. FIG. 20 is a top view of some components of a semiconductor device viewed from bottom to top according to another aspect of some embodiments of the present invention. FIG. 21 is a top view of some components of a semiconductor device viewed from top to bottom according to another aspect of some other embodiments of the present invention. FIG. 22 is a top view showing some components of a semiconductor device viewed from bottom to top according to another aspect of some other embodiments of the present invention. Fig. 23 is an enlarged schematic view of the box in Fig. 19 or Fig. 21. 24-32 are schematic cross-sectional views illustrating different stages of forming a semiconductor device according to other embodiments of the present invention. FIG. 33 is a top view showing some components of a semiconductor device viewed from top to bottom according to still other embodiments of the present invention. FIG. 34 is a bottom-up top view showing some components of a semiconductor device according to still other embodiments of the present invention. FIG. 35 is an enlarged schematic view of the box in FIG. 33 . 36-43 are schematic cross-sectional views illustrating different stages of forming a semiconductor device according to still other embodiments of the present invention.

100: Substrate

200: epitaxial layer

300: well area

400: contact doped area

410': first contact doped region

420': second contact doped region

500: doped area

510,520: sidewall doped region

530: bottom doped region

600: electrode structure

610': masking dielectric layer

620: bottom electrode

630: dielectric layer

640: insulation part

650: top electrode

X, Y, Z: direction

Claims (20)

A semiconductor device, comprising: a substrate having a first conductivity type; an epitaxial layer having the first conductivity type disposed on the substrate; an electrode structure disposed in the epitaxial layer, wherein the electrode structure extending along a first direction; a first sidewall doped region having a first conductivity type and disposed on one side of the electrode structure; a second sidewall doping region having a first conductivity type different from the first a second conductivity type and disposed on the other side of the electrode structure; and a bottom doped region having the second conductivity type and disposed under the electrode structure, wherein the second sidewall doped region is connected to the bottom doped region . The semiconductor device according to claim 1, wherein the electrode structure includes an insulating portion and a top electrode and a bottom electrode separated by the insulating portion. The semiconductor device according to claim 1, wherein the second sidewall doped region covers the entire sidewall of the bottom electrode. The semiconductor device according to claim 1, further comprising: another electrode structure disposed beside the electrode structure and in a second direction, wherein the first direction is perpendicular to the second direction, wherein the another electrode structure separated from the electrode structure by the epitaxial layer; another first sidewall doped region having the first conductivity type and disposed on one side of the other electrode structure; another second sidewall doped region having the second conductivity type and disposed on the other side of the other electrode structure; and another bottom doped region having the second conductivity type disposed on the other side Under the electrode structure, wherein the other second sidewall doped region is connected to the other bottom doped region, wherein the first sidewall doped region of the electrode structure, the other second sidewall doped region of the other electrode structure The impurity region and the epitaxial layer disposed between the first sidewall doped region and the other second sidewall doped region are a superjunction. The semiconductor device according to claim 1, wherein the electrode structure is divided into a first region and a second region along the first direction, wherein the first sidewall doped region and the second sidewall doped region are disposed on the second sidewall doped region In a region, wherein the semiconductor device further includes: a third sidewall doped region disposed on one side of the electrode structure in the second region; and a fourth sidewall doped region disposed in the second region the other side of the electrode structure. The semiconductor device according to claim 5, wherein the third sidewall doped region and the fourth sidewall doped region have the first conductivity type and the second conductivity type respectively, wherein the semiconductor device further comprises: another bottom doped The impurity region has the second conductivity type and is disposed under the electrode structure in the second region, wherein the fourth sidewall doped region is connected to the other bottom doped region. The semiconductor device according to claim 6, wherein the bottom doped region is connected to the other bottom doped region. The semiconductor device according to claim 5, wherein both the third sidewall doped region and the fourth sidewall doped region have the first conductivity type, wherein in the second region, the bottom of the electrode structure directly contacts the epitaxy layer. The semiconductor device according to claim 1, further comprising: a well region disposed on one side of the electrode structure and having the second conductivity type; and a doped contact region disposed in the well region; wherein the first The sidewall doped region is separated from the contact doped region by the well region; wherein the second sidewall doped region contacts the contact doped region through the well region. The semiconductor device according to claim 9, wherein the contact doped region includes a first contact doped region and a second contact doped region adjacent to each other, wherein the first contact doped region and the second contact doped region The two contact doped regions respectively have the first conductivity type and the second conductivity type, wherein the second sidewall doped region is in contact with the second contact doped region. A method for forming a semiconductor device, comprising: providing a substrate, wherein the substrate has a first conductivity type; forming an epitaxial layer on the substrate, wherein the epitaxial layer has the first conductivity type; along a first A groove is formed in the epitaxial layer in a direction; forming a doped region to surround the groove, wherein forming the doped region includes: performing a first first on both sides of the groove in a non-perpendicular manner to the substrate ion implantation and a second ion implantation to form a first sidewall doped region and a second sidewall a sidewall doped region, wherein the first sidewall doped region and the second sidewall doped region respectively have the first conductivity type and a second conductivity type different from the first conductivity type; and An electrode structure is formed in the groove. The method for forming a semiconductor device according to claim 11, wherein performing the first ion implantation includes not performing ion implantation on the bottom of the trench. The method for forming a semiconductor device according to claim 11 further includes: performing a third ion implantation on the bottom of the trench to form a bottom doped region, wherein the bottom doped region has the second conductivity type. The method for forming a semiconductor device as claimed in claim 13, further comprising: while forming the trench, forming another trench in the epitaxial layer in a second direction of the trench, wherein the second direction is perpendicular to the first direction; While forming the doped region, forming another doped region surrounding the other trench, wherein the another doped region is separated from the doped region by the epitaxial layer; and While forming the electrode structure, another electrode structure is formed in the other groove along the second direction of the electrode structure. The method for forming a semiconductor device according to claim 11, wherein the trench is divided into a first region and a second region along the first direction, wherein the doped region is formed in the first region, and the forming method Also includes: Another doped region is formed in the second region to surround the trench. The method for forming a semiconductor device according to claim 15, wherein forming the other doped region in the second region comprises: overfilling a photoresist in the trench in the first region; Performing a third ion implantation and a fourth ion implantation on both sides of the trench in the second region respectively to form a third sidewall doped region and a fourth sidewall doped region with different conductivity types. heterogeneous area; remove the photoresist. The method for forming a semiconductor device according to claim 16, wherein forming the doped region further includes: before performing the first ion implantation and the second ion implantation, overfilling another photoresist in the second region in the trench; and after performing the first ion implantation and the second ion implantation, removing the other photoresist. The method for forming a semiconductor device according to claim 15, wherein forming the doped region in the first region and forming the other doped region in the second region further includes: simultaneously forming the doped region in the first region and the second region A third ion implantation is performed on the bottom of the trench to form a bottom doped region, wherein the bottom doped region has the second conductivity type. The method for forming a semiconductor device according to claim 15, wherein forming the doped region in the first region and forming the other doped region in the second region comprises: simultaneously performing the operations on the first region and the second region performing the first ion implantation on one side wall of the trench to form the first side wall doped region and a third side wall doped region in the first region and the second region respectively; overfilling a photoresist in the In the trench in the first region; performing a third ion implantation on the other side of the trench in the second region to form a fourth sidewall doped region in the second region; removing the photoresist; overfilling another photoresist in the trench in the second region; performing the second ion implantation on the other side wall of the trench in the first region, so that the first forming the second sidewall doped region; and removing the other photoresist. The method for forming a semiconductor device according to claim 19, wherein forming the doped region in the first region and forming the other doped region in the second region further includes: overfilling the trench in the second region In the case of photoresist, a fourth ion implantation is performed on the bottom of the trench in the first region to form a bottom doped region, wherein the bottom doped region has the second conductivity type.

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