CN112928025A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112928025A
CN112928025A CN201911244623.2A CN201911244623A CN112928025A CN 112928025 A CN112928025 A CN 112928025A CN 201911244623 A CN201911244623 A CN 201911244623A CN 112928025 A CN112928025 A CN 112928025A
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layer
work function
forming
region
side wall
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CN112928025B (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein a source drain doping layer is arranged on the substrate; forming a channel column on the source-drain doping layer, wherein the channel column comprises a first region and a second region positioned on the first region; forming a first work function layer on the surface of the side wall of the first region or the surface of the side wall of the second region; a gate layer is formed on the trench pillar sidewall surface and the first work function layer surface. The performance of the formed semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall of the Fin portion, and source-drain doped regions in the Fin portion located at both sides of the gate structure. Compared with a planar metal-oxide semiconductor field effect transistor, the fin type field effect transistor has stronger short channel inhibition capability and stronger working current.
With the further development of semiconductor technology, the size of integrated circuit devices is smaller and smaller, and the conventional fin field effect transistor has a limitation in further increasing the operating current. Specifically, only the region near the top surface and the sidewall in the fin is used as a channel region, so that the volume of the fin used as the channel region is small, which limits the increase of the operating current of the finfet. Therefore, a gate-all-around (GAA) structure fin field effect transistor is proposed, so that the volume of the fin field effect transistor used as a channel region is increased, and the working current of the gate-all-around structure fin field effect transistor is further increased.
However, the performance of the prior art finfet with a trench gate wrap-around structure is still to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of a channel gate surrounding structure fin field effect transistor.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a source drain doping layer is arranged on the substrate; forming a channel column on the source-drain doping layer, wherein the channel column comprises a first region and a second region positioned on the first region; forming a first work function layer on the surface of the side wall of the first region or the surface of the side wall of the second region; a gate layer is formed on the trench pillar sidewall surface and the first work function layer surface.
Optionally, the first work function layer is located on the surface of the sidewall of the second region.
Optionally, the method for forming the first work function layer includes: forming a first sacrificial layer on the surface of the source drain doped layer and the surface of the side wall of the first region; forming a first work function layer on the surface of the side wall of the second area; and removing the first sacrificial layer after the first work function layer is formed.
Optionally, the method for forming the gate layer includes: after removing the first sacrificial layer, forming a gate material layer on the surface of the side wall of the first work function layer and the surface of the side wall of the first region; forming a patterned layer on the gate material layer; and etching the grid electrode material layer by taking the patterning layer as a mask until the surface of the substrate is exposed to form the grid electrode layer, wherein part of the grid electrode layer also extends to the surface of the substrate at one side of the channel column.
Optionally, the first work function layer is located on the surface of the first region sidewall.
Optionally, the method for forming the first work function layer includes: forming a first work function material layer on the side wall surface of the first region and the side wall surface of the second region; forming a second sacrificial layer on the surface of the side wall of the first area, wherein the first work function material layer on the surface of the second area is exposed by the second sacrificial layer; removing the first work function material layer on the surface of the side wall of the second area, and forming a first work function layer on the surface of the side wall of the first area; and removing the second sacrificial layer after the first work function layer is formed.
Optionally, the method for forming the gate layer includes: after removing the second sacrificial layer, forming a gate material layer on the surface of the side wall of the first work function layer and the surface of the side wall of the second area; forming a patterned layer on the gate material layer; and etching the grid electrode material layer by taking the patterning layer as a mask until the surface of the substrate is exposed to form the grid electrode layer, wherein part of the grid electrode layer also extends to the surface of the substrate at one side of the channel column.
Optionally, before forming the first work function layer on the sidewall surface of the first region or the sidewall surface of the second region, the method further includes: and forming a second work function layer on the surface of the side wall of the channel pillar.
Optionally, the material of the first work function layer and the material of the second work function layer are both P-type work function materials or N-type work function materials; the P-type work function material comprises titanium nitride or tantalum nitride; the N-type work function material comprises titanium aluminum.
Optionally, the material of the first work function layer and the material of the second work function layer are a P-type work function material and an N-type work function material; the P-type work function material comprises titanium nitride or tantalum nitride; the N-type work function material comprises titanium aluminum.
Optionally, after forming the channel pillar, the method further includes: forming an interface layer and a gate dielectric layer positioned on the interface layer on the surface of the side wall of the channel column; the second work function layer is positioned on the surface of the gate dielectric layer.
Optionally, after forming the channel pillar and before forming the interface layer, the method further includes: and forming an isolation layer on the surface of the source-drain doping layer, wherein the isolation layer is positioned on the surface of the side wall of the trench column part, and the top surface of the isolation layer is lower than that of the trench column.
Optionally, after forming the gate layer, forming a dielectric layer on the substrate, wherein the channel pillar is located in the dielectric layer; and forming a first conductive plug, a second conductive plug and a third conductive plug in the dielectric layer, wherein the first conductive plug is electrically connected with the grid layer, the second conductive plug is electrically connected with the top of the channel column, and the third conductive plug is electrically connected with the source-drain doping layer.
Correspondingly, the technical solution of the present invention further provides a semiconductor structure formed by any one of the above methods, including: the semiconductor device comprises a substrate, a source-drain doping layer and a source-drain doping layer, wherein the substrate is provided with the source-drain doping layer; the channel column is positioned on the source-drain doped layer and comprises a first region and a second region positioned on the first region; the first work function layer is positioned on the surface of the side wall of the first region or the surface of the side wall of the second region; and a gate layer located on the sidewall surface of the channel pillar and the surface of the first work function layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the forming method in the technical scheme of the invention, the channel column comprises a first region and a second region positioned on the first region, and the first work function layer is formed on the surface of the side wall of the first region or the surface of the side wall of the second region. The first work function layer can adjust the driving current in the channel column to be in a relatively balanced state, and the condition that the performance of the semiconductor structure is unstable due to the fact that the driving current in the channel column is not balanced is avoided.
Furthermore, the material of the first work function layer and the material of the second work function layer are both P-type work function materials or N-type work function materials, and the first work function layer enables the threshold voltage of the semiconductor structure to be reduced, so that the semiconductor structure has high driving current, and the reaction speed of the semiconductor structure is high.
Furthermore, the material of the first work function layer and the material of the second work function layer are a P-type work function material and an N-type work function material, and the first work function layer raises the threshold voltage of the semiconductor structure, so that the semiconductor structure has a smaller driving current, thereby avoiding the occurrence of electric leakage.
Drawings
FIG. 1 is a schematic cross-sectional view of a vertical nanowire transistor in one embodiment;
FIGS. 2-9 are cross-sectional structural diagrams illustrating a semiconductor structure formation process according to an embodiment of the present invention;
fig. 10 to 13 are schematic cross-sectional views illustrating a semiconductor structure forming process according to another embodiment of the present invention.
Detailed Description
As described in the background, the performance of the conventional trench gate surrounding finfet is desired to be improved. The analysis will now be described with reference to specific examples.
FIG. 1 is a cross-sectional view of a vertical nanowire transistor in an embodiment.
Please refer to fig. 1, which includes: a substrate 100; a source-drain doping layer 101 located on the substrate 100; a channel pillar 102 on the source-drain doping layer 101; the isolation layer 103 is positioned on the surface of the source-drain doping layer 101 and on partial side wall of the channel column 102, and the top surface of the isolation layer 103 is lower than that of the channel column 102; the gate structure is positioned on the side wall of the channel column 102 and comprises an interface layer 104, a gate dielectric layer 105 positioned on the interface layer 104, a work function layer 106 positioned on the gate dielectric layer 105 and a gate layer 107 positioned on the work function layer 106, and part of the gate structure is also positioned on the surface of the isolation layer 103 on one side of the channel column 102; a dielectric layer 108 on the substrate, the gate structure being located within the dielectric layer 108; the first conductive structure 109 is electrically connected with the gate layer 107 on the surface of the isolation layer 103 on one side of the channel column 102, the second conductive structure 110 is electrically connected with the top of the channel column 102, and the third conductive structure 111 is electrically connected with the source-drain doped layer 101.
In the vertical nanowire transistor, the channel pillar 102 is a channel of the vertical nanowire transistor, and a driving current of the vertical nanowire transistor flows in a vertical direction of the channel pillar 102. In the channel region of the vertical nanowire transistor, the driving current in the channel column 102 is differentiated in the vertical direction due to an electrical or process influence. The driving current is small, so that the reaction speed of the vertical nanowire transistor is low; the driving current is large, so that the vertical nanowire transistor is easy to leak electricity. The unbalanced drive current results in unstable performance of the vertical nanowire transistor.
In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, in which different work function layers are formed at different positions of a channel pillar in a vertical direction, so as to solve the problem of overall difference of driving currents in a channel, thereby improving the performance of the vertical nanowire transistor.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 2 to 9 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 2, a substrate 200 is provided, wherein the substrate 200 has a source-drain doping layer 201 thereon.
The source-drain doping layer 201 has doping ions therein. The type of the doped ions is N type or P type; the N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include boron ions or indium ions.
In this embodiment, the forming process of the source-drain doping layer 201 includes an ion implantation process. In other embodiments, the forming process of the source-drain doping layer includes an in-situ doping process.
In this embodiment, the material of the substrate 200 is monocrystalline silicon; in other embodiments, the substrate may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide, or silicon-on-insulator.
Referring to fig. 3, a channel pillar 202 is formed on the source-drain doped layer 201, where the channel pillar 202 includes a first region I and a second region II located on the first region I.
The method for forming the channel column 202 comprises the following steps: forming a channel material layer (not shown) on the substrate 200; forming a patterned mask layer (not shown) on the surface of the channel material layer, wherein the patterned mask layer exposes a part of the surface of the channel material layer; and etching the channel material layer by taking the patterned mask layer as a mask until the surface of the source-drain doping layer 201 is exposed, and forming the channel column 202 on the source-drain doping layer 201.
In the present embodiment, the material of the channel pillar 202 includes silicon. In other embodiments, the material of the channel pillar includes a semiconductor material such as germanium, silicon germanium, gallium arsenide, or the like.
The process for etching the channel material layer comprises a dry etching process or a wet etching process; the process for forming the channel material layer comprises a physical vapor deposition process, an epitaxial growth process or an atomic layer deposition process.
In this embodiment, the process of etching the channel material layer includes a dry etching process, and the dry etching process can form a channel pillar 202 with a good sidewall profile; the process for forming the channel material layer comprises a physical vapor deposition process, and the physical vapor deposition process can form the channel material layer with a compact structure and a thicker thickness.
In this embodiment, the material of the patterned mask layer includes a photoresist; the process for forming the patterned mask layer includes a spin-on process.
In other embodiments, the patterned mask layer includes a hard mask layer and a photoresist layer on the hard mask layer, and the material of the hard mask layer includes silicon oxide or silicon nitride.
After the channel pillar 202 is formed, the patterned mask layer is removed. In this embodiment, the process of removing the patterned mask layer includes an ashing process.
With reference to fig. 3, an isolation layer 203 is formed on the surface of the source/drain doped layer 201, wherein the isolation layer 203 is located on the sidewall surface of the first region I of the channel pillar 202, and the top surface of the isolation layer 203 is lower than the top surface of the channel pillar 202.
The isolation layer 203 is used to electrically isolate the device.
The forming method of the isolation layer 203 comprises the following steps: forming a layer of isolating material (not shown) on the substrate 200; and etching back the isolation material layer to form the isolation layer 203.
The material of the isolation layer 203 comprises silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride; the process for forming the isolating material layer comprises a chemical vapor deposition process or an atomic layer deposition process.
In the present embodiment, the material of the isolation layer 203 includes silicon oxide; the process for forming the isolating material layer comprises a chemical vapor deposition process, and the chemical vapor deposition process can form the isolating material layer with a compact structure and a thicker thickness.
Referring to fig. 4, an interfacial layer 204 and a gate dielectric layer 205 on the interfacial layer 204 are formed on the sidewall surface of the trench pillar 202.
The material of the interfacial layer 204 includes silicon oxide. The process of forming the interfacial layer 204 may include an in-situ moisture generation process, an atomic layer deposition process, or a chemical vapor deposition process. In this embodiment, the process of forming the interface layer 204 includes an in-situ moisture generation process, which can form the interface layer 204 with a dense structure and a thin thickness on the surface of the channel pillar 202.
The material of the gate dielectric layer 205 includes a high-K (greater than 3.9) dielectric material, which includes hafnium oxide or aluminum oxide. The process for forming the gate dielectric layer 205 includes an atomic layer deposition process or a chemical vapor deposition process. In this embodiment, the process of forming the gate dielectric layer 205 includes an atomic layer deposition process, and the atomic layer deposition process can form the gate dielectric layer 205 with a dense structure and a thin thickness.
The gate dielectric layer 205 has a higher dielectric constant and the channel pillar 202 has a lower dielectric constant. The interfacial layer 204 is used to transition the interface between the gate dielectric layer 205 and the channel pillar 202.
Referring to fig. 5, a second work function material layer 206 is formed on the sidewall surface of the channel pillar 202.
The second work function material layer 206 provides a material layer for a subsequent formation of a second work function layer on the sidewall surface of the channel pillar 202.
The material of the second work function material layer 206 comprises a P-type work function material or an N-type work function material; the P-type work function material comprises titanium nitride or tantalum nitride; the N-type work function material comprises titanium aluminum.
The process of forming the second work-function material layer 206 includes an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process. In this embodiment, the process of forming the second work function material layer 206 includes an atomic layer deposition process, which can form the second work function material layer 206 with a thin thickness and a dense structure.
And then, forming a first work function layer on the surface of the side wall of the second area II. Please refer to fig. 6 and fig. 7 for a specific process of forming the first work function layer.
In another embodiment, a first work function layer is formed on the surface of the sidewall of the first region I.
Referring to fig. 6, a first sacrificial layer 207 is formed on the surface of the second work function material layer 206 and the surface of the first region I sidewall.
The first sacrificial layer 207 is used to protect the first I-sidewall surface, so as to prevent a subsequently formed first work function from being located on the first I-sidewall surface, thereby deviating from the design rule of the device structure, so that the performance of the device is affected.
The method for forming the first sacrificial layer 207 includes: forming a sacrificial material layer (not shown) on the surface of the substrate 200; and etching back the sacrificial material layer until the surface of the second work function material layer 206 on the side wall surface of the second region II is completely exposed, and forming a first sacrificial layer 207 on the side wall surface of the first region I.
The material of the first sacrificial layer 207 includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. The process of forming the sacrificial material layer includes a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the material of the first sacrificial layer 207 includes silicon oxide; the process for forming the sacrificial material layer comprises a chemical vapor deposition process, and the chemical vapor deposition process can quickly form the sacrificial material layer with thicker thickness and dense structure.
Referring to fig. 7, a first work function layer 208 is formed on the sidewall surface of the second region II.
In the present embodiment, the material of the first work function layer 208 and the material of the second work function material layer 206 are both P-type work function material or N-type work function material; the P-type work function material comprises titanium nitride or tantalum nitride; the N-type work function material comprises titanium aluminum.
The method of forming the first work function layer 208 includes: forming a first work function material layer (not shown) on the surface of the first sacrificial layer 207 and the top surface and sidewall surface of the second region II; and etching back the first work function material layer until the surface of the first sacrificial layer 207 is exposed, and forming a first work function layer 208 on the surface of the side wall of the second region II.
The process for forming the first work function material layer comprises an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process. In this embodiment, the process of forming the first work function material layer includes an atomic layer deposition process, and the atomic layer deposition process can form the first work function material layer with a thin thickness and a dense structure.
When the semiconductor structure is a P-type device, the material of the first work function layer 208 and the material of the second work function layer are both P-type work function materials, and the first work function layer 208 on the sidewall surface of the second region II lowers the threshold voltage of the semiconductor structure, so that the semiconductor structure has a higher driving current, and the reaction speed of the semiconductor structure is faster.
When the semiconductor structure is an N-type device, the material of the first work function layer 208 and the material of the second work function layer are both N-type work function materials, and the first work function layer 208 on the sidewall surface of the second region II lowers the threshold voltage of the semiconductor structure, so that the semiconductor structure has a higher driving current, and the reaction speed of the semiconductor structure is faster.
In another embodiment, the material of the first work function layer and the material of the second work function layer are a P-type work function material and an N-type work function material; the P-type work function material comprises titanium nitride or tantalum nitride; the N-type work function material comprises titanium aluminum.
When the semiconductor structure is a P-type device, the first work function layer is made of an N-type work function material, the second work function layer is made of a P-type work function material, and the first work function layer on the side wall surface of the second region II raises the threshold voltage of the semiconductor structure, so that the semiconductor structure has a smaller driving current to avoid the occurrence of electric leakage.
When the semiconductor structure is an N-type device, the first work function layer is made of a P-type work function material, the second work function layer is made of an N-type work function material, and the first work function layer on the side wall surface of the second region II raises the threshold voltage of the semiconductor structure, so that the semiconductor structure has a smaller driving current to avoid the occurrence of electric leakage.
Referring to fig. 8, the first sacrificial layer 207 is removed; after removing the first sacrificial layer 207, a gate layer 209 is formed on the sidewall surface of the channel pillar 202 and the surface of the first work function layer 208.
The process of removing the first sacrificial layer 207 includes an isotropic wet etching process or an isotropic dry etching process. In this embodiment, the process of removing the first sacrificial layer 207 includes an isotropic wet etching process. The isotropic wet etching process can remove the first sacrificial layer 207, so as to prevent the first sacrificial layer 207 from remaining on the surface of the second work function material layer 206, and influence the electrical performance of the semiconductor structure after a gate layer is formed on the sidewall surface of the channel column 202.
The forming method of the gate layer 209 comprises the following steps: forming a gate material layer (not shown) on the sidewall surface of the first work function layer 208 and the sidewall surface of the first region I; forming a patterned layer (not shown) on the gate material layer; and etching the gate material layer and the second work function material layer 206 by using the patterned layer as a mask until the surface of the gate dielectric layer 205 is exposed, forming the gate layer 209 and the second work function layer 306 on the sidewall of the channel column 202, and extending part of the gate layer 209 to the surface of the substrate 200 on one side of the channel column 202.
The material of the gate layer 209 comprises a metal, and the metal comprises copper, tungsten or aluminum; the process for forming the grid material layer comprises a physical vapor deposition process or an electroplating process; the process of etching the gate material layer and the second work function material layer 206 includes a dry etching process or a wet etching process.
In this embodiment, the material of the gate layer 209 includes tungsten; the process for forming the gate material layer comprises a physical vapor deposition process; the process of etching the gate material layer and the second work function material layer 206 includes a dry etching process, and the dry etching process can form the gate layer 209 and the second work function layer 306 with good sidewall morphology.
Referring to fig. 9, after forming the gate layer 209, a dielectric layer 210 is formed on the substrate 200, and the channel pillar 202 is located in the dielectric layer 210; forming a first conductive plug 211, a second conductive plug 212 and a third conductive plug 213 in the dielectric layer 210, wherein the first conductive plug 211 is electrically connected with the gate layer 209, the second conductive plug 212 is electrically connected with the top of the channel column 202, and the third conductive plug 213 is electrically connected with the source-drain doping layer 201.
The forming method of the dielectric layer 210 comprises the following steps: forming a dielectric material layer (not shown) on the substrate 200, the dielectric material layer covering the top surface of the channel pillar 202; and flattening the dielectric material layer to form the dielectric layer 210.
The material of the dielectric layer 210 includes silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride; the process for forming the dielectric material layer comprises a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the material of the dielectric layer 210 includes silicon oxide; the process for forming the dielectric material layer comprises a chemical vapor deposition process, and the chemical vapor deposition process can quickly form the dielectric material layer with thicker thickness and dense structure.
The material of the first conductive plug 211, the second conductive plug 212, and the third conductive plug 213 includes a metal including one or a combination of copper, tungsten, aluminum, and titanium nitride.
Thus, the first work function layer 208 is formed on the sidewall surface of the second region II in the formed semiconductor structure. The first work function layer 208 can adjust the driving current in the channel pillar 202 to a relatively balanced state, thereby avoiding unstable performance of the semiconductor structure caused by unbalanced driving current in the channel pillar 202.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 9, including:
the semiconductor device comprises a substrate 200, wherein a source-drain doping layer 201 is arranged on the substrate 200;
the channel pillar 202 is positioned on the source-drain doping layer 201, and the channel pillar 202 comprises a first region I and a second region II positioned on the first region I;
the isolation layer 203 is positioned on the source-drain doping layer 201, and the isolation layer 203 is also positioned on the surface of part of the side wall of the first region I;
the interface layer 204 is positioned on the surface of the side wall of the channel column 202, the gate dielectric layer 205 is positioned on the surface of the interface layer 204, and the second work function layer 306 is positioned on the surface of the gate dielectric layer 205;
a first work function layer 208 located on a sidewall surface of the second region II, wherein the first work function layer 208 is located on a surface of the second work function layer 306;
a gate layer 209 on the sidewall surface of the channel pillar 202 and the surface of the first work function layer 208;
a dielectric layer 210 located on the substrate 200;
the first conductive plug 211, the second conductive plug 212 and the third conductive plug 213 are located in the dielectric layer 210, the first conductive plug 211 is electrically connected with the gate layer 209, the second conductive plug 212 is electrically connected with the top of the channel column 202, and the third conductive plug 213 is electrically connected with the source-drain doping layer 201.
Fig. 10 to 13 are schematic cross-sectional views illustrating a semiconductor structure forming process according to another embodiment of the present invention.
In this embodiment, the first work function layer is located on the surface of the first I-side wall.
Referring to fig. 10, fig. 10 is a schematic cross-sectional view based on fig. 5, after forming the second work function material layer 206, a first work function material layer 307 is formed on the sidewall surface of the first region I and the sidewall surface of the second region II.
The first work function material layer 307 provides a material layer for forming a first work function layer on the surface of the first I sidewall.
In the present embodiment, the material of the first work function material layer 307 and the material of the second work function material layer 206 are both P-type work function materials or N-type work function materials; the P-type work function material comprises titanium nitride or tantalum nitride; the N-type work function material comprises titanium aluminum.
The process of forming the first work function material layer 307 includes an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process. In this embodiment, the process of forming the first work function material layer 307 includes an atomic layer deposition process, and the atomic layer deposition process can form the first work function material layer 307 with a thin thickness and a dense structure.
In another embodiment, the material of the first work function material layer 307 and the material of the second work function material layer 206 are a P-type work function material and an N-type work function material; the P-type work function material comprises titanium nitride or tantalum nitride; the N-type work function material comprises titanium aluminum.
With reference to fig. 10, after forming the first work function material layer 307, a second sacrificial layer 308 is formed on the sidewall surface of the first region I, and the second sacrificial layer 308 exposes the first work function material layer 307 on the surface of the second region II.
The second sacrificial layer 308 is used to protect the first I-side wall surface, so that when the first work function material layer 307 on the second II-side wall surface is subsequently removed, the first work function material layer 307 on the first I-side wall surface is also removed, which deviates from the design rule of the device structure, and the performance of the device is affected.
The method for forming the second sacrificial layer 308 includes: forming a sacrificial material layer (not shown) on the surface of the substrate 200; and etching back the sacrificial material layer until the surface of the first work function material layer 307 on the side wall surface of the second region II is completely exposed, and forming a second sacrificial layer 308 on the side wall surface of the first region I.
The material of the second sacrificial layer 308 includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. The process of forming the sacrificial material layer includes a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the material of the second sacrificial layer 308 includes silicon oxide; the process for forming the sacrificial material layer comprises a chemical vapor deposition process, and the chemical vapor deposition process can quickly form the sacrificial material layer with thicker thickness and dense structure.
Referring to fig. 11, the first work function material layer 307 on the sidewall surface of the second region II is removed, and a first work function layer 407 is formed on the sidewall surface of the first region I.
The process of removing the first work function material layer 307 on the sidewall surface of the second region II includes an isotropic dry etching process or an isotropic wet etching process. In this embodiment, the process of removing the first work function material layer 307 on the sidewall surface of the second region II includes an isotropic dry etching process. The isotropic dry etching process can remove the first work function material layer 307 on the surface of the side wall of the second region II, and prevent the subsequently formed first work function layer from being also located on the surface of the side wall of the second region II, so that the design rule of the device structure is deviated, and the performance of the device is affected.
In this embodiment, the material of the first work function layer 407 and the material of the second work function layer are both P-type work function material or N-type work function material.
When the semiconductor structure is a P-type device, the material of the first work function layer 407 and the material of the second work function layer are both P-type work function materials, and the first work function layer 407 on the sidewall surface of the first region I lowers the threshold voltage of the semiconductor structure, so that the semiconductor structure has a higher driving current, and the reaction speed of the semiconductor structure is faster.
When the semiconductor structure is an N-type device, the material of the first work function layer 407 and the material of the second work function layer are both N-type work function materials, and the first work function layer 407 on the sidewall surface of the first region I lowers the threshold voltage of the semiconductor structure, so that the semiconductor structure has a higher driving current, and the reaction speed of the semiconductor structure is faster.
In another embodiment, the material of the first work function layer and the material of the second work function layer are a P-type work function material and an N-type work function material.
When the semiconductor structure is a P-type device, the first work function layer is made of an N-type work function material, the second work function layer is made of a P-type work function material, and the first work function layer on the surface of the side wall of the first region I enables the threshold voltage of the semiconductor structure to be increased, so that the semiconductor structure has a smaller driving current to avoid the electric leakage.
When the semiconductor structure is an N-type device, the first work function layer is made of a P-type work function material, the second work function layer is made of an N-type work function material, and the first work function layer on the surface of the side wall of the first region I enables the threshold voltage of the semiconductor structure to be increased, so that the semiconductor structure has a small driving current to avoid electric leakage.
With continued reference to fig. 11, after the first work function layer 407 is formed, the second sacrificial layer 308 is removed.
The process of removing the second sacrificial layer 308 includes an isotropic wet etching process or an anisotropic dry etching process. In this embodiment, the process of removing the second sacrificial layer 308 includes an anisotropic dry etching process. The anisotropic dry etching process can remove the second sacrificial layer 308 completely, so as to prevent the second sacrificial layer 308 from remaining on the surface of the second work function material layer 206 and influence the electrical performance of the semiconductor structure after a gate layer is formed on the sidewall surface of the channel pillar 202.
Referring to fig. 12, after removing the second sacrificial layer 308, a gate layer 309 is formed on the sidewall surface of the channel pillar 202 and the surface of the first work function layer 407.
The forming method of the gate layer 309 includes: forming a gate material layer (not shown) on the sidewall surface of the first work function layer 407 and the sidewall surface of the second region II; forming a patterned layer (not shown) on the gate material layer; and etching the gate material layer and the second work function material layer 206 by using the patterned layer as a mask until the surface of the gate dielectric layer 205 is exposed, so as to form the gate layer 309 and the second work function layer 406, wherein part of the gate layer 309 extends to the surface of the substrate 200 on one side of the channel column 202.
The material of the gate layer 309 includes a metal, and the metal includes copper, tungsten, or aluminum; the process for forming the grid material layer comprises a physical vapor deposition process or an electroplating process; the process of etching the gate material layer and the second work function material layer 206 includes a dry etching process or a wet etching process.
In this embodiment, the material of the gate layer 309 includes tungsten; the process for forming the gate material layer comprises a physical vapor deposition process; the process of etching the gate material layer and the second work function material layer 206 includes a dry etching process, and the dry etching process can form the gate layer 309 and the second work function layer 406 with good sidewall morphology.
Referring to fig. 13, after forming the gate layer 309, a dielectric layer 310 is formed on the substrate 200, and the channel pillar 202 is located in the dielectric layer 310; forming a first conductive plug 311, a second conductive plug 312 and a third conductive plug 313 in the dielectric layer 310, where the first conductive plug 311 is electrically connected to the gate layer 309, the second conductive plug 312 is electrically connected to the top of the channel pillar 202, and the third conductive plug 313 is electrically connected to the source-drain doping layer 201.
The forming method of the dielectric layer 310 includes: forming a dielectric material layer (not shown) on the substrate 200, the dielectric material layer covering the top surface of the channel pillar 202; and flattening the dielectric material layer to form the dielectric layer 310.
The material of the dielectric layer 310 comprises silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride; the process for forming the dielectric material layer comprises a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the material of the dielectric layer 310 includes silicon oxide; the process for forming the dielectric material layer comprises a chemical vapor deposition process, and the chemical vapor deposition process can quickly form the dielectric material layer with thicker thickness and dense structure.
The material of first, second, and third conductive plugs 311, 312, and 313 includes a metal including a combination of one or more of copper, tungsten, aluminum, and titanium nitride.
Thus, in the formed semiconductor structure, the first work function layer 407 is formed on the surface of the sidewall of the first region I. The first work function layer 407 can adjust the driving current in the trench pillar 202 to a relatively balanced state, thereby avoiding the unstable performance of the semiconductor structure caused by the unbalanced driving current in the trench pillar 202.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 13, including:
the semiconductor device comprises a substrate 200, wherein a source-drain doping layer 201 is arranged on the substrate 200;
the channel pillar 202 is positioned on the source-drain doping layer 201, and the channel pillar 202 comprises a first region I and a second region II positioned on the first region I;
the isolation layer 203 is positioned on the source-drain doping layer 201, and the isolation layer 203 is also positioned on the surface of part of the side wall of the first region I;
the interface layer 204 is positioned on the surface of the side wall of the channel column 202, the gate dielectric layer 205 is positioned on the surface of the interface layer 204, and the second work function layer 406 is positioned on the surface of the gate dielectric layer 205;
a first work function layer 407 on a sidewall surface of the first region I, wherein the first work function layer 407 is on a surface of the second work function layer 406;
a gate layer 309 on a sidewall surface of the channel pillar 202 and a surface of the first work function layer 407;
a dielectric layer 310 on the substrate 200;
a first conductive plug 311, a second conductive plug 312, and a third conductive plug 313 located in the dielectric layer 310, where the first conductive plug 311 is electrically connected to the gate layer 309, the second conductive plug 312 is electrically connected to the top of the channel pillar 202, and the third conductive plug 313 is electrically connected to the source-drain doping layer 201.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a source drain doping layer is arranged on the substrate;
forming a channel column on the source-drain doping layer, wherein the channel column comprises a first region and a second region positioned on the first region;
forming a first work function layer on the surface of the side wall of the first region or the surface of the side wall of the second region;
a gate layer is formed on the trench pillar sidewall surface and the first work function layer surface.
2. The method of claim 1, wherein the first work function layer is located on a sidewall surface of the second region.
3. The method of forming a semiconductor structure of claim 2, wherein the method of forming the first work function layer comprises: forming a first sacrificial layer on the surface of the source drain doped layer and the surface of the side wall of the first region; forming a first work function layer on the surface of the side wall of the second area; and removing the first sacrificial layer after the first work function layer is formed.
4. The method of forming a semiconductor structure of claim 3, wherein the method of forming the gate layer comprises: after removing the first sacrificial layer, forming a gate material layer on the surface of the side wall of the first work function layer and the surface of the side wall of the first region; forming a patterned layer on the gate material layer; and etching the grid electrode material layer by taking the patterning layer as a mask until the surface of the substrate is exposed to form the grid electrode layer, wherein part of the grid electrode layer also extends to the surface of the substrate at one side of the channel column.
5. The method of claim 1, wherein the first work function layer is located on the first region sidewall surface.
6. The method of forming a semiconductor structure of claim 5, wherein the method of forming the first work function layer comprises: forming a first work function material layer on the side wall surface of the first region and the side wall surface of the second region; forming a second sacrificial layer on the surface of the side wall of the first area, wherein the first work function material layer on the surface of the second area is exposed by the second sacrificial layer; removing the first work function material layer on the surface of the side wall of the second area, and forming a first work function layer on the surface of the side wall of the first area; and removing the second sacrificial layer after the first work function layer is formed.
7. The method of forming a semiconductor structure of claim 6, wherein the method of forming the gate layer comprises: after removing the second sacrificial layer, forming a gate material layer on the surface of the side wall of the first work function layer and the surface of the side wall of the second area; forming a patterned layer on the gate material layer; and etching the grid electrode material layer by taking the patterning layer as a mask until the surface of the substrate is exposed to form the grid electrode layer, wherein part of the grid electrode layer also extends to the surface of the substrate at one side of the channel column.
8. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the first work function layer on the first region sidewall surface or the second region sidewall surface: and forming a second work function layer on the surface of the side wall of the channel pillar.
9. The method of forming a semiconductor structure of claim 8, wherein the material of the first work function layer and the material of the second work function layer are both a P-type work function material or an N-type work function material; the P-type work function material comprises titanium nitride or tantalum nitride; the N-type work function material comprises titanium aluminum.
10. The method of claim 8, wherein the material of the first work function layer and the material of the second work function layer are a P-type work function material and an N-type work function material; the P-type work function material comprises titanium nitride or tantalum nitride; the N-type work function material comprises titanium aluminum.
11. The semiconductor structure of claim 8, further comprising, after forming the channel pillar: forming an interface layer and a gate dielectric layer positioned on the interface layer on the surface of the side wall of the channel column; the second work function layer is positioned on the surface of the gate dielectric layer.
12. The semiconductor structure of claim 11, after forming the channel pillar and before forming the interfacial layer, further comprising: and forming an isolation layer on the surface of the source-drain doping layer, wherein the isolation layer is positioned on the surface of the side wall of the trench column part, and the top surface of the isolation layer is lower than that of the trench column.
13. The semiconductor structure of claim 1, wherein a dielectric layer is formed on the substrate after forming the gate layer, the channel pillar being located within the dielectric layer; and forming a first conductive plug, a second conductive plug and a third conductive plug in the dielectric layer, wherein the first conductive plug is electrically connected with the grid layer, the second conductive plug is electrically connected with the top of the channel column, and the third conductive plug is electrically connected with the source-drain doping layer.
14. A semiconductor structure formed by the method of any of claims 1 to 13, comprising:
the semiconductor device comprises a substrate, a source-drain doping layer and a source-drain doping layer, wherein the substrate is provided with the source-drain doping layer;
the channel column is positioned on the source-drain doped layer and comprises a first region and a second region positioned on the first region;
the first work function layer is positioned on the surface of the side wall of the first region or the surface of the side wall of the second region;
and a gate layer located on the sidewall surface of the channel pillar and the surface of the first work function layer.
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