CN108538837A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
- Publication number
- CN108538837A CN108538837A CN201810274081.2A CN201810274081A CN108538837A CN 108538837 A CN108538837 A CN 108538837A CN 201810274081 A CN201810274081 A CN 201810274081A CN 108538837 A CN108538837 A CN 108538837A
- Authority
- CN
- China
- Prior art keywords
- layer
- barrier layer
- side wall
- active region
- semiconductor devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
Abstract
The present invention provides a kind of semiconductor devices and forming method thereof, the semiconductor devices includes the first grid structure for being set to the first active region, and first grid structure includes the first dielectric layer, the first side wall barrier layer, p-type workfunction layers, second sidewall barrier layer, N-shaped workfunction layers；And it is set to the second grid structure of the second active region, second grid structure includes the second dielectric layer, the first side wall barrier layer, second sidewall barrier layer, N-shaped workfunction layers, by being respectively formed the first side wall barrier layer and second sidewall barrier layer in the gate structure of PMOS transistor and NMOS transistor, the influence of the metal diffusion couple semiconductor device characteristic in N-shaped workfunction layers and conductive layer can be improved.In addition, by being adapted to the work function of adjacent layer to the first side wall barrier layer and the second sidewall barrier layer, the work function adaptation of semiconductor devices can be optimized, to reduce threshold voltage.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of semiconductor devices and forming method thereof.
Background technology
As dimensions of semiconductor devices continues micro, being utilized in conventional method reduces gate dielectric, such as reduces dioxy
To reach the method for optimizing purpose, face causes to leak SiClx thickness because of the tunneling effect of electronics (tunneling effect)
The excessive physical limit of electric current.High-k (high-k) material has as effectively reduced physics limit thickness, and in phase
Under same equivalent oxide thickness (equivalent oxide thickness, EOT), effectively reduces leakage current and simultaneously reach equivalent electricity
The advantages that holding to control channel switches, and substitution traditional silicon dioxide layer or silicon oxynitride layer are used to as gate dielectric.
On the other hand, traditional p-type metal oxide semiconductor (p-type MOS, hereinafter referred to as PMOS) transistor and n
Type metal oxide semiconductor (n-type MOS, hereinafter referred to as NMOS) majority is to manufacture grid using polysilicon.But both
Some will produce boron penetration (boronpenetration) effect using DOPOS doped polycrystalline silicon as the method for gate structure, lead to device
Part efficiency reduces, and polysilicon gate is easier to exhaust (depletion) effect so that equivalent gate dielectric thickness
Degree increases, grid capacitance reduces, and then leads to device drive reduced capability.To avoid the boron penetration effects of above-mentioned polysilicon gate
And depletion effect, utilize metal gates (metal gate) that polysilicon gate, processing procedure is replaced usually to utilize rear grid work at present more
Skill (gate last) formation, such as it is initially formed a sacrifice grid or nominal grid (sacrifice gate), and complete part
After MOS transistor makes, sacrifice/nominal grid is removed and forms a gate recess (gate trench), needed according still further to electrical
It asks and forms metal gates in the gate recess.
In another aspect, complementary metal oxide semiconductor (Complementary Metal Oxide
Semiconductor, CMOS) for device due to the characteristic with low power consumption, the application in electronic circuit is increasingly extensive.
Cmos device includes one group of pairs of PMOS transistor and NMOS transistor, usually using PMOS transistor and NMOS transistor its
One of in open state with conducting electric current.In order to obtain optimum efficiency, PMOS transistor and the NMOS crystal of cmos device
Pipe should have the threshold voltage (thresholdvoltage) being closer to.
In order to which the threshold voltage of cmos device is arranged, grid can utilize the workfunction metal (work of p-type and/or N-shaped
Functionmetal, WFM) metal gates of the layer as matching high dielectric constant gate dielectric layer.In certain cmos devices,
Conductive layer, N-shaped workfunction layers (n-eWFM) are stacked on p-type workfunction layers (p-eWFM) by PMOS transistor to be made
For metal gates, and NMOS transistor is using conductive layer and N-shaped workfunction layers as metal gates.
But it has been found that in PMOS transistor, conductive layer can be because of warm with the aluminium element in N-shaped workfunction layers
Effect and spread, cause the effective work function (effective work function) of p-type workfunction layers to change,
And then influence component characteristic and reliability test result.In addition, the PMOS transistor and NMOS transistor of existing cmos device are only
One layer of side wall barrier layer (side wallbarrier, SWB) is set to obstruct p-type or N-shaped workfunction layers and gate dielectric
Layer, in terms of the matching of work function, still there is the space of optimization.
Invention content
The purpose of the present invention is to provide a kind of semiconductor devices and forming method thereof, to reduce or avoid in PMOS device
The problem of metal diffusion causes in conductive layer and N-shaped workfunction layers.It is another object of the present invention to optimize PMOS transistor
With the work function matching of grid in NMOS transistor, the reliability of semiconductor devices is promoted.
In order to achieve the above objectives, the present invention provides a kind of semiconductor devices, including：
Substrate has the first active region and the second active region in the substrate；It is set to first active region
First grid structure, the first grid structure include the first dielectric layer, the first side wall barrier layer, p-type workfunction layers,
Second sidewall barrier layer, N-shaped workfunction layers；And it is set to the second grid structure of second active region, it is described
Second grid structure includes the second dielectric layer, the first side wall barrier layer, second sidewall barrier layer, N-shaped workfunction layers；Its
In, first dielectric layer and second dielectric layer include dielectric layer with high dielectric constant.
Optionally, the semiconductor devices further includes：Bottom barrier layer, the bottom barrier layer are located at first active region
First dielectric layer and the first side wall barrier layer between and/or second active region second dielectric layer
Between the first side wall barrier layer.
Optionally, the semiconductor devices further includes：Barrier layer is pushed up, the top barrier layer is located at first active region
With the top of the N-shaped workfunction layers of second active region.
Optionally, the semiconductor devices further includes：Conductive layer, the conductive layer are located at the top on the top barrier layer.
Optionally, it is provided with interlayer dielectric layer between the first grid structure and the second grid structure, it is described
The upper surface flush of the upper surface of conductive layer and the interlayer dielectric layer.
Optionally, the dielectric constant of the dielectric layer of high dielectric constant is more than 4.
Optionally, the first side wall barrier layer and second sidewall barrier layer include high temperature transition metal, it is precious metal, dilute
Earth metal and its carbide, nitride, silicide, aln precipitation or nitrogen silicide.
Optionally, the first side wall barrier layer includes tantalum nitride, and the second sidewall barrier layer includes titanium nitride.
Optionally, the semiconductor devices includes PMOS transistor and NMOS transistor.
The present invention also provides the forming methods of above-mentioned semiconductor device, include the following steps：
Substrate is provided, being defined in the substrate has the first active region and the second active region；
The first nominal grid is formed in first active region, the second dummy grid are formed in second active region
Pole, first nominal grid includes being sequentially overlapped the first dielectric layer and the first sacrificial layer to be formed on the substrate, described
Second nominal grid includes being sequentially overlapped the second dielectric layer and the second sacrificial layer to be formed on the substrate；
The first side wall is formed in the both sides of first nominal grid, second is formed in the both sides of second nominal grid
Side wall；
First sacrificial layer and second sacrificial layer are removed, to form the first groove in first active region,
And form the second groove in second active region；
The first side wall barrier layer and p-type workfunction layers, and institute are sequentially formed in the inner surface of first groove
State the inner surface that the first side wall barrier layer also covers second groove；
Second sidewall barrier layer is formed, the second sidewall barrier layer covers the p-type work function gold in first groove
Belong to the surface of layer and the surface on the first side wall barrier layer in second groove, then stops in the second sidewall
Layer surface forms N-shaped workfunction layers；And
Top barrier layer and conductive layer are sequentially formed in the N-shaped workfunction metal layer surface, until filling up described first
Groove and second groove.
It has compared for prior art, the forming method of semiconductor devices provided by the invention does not increase additional light shield,
It is respectively formed the first side wall barrier layer and second sidewall barrier layer in the gate structure of PMOS transistor and NMOS transistor, it can be with
Improve or avoid the influence of the metal diffusion couple semiconductor device characteristic in N-shaped workfunction layers and conductive layer.Further,
The semiconductor devices can be cmos device (including PMOS transistor and NMOS transistor), by hindering the first side wall
Barrier layer and the second sidewall barrier layer are adapted to the work function of adjacent layer, can optimize the work function adaptation of cmos device, from
And reduce threshold voltage.
Description of the drawings
Fig. 1 is the flow chart of the forming method of the semiconductor devices of the embodiment of the present invention.
Fig. 2 to Fig. 8 is the schematic diagram of each processing step of the forming method of the semiconductor devices of the embodiment of the present invention.
Fig. 9 is energy band schematic diagram of the semiconductor devices provided in an embodiment of the present invention by grid direction to substrate direction.
Reference sign：
100- substrates；The first active regions of 110-；The second active regions of 120-；101- isolated parts；The interfaces 102- dielectric
Layer；103- dielectric layer with high dielectric constant；The bottoms 104- barrier layer；105- grid sacrificial layers；106- hard mask layers；The first dielectrics of 111-
Layer；The second dielectric layers of 121-；The first sacrificial layers of 112-；The second sacrificial layers of 122-；The first side walls of 113-；The second side walls of 123-；
The first source-drain areas of 114-；The second source-drain areas of 124-；107- metal silicide layers；108- contact etch stop layers；109- interlayers are situated between
Electric layer；The first grooves of 130-；The second grooves of 140-；131- the first side walls barrier layer；132-p type workfunction layers；133-
Two side wall barrier layers；141-n type workfunction layers；151- pushes up barrier layer；152- conductive layers；200- semiconductor devices.
Specific implementation mode
Semiconductor devices of the present invention and forming method thereof is made below in conjunction with the drawings and specific embodiments further detailed
Explanation.According to following explanation, advantages and features of the invention will become apparent from.Simplify very much it should be noted that attached drawing is all made of
Form and use non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Term " first " " second " etc. is used between similar element distinguish, and is not necessarily for describing certain order
Or time sequencing.It is appreciated that in the appropriate case, these terms so used are replaceable, such as may make as described herein
The embodiment of the present invention can be different from it is as described herein or shown in other sequentially operate.Similar, if described herein
Method include series of steps, and the sequence of these steps presented herein is not necessarily that can perform these steps only
One sequence, other steps that the step described in some can be omitted and/or some are not described here can be added to this method.
If the component of the embodiment of the present invention is identical as the component in other icons in figure, although can all be recognized easily in all figures
These components, but in order to keep the explanation of icon apparent, the label of all identical components will not be marked in each by this specification
In figure.
Core of the invention thought is, is arranged or is formed the in the gate structure of PMOS transistor and NMOS transistor
On the one hand the second sidewall barrier layer of one side wall barrier layer sum can improve the aluminium element in N-shaped workfunction layers and conductive layer
The influence for spreading the characteristic of pair pmos transistor and NMOS transistor device, on the other hand can stop by adjusting the first side wall
Material composition, thickness and the work function of layer and the second barrier layer, need not increase additional light shield so that N-shaped workfunction layers
Prior art is compared with p-type workfunction layers, respectively effectively close to the conduction band edge (conductionband of substrate
Edge) and valence band edge (valance band edge), to reduce the threshold voltage of PMOS transistor and NMOS transistor.
Technical scheme of the present invention is described in detail below in conjunction with drawings and examples.
Fig. 1 is the flow chart of the forming method of the semiconductor devices of the embodiment of the present invention.As shown in Figure 1, the present embodiment
The forming method of semiconductor devices includes the following steps：
S1：Substrate is provided, being defined in the substrate has the first active region and the second active region；
S2：The first nominal grid is formed in first active region, it is dummy to form second in second active region
Grid, first nominal grid include being sequentially overlapped the first dielectric layer and the first sacrificial layer to be formed, institute on the substrate
It includes being sequentially overlapped the second dielectric layer and the second sacrificial layer to be formed on the substrate to state the second nominal grid；
S3：The first side wall is formed in the both sides of first nominal grid, is formed in the both sides of second nominal grid
Second side wall；
S4：First sacrificial layer and second sacrificial layer are removed, it is recessed to form first in first active region
Slot forms the second groove in second active region；
S5：The first side wall barrier layer and p-type workfunction layers are sequentially formed in the inner surface of first groove, it is described
The first side wall barrier layer also covers the inner surface of second groove；
S6：Second sidewall barrier layer is formed, the second sidewall barrier layer covers the p-type work function in first groove
Then the surface on the first side wall barrier layer in the surface of metal layer and second groove is hindered in the second sidewall
Barrier surface forms N-shaped workfunction layers；
S7：Top barrier layer and conductive layer is sequentially formed in the N-shaped workfunction metal layer surface, until filling up described the
One groove and second groove.
Fig. 2 to Fig. 8 is the schematic diagram of each processing step of the forming method of the semiconductor devices of the embodiment of the present invention.Below
Some embodiments of the present invention are explained in detail in conjunction with Fig. 1 to Fig. 8.
As shown in Fig. 2, executing step S1, provide a substrate 100, in substrate 100 definition have the first active region 110 and the
Two active regions 120.
Substrate 100 can be the semiconductor substrate for including silicon.Optional substrate 100 is for example：Another elemental semiconductor, it is another
Element is, for example, germanium；Compound semiconductor, the compound are, for example, silicon carbide, GaAs, gallium phosphide, indium phosphide and/or antimony
Change indium；Alloy semiconductor, the alloy be, for example, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or
Their combination；Silicon-on-insulator (silicon-on-insulator, SOI) substrate.Substrate 100 may include the outer of doping
Prolong layer, gradient semiconductor layer and/or the semiconductor layer (silicon on such as germanium silicon layer on another different types of semiconductor layer
Layer), substrate 100 may include depending on the other configurations that semiconductor device design requires.
Definition has the first active region 110 and the second active region 120 in substrate 100, as an example, the present embodiment is the
One active region 110 arranges PMOS transistor, and arranges NMOS transistor in the second active region 120.It can be formed in substrate 100
There are multiple isolated parts 101 (being, for example, shallow isolating trough, STI) to define and electrical areas is isolated.The material of isolated part 101
Including silica, silicon nitride, silicon oxynitride, other suitable materials or combination thereof.Forming isolated part 101 can utilize
Method disclosed in this field.
Then step S2 is executed, the first nominal grid DG1 is formed in the first active region 110, in the second active region 120
It includes that the first dielectric layer 111 to be formed is sequentially overlapped in substrate 100 to form the second nominal grid DG2, the first nominal grid DG1
With the first sacrificial layer 112, the second nominal grid DG2 includes that the second dielectric layer 113 to be formed and are sequentially overlapped in substrate 100
Two sacrificial layers 122.
With reference to Fig. 2 and Fig. 3, the first dielectric layer 111 is formed in the first active region 110 first, in the second active region 120
The second dielectric layer 113, the first dielectric layer 111 and the second dielectric layer 113 is formed to be formed using identical deposition and patterning process
(Fig. 2), the first dielectric layer 111 and the second dielectric layer 113 include the following trilaminate materials being sequentially overlapped along the surface of substrate 100：
Interface dielectric layer 102 (interfacial layer), high-k (high-k) dielectric layer 103 and bottom barrier layer
(bottom barrierlayer)104.In other embodiments, the first dielectric layer 111 and the second dielectric layer 113 can use
Different materials and technique are formed.
Interface dielectric layer 102 can have oxygen atom or nitrogen-atoms by oxide, nitrogen oxides (Oxy-nitride) etc.
Dielectric material is constituted, and in preferred embodiment, interface dielectric layer 102 includes 5 angstroms to 20 angstromsSilicon dioxide layer.High dielectric is normal
Number dielectric layer 103 is formed in 102 surface of interface dielectric layer.In some embodiments, it is also possible to do not form interface dielectric layer 102 and
It is directly to form dielectric layer with high dielectric constant 103 on 100 surface of substrate.
Dielectric layer with high dielectric constant 103 can have one or more layers structure, dielectric layer with high dielectric constant 103 may include
Various high-k dielectric materials (dielectric constant is greater than 4), such as rare-earth oxide layer or lanthanide series metal oxygen
Compound layer can be hafnium oxide (hafnium oxide, HfO2), hafnium silicate oxygen compound (hafnium silicon oxide,
HfSiO), hafnium silicate nitrogen oxide (hafnium silicon oxynitride, HfSiOn), aluminium oxide (alumium
Oxide, AlO), lanthana (lanthanum oxide, La2O3), lanthanum aluminate (lanthanum aluminum oxide,
LaAlO), tantalum oxide (tantalum oxide, Ta2O3), zirconium oxide (Zirconium oxide, ZrO2), zirconium silicate oxidation close
Object (zirconium silicon oxide, ZrSiO), zirconic acid hafnium (hafnium zirconium oxide, HfZrO), strontium bismuth
Tantalum pentoxide (strontium bismuth tantalate, SrBi2Ta2O9, SBT), lead zirconate titanate (lead zirconate
Titanate, pbZrxTi1-xO3, pZT) and barium strontium (barium strontium titanate, BaxSr1-xTiO3,
BST), other suitable high-k dielectric materials or combination thereof.The thickness of dielectric layer with high dielectric constant 103 depends on
The design requirement of semiconductor devices, as an example, about 5 angstroms to 30 angstroms of the thickness of dielectric layer with high dielectric constant 103.
Bottom barrier layer 104 is formed in 103 surface of dielectric layer with high dielectric constant, and bottom barrier layer 104 can be used as subsequent technique
Etching stopping layer, forming method includes atomic layer deposition method (ALD), chemical vapour deposition technique (CVD) or physical vapor
Sedimentation (PVD) etc., the material on bottom barrier layer 104 may include the elements such as high temperature transition metal, precious metal, rare earth metal and
Its carbide, nitride, silicide, aln precipitation or nitrogen silicide, such as titanium nitride (TiN), tantalum nitride (TaN), ramet
(TaC), the materials such as nitrogen tantalum silicide (TaSiN), aluminium molybdenum nitride (MoAlN).As an example, the material on bottom barrier layer 104 is
Titanium nitride.In some embodiments, bottom barrier layer 104 can also omit.
For later grid technique, grid sacrificial layer 105 and hard mask layer 106 are sequentially formed on 104 surface of bottom barrier layer, so
After be sequentially etched hard mask layer 106, grid sacrificial layer 105, bottom barrier layer 104, so as to the first active region 110 formed first
Nominal grid DG1 and form the second nominal grid DG2 in the second active region 120, wherein the first nominal grid DG1 includes
The first dielectric layer 111, the first sacrificial layer 112 and hard mask layer 106 to be formed, the second dummy grid are sequentially overlapped in substrate 100
Pole DG2 includes that the second dielectric layer 113, the second sacrificial layer 122 and hard mask layer 106 to be formed are sequentially overlapped in substrate 100.Its
In, grid sacrificial layer 105 can be the materials such as undoped polysilicon, DOPOS doped polycrystalline silicon, non-crystalline silicon or germanium, hard mask layer
106 may include that oxide, nitride or nitrogen oxides, effect are optimization etching effect and protection 112 He of the first sacrificial layer
Second sacrificial layer 122, for the function of nominal grid, hard mask layer 106 is not necessary.As an example, grid
Pole sacrificial layer 105 includes 350 to 700 angstroms thick of un-doped polysilicon.
Referring next to Fig. 4, step S3 is executed, the first side wall 113 is formed in the both sides of the first nominal grid DG1, second
The both sides of nominal grid DG2 form the second side wall 123.First side wall 113 and the second side wall 123 can be single layer structure or multilayer
Structure specifically may include silica, high temperature oxygen SiClx (hightemperature oxide, HTO), silicon nitride or silicon nitride.
The embodiment of the present invention may include some Conventional process steps, as shown in figure 4, being formed for example in substrate 100 light
The step of region doped-drain (LDD), LDD region domain can be formed at various time points as needed, in other embodiment
In, heavy doping drain electrode region (HDD) can also be formed in substrate 100；In the substrate 100 of the first both sides nominal grid DG1
The step of forming the first source-drain area 114, and form the second source and drain in the substrate 100 of the second both sides nominal grid structure DG2
The step of area 124, the first source-drain area 114 and the second source-drain area 124 may include the component of protrusion, such as epitaxial membrane (such as
Germanium and silicon epitaxial component or silicon epitaxy component).
The embodiment of the present invention may also include the step of forming metal silicide layer, such as first including the first nominal grid
The substrate of DG1, the first side wall 113, the first source-drain area 114, the second nominal grid DG2, the second side wall 123, the second source-drain area 124
The metal layer being made of cobalt (Co), nickel (N), platinum (Pt), palladium (Pd), molybdenum (Mo) or combinations thereof etc. is formed on 100, followed by
Rapid temperature annealing (RTA) technique keeps the silicon of the metal layer and the first source-drain area 114 and the second source-drain area 124 anti-at least once
It answers, to form metal silicide layer 107, finally removes unreacted metal layer.
The embodiment of the present invention, which may also include, sequentially forms contact etch stop layer (CESL) 108 and interlayer dielectric layer
(ILD) 109 the step of, specifically, being initially formed contact etch stop layer 108 in including 120 He of the first nominal grid structure
100 surface of substrate of second nominal grid structure 122, then re-forms interlayer dielectric layer 109 in contact etch stop layer 108
Surface.Contact etch stop layer 108 other than the stop-layer etched as subsequent touch hole, can also generate compression or
Pressure is stretched, between the channel region and the first source-drain area 114 below the first nominal grid structure 120 and second is dummy
Strain structure is formed between the channel region and the second source-drain area 124 of 122 lower section of gate structure, so as to promote corresponding raceway groove
Charge mobility or hole mobility.Nitridation of the contact etch stop layer 108 containing silica or mixed with boron, phosphorus
Silicon.For interlayer dielectric layer 109 containing oxide or mixed with boron, the silica of phosphorus, the thickness of interlayer dielectric layer 109 can be more than first
The height of side wall 113 and the second side wall 123, specifically preferably from about 3000 angstroms between 1500 to 5000 angstroms, in preferred embodiment, layer
Between dielectric layer 109 be low dielectric coefficient medium layer (k<3).
Chemical mechanical grinding (CMP) technique can be used for removing part interlayer dielectric layer 109, part contact etch stop layer
It 108 and hard mask layer 106 and is parked on grid sacrificial layer 105, i.e., so that the upper surface of interlayer dielectric layer 109 is sacrificed with first
The upper surface flush of layer 112 and/or the second sacrificial layer 122.
With reference to Fig. 5, step S4 is then executed, the first sacrificial layer 112 and the second sacrificial layer 122 are removed, with active first
Region 110 forms the first groove 130, and the second groove 140 is formed in the second active region 120.
Specifically, being etched technique and completely removing the first sacrificial layer 112, Yi Ji in the first nominal grid DG1
The second sacrificial layer 122 in two nominal grid DG2 has to form the first groove 130 in the first active region 110 second
Source region 120 forms the second groove 140.The bottom surface of first groove 140 and the second groove 142 exposes bottom barrier layer 104,
The present invention is not formed in some embodiments on bottom barrier layer 104, and the bottom surface of the first groove 130 and the second groove 140 exposes
Dielectric layer with high dielectric constant 103.Although it is easily understood that it is described herein be with and meanwhile remove two regions grid it is sacrificial
For domestic animal layer 105, but in some embodiments, the grid sacrificial layer 105 that also may be selected first to remove one of region forms one
A groove and grid sacrificial layer 105 for completing subsequent fill process and then another region of removal forms another groove simultaneously
It is filled technique.
Wet method erosion may be selected in the technique for removing grid sacrificial layer 105 (including the first sacrificial layer 112 and second sacrificial layer 122)
Either dry etching is carved, if removing the grid sacrificial layer 105 of polycrystalline silicon material with wet etching, use may be selected and include nitric acid
Etching solution, if being removed with dry etching, using chlorine or hydrogen bromide as process gas.Grid sacrificial layer 105
Material is not limited to polysilicon, as long as and bottom barrier layer 104 have appropriate etching selectivity material all it is optional be used as grid
The material of sacrificial layer 105.
With reference to Fig. 6, step S5 is executed, the first side wall barrier layer 131 and p are sequentially formed in the inner surface of the first groove 130
Type workfunction layers 132, the first side wall barrier layer 131 also cover the inner surface of the second groove 140.
Specifically, being sequentially depositing the first side wall barrier layer 131 and p-type workfunction layers 132 first in interlayer dielectric
On layer 108 and the inner surface of the first groove 130 of covering and the second groove 140 (does not fill up the first groove 130 and the second groove
140) it includes the p-type workfunction layers 132 in the second groove 140, to be then optionally removed the second active region 120, is gone
Except method for example includes forming patterned photoresist layer in substrate 100, then using patterned photoresist layer as mask, do
The p-type workfunction layers 132 of method etching the second active region 120 of removal.
P-type workfunction layers 132 include the metal material for meeting work function needed for PMOS transistor and requiring, e.g. nitrogen
Change titanium (TiN), can also be nickel (Ni), palladium (Pd), platinum (Pt), beryllium (Be), iridium (Ir), tellurium (Te), rhenium (Re), ruthenium (Ru), rhodium
(Rh), tungsten (W), molybdenum (Mo) they can also include the carbide etc. of tungsten, ruthenium, molybdenum, the nitride of tantalum (Ta) or tungsten, tantalum, titanium, but
It is without being limited thereto.As an example, the material of p-type workfunction layers 132 is titanium nitride.
It, can be with the first side wall barrier layer 131 and bottom when the second active region 120 removes p-type workfunction layers 132
Barrier layer 104 is collectively as stop-layer.In order to reach preferable etching stopping effect, p-type workfunction layers 132 and the first side
It is preferable to use different materials on wall barrier layer 131, and further, the two can select dry etching to select relatively high material,
As an example, titanium nitride can be selected as the material of p-type workfunction layers 132 and bottom barrier layer 104, it is corresponding to select
Select material of the tantalum nitride as the first side wall barrier layer 131.
With reference to Fig. 7, step S6 is executed, forms second sidewall barrier layer 133, the covering first of second sidewall barrier layer 133 is recessed
The surface on 140 the first side wall barrier layer 131 in the surface of p-type workfunction layers 132 in slot 130 and the second groove,
Then N-shaped workfunction layers 141 are formed on 133 surface of second sidewall barrier layer.
Specifically, first successively comprehensive deposition second sidewall barrier layer 133 and N-shaped workfunction layers 141 in base
On bottom 100, second sidewall barrier layer 133 and N-shaped workfunction layers 141 are covered in p-type work function gold in the first groove 130
The surface for belonging to layer 132, is covered in the surface on the first side wall barrier layer 131 in the second groove 140.The second side deposited at this time
Wall barrier layer 133 and N-shaped workfunction layers 141 not yet fill up the first groove 130 and the second groove 140.
N-shaped workfunction layers 141 are the metal for meeting work function needed for NMOS transistor and requiring, e.g. titanium aluminide
(titanium aluminides, TiAl), calorize zirconium (aluminum zirconium, ZrAl), calorize tungsten (aluminium
Tungsten, WAl), calorize tantalum (aluminium tantalum, TaAl) or calorize hafnium (aluminum hafnium, HfAl),
But not limited to this.
With reference to Fig. 8, step S7 is executed, top barrier layer 151 is sequentially formed on 141 surface of N-shaped workfunction layers and is led
Electric layer 152, until filling up the first groove 130 and the second groove 140.
Specifically, top barrier layer 151 is, for example, titanium nitride, aluminium-titanium carbonate (TiAlC), TiAlN (TiAlN), nitridation
Tantalum, aluminium carbide tantalum (TaAlC), carbonization copper titanium (TiCuC), copper nitride titanium (TiCuN), carbonization copper tantalum (TaCuC), copper nitride tantalum
(TaCun) etc., but not limited to this.The small conductive material of 152 preferred resistance of conductive layer, such as aluminium, titanium (Ti), tantalum (Ta), tungsten
(W), niobium (Nb), molybdenum (Mo), copper, titanium nitride, titanium carbide, tantalum nitride, titanium tungsten (Ti/W) or the shapes such as titanium and titanium nitride (Ti/TiN)
At complex metal layer, conductive layer 152 can be carried by physical vapour deposition (PVD), chemical vapor deposition, atomic layer deposition, plasma
Enhancing CVD, remote plasma cvd, molecule organic deposit, sputtering, plating or other appropriate methods or combination thereof are formed.
In the step s 7, one or multi-channel flatening process pair the first active region 120 and the second active area can be utilized
Domain 110 is planarized, until exposing the surface of interlayer dielectric layer 108.In the present embodiment, carried out using CMP process flat
Change, the conductive layer 152 of 108 top of removal interlayer dielectric layer, N-shaped workfunction layers 141, second sidewall barrier layer 133, p-type
Workfunction layers 132 and the first side wall barrier layer 131, in some embodiments, part interlayer dielectric layer 108 can also be gone
It removes.
Thus, the first dielectric layer 111, bottom barrier layer 104 in the first groove 130, the first side wall barrier layer
131, p-type workfunction layers 132, second sidewall barrier layer 133, N-shaped workfunction layers 141, top and are led at barrier layer 151
Electric layer 152 constitutes the first grid structure MG1 of the first active region 110；And the second dielectric layer in the second groove 140
121, bottom barrier layer 104, the first side wall barrier layer 131, second sidewall barrier layer 133, the blocking of the top of N-shaped workfunction layers 141
Layer 151 and conductive layer 152 constitute the second grid structure MG2 positioned at the second active region 120.
First grid structure MG1 and the first source-drain area 114 being distributed in its both sides substrate 100 constitute reality described herein
The PMOS transistor of example is applied, and second grid structure MG2 is constituted herein with the second source-drain area 124 being distributed in its both sides substrate
The NMOS transistor of the embodiment of description.It subsequently can be in the substrate including first grid structure MG1 and second grid structure MG2
Dielectric layer, metal plug and metal interconnection structure are formed on 100, so as to the PMOS transistor and NMOS transistor into
Row control.
In some embodiments of the present invention, semiconductor devices be preferably CMOS transistor (including a pair pmos transistor and
NMOS transistor), and use post tensioned unbonded prestressed concrete technique and preceding dielectric layer with high dielectric constant (high-k first) technique.This field
Technical staff it is to be appreciated that the present invention also can formed first grid structure MG1 and second grid structure MG2 metal gates
It forms dielectric layer with high dielectric constant (high-Klast) again before, such as is formed in the first groove 130 and the second groove 140
Before the first side wall barrier layer 131, the dielectric layer with high dielectric constant 103 of previous generation can be first removed, then in the first groove 130
And second groove 140 surface on form dielectric layer with high dielectric constant again, then sequentially form the first side wall barrier layer again
131, materials and the structure such as p-type workfunction layers 132, second sidewall barrier layer 133.Using this method, it is located at the first groove
Dielectric layer with high dielectric constant in 130 can have U-shaped section as p-type workfunction layers 132.In addition, being described herein as
Embodiment with planar transistor (planartransistor) for example, those of ordinary skill in the art will also be understood that, this hair
Bright structure is also applicable in manufacture craft on non-planar transistor, e.g. fin transistor (Fin-FET) etc..
The present embodiment also provides a kind of semiconductor devices 200.With reference to Fig. 2 to Fig. 8, semiconductor devices 200 includes at least：
Substrate 100 has the first active region 110 and the second active region 120 in substrate 100；
It is set to the first grid structure MG1 of the first active region 110, first grid structure MG1 includes the first dielectric layer
111, the first side wall barrier layer 131, p-type workfunction layers 132, second sidewall barrier layer 133, N-shaped workfunction layers
141, barrier layer 151 and conductive layer 152 are pushed up；
Second grid the structure MG2, the second grid structure MG2 for being set to the second active region 120 include second Jie
Electric layer 121, the first side wall barrier layer 131, second sidewall barrier layer 133, N-shaped workfunction layers 141, top barrier layer 151 with
And conductive layer 152.
Wherein, in preferred embodiment, the first dielectric layer 111 and the second dielectric layer 111 include at least a floor height dielectric constant
Dielectric layer 103, such as it includes interface dielectric layer 102, high-k that the first dielectric layer 111 and the second dielectric layer 121, which can be,
The three-decker on dielectric layer 103 and bottom barrier layer 104.
In addition, semiconductor devices 200 further includes the first source and drain formed in 150 both sides substrate 100 of first grid structure
Area 114, and the second source-drain area 124 for being formed in 152 both sides substrate 100 of second grid structure.
Corresponding function layer described in the forming method of each functional layer and aforementioned semiconductor device in semiconductor devices 200
It is corresponding.Details are not described herein again.
In the embodiment of the present invention, the first side wall barrier layer is formed in above dielectric layer with high dielectric constant, second sidewall blocking
P-type workfunction metal layer surface layer setting or be formed in first grid structure MG1 (grid as PMOS transistor), and
And second sidewall barrier layer also set up or be formed in second grid structure MG2 (grid as NMOS transistor) first
Side wall barrier layer surface.Wherein, it is miscellaneous can be substantially prevented from (or reduction) metal for the first side wall barrier layer and second sidewall barrier layer
Aluminium element in matter such as conductive layer and/or N-shaped workfunction layers penetrates into p-type workfunction layers and/or high-k is situated between
In electric layer, so as to fully avoid impacting the characteristic of CMOS transistor device and the reliability of erasing operation.
Further, second sidewall barrier layer is in second grid structure MG2, also with the first side wall barrier layer collectively as
Etch stop layer during removing p-type workfunction layers, can be with enhanced etching blocking effect, while also providing enhanced to gold
Belong to the blocking effect of impurity；About 30 to 100 angstroms of the thickness on the first side wall barrier layer and second sidewall barrier layer, in forming process
The adherency between its lower layer's (such as p-type workfunction layers) and upper layer (N-shaped workfunction layers) can be enhanced, thus can be led to
It crosses adjustment and obtains the desired interface quality before forming upper layer of material.
It is worth noting that the bottom barrier layer, the first side wall barrier layer in the embodiment of the present invention and second sidewall barrier layer
Also has the function of work function adjusting.By taking the first active region as an example, the first side wall barrier layer overlying contact is p-type work function
Metal layer, and second sidewall barrier layer overlying contact is N-shaped workfunction layers, thus preferably the first side wall barrier layer and the
Two side wall barrier layers select different materials, and are adjusted by the technique to the first side wall barrier layer and second sidewall barrier layer
Work function, for example, can select titanium nitride, tantalum nitride and titanium nitride as bottom barrier layer, the first side wall barrier layer and respectively
The material of two side wall barrier layers；Consider for electrical collocation, can by the concentration of process adjustments nitrogen or the concentration of titanium/tantalum,
If such as form the material of nitrogen concentration high (N rich), forming method can be initially formed titanium nitride or tantalum nitride layer, then again
Carry out nitrogen treatment.In some embodiments, also can nitrogen treatment only be carried out to second sidewall barrier layer, to realize work function
It adjusts.
Fig. 9 is the semiconductor devices of the embodiment of the present invention by the energy band schematic diagram in grid direction to substrate direction.Such as Fig. 9 institutes
Show, energy gap EgateWith EFThe respectively fermi level (fermi level) of gate structure and substrate.qФGateFor the work content of grid
Number, q ΦsFor the work function of substrate, wherein q is the charge of electron institute band, and Fig. 9 also shows the conduction band E of substrateC, valence band EVAnd base
Middle energy gap (mid-gap) the energy level Ei at bottom.Work function is defined as an electronics in the atom of material by fermi level turn herein
Move to the energy needed for vacuum level (vacuum level).
By taking PMOS transistor as an example, correspond to first grid structure, if N-shaped workfunction layers are formed directly into p-type
On workfunction layers, the work function of p-type workfunction layers needs to be in close proximity to valence band edge, to make up N-shaped work content
Effect of the work function of number metal layer close to conduction band edge；And according to the technical solution of the present embodiment, in p-type workfunction metal
Before layer and the growth of N-shaped workfunction layers, each the first side wall barrier layer (such as tantalum nitride) formed with heterogeneity and
Second sidewall barrier layer (such as titanium nitride) so that N-shaped workfunction layers are not direct to be contacted with p-type workfunction layers, and
And the first side wall barrier layer can be utilized by the selection to the first side wall barrier layer and second sidewall barrier material and technique
The work function of grid is adjusted with second sidewall barrier layer, to advantageously reduce the threshold voltage of CMOS transistor.
In short, technical solution described in the embodiment of the present invention need not increase light shield relative to prior art, pass through the first side
The process conditions on wall barrier layer and second sidewall barrier layer are adjusted, and can improve N-shaped workfunction metal in PMOS transistor
Layer is in direct contact the metallic element diffusion of p-type workfunction layers generation and influences PMOS transistor characteristic.In addition, by adjusting
Material, thickness and the work function on second sidewall barrier layer, may make compared to prior art so that first grid structure MG1 and
Second grid structure MG2 is effectively close to the conduction band edge of substrate and valence band edge, to reduce the threshold voltage of cmos device.
It should be noted that the content of embodiment is described by the way of progressive in this specification, in the part of rear description
Stress be all with the difference in the part of preceding description, between various pieces identical and similar part mutually referring to
.For semiconductor devices disclosed in embodiment, due to the forming method phase with semiconductor devices disclosed in embodiment
Corresponding, so description is fairly simple, reference may be made to the description of the method.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of interest field of the present invention,
Any those skilled in the art without departing from the spirit and scope of the present invention, may be by the methods and techniques of the disclosure above
Content makes possible variation and modification to technical solution of the present invention, therefore, every content without departing from technical solution of the present invention,
According to the technical essence of the invention to any simple modifications, equivalents, and modifications made by above example, this hair is belonged to
The protection domain of bright technical solution.
Claims (10)
1. a kind of semiconductor devices, which is characterized in that including：
Substrate has the first active region and the second active region in the substrate；
It is set to the first grid structure of first active region, the first grid structure includes the first dielectric layer, first
Side wall barrier layer, p-type workfunction layers, second sidewall barrier layer, N-shaped workfunction layers；And
It is set to the second grid structure of second active region, the second grid structure includes the second dielectric layer, first
Side wall barrier layer, second sidewall barrier layer, N-shaped workfunction layers；
Wherein, first dielectric layer and second dielectric layer include dielectric layer with high dielectric constant.
2. semiconductor devices as described in claim 1, which is characterized in that the semiconductor devices further includes：Bottom barrier layer, institute
Bottom barrier layer is stated to be located between first dielectric layer and the first side wall barrier layer of first active region and/or institute
It states between second dielectric layer of the second active region and the first side wall barrier layer.
3. semiconductor devices as described in claim 1, which is characterized in that the semiconductor devices further includes：Push up barrier layer, institute
State the top that top barrier layer is located at the N-shaped workfunction layers of first active region and second active region.
4. semiconductor devices as claimed in claim 3, which is characterized in that the semiconductor devices further includes：Conductive layer, it is described
Conductive layer is located at the top on the top barrier layer.
5. semiconductor devices as claimed in claim 4, which is characterized in that in the first grid structure and the second grid
Interlayer dielectric layer, the upper surface flush of the upper surface of the conductive layer and the interlayer dielectric layer are provided between structure.
6. such as semiconductor devices described in any one of claim 1 to 5, which is characterized in that the dielectric layer of high dielectric constant
Dielectric constant is more than 4.
7. such as semiconductor devices described in any one of claim 1 to 5, which is characterized in that the first side wall barrier layer and the
Two side wall barrier layers include high temperature transition metal, precious metal, rare earth metal and its carbide, nitride, silicide, aluminium nitrogen
Compound or nitrogen silicide.
8. semiconductor devices as claimed in claim 7, which is characterized in that the first side wall barrier layer includes tantalum nitride, institute
It includes titanium nitride to state second sidewall barrier layer.
9. such as semiconductor devices described in any one of claim 1 to 5, which is characterized in that the semiconductor devices includes PMOS
Transistor and NMOS transistor.
10. a kind of forming method of semiconductor devices as described in any one of claim 1 to 9, which is characterized in that including：
Substrate is provided, being defined in the substrate has the first active region and the second active region；
The first nominal grid is formed in first active region, the second nominal grid, institute are formed in second active region
It includes being sequentially overlapped the first dielectric layer and the first sacrificial layer to be formed on the substrate to state the first nominal grid, and described second is empty
It includes being sequentially overlapped the second dielectric layer and the second sacrificial layer to be formed on the substrate to set grid；
The first side wall is formed in the both sides of first nominal grid, the second side is formed in the both sides of second nominal grid
Wall；
Remove first sacrificial layer and second sacrificial layer, with first active region formed the first groove, and
Second active region forms the second groove；
The first side wall barrier layer and p-type workfunction layers, and described are sequentially formed in the inner surface of first groove
One side wall barrier layer also covers the inner surface of second groove；
Second sidewall barrier layer is formed, the second sidewall barrier layer covers the p-type workfunction layers in first groove
Surface and the first side wall barrier layer in second groove surface, then in second sidewall barrier layer table
Face forms N-shaped workfunction layers；And
Top barrier layer and conductive layer are sequentially formed in the N-shaped workfunction metal layer surface, until filling up first groove
With second groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810274081.2A CN108538837A (en) | 2018-03-29 | 2018-03-29 | Semiconductor devices and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810274081.2A CN108538837A (en) | 2018-03-29 | 2018-03-29 | Semiconductor devices and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108538837A true CN108538837A (en) | 2018-09-14 |
Family
ID=63482606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810274081.2A Pending CN108538837A (en) | 2018-03-29 | 2018-03-29 | Semiconductor devices and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108538837A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110931431A (en) * | 2018-09-19 | 2020-03-27 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing semiconductor device |
| CN111987096A (en) * | 2019-05-22 | 2020-11-24 | 台湾积体电路制造股份有限公司 | Gate structure of semiconductor device and forming method thereof |
| CN112542456A (en) * | 2019-09-23 | 2021-03-23 | 格芯(美国)集成电路科技有限公司 | Field effect transistor with independently tuned threshold voltages |
| CN113506801A (en) * | 2021-06-28 | 2021-10-15 | 上海华力集成电路制造有限公司 | Novel metal grid structure and manufacturing method thereof |
| CN113540085A (en) * | 2020-06-29 | 2021-10-22 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| CN113644068A (en) * | 2021-07-20 | 2021-11-12 | 上海华力集成电路制造有限公司 | Novel metal grid structure and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856256A (en) * | 2011-06-29 | 2013-01-02 | 联华电子股份有限公司 | Semiconductor element and manufacture method thereof |
| CN104425575A (en) * | 2013-09-03 | 2015-03-18 | 联华电子股份有限公司 | Metal gate structure and manufacturing method thereof |
| US9018086B2 (en) * | 2012-01-04 | 2015-04-28 | United Microelectronics Corp. | Semiconductor device having a metal gate and fabricating method thereof |
| CN104752447A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN105448918A (en) * | 2014-09-30 | 2016-03-30 | 联华电子股份有限公司 | Complementary metal oxide semiconductor and manufacturing method thereof |
-
2018
- 2018-03-29 CN CN201810274081.2A patent/CN108538837A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856256A (en) * | 2011-06-29 | 2013-01-02 | 联华电子股份有限公司 | Semiconductor element and manufacture method thereof |
| US9018086B2 (en) * | 2012-01-04 | 2015-04-28 | United Microelectronics Corp. | Semiconductor device having a metal gate and fabricating method thereof |
| CN104425575A (en) * | 2013-09-03 | 2015-03-18 | 联华电子股份有限公司 | Metal gate structure and manufacturing method thereof |
| CN104752447A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN105448918A (en) * | 2014-09-30 | 2016-03-30 | 联华电子股份有限公司 | Complementary metal oxide semiconductor and manufacturing method thereof |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110931431A (en) * | 2018-09-19 | 2020-03-27 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing semiconductor device |
| CN110931431B (en) * | 2018-09-19 | 2022-10-11 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing semiconductor device |
| US11749682B2 (en) | 2018-09-19 | 2023-09-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selective dual silicide formation using a maskless fabrication process flow |
| CN111987096A (en) * | 2019-05-22 | 2020-11-24 | 台湾积体电路制造股份有限公司 | Gate structure of semiconductor device and forming method thereof |
| CN111987096B (en) * | 2019-05-22 | 2023-11-17 | 台湾积体电路制造股份有限公司 | Gate structure of semiconductor device and forming method thereof |
| CN112542456A (en) * | 2019-09-23 | 2021-03-23 | 格芯(美国)集成电路科技有限公司 | Field effect transistor with independently tuned threshold voltages |
| CN113540085A (en) * | 2020-06-29 | 2021-10-22 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| CN113540085B (en) * | 2020-06-29 | 2023-11-21 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| CN113506801A (en) * | 2021-06-28 | 2021-10-15 | 上海华力集成电路制造有限公司 | Novel metal grid structure and manufacturing method thereof |
| CN113644068A (en) * | 2021-07-20 | 2021-11-12 | 上海华力集成电路制造有限公司 | Novel metal grid structure and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10109630B2 (en) | Semiconductor device and method of forming the same | |
| US9875901B2 (en) | Manufacturing method of metal oxide semiconductor transistor | |
| US8673758B2 (en) | Structure of metal gate and fabrication method thereof | |
| US8669618B2 (en) | Manufacturing method for semiconductor device having metal gate | |
| CN106684041B (en) | Semiconductor element and manufacturing method thereof | |
| US10199228B2 (en) | Manufacturing method of metal gate structure | |
| US8890218B2 (en) | Semiconductor device | |
| CN108538837A (en) | Semiconductor devices and forming method thereof | |
| CN105448918B (en) | Complementary metal oxide semiconductor and manufacturing method thereof | |
| CN116705613A (en) | Semiconductor element and manufacturing method thereof | |
| US9105623B2 (en) | Semiconductor device having metal gate and manufacturing method thereof | |
| US9496361B1 (en) | Selectively deposited metal gates and method of manufacturing thereof | |
| US9673040B2 (en) | Semiconductor device and method for fabricating the same | |
| TW201705298A (en) | Semiconductor device having metal gate and fabrication method thereof | |
| US10249488B1 (en) | Semiconductor devices with same conductive type but different threshold voltages and method of fabricating the same | |
| US10886395B2 (en) | Method for fabricating tunneling field effect transistor having interfacial layer containing nitrogen | |
| CN102856256B (en) | Semiconductor element and preparation method thereof | |
| TWI446456B (en) | Metal gate transistor and method for fabricating the same | |
| US20190189738A1 (en) | Semiconductor device and method for fabricating the same | |
| TWI569333B (en) | Method for fabricating semiconductor device | |
| TWI515830B (en) | Method for fabricating semiconductor device | |
| TWI582839B (en) | Structure of metal gate structure and manufacturing method of the same | |
| US11227769B2 (en) | Method for fabricating semiconductor device | |
| US20230378167A1 (en) | Semiconductor device and method of fabricating the same | |
| TW201320336A (en) | Metal oxide semiconductor transistor and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180914 |