JP2011210750A - Field effect transistor, method of manufacturing field effect transistor, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor which attains a high threshold voltage and low ON resistance, and in which parallel conduction is suppressed.SOLUTION: The field effect transistor has a buffer layer 602 of group III nitride, a channel layer 603, a barrier layer 605 and a cap layer 606 which are laminated in this order on a substrate 601. An upper surface of each semiconductor layer is a group III atom surface perpendicular to a (0001) crystal axis, the buffer layer 602 is lattice-relaxed, and the barrier layer 605 has tensile strain and the channel layer 603 and cap layer 606 have compressive strain, or the channel layer 603 is lattice-relaxed and the cap layer 606 has tensile strain. The cap layer 606, a gate insulating film 607 and a gate electrode 608 are laminated in this order in a part of a region on the barrier layer 605, and a source electrode 609 and a drain electrode 610 are formed in the other region.

Description

  The present invention relates to a field effect transistor, a method for manufacturing a field effect transistor, and an electronic device.

In recent years, there has been a strong social demand for technological development for energy saving in consideration of global environmental conservation such as global warming prevention measures. Among technological developments, reductions in power consumption of in-vehicle electronic devices mounted on IT equipment, home appliances, products, and automobiles are important because they are directly linked to the reduction of carbon dioxide (CO ₂ ), which is a greenhouse gas.

  Examples of the power supply device include an inverter that generates AC power from DC power and a converter that generates DC power from AC power. Many silicon (Si) transistors have been used for power supply devices. However, a silicon transistor has a large energy loss because both a power loss (on loss) in an energized state and a power loss (switching loss) when switching between an energized state and a cut-off state are relatively large. Therefore, field effect transistors (hereinafter referred to as FETs) having excellent properties such as high breakdown voltage and low on-resistance compared to silicon (Si) transistors have recently been actively used. Research and development is underway. As such a field effect transistor, there are a field effect transistor formed from silicon carbide (SiC) and a field effect transistor formed from a group III nitride semiconductor such as gallium nitride (GaN) or aluminum gallium nitride (AlGaN). is there.

  The SiC or group III nitride semiconductor is a wide band gap semiconductor and a high pressure resistant material. In a transistor composed of such a high withstand voltage material, the distance between the electrodes can be shortened, so that the channel distance can be shortened. As a result, the on-resistance during energization can be reduced, that is, the on-loss can be reduced. Also, for example, when using a III-nitride heterojunction field effect transistor (HEMT), the semiconductor heterojunction interface can be used as a channel, so high channel electron mobility can be utilized, and high-speed operation characteristics Excellent switching loss. When high-speed operation (high-frequency operation) is possible, the inductive element can be reduced in size, and the power supply device can also be reduced in size.

  As a field effect transistor (FET) formed of a group III nitride semiconductor, for example, there is an FET described in Non-Patent Document 1. FIG. 19 shows the structure of this FET. As shown in the figure, this FET is a heterojunction field transistor (commonly known as HEMT: High Electron Mobility Transistor) in which a GaN buffer layer 102 and an n-AlGaN electron supply layer 104 are stacked in the above order on a SiC substrate 101. (Also referred to as a transistor). A part of the n-AlGaN electron supply layer 104 is formed with a three-layer cap layer 105 in which an n-GaN layer 106, an AlN layer 107, and an n-GaN layer 108 are stacked in the above order. An opening (recess) is formed in the vicinity of the center of the three-layer cap layer 105, and reaches the upper portion of the n-AlGaN electron supply layer 104 through the three-layer cap layer 105. The gate insulating film 109 is formed so as to cover the upper surface of the three-layer cap layer 105 and the inside of the opening (recess). The gate electrode 110 is formed so as to fill the opening (recess) with the gate insulating film 109 interposed therebetween. The source electrode 111 and the drain electrode 112 are each formed in a portion where the three-layer cap layer 105 is not formed on the upper surface of the n-AlGaN electron supply layer 104. The source electrode 111 and the drain electrode 112 are arranged to face each other with the three-layer cap layer 105 and the gate electrode 110 interposed therebetween, and are in contact with both side surfaces of the three-layer cap layer 105, respectively. In the GaN buffer layer 102, a channel (energization path) due to the two-dimensional electron gas (2DEG) 103 is generated at the interface with the n-AlGaN electron supply layer 104.

M. Kanamura, T. Ohki, T. Kikkwa, T. Imada, A. Yamada, and N. Hara, “Enhancement-Mode GaN MIS-HEMTs With n-GaN / i-AlN / n-GaN Triple Cap Layer and High -k Gate Dielectrics, ”IEEE Electron Device Letters, Vol. 31, No. 3, pp. 189-191, March 2010.

  On the other hand, in order to increase the power and reduce the loss (energy saving) of an electronic device (electronic device) using a field effect transistor (FET), both a high threshold voltage and a low on-resistance are required. However, the field effect transistor (FET) described in Non-Patent Document 1 cannot achieve both a high threshold voltage and a low on-resistance. Furthermore, in the field effect transistor (FET) of Non-Patent Document 1, there is a possibility that a problem may occur in operation due to parallel conduction in which an unintended energization path is formed. That is, in the case of the device structure of FIG. 19, the energization path indicated by 113 in FIG. 23 is formed by turning on the MIS (MOS) channel. This is parallel conduction. Since this parallel conduction is via the MIS (MOS) channel having a relatively low electron mobility, it leads to a reduction in on-current, an increase in on-resistance, and a reduction in switching speed.

  Accordingly, an object of the present invention is to provide a field effect transistor, a method of manufacturing a field effect transistor, and an electronic device that can achieve both a high threshold voltage and a low on-resistance and can suppress parallel conduction. .

In order to achieve the above object, the first field effect transistor of the present invention comprises:
Including substrate, buffer layer, channel layer, barrier layer, cap layer, gate insulating film, gate electrode, source electrode, and drain electrode,
The buffer layer is formed of lattice-relaxed Al _x Ga _1-x N (0 ≦ x <1),
The channel layer is Al _u Ga _1-u N (0 ≦ u <x) having an Al composition ratio smaller than that of the buffer layer, and Al _x Ga _1-x N (0 ≦ x <1) having the same composition as the buffer layer. Or formed from InGaN,
The barrier layer is made of Al _y Ga _1-y N (x <y ≦ 1) having a larger Al composition ratio than the buffer layer,
The cap layer is formed of Al _z Ga _1-z N (0 ≦ z <y) having a smaller Al composition ratio than the barrier layer,
The upper surface of the buffer layer, the upper surface of the channel layer, the upper surface of the barrier layer, and the upper surface of the cap layer are respectively a Ga plane or an Al plane perpendicular to the (0001) crystal axis,
The buffer layer, the channel layer, and the barrier layer are stacked in the order on the substrate,
The cap layer is formed in a partial region on the barrier layer;
The gate insulating film and the gate electrode are stacked in the order on the cap layer,
The source electrode and the drain electrode are formed on a region on the barrier layer where the cap layer is not formed.

The second field effect transistor of the present invention is
Including substrate, buffer layer, channel layer, barrier layer, cap layer, gate insulating film, gate electrode, source electrode, and drain electrode,
The buffer layer, the channel layer, the barrier layer, and the cap layer are each formed of a group III nitride semiconductor,
The upper surface of the buffer layer, the upper surface of the channel layer, the upper surface of the barrier layer, and the upper surface of the cap layer are each a group III atomic plane perpendicular to the (0001) crystal axis,
The buffer layer is lattice-relaxed;
The barrier layer has tensile strain;
The channel layer and the cap layer both have compressive strain, or the channel layer is lattice relaxed and the cap layer has tensile strain;
The buffer layer, the channel layer, and the barrier layer are stacked in the order on the substrate,
The cap layer is formed in a partial region on the barrier layer;
The gate insulating film and the gate electrode are stacked in the order on the cap layer,
The source electrode and the drain electrode are formed on a region on the barrier layer where the cap layer is not formed.

The first method for producing a field effect transistor of the present invention is as follows.
A semiconductor layer laminating step of laminating a buffer layer, a channel layer, a barrier layer, and a cap layer in the above order on a substrate;
A gate insulating film material forming step of forming a gate insulating film material on the cap layer;
A gate electrode material forming step of forming a gate electrode material on the gate insulating film material;
Forming a gate electrode by removing a part of the gate electrode material; and
A gate insulating film forming step of forming a gate insulating film by removing a part of the gate insulating film material;
A cap layer partial removal step of removing a part of the cap layer;
Forming a source electrode and a drain electrode on the barrier layer on the region where the cap layer has been removed,
In the semiconductor layer stacking step, the buffer layer, the channel layer, the barrier layer, and the cap layer are each grown on a group III atomic plane perpendicular to the (0001) crystal axis,
The buffer layer is formed of lattice-relaxed Al _x Ga _1-x N (0 ≦ x <1),
The channel layer is made of Al _u Ga _1-u N (0 ≦ u <x) having an Al composition ratio smaller than that of the buffer layer, Al _x Ga _1-x N (0 ≦ x <1) having the same composition as the buffer layer. Or formed from InGaN,
The barrier layer is formed of Al _y Ga _1-y N (x <y ≦ 1) having a higher Al composition ratio than the buffer layer,
The cap layer is formed of Al _z Ga _1-z N (0 ≦ z <y) having an Al composition ratio smaller than that of the barrier layer.

The method for producing the second field effect transistor of the present invention comprises:
A semiconductor layer laminating step of laminating a buffer layer, a channel layer, a barrier layer, and a cap layer in the above order on a substrate;
A gate insulating film material forming step of forming a gate insulating film material on the cap layer;
A gate electrode material forming step of forming a gate electrode material on the gate insulating film material;
Forming a gate electrode by removing a part of the gate electrode material; and
A gate insulating film forming step of forming a gate insulating film by removing a part of the gate insulating film material;
A cap layer partial removal step of removing a part of the cap layer;
Forming a source electrode and a drain electrode on the barrier layer on the region where the cap layer has been removed,
In the semiconductor layer stacking step, the buffer layer, the channel layer, the barrier layer, and the cap layer are each grown on a group III atomic plane perpendicular to the (0001) crystal axis,
Forming the buffer layer so as to be lattice-relaxed;
Forming the barrier layer to have tensile strain;
Forming the channel layer and the cap layer so that both the channel layer and the cap layer have compressive strain, or the channel layer is lattice-relaxed and the cap layer has tensile strain. Features.

  The electronic device of the present invention includes the first or second field effect transistor of the present invention or the field effect transistor manufactured by the first or second manufacturing method of the present invention.

  According to the present invention, it is possible to provide a field effect transistor that can achieve both a high threshold voltage and a low on-resistance, and that can suppress parallel conduction, a method for manufacturing the field effect transistor, and an electronic device. .

It is sectional drawing which shows the structure of FET in Embodiment 1 of this invention. FIG. 2 is a conceptual diagram (in the case of gate voltage Vg = threshold voltage _Vth ) of a conduction band potential in an example of the structure of the multilayer epitaxial layer in FIG. 1 (AlGaN buffer type). FIG. 3 is a potential diagram illustrating the energy distribution of a conduction band and a valence band immediately below a gate of a GaN-FET in Embodiment 1 of the present invention. FIG. 3 is a potential diagram illustrating the energy of a conduction band and a valence band in a region other than the gate of the GaN-FET in Embodiment 1 of the present invention. It is a graph which shows the gate insulating film (alumina) thickness dependence of the threshold value _Vth in GaN-FET in Example 1 of this invention. It is sectional drawing which shows the structure of FET in Embodiment 2 of this invention. It is sectional drawing which shows the structure of FET in Embodiment 3 of this invention. It is a potential diagram which illustrates the energy distribution of the conduction band and valence band right under the gate of GaN-FET in Embodiment 3 of this invention. It is an enlarged view of the channel part in FIG. 8A. It is a graph which illustrates distribution of the conduction-band potential and carrier electron concentration in the area | region between a gate electrode and an ohmic electrode of GaN-FET in Embodiment 3 of this invention. It is a graph which illustrates distribution of the conduction band potential and carrier electron concentration in the area | region under an ohmic electrode of GaN-FET in Embodiment 3 of this invention. It is a graph which illustrates the calculation result of the gate insulating film thickness dependence of carrier electron concentration in FET of Embodiment 1 of this invention. It is a graph which illustrates the calculation result of the cap layer thickness dependence of carrier electron concentration in FET of Embodiment 1 of this invention. It is a graph which shows the calculation result of barrier layer Al composition ratio dependence of carrier electron concentration in FET of Embodiment 1 of this invention. It is a graph which illustrates the calculation result of the barrier layer thickness dependence of carrier electron concentration in FET of Embodiment 1 of this invention. It is a graph which illustrates the calculation result of the gate insulating film thickness dependence of carrier electron concentration in the modification of FET of Embodiment 1 of this invention. It is a graph which illustrates the calculation result of the cap layer thickness dependence of carrier electron concentration in the modification of FET of Embodiment 1 of this invention. It is a graph which shows the calculation result of barrier layer Al composition ratio dependence of the carrier electron concentration in the modification of FET of Embodiment 1 of this invention. It is a graph which illustrates the calculation result of the barrier layer thickness dependence of carrier electron concentration in the modification of FET of Embodiment 1 of this invention. 2 is a cross-sectional view showing the structure of MIS GaN-HEMT of Non-Patent Document 1. 20 is a graph illustrating calculation results of a conduction band and a valence band potential directly under a gate in the MIS GaN-HEMT of FIG. 19. 20 is a graph illustrating calculation results of a conduction band potential and a carrier electron concentration distribution in a region between a gate electrode and an ohmic electrode in the MIS GaN-HEMT of FIG. 20 is a graph illustrating calculation results of a conduction band potential and a carrier electron concentration distribution in a region below an ohmic electrode in the MIS GaN-HEMT of FIG. FIG. 20 is a cross-sectional view schematically showing a parallel conduction generation mechanism in the normally-OFF characteristic MIS GaN-HEMT of FIG.

  Hereinafter, the present invention will be described more specifically. However, the present invention is not limited by the following description.

  In the field effect transistor of the present invention, the `` on resistance '' is an electric current between the positive bias application side and the negative bias application side (for example, between the source electrode and the drain electrode) when the voltage is on (voltage application). Say resistance. `` Contact resistance '' refers to the resistance between two parts that are in direct contact.For example, `` ohmic contact resistance '' is when the ohmic electrode (source electrode, drain electrode) is in direct contact with the electron supply layer. The electrical resistance between the ohmic electrode and the electron supply layer.

  In the present invention, in the case of showing the arrangement relationship of each component, unless otherwise specified, “on” may be in a state of directly contacting the upper surface without passing through other components, and other components may be in between. May exist. The same applies to “under”. Further, in the case of showing the arrangement relationship of each component, “on the upper surface” is in a state of being in direct contact with the upper surface without passing through other components. The same applies to “on the bottom surface”.

In the present invention, when n-type impurity (donor impurity) concentration, p-type impurity (acceptor impurity) concentration, carrier concentration, etc. are expressed by volume density (cm ^−3, etc.) Represents the volume density. Similarly, when the n-type impurity concentration, p-type impurity (acceptor impurity) concentration, carrier concentration, etc. are expressed in area density (cm ^-2 etc.), the area density in terms of the number of atoms is expressed unless otherwise specified. .

  In the present invention, the concentration of ionized impurities means a concentration in a state where no voltage is applied to any electrode of the field effect transistor unless otherwise specified.

In the present invention, “composition” and “composition ratio” refer to, for example, the numerical value of x in the semiconductor layer represented by the composition of Al _x Ga _1-x N as “Al composition ratio”. In the present invention, when defining the composition or composition ratio of the semiconductor layer, impurities (dopants) that develop conductivity and the like are not considered as elements constituting the semiconductor layer. For example, a p-type GaN layer and an n-type GaN layer are different in impurity (dopant) but have the same composition. Further, for example, when there are an n-type GaN layer and an n ⁺ GaN layer having a higher impurity concentration, the compositions thereof are assumed to be the same.

  In the present invention, a “main surface” of a substrate, a semiconductor layer or the like refers to a surface having the largest area, for example, a so-called upper surface or lower surface, or front surface or back surface.

  Here, in the FET of the present invention, “lattice relaxation” refers to a state in which the lattice constant of the thin film (each semiconductor layer constituting the FET) matches the lattice constant of the bulk material. In the semiconductor crystal, the “bulk material” refers to a semiconductor crystal in which the effects of the surface, interface, and edge are negligible. Note that the state in which the lattice constant matches the lattice constant of the bulk material may be that the lattice constant exactly matches the lattice constant of the bulk material, but is not exactly the same. May have an error of. The error is preferably within ± 0.1%, more preferably within ± 0.03%, ideally zero. In the present invention, the “lattice-relaxed” layer may be partially lattice-relaxed even if it is not entirely lattice-relaxed. For example, the buffer layer is a lattice-relaxed layer as described above. When the lattice constants of the substrate and the buffer layer are different and there is no layer having a lattice relaxation action between them, the buffer layer has a function of releasing strain energy by the occurrence of dislocation, It is necessary to have a sufficient thickness to reduce the influence. When the buffer layer is sufficiently thick and no other component is laminated thereon, the lattice constant of the outermost surface of the buffer layer (the uppermost lattice plane is the same as the “upper surface”) is This is consistent with that of a bulk semiconductor of the same composition. When a thin film semiconductor layer having the same composition is epitaxially grown on such a buffer layer, generation of new dislocations is suppressed. On the other hand, when the lattice constants of the substrate and the buffer layer are equal, the influence of dislocation can be ignored, but in order to suppress the influence of crystal defects and interface states at the substrate-buffer layer interface, the thickness of the buffer layer The size needs to be large to some extent. The appropriate thickness of the buffer layer is approximately 0.1 to 10 μm, although it depends on the lattice constant difference between the substrate and the buffer layer and the state of the substrate-buffer layer interface.

In the present invention, the “threshold voltage” refers to a gate voltage at a critical point where the carrier concentration in the channel layer becomes positive from 0. In actual GaN-FETs, for the convenience of measurement, the threshold is often defined by the gate voltage at which the drain current density is I _d = 1 mA / mm when the drain voltage V _d = 10 to 15 V is applied. . The threshold voltage in the FET of the present invention may be defined by the same definition. Further, the threshold voltage may be represented by the symbol V _th as described above. In the FET of the present invention, the threshold voltage V _th is not particularly limited, but when the element of the present invention is used as a power control device, it is preferable that 0 V or more, that is, normally OFF operation is possible, and 3 V More preferably, it is 4V or more, more preferably 5V or more, and further preferably 6V or more. The upper limit value of the threshold voltage _Vth is not particularly limited, but is, for example, 10V or 20V.

  Hereinafter, embodiments of the present invention will be described. However, the following embodiment is an illustration and this invention is not limited to these. In the drawings, for convenience of explanation, the structure of each part may be simplified as appropriate, and the dimensional ratio of each part may be different from the actual one. The mathematical formulas, graphs, explanations thereof, and the like are based on the theory, and these show qualitatively or approximately the actual phenomenon in the field effect transistor or the like of the present invention.

  Prior to describing specific embodiments of the FET of the present invention, the related art of the present invention will be described. As a result of verifying or independently researching the FET and the general FET of Non-Patent Document 1, the present inventors have found the following.

First, the FET of Non-Patent Document 1 will be described. As shown in FIG. 19, in the portion where the gate of this FET is formed, a gate recess is formed in the three-layer cap layer and the n-AlGaN electron supply layer, and the n-AlGaN electron supply layer 104 is left slightly. Therefore, according to the theoretical calculation, as shown in the band diagram of FIG. 20, this FET can obtain a normally OFF characteristic (threshold voltage _Vth is a positive value), and has a shielding performance during standby. It is considered that high-speed performance during energization can be obtained. FIG. 20 is a graph (band diagram) illustrating the calculation results of the conduction band and valence band potential directly under the gate in the MIS (Metal-Insulator-Semiconductor) GaN-HEMT of FIG. In the figure, the horizontal axis indicates the distance [Å] in the direction perpendicular to the main surface of the substrate from the lowermost end of the gate electrode 110 downward. Note that 1 mm is equal to 10 ⁻¹⁰ m, that is, 0.1 nm. The vertical axis represents the conductor lower end energy Ec [eV]. From left to right in the figure, the states of the gate insulating film 109 (alumina), the n-AlGaN electron supply layer 104 (n-AlGaN), and the GaN buffer layer 102 (GaN) are shown. “Fermi Level” indicates the Fermi level. The same applies to all band diagrams described below. Further, the calculation shown in FIG. 20 was performed under the condition of the gate voltage V _g = 0. Here, in the calculation of the band diagram, the Schrödinger equation and the Poisson equation were combined to obtain a self-consistent solution. With this method, it is possible to obtain a one-dimensional conduction band / valence band potential that incorporates quantum mechanical effects and carrier concentrations of electrons and holes. Regarding carrier statistics, we adopted two-dimensional quantum statistics for the two-dimensional electron gas (2DEG) and Fermi-Dirac statistics for the bulk electrons and holes. Regarding the polarization effect, the model of ambassador (O. Ambacher, et al., "Pyroelectric properties of Al (In) GaN / GaN hetero- and quantum well structures," Journal of Physics C: Condensed Matter, Vol. 14, pp. 3399-3434 (2002)) and the polarization charge was introduced as a fixed charge. The same calculation method was used for all band diagrams described below.

In the FET of FIG. 19, a three-layer cap structure is applied. Therefore, in the theoretical calculation, between the gate and the ohmic electrode, that is, between the gate and the source (the region between the gate electrode and the source electrode) or between the gate and the drain (the region between the gate electrode and the drain electrode), theoretically, FIG. As shown in the graph, the sum of polarization charges in the epi can be made positive. As a result, sufficient channel carrier electrons are secured between the gate and the ohmic electrode under a bias condition where the gate voltage is zero volt or less (V _g ≦ 0 V), and the on-resistance is reduced. FIG. 21 is a graph illustrating calculation results of the conduction band potential and the carrier electron concentration distribution in the region between the gate electrode and the ohmic electrode in the MISGaN-HEMT of FIG. In the figure, the horizontal axis indicates the distance [Å] perpendicular to the substrate main surface from the outermost surface (upper surface) of the GaN layer 108 downward. Note that 1 mm is equal to 10 ⁻¹⁰ m, that is, 0.1 nm. The vertical axis represents the conductor lower end energy Ec [eV] or the carrier electron concentration [cm ⁻³ ]. From left to right in the figure, n-GaN layer 108 (n-GaN), AlN layer 107 (AlN), n-GaN layer 106 (n-GaN), n-AlGaN electron supply layer 104 (n-AlGaN), And states of the GaN buffer layer 102 (GaN) are shown.

In the FET of FIG. 19, the ohmic electrodes (source electrode 111 and drain electrode 112) are formed in contact with the n-AlGaN electron supply layer 104, as shown. Therefore, in the theoretical calculation, as shown in the graph of FIG. 22, the total sum of the polarization charges in the epi can also be positive here. Therefore, as described in the description of FIG. 21, sufficient channel carrier electrons are secured between the gate and the ohmic electrode under the bias condition where the gate voltage is zero volts or less (V _g ≦ 0 V), and the on-resistance is reduced. Is realized. FIG. 22 is a graph illustrating the calculation results of the conduction band potential and the carrier electron concentration distribution in the region below the ohmic electrode in the MISGaN-HEMT of FIG. In the figure, the horizontal axis indicates the distance [Å] perpendicular to the main surface of the substrate from the bottom end of the ohmic electrode downward. Note that 1 mm is equal to 10 ⁻¹⁰ m, that is, 0.1 nm. The vertical axis represents the conductor lower end energy Ec [eV]. From the left to the right, the n-AlGaN electron supply layer 104 (n-AlGaN) and the GaN buffer layer 102 (GaN) are shown.

Further, in the FET of Non-Patent Document 1, as shown in FIG. 19, a gate insulating film 109 (alumina) is formed between the gate and the ohmic. As a result, it is possible to suppress a gate leakage current in which traveling electrons flow into the gate electrode when energized. Therefore, a positive voltage higher than the turn-on voltage (V _f ) of the gate-Schottky junction can be applied to the FET as the gate voltage. In other words, the presence of the gate insulating film 109 improves the on-current density during energization as compared to the case without the gate insulating film 109.

Here, as described above, an FET formed from a group III nitride semiconductor (hereinafter sometimes simply referred to as a “group III nitride FET”) has a breakdown voltage, an on-resistance, and the like as compared with a silicon transistor. There is an advantage of excellent characteristics. On the other hand, the structure of the currently proposed group III nitride FET has a problem that it is difficult to make the threshold voltage higher than 3V. For example, in the FET structure described in Non-Patent Document 1 (FIG. 19), in principle, the threshold voltage (V _th ) cannot be increased beyond a certain level. Since the epi structure below the gate electrode (directly under the gate) is a simple HEMT structure of n-AlGaN / GaN, positive polarization charges are generated in the epi directly under the gate. Therefore, no matter how thin the n-AlGaN electron supply layer is when the gate recess is formed, the amount of shift of _{Vth in} the positive direction is limited. According to the one-dimensional band calculation including the quantum effect based on the material property values, when the description of Non-Patent Document 1 is interpreted as it is, in the FET structure of Non-Patent Document 1 (FIG. 19), V _th is It is obvious to those skilled in the art that even if it is high, it is only about 1V. Non-Patent Document 1 describes that “the threshold value of the device is 3 V”, which is because negative charges are trapped at the interface between the gate insulating film and the underlying semiconductor. It is thought that. This electric charge is not stably fixed but has a property of being charged and discharged by voltage application. Therefore, the numerical value of the threshold value 3V described in Non-Patent Document 1 is apparent, and it is difficult for this FET to actually operate stably at the threshold voltage 3V.

In power supply applications where a drain voltage of several hundred volts is applied, the threshold voltage (V _th ) of the FET is preferably about 3V or higher. In particular, in order to use a group III nitride FET instead of Si-IGBT (Insulated Gate Bipolar Transistor), V _th = 5 to 6 V or more is often necessary.

In III-nitride FETs with a GaN-HEMT structure, when the gate voltage _Vg is increased, an electron storage type secondary channel is formed in addition to the originally intended energization path (channel). There is. For example, in the FET structure of FIG. 19, as can be seen from the band diagram of FIG. 21, a channel is also formed at the interface between the AlN layer 107 in the three-layer cap and the n-GaN layer 106 below it. Further, when the gate voltage _Vg is increased, an electron storage type secondary is formed directly below the gate (below the gate electrode) at the MIS interface (or MOS interface) between the gate insulating film 109 and the semiconductor 104 as shown in FIG. A typical channel (parallel conduction path) 113 is formed. As a result, parallel conduction between the channel by the 2DEG 103 and the channel 113 occurs. Note that MIS is an abbreviation for Metal-Insulator-Semiconductor, and MOS is an abbreviation for Metal-Oxide-Semiconductor.

When parallel conduction occurs, the parallel conduction path (MIS (MOS) channel 113 in FIG. 23) is modulated instead of modulating the semiconductor heterointerface channel (2DEG103 in FIG. 23), which is the original conduction path. become. Therefore, the sheet electron density in the original energization path is lowered. Here, when the electron mobility of the parallel conduction path (MIS (MOS) interface channel) is relatively high, there is a possibility that the on-current is increased by that amount and the on-resistance is reduced. This is because when parallel conduction occurs, the channel current at the MIS (MOS) interface is added to the current at the semiconductor heterointerface channel. However, when the electron mobility of the MIS (MOS) interface channel is extremely lower than the electron mobility of the semiconductor heterojunction channel (for example, 1/10 or less), when parallel conduction occurs, the on-current decreases, On-resistance increases. Furthermore, the channel mobility of the entire device is determined by the channel mobility at the MIS (MOS) interface with the lower (slower) electron mobility. According to the latest research results published by academic societies, academic papers, etc., in the FET having the structure of FIG. 19, the electron mobility at the MIS (MOS) interface is the highest even at the highest level because of interface scattering. cm ² / Vs]. This figure is an order of magnitude lower than the electron mobility at the semiconductor heterojunction (layer 104/103) interface in the same FET. For this reason, when parallel conduction occurs in this FET, the above-mentioned demerits of channel mobility reduction, on-current reduction, and on-resistance increase occur. The FET of Non-Patent Document 1 (FIG. 19) is originally expected to operate at high speed using the high channel electron mobility (1700 to 2000 [cm ² / Vs]) of the two-dimensional electron gas 103 at the semiconductor heterojunction interface. . However, in practice, the parallel conduction reduces the channel mobility of the device, and hinders high-speed switching operation and reduction of switching loss.

  As a result of finding out such a problem and repeating researches, the present inventors have reached the present invention.

[Embodiment 1]
Hereinafter, the FET according to the first embodiment of the present invention will be described. The cross-sectional view of FIG. 1 schematically shows the structure of this FET. The FET shown in the figure is an example of the first field effect transistor of the present invention and also an example of the second field effect transistor of the present invention. The modification of the present embodiment and the field effect transistors (FETs) of the other embodiments are also examples of the first field effect transistor of the present invention, and the second electric field of the present invention. It is also an example of an effect transistor.

As shown in FIG. 1, the FET includes a substrate 601, a buffer layer 602, a channel layer 603, a barrier layer 605, a cap layer 606, a gate insulating film 607, a gate electrode 608, a source electrode 609, and a drain electrode 610. The buffer layer 602 is made of lattice-relaxed Al _x Ga _1-x N (0 ≦ x <1). The channel layer 603 includes Al _u Ga _1-u N (0 ≦ u <x) having a smaller Al composition ratio than the buffer layer, and Al _x Ga _1-x N (0 ≦ x <1) having the same composition as the buffer layer. ) Or InGaN. The barrier layer 604 is made of Al _y Ga _1-y N (x <y ≦ 1) having a larger Al composition ratio than the buffer layer 602. The cap layer 606 is made of Al _z Ga _1-z N (0 ≦ z <y) having a smaller Al composition ratio than the barrier layer 604. The upper surface of the buffer layer 602, the upper surface of the channel layer 603, the upper surface of the barrier layer 605, and the upper surface of the cap layer 606 are respectively a Ga plane or an Al plane perpendicular to the (0001) crystal axis. On the substrate 601, the buffer layer 602, the channel layer 603, and the barrier layer 605 are stacked in the above order. The cap layer 606 is formed in a partial region on the barrier layer 605. On the cap layer 606, the gate insulating film 607 and the gate electrode 608 are stacked in the above order. The source electrode 609 and the drain electrode 610 are formed on a region on the barrier layer 605 where the cap layer 606 is not formed. In the FET in the figure, the source electrode 609 and the drain electrode 610 are formed so as to face each other with the gate electrode 608 interposed therebetween. In the channel layer 603, a channel (energization path) is formed by 2DEG 604 at the interface with the barrier layer 605. In addition, the FET in the figure further includes a surface protective film 611 formed of an insulator. The surface protection film 611 includes a top surface of the barrier layer 605 between the gate and the source and between the gate and drain, the side surface of the cap layer 606 adjacent thereto, the side surface of the gate insulating film 607, the side surface of the gate electrode 608, the side surface of the source electrode 609, and the drain electrode 610. It is formed so as to cover the side surface. In the FET of the present invention, the surface protective film may be omitted, but it is preferable to have a surface protective film as shown in FIG.

  1 has a configuration, the buffer layer 602 is lattice-relaxed, and the barrier layer 605 has tensile strain. Further, both the channel layer 603 and the cap layer 607 have compressive strain, or the channel layer 603 is lattice-relaxed and the cap layer 606 has tensile strain. The upper surface of the buffer layer 602, the upper surface of the channel layer 603, the upper surface of the barrier layer 605, and the upper surface of the cap layer 606 are each a group III atomic plane perpendicular to the (0001) crystal axis.

It said first field effect transistor of the present invention, for example, the Al composition ratio x of the buffer layer is, 0 <meet x <1, wherein the channel layer is less Al _u Ga ₁ Al composition ratio than that of the buffer layer Preferably, the cap layer is made of _-uN (0 ≦ u <x) or InGaN, and the Al composition ratio z of the cap layer is smaller than the Al composition ratio x of the buffer layer (0 ≦ z <x). In this case, the Al composition ratio x of the buffer layer is preferably 0.05 or more and 0.2 or less from the viewpoint of further optimization of the threshold voltage V _th and further improvement of the on-resistance. The Al composition ratio y of the barrier layer is preferably 0.2 or more and 1 or less from the viewpoint of further improvement of carrier confinement and further improvement of on-resistance. The Al composition ratio u of the channel layer is preferably 0.1 or less from the viewpoint of further improving the electron mobility. The Al composition ratio z of the cap layer is also preferably 0.1 or less from the viewpoint of further improving the electron mobility. The channel layer is particularly preferably made of gallium nitride (GaN). The cap layer is particularly preferably formed from gallium nitride (GaN). The cap layer is preferably non-doped (undoped), but may contain an n-type impurity or a p-type impurity.

As another example of the first field effect transistor of the present invention, the channel layer is formed of Al _x Ga _1-x N (0 ≦ x <1) or InGaN having the same composition as the buffer layer, At least one of the semiconductor layers formed below the gate electrode may be a p-type layer. In this case, at least one of the buffer layer and the channel layer may be the p-type layer. In this case, the Al composition ratio y of the barrier layer is preferably 0.2 or more and 1 or less from the viewpoint of further improvement of carrier confinement and further improvement of on-resistance. The Al composition ratio x of the buffer layer is preferably 0.2 or less from the viewpoint of further improving the electron mobility. The Al composition ratio z of the cap layer is also preferably 0.2 or less from the viewpoint of further improving the electron mobility. The buffer layer is particularly preferably formed from lattice-relaxed GaN. The channel layer is more preferably formed of GaN or InGaN, and particularly preferably formed of GaN. The cap layer is particularly preferably made of GaN. If etching conditions are appropriately selected, GaN tends to increase the dry etching rate as compared with other group III nitride semiconductors containing Al. For this reason, when the cap layer is formed of GaN, a part of the cap layer is easily removed by etching (selective etching). The cap layer is preferably non-doped (undoped), but may contain an n-type impurity or a p-type impurity. Further, when the cap layer is formed of GaN, the surface density (ξ _c / q [cm ⁻² ]) of ionized p-type impurities in the p-type layer and the Al composition of the barrier layer It is preferable that the ratio y satisfies the following formula (A) because a normally OFF operation is possible.

ξ _c /q<5.25×10 ¹³ y (A)

  In the second field effect transistor of the present invention, for example, it is preferable that both the channel layer and the cap layer have compressive strain. In this case, the buffer layer may be formed of, for example, GaN, AlGaN, InGaN, InAlN, or InAlGaN. The channel layer forming material may have a smaller band gap than the buffer layer forming material. For example, the channel layer may be formed of InGaN, InAlN, InAlGaN, or InN. The material for forming the barrier layer may have a larger band gap than the material for forming the buffer layer. For example, the barrier layer may be made of AlGaN, AlN, InGaN, InAlN, InAlGaN, or GaN. The material for forming the cap layer may have a smaller band gap than the material for forming the buffer layer. For example, the cap layer may be made of InGaN, InAlN, InAlGaN, or InN.

  As another example of the second field effect transistor of the present invention, the channel layer is lattice-relaxed, the cap layer has tensile strain, and a semiconductor layer formed below the gate electrode At least one of them may be a p-type layer. In this case, the buffer layer may be made of, for example, GaN, AlGaN, InGaN, InAlN, InAlGaN, or InN. The channel layer may be formed of, for example, GaN, AlGaN, InGaN, InAlN, InAlGaN, or InN. The material for forming the barrier layer may have a larger band gap than the material for forming the buffer layer. For example, the barrier layer may be made of AlGaN, AlN, InGaN, InAlN, InAlGaN, or GaN. The material for forming the cap layer may have a smaller band gap than the material for forming the barrier layer. For example, the cap layer may be made of GaN, AlGaN, InGaN, InAlN, InAlGaN, or InN.

In the first or second field effect transistor of the present invention, an n-type impurity-containing region is formed at least partly below the source electrode and the drain electrode, and the n-type impurity-containing region is at least It is preferable that a part of the barrier layer is included. Thereby, the resistance component resulting from the conduction band barrier formed by the barrier layer is reduced, and the effect of further reducing the contact resistance can be obtained. The n-type impurity concentration in the n-type impurity-containing region is, for example, 1 × 10 ¹⁷ (1E17) cm ⁻³ or more, preferably 1 × 10 ¹⁸ (1E18) cm ⁻³ or more, more preferably 1 × 10. ¹⁹ (1E19) cm ⁻³ or more. The upper limit value of the n-type impurity concentration in the n-type impurity-containing region is not particularly limited, but is, for example, 1 × 10 ²³ (1E23) cm ⁻³ or less.

  In the first or second field effect transistor of the present invention, the thickness of the barrier layer is not particularly limited, but from the viewpoint of further improving carrier confinement and maintaining the crystal quality of the barrier layer, It is preferably 10 nm or less.

  The method for producing the first or second field effect transistor of the present invention is not particularly limited, but is preferably produced by the first or second production method of the present invention. In the first or second production method of the present invention, the order of performing each step is not particularly limited, and may be simultaneous or sequential. The formation method of each layer is not particularly limited, and for example, a metal organic chemical vapor deposition (abbreviated as MOCVD) method, an atomic layer deposition (ALD) method, or the like can be used as appropriate. The method for removing each layer is not particularly limited, and for example, wet etching, dry etching, or the like can be used as appropriate.

  In the first or second manufacturing method of the present invention, for example, first, an epitaxial wafer epitaxially grown up to the cap layer is prepared, and then the cap layer in the ohmic electrode formation region and the gate-ohmic electrode region is removed (hereinafter, referred to as the following). (Sometimes called “recesses outside the gate”). Other than this, the first or second field effect transistor of the present invention uses, for example, a method in which the barrier layer is formed by epitaxial growth and then the cap layer is formed by regrowth only at the portion where the gate electrode is formed. May be manufactured. However, since it is easier to control the manufacturing conditions without using regrowth, it is preferable to manufacture the first or second manufacturing method of the present invention. More specifically, the first or second production method of the present invention can be performed, for example, by the method described in Examples described later.

Note that the FET of Non-Patent Document 1 needs to be manufactured by forming a gate recess (an opening in which the gate electrode and the gate insulating film are embedded), as is apparent from the structure of FIG. In contrast, the first or second field effect transistor of the present invention may be manufactured by forming a gate recess, but has an advantage that it can be manufactured without forming a gate recess. If manufactured without forming the gate recess, for example, the following effects (a) to (d) are obtained.

(a) The threshold voltage (V _th ) does not vary due to variations in the recess etching depth.
(b) The recess etching does not increase the roughness of the semiconductor on the bottom surface of the gate recess, and does not disturb the stoichiometry.
(c) Due to the above (b), interface states are not easily formed at the interface between the gate insulating film (607 in FIG. 1) and the barrier layer (605 in FIG. 1), and electron traps and emission are less likely to occur. For this reason, the hysteresis of the IV characteristics of the FET and the occurrence of the shift of the gate voltage in the plus / minus direction are suppressed, and IV and CV characteristics that are very close to the ideal characteristics can be obtained.
(d) The cap layer can be made extremely thin (for example, 2 nm). Thereby, MIS (MOS) channel electron accumulation can be suppressed.

  Here, in the first or second field effect transistor of the present invention, parallel conduction is suppressed as described above. Hereinafter, the effect obtained by suppressing parallel conduction will be specifically described.

The first or second field effect transistor of the present invention has a cap on the barrier layer (605 in FIG. 1) between the gate and the ohmic electrode (region between the gate electrode and the ohmic electrode) and below the ohmic electrode. There is no layer (606 in FIG. 1). Therefore, the first or second field effect transistor of the present invention does not form a parallel conduction path even when the gate voltage _Vg is increased, and this secondary channel is the FET (see FIG. No parallel conduction occurs as in 19). Therefore, the channel is only a two-dimensional electron gas (604 in FIG. 1) at the semiconductor heterojunction interface (interface of the layers 605 and 603 in FIG. 1), and the channel electron mobility inherent in the HEMT structure (for example, 1700 to 2000 [ cm ² / Vs]) is not sacrificed. For this reason, the high frequency operation of the FET and the on-resistance of the channel can be reduced. Further, the first or second field effect transistor of the present invention may have a structure in which no gate electrode is present except above the intrinsic channel (the portion where the two-dimensional electron gas actually travels). In this case, the gate electrode is a gate electrode portion other than the field plate portion when a field plate structure is applied. According to such a structure, it is possible to remove as much as possible the parasitic gate capacitance of the portion composed of the laminated structure of the gate electrode, the gate insulating film, and the semiconductor, and to minimize the channel charging delay τ _c . This further increases the switching speed in the first or second field effect transistor of the present invention. Since the first or second field effect transistor of the present invention has a high switching speed and a low on-resistance, if it is used in a power supply device or the like, switching loss can be reduced and the device can be downsized.

In general, the FET switching delay (the reciprocal of the switching speed) is the sum of the intrinsic FET delay and the FET parasitic delay. Further, the delay of the intrinsic FET is divided into an intrinsic delay τ _i , a drain delay τ _d , and a charge delay τ _c , and the delay of the FET parasitic part is composed of a parasitic resistance delay τ _R and a delay τ _LC due to parasitic reactance. Usually, about 60% of the delay of the FET is the delay of the intrinsic FET, and more than two-thirds is the intrinsic delay τ _i . This intrinsic delay τ _i is proportional to the reciprocal of the channel electron mobility. FET switching speed is not only determined by channel electron mobility, but improving channel electron mobility will most effectively increase FET switching speed and reduce channel on-resistance. Can do.

Further, in the first or second field effect transistor of the present invention, for example, the cap layer (606 in FIG. 1) is as thin as possible from the viewpoint of carrier accumulation in the channel and further improvement of on-resistance. Is preferred. The thickness of the cap layer is preferably 1 nm or more and 20 nm or less, more preferably 1 nm or more and 5 nm or less, and further preferably 1 nm or more and 3 nm or less, for example, 2 nm. . By making the cap layer as thin as possible, the amount of sheet charge (electrons accumulated at the interface with the gate insulating film in the cap layer) stored in the MIS (MOS) channel when the FET is on is suppressed as much as possible. be able to. As a result, when the gate voltage _Vg is increased in the positive direction, it is possible to prevent the semiconductor heterojunction interface channel from being modulated due to the accumulation of electrons in the MIS (MOS) channel as much as possible. Furthermore, any chance, even the gate voltage V _g as applied to the extreme forward direction or device operation voltage, if the thickness of the cap layer is thin, prevented to the utmost sheet the amount of electric charge stored in the MIS (MOS) channel Is possible.

The first or second field effect transistor according to the present invention includes, for example, a negative polarization charge at a heterojunction interface between the channel layer and the buffer layer, or ionized p contained in the channel layer or the buffer layer. It has a negative fixed charge of -type impurity (ionization acceptor). Due to these negative charges, the first or second field effect transistor of the present invention can realize a normally-off threshold voltage of V _th = 5 to 6 V, for example, without digging a gate recess. This is a specification that can be used in place of (replaces) Si-IGBT. However, this description does not limit the present invention. For example, the first or second field effect transistor of the present invention can be manufactured by digging a gate recess as described above. V _th = 5 to 6 V is an example of a suitable numerical value, and is not limited to this.

  Hereinafter, the theoretical calculation is used to determine how the first or second field effect transistor of the present invention can realize a high threshold voltage and effectively suppress MIS (MOS) channel electron accumulation. I will explain. However, these are examples and do not limit the present invention. Further, as described above, the mathematical formulas, graphs, explanations thereof, and the like are based on the theory, and these qualitatively represent the actual phenomenon in the first or second field effect transistor of the present invention. Or it shows approximately.

  First, as described above, the first or second field effect transistor of the present invention has a group III atomic plane perpendicular to the (0001) crystal axis (in the first field effect transistor, the (0001) crystal axis It has a multi-layer structure of a group III nitride semiconductor having a vertical Ga plane or Al plane) as an upper surface. The first or second field effect transistor of the present invention can be, for example, a GaN-FET using GaN (gallium nitride) and AlGaN (aluminum gallium nitride). More specifically, for example, a channel (energization path) can be formed by an AlGaN / GaN heterojunction using AlGaN as the barrier layer and GaN as the channel layer. The AlGaN barrier layer functions as an electron supply layer, and the GaN channel layer functions as an electron transit layer.

In the first or second field effect transistor of the present invention, the buffer layer, the channel layer, and the barrier layer are stacked in the above order on the substrate. In addition to the buffer layer, the channel layer, and the barrier layer, other semiconductor layers may or may not be included. Hereinafter, when the first or second field effect transistor of the present invention is described, the whole or a part of the laminated structure of the semiconductor layer including the buffer layer, the channel layer, and the barrier layer is simply referred to as “epi. Sometimes referred to as “layer”. Further, when clearly showing whether it is a part or the whole of the epi layer, it may be referred to as “a part of the epi layer”, “the whole epi layer” or the like. In the epilayer, for example, positive polarization charges (natural polarization and piezoelectric polarization) are generated at the heterojunction interface of the AlGaN / GaN channel. For this reason, in order to make it easier for the FET to obtain a normally OFF characteristic (threshold voltage V _th > 0 V), as described in detail below, the sum of polarization charges or fixed charges of the entire epi layer should be negative. Is preferred.

  Here, a general fact (physical law) about the generation of polarization charge (interface charge) accompanying the polarization effect in the AlGaN heterojunction will be described.

When grown to lattice relaxation (0001) plane Al _x Ga _1-x N layer on the Al _x Ga _1-x N low Al composition ratio than AlaGa _1-a N layer _{(a <x), Al a} Ga 1 _-a Compressive strain is applied to the N layer to generate polarization charge (interface charge) due to piezoelectric polarization. Furthermore, since the difference in spontaneous polarization is added as polarization charge (interface charge), a negative charge with surface density (-σ _a ) is generated on the substrate side of the Al _a Ga _1-a N layer, and the surface side ( A positive charge having _a surface density (+ σ _a ) is generated on the opposite side of the substrate. Here, the absolute value σa of the polarization charge increases almost in proportion to the difference (xa) in the composition ratio. That is, σ _a is approximately expressed as the following formula (B). In the following formula (B), q is an elementary charge, and q = 1.60219 × 10 ⁻¹⁹ C. The same applies to the following formulas unless otherwise specified.

σ _a / q [cm ^-2 ] = 5.25 × 10 ¹³ × (xa) (B)

Even when another semiconductor layer is inserted between the Al _x Ga _1-x N layer and the Al _a Ga _1-a N layer, as long as the semiconductor layer is not lattice-relaxed, the same polarization charge (interface) Charge) is generated.

On the other hand, when grown to lattice relaxation (0001) plane Al _x Ga _1-x N layer on the Al _x Ga _1-x N high Al composition ratio than Al _b Ga _1-b N layer (x <b), In the Al _b Ga _1-b N layer, tensile strain acts to generate a polarization charge (interface charge) due to piezoelectric polarization. Furthermore, since the difference in spontaneous polarization is added as a polarization charge (interface charge), a positive charge having a surface density (+ σ _b ) is generated on the substrate side of the Al _b Ga _1-b N layer, and the surface side ( A negative charge having an areal density (−σ _b ) is generated on the opposite side of the substrate. Here, the absolute value σ _b of the polarization charge increases almost in proportion to the difference (bx) in the composition ratio. That is, σ _b is approximately expressed as the following formula (C).

σ _b / q [cm ^-2 ] = 5.25 × 10 ¹³ × (bx) (C)

Even when another semiconductor layer is inserted between the Al _x Ga _1-x N layer and the Al _b Ga _1-b N layer, as long as the semiconductor layer is not lattice-relaxed, the same polarization charge (interface) Charge) is generated.

  In order to make the total polarization charge or fixed charge of the entire epilayer negative, for example, first, a method in which a negative polarization charge is generated at the heterointerface between the channel layer and the buffer layer and used. (Case A below), second, a method of doping a p-type impurity in the channel layer or buffer layer (Case B below), and third, a method of employing an InGaN cap layer (Case C below), etc. Conceivable. Hereinafter, these will be described in the above order.

[Case A. Type using AlGaN buffer layer]
For the type of FET that uses AlGaN as the buffer layer and uses negative polarization charge at the hetero interface of the GaN channel layer / AlGaN buffer layer, the epi structure shown in Table 1 is assumed directly under the gate (below the gate electrode) Then, consider the threshold voltage V _{th of the} FET. In the following theoretical calculation, it is assumed that the polarization charge on the surface of the semiconductor is zero by being compensated by the charge induced in the electrode, the surface protective film, or the like. Further, based on the tendency verified by the experimental results, it is assumed that the polarization charge in the back surface of the buffer layer and in the buffer layer is compensated in the process of relaxing the buffer layer.

Here, in Table 1, the thickness of the gate insulating film is T _f , the relative dielectric constant is ε _f , the thickness of the cap layer is T _s , the relative dielectric constant is ε _s , and the thickness of the barrier layer is T _h , The relative dielectric constant is ε _h , the channel layer thickness is T _c , the relative dielectric constant is ε _c , the buffer layer thickness is sufficient for lattice relaxation, and the relative dielectric constant is ε _b . The interface polarization density was assumed to be zero between the gate insulating film and the cap layer, and was assumed to be −σ _s between the cap layer and the barrier layer, σ _h between the barrier layer and the channel layer, and −σ _c between the channel layer and the buffer layer. Further, the discontinuity of the conduction band bottom potential is expressed as ΔEc3 between the gate insulating film and the cap layer, ΔEc2 between the cap layer and the barrier layer, ΔEc1 between the barrier layer and the channel layer, and ΔEc0 between the channel layer and the buffer layer. Note that the use of an AlGaN buffer structure makes it easier to obtain normally-OFF characteristics in GaN-FETs, as described in T. Inoue et al., “Polarization Engineering on Buffer Layer in GaN-Based Heterojunction FETs,” IEEE Trans. Electron Devices , Vol.55, No.2, pp.483-488, Feb.2008.

The AlGaN of the buffer layer is Al _x Ga _1-x N where the Al composition ratio is x (0 <x <1). The AlGaN of the barrier layer is Al _y Ga _1-y N where the Al composition ratio is y. In order for the hetero interface between the Al _y Ga _1-y N barrier layer and the GaN channel layer to function effectively as a channel, the Al composition ratio y is larger than x and x <y ≦ 1. Accordingly, 0 <σ _h −σ _c, that is, the total polarization charge of the entire epilayer is positive between the gate and ohmic electrodes and immediately below the ohmic electrodes (source and drain electrodes). As a result, the heterointerface channel between the Al _y Ga _1-y N barrier layer and the GaN channel layer is ON at V _g = 0 V, that is, normally ON, between the gate and the ohmic electrode and directly below the ohmic electrode (below the ohmic electrode). It becomes a state. Here, the AlGaN of the cap layer is Al _z Ga _1-z N where the Al composition ratio is z.

As an example of the simplest structure, consider the case where all epitaxial layers in the epi layer are non-doped. The conduction band potential below the gate (below the gate electrode) is as shown in the overview diagram of FIG. 2 when V _g = V _th . In the figure, in order from the left side, the gate insulating film (Al ₂ O _3), the cap layer _{(Al z Ga 1-z N} ), the barrier layer _{(Al y Ga 1-y N} ), the channel layer (GaN) and the buffer layer The state of (Al _x Ga _1-x N) is shown. In the figure, other symbols and the like are as shown in Table 1 and the description thereof, for example. Here, when F is the electric field strength and qΦ _B (q: elementary electric quantity) is the potential barrier between the gate electrode and the gate insulator and the threshold voltage V _th is expressed, V _th does not depend on the distance T _c and the following formula As shown in (1).

qV _th = -ΔEc3 + ΔEc2-ΔEc1 + qΦ _B ― F _f T _f -F _s T _s -F _h T _h [eV] (1)

When the system is in an equilibrium state, the sum of the charge induced in the gate electrode and the polarization charge in the epi (an arithmetic sum considering ±) becomes zero from the charge neutral condition. By utilizing this, by applying Gauss's theorem between polarization charges, each electric field F can be easily written down as in the following formulas (2) to (5), for example. In the following equations, ε _o is a vacuum dielectric constant.

F _f = -q (σ _s + σ _c -σ _h ) / ε _o ε _f (2)
F _s = -q (σ _s + σ _c -σ _h ) / ε _o ε _s (3)
F _h = q (σ _h -σ _c ) / ε _o ε _h (4)
F _c = -qσ _c / ε _o ε _c (5)

Based on the formulas (1) to (5), V _th is expressed as the following formula (6).

qV _th = -ΔEc3 + ΔEc2-ΔEc1 + qΦ _B
+ (q / ε _o ) (σ _s + σ _c -σ _h ) (T _f / ε _f + T _s / ε _s ) + (q / ε _o ) (σ _c -σ _h ) T _h / ε _h ( 6)
= -ΔEc3 + ΔEc2-ΔEc1 + qΦ _B
+ (q / ε _o ) σ _s (T _f / ε _f + T _s / ε _s ) + (q / ε _o ) (σ _c -σ _h ) (T _f / ε _f + T _s / ε _s + T _h / ε _h ) (7)

Here, the effective distances T ₁ and T ₂ are defined as in the following formulas (8) and (9).

T ₁ ≡ T _f / ε _f + T _s / ε _s (8)
T ₂ ≡T _f / ε _f + T _s / ε _s + T _h / ε _h (9)

According to this, V _th can be expressed more clearly as the following formula (10).

qV _th = -ΔEc3 + ΔEc2-ΔEc1 + qΦ _B + (q / ε _o ) σ _s T ₁ + (q / ε _o ) (σ _c -σ _h ) T ₂ (10)

Next, the contribution of various physical parameters to _Vth is classified by the sum of polarization charges (σ _h -σ _s -σ _c ), and the Al composition ratio z of the Al _z Ga _1-z N cap layer falls within the range. On the other hand, a condition suitable for the FET to exhibit a normally OFF characteristic or to exhibit a higher threshold voltage _Vth will be verified.

[A- (1). When total polarization charge (σ _h -σ _s -σ _c )> 0]
When the Al composition ratio z of the Al _z Ga _1-z N cap layer is larger than the Al composition ratio x of the Al _x Ga _1-x N buffer layer and x <z ≦ 1, the sum of polarization charges in the epi (σ _h -σ _s -σ _c ) becomes positive. If the total sum of polarization charges in epi (σ _h -σ _s -σ _c ) is positive, an electric field is applied to the gate insulating film from the back to the front, so from the formula (6), the gate insulating film and the cap layer As the thicknesses T _f and T _s increase, V _th shifts in the negative direction. Conversely, _Vth shifts in the positive direction as the thicknesses T _f and T _s of the gate insulating film and the cap layer are reduced. However, it is preferable that the thickness of the gate insulating film is not too thin so as not to cause deterioration of the gate breakdown voltage. In addition, there is a limit to thinning the cap layer.

[A- (2). Total polarization charge (σ _h -σ _s -σ _c ) <0]
When the Al composition ratio z of the Al _z Ga _1-z N cap layer is smaller than the Al composition ratio x of the Al _x Ga _1-x N buffer layer and 0 ≦ z <x, the sum of polarization charges in the epi (σ _h -σ _s -σ _c ) becomes negative. In order for the device to actually be normally OFF, V _th > 0V must be satisfied. The threshold voltage V _th needs to be calculated in consideration of the ΔEc and [Phi _B. If the sum of the polarization charges of the entire epi (σ _h -σ _s -σ _c ) is negative, an electric field is applied from the front to the back of the gate insulating film, so from the formula (6), the gate insulating film and the cap layer As the thicknesses T _f and T _s increase, V _th shifts in the positive direction. This can be used to increase the FET threshold V _th to, for example, V _th = + 5 to +6 V or higher.

Therefore, in order for the first or second field effect transistor of the present invention to have a normally OFF characteristic (enhancement mode), the sum of polarization charges (σ _h −σ _s −σ _c ) <0 may be satisfied. preferable. However, it is preferable not to make the gate insulating film thickness too large from the viewpoint of preventing a decrease in mutual conductance (g _m ) due to a decrease in intrinsic gate capacitance. Therefore, the thickness of the gate insulating film is preferably not less than 30 nm and not more than 70 nm from the viewpoint of achieving both forward breakdown voltage maintenance and g _m maintenance.

When GaN is adopted as the cap layer (Al _z Ga _1-z N) (z = 0), when the device structure outside the gate (between the gate and ohmic and directly under the ohmic electrode) is formed by recess etching or the like, Selective etching can be applied to the Al _y Ga _1-y N barrier layer of the GaN cap layer. This is a great merit in actual device fabrication. When the cap layer Al _z Ga _1-z N is i-GaN, since ΔE _c2 = ΔE _c1 and σ _s = σ _h , the threshold voltage V _th is simplified as shown in the following formula (11). Can be expressed.

qV _th = -ΔE _c3 + qΦ _B + (q / ε _o ) σ _h T ₁ + (q / ε _o ) (σ _c -σ _h ) T ₂
= -ΔE _c3 + qΦ _B- (q / ε _o ) σ _h T _h / ε _h + (q / ε _o ) σ _c T ₂ (11)

In the equation (11), the term (q / ε _o ) σ _h T _h / ε _h represents the contribution of the barrier layer thickness and the channel polarization charge to V _th , and (q / ε _o ) σ _c T ₂ This term indicates the contribution of the buffer layer polarization charge to _Vth . Based on the equation (11), in order to shift V _th in a more positive direction, from the term (q / ε _o ) σ _h T _h / ε _h , the thinner barrier layer is preferable, and the channel The polarization σ _h is preferably smaller, that is, the Al composition ratio of the barrier layer is preferably lower. Further, from the term of (q / ε _o ) σ _c T ₂ , it is preferable that the buffer layer polarization charge σ _c is larger, that is, the Al composition ratio of the buffer layer is higher.

However, the barrier layer thickness T _h is preferably not too thin. When the barrier layer thickness T _h is moderate, the channel is too close to the outermost surface (upper surface) of the epi between the gate and ohmic, and the channel electrons are affected by the uppermost surface (upper surface) of the epi. This is because it is easy to prevent current collapse from occurring. Further, the Al composition ratio y of the Al _y Ga _1-y N barrier layer is preferably not too low. If y is not too low, the channel electron concentration will be too low due to the decrease in positive polarization charge induced in the hetero interface channel of the Al _y Ga _1-y N barrier layer / GaN channel layer (that is, the off breakdown voltage is Increase, but the on-current decreases and the on-resistance increases). Also, increasing the Al composition ratio x of the buffer layer, Al _y Ga _1-y Al to ensure a positive polarization charge induced in the hetero interface channel N barrier layer / GaN channel layer _y Ga _1-y N It is necessary to increase the Al composition ratio y of the barrier layer accordingly. The Al composition ratio y is preferably 30% (0.3) or less from the viewpoint of epi growth. If the range of the Al composition ratio y is y ≦ 0.3, even when mass-producing FETs using MOCVD for epi growth, the ternary Al _y Ga _1-y N (1 <y <1 and AlN It is easy to grow stably. Further, if y ≦ 0.3, the film thickness that can be grown without causing lattice defects or dislocations (so-called critical film thickness) is not too small, which is preferable from the viewpoint of film thickness tolerance.

  On the other hand, when binary AlN is used for the barrier layer, alloy scattering given to channel electrons is reduced, the sheet / channel electron concentration of the AlN / GaN channel is maximized, the on-current density is maximized, and the on-resistance is minimized. It is preferable from the viewpoint of having merit such as. The critical film thickness of AlN varies depending on various conditions, but is about 2 nm on GaN, for example. However, this numerical value is an example and does not limit the present invention.

[A- (3). When total polarization charge (σ _h -σ _s -σ _c ) = 0]
In the case where the cap layer Al _z Ga _1-z N has the same composition as the buffer layer Al _x Ga _1-x N, that is, x = z, σ _s = σ _h -σ _c The sum (σ _h −σ _s −σ _c ) becomes zero when σ _h −σ _s −σ _c = 0. In this case, from the formula (6), V _th is expressed as the following formula (12).

qV _th = -ΔE _c3 + ΔE _c2 -ΔE _c1 + qΦ _B + (q / ε _o ) (σ _c -σ _h ) T _h / ε _h (12)

According to the equation (12), V _th does not depend on the thickness of the gate insulating film or the cap layer. The potential characteristic in this case is that the total polarization charge of the entire epi is zero, so when the gate voltage is zero (V _g = 0V), no electric field is applied to the gate insulating film and cap layer, and the gate insulating film and cap The conduction band potential of the layer becomes horizontal (flat band). Thereby, even if the cap layer thickness and the gate insulating film thickness are changed by the manufacturing process, _Vth does not change. That is, _Vth is stable and the manufacturing process can be easily controlled even if the cap layer thickness of the FET and the gate insulating film thickness are not strictly controlled. However, in this case, the Al composition ratio z of the Al _z Ga _1-z N cap layer is smaller than the Al composition ratio x of the Al _x Ga _1-x N buffer layer, and 0 ≦ z <x. As the thicknesses T _f and T _s of the insulating film and the cap layer are increased, V _th does not shift in the positive direction. From this viewpoint, in this case, there is a limit to the increase in the threshold voltage V _th of the FET.

[Case B. Type using p-GaN channel layer or p-GaN buffer layer]
In Case A above, the case where AlGaN is used for the buffer layer and negative polarization charge at the heterointerface between the GaN channel layer and the AlGaN buffer layer is used mainly for the purpose of giving the GaN-FET normally OFF characteristics. . In this case, a device structure will be described in which GaN is used for the buffer layer and p-type impurities are doped in the channel layer or the buffer layer to give the GaN-FET normally OFF characteristics. An epiwafer using GaN as a buffer layer may be less likely to warp (strain) than a wafer using AlGaN as a buffer layer depending on the growth conditions of the epitaxial multilayer. However, by using the p-type impurity doping instead of the polarization charge due to strain, for example, a normally OFF operation can be performed.

In the following, the epi structure shown in Table 2 below is assumed. In order for the Al _y Ga _1-y N barrier layer to function effectively as a barrier layer, the Al composition ratio z of the Al _z Ga _1-z N cap layer is equal to the Al composition ratio _y of the Al _y Ga _1-y N barrier layer. And 0 ≦ z <y.

Assume that a channel layer or buffer layer made of GaN is doped with an acceptor of p-type impurities at the stage of epi growth. In this case, the acceptors are distributed from t ₁ to t ₂ in the epi layer thickness t direction, and the volume concentration of the ionized acceptor is expressed as Na (t) [1 / cm ³ ] as _a function of the thickness direction distance t. Shall be given. At this time, the sheet charge amount of the negative charge due to the ionized acceptor can be expressed by the following formula (13).

In this case, the threshold value V _th of the FET is expressed by substituting ξ _c of Equation (13) into σ _c in Equation (6). That is, the following formulas (14) to (16) are established.

qV _th = -ΔE _c3 + ΔE _c2 -ΔE _c1 + qΦ _B
+ (q / ε _o ) (σ _s + ξ _c -σ _h ) (T _f / ε _f + T _s / ε _s ) + (q / ε _o ) (ξ _c -σ _h ) T _h / ε _h ( 14)
= -ΔEc3 + ΔEc2-ΔEc1 + qΦ _B
+ (q / ε _o ) σ _s (T _f / ε _f + T _s / ε _s ) + (q / ε _o ) (ξ _c -σ _h ) (T _f / ε _f + T _s / ε _s + T _h / ε _h ) (15)
= -ΔEc3 + ΔEc2-ΔEc1 + qΦ _B + (q / ε _o ) σ _s T ₁ + (q / ε _o ) (ξ _c -σ _h ) T ₂ (16)

Hereinafter, as in Case A, the contribution of various physical parameters to V _th is classified by the sum of fixed charges (σ _h -σ _s -ξ _c ), which is suitable for the FET to show normally-off characteristics. Verify the conditions.

[B- (1). When total fixed charge (σ _h -σ _s -ξ _c )> 0]
If the total of fixed charges in the epi (σ _h −σ _s −ξ _c ) is positive, an electric field is applied from the back to the front of the gate insulating film. Therefore, from the formula (14), _Vth shifts in the negative direction as the thicknesses T _f and T _s of the gate insulating film and the cap layer increase. Conversely, _Vth shifts in the positive direction as the thicknesses T _f and T _s of the gate insulating film and the cap layer are reduced. However, it is preferable that the thickness of the gate insulating film is not too thin so as not to cause deterioration of the gate breakdown voltage. In addition, there is a limit to thinning the cap layer.

[B- (2). When the total fixed charge (σ _h -σ _s -ξ _c ) <0]
In order for the device to actually be normally OFF, V _th > 0V must be satisfied. The threshold voltage V _th needs to be calculated in consideration of ΔEc and [Phi _B. If the sum of the fixed charges in the epi (σ _h -σ _s -ξ _c ) is negative, an electric field is applied to the gate insulating film from the front to the back, so from the equation (14), the gate insulating film and the cap layer As the thicknesses T _f and T _s increase, V _th shifts in the positive direction. Using this, the threshold voltage V _{th of the} FET can be increased to V _th = + 5 to +6 V or higher. Therefore, in order for the first or second field effect transistor of the present invention to have a normally OFF characteristic (enhancement mode), the total fixed charge (σ _h −σ _s −ξ _c ) <0. preferable. However, it is preferable not to make the gate insulating film thickness too large from the viewpoint of preventing a decrease in mutual conductance (g _m ) due to a decrease in intrinsic gate capacitance. Therefore, the thickness of the gate insulating film is preferably not less than 30 nm and not more than 70 nm from the viewpoint of achieving both forward breakdown voltage maintenance and g _m maintenance.

In order for the heterointerface channel between the Al _y Ga _1-y N barrier layer and the GaN channel layer to be ON at Vg = 0V, that is, normally ON, between the gate and ohmic electrodes and directly below the ohmic electrode, ξ _c <σ Must be _h . Therefore, the range of ξ _c is expressed by the following formula (17).

σ _h -σ _s <ξ _c <σ _h (17)

When GaN is adopted for the cap layer Al _z Ga _1-z N (z = 0), when forming the device structure outside the gate (between the gate and ohmic and directly under the ohmic electrode) by recess etching, etc. Selective etching of the Al _y Ga _1-y N barrier layer can be applied. This is a great merit in actual device fabrication. In this case, since σ _h = σ _s , the range of ξc may be 0 <ξ _c <σ _h from Equation (17). In the GaN buffer structure, the surface density σ _h / q of polarization charge at the hetero interface between the Al _y Ga _1-y N barrier layer and the GaN channel layer is equal to the Al composition ratio y of the Al _y Ga _1-y N barrier layer. Depending on the relationship, σ _h /q=5.25×10 ¹³ × y [cm ⁻² ]. Therefore, the specific range required for the surface density ξ _c / q of the ionized acceptor that becomes a p-type impurity depends on the Al composition ratio y of the Al _y Ga _1-y N barrier layer, and the following formula (18 ) As follows.

O <ξ _c /q<5.25×10 ¹³ y [cm ^-2 ] (18)

When the cap layer Al _z Ga _1-z N is i-GaN, since ΔE _c2 = ΔE _c1 and σ _s = σ _h , the threshold V _th is simplified as shown in the following equation (19). Can be represented.

qV _th = -ΔE _c3 + qΦ _B + (q / ε _o ) σ _h T ₁ + (q / ε _o ) (ξ _c -σ _h ) T ₂
= -ΔE _c3 + qΦ _B- (q / ε _o ) σ _h T _h / ε _h + (q / ε _o ) ξ _c T ₂ (19)

In the equation (19), the term (q / ε _o ) σ _h T _h / ε _h represents the contribution of the barrier layer thickness and the channel polarization charge to V _th , and (q / ε _o ) ξ _c T ₂ This term indicates the contribution of negative charge to V _th by the ionized acceptor.

[B- (3). Fixed charge total (σ _h -σ _s -ξ _c ) = 0]
In this case, V _th is represented by the following formula (20) based on the formula (14).

qV _th = -ΔE _c3 + ΔE _c2 -ΔE _c1 + qΦ _B + (q / ε _o ) (ξ _c -σ _h ) T _h / ε _h (20)

That is, V _th does not depend on the thickness of the gate insulating film or the cap layer. As a feature of the potential in this case, since the sum of polarization charges in the epi is zero, when the gate voltage is zero (Vg = 0V), no electric field is applied to the gate insulating film and the cap layer, and the gate insulating film and the cap layer The conduction band potential of becomes horizontal (flat band). Thereby, even if the cap layer thickness and the gate insulating film thickness are changed by the manufacturing process, _Vth does not change. That is, _Vth is stable and the manufacturing process can be easily controlled even if the cap layer thickness of the FET and the gate insulating film thickness are not strictly controlled. However, in this case, the V _th increases as the thicknesses T _f and T _s of the gate insulating film and the cap layer increase as in the case where the total fixed charge (σ _h −σ _s −ξ _c ) <0. There is no shift in the positive direction. From this viewpoint, in this case, there is a limit to the increase in the threshold voltage V _th of the FET.

[Case C. Type using InGaN cap]
In Cases A and B, the method for realizing a normally OFF characteristic as an FET has been described by devising the buffer layer. In this case, GaN for the buffer layer, GaN for the channel layer, Al _y Ga _1-y N (0 <y ≦ 1) for the barrier layer, and In _z Ga _1-z N (0 <z ≦ 1) for the cap layer Is used. Thus, the type using an InGaN cap (T. Mizutani, “AlGaN / GaN HEMTs With Thin InGaN Cap Layer for Normally Off Operation,” IEEE Electron Device Letters, Vol. 28, No. 7, pp. 549-551, July In the FET of 2007.), the total polarization charge (σ _h -σ _s ) in the multilayer epitaxial film is always negative (σ _h -σ _s ) <0 in this case (σ _c in this case σ _c As the gate insulating film thickness increases, the FET threshold value Vth shifts in the positive direction, whereby a normally-off characteristic with a high threshold value can be obtained. When the “outside gate recess structure” is applied, the polarization charge sum of the entire epi is σ _h between the gate and ohmic electrodes and directly under the ohmic electrodes (source and drain electrodes), and 0 <σ _h and positive It is. Therefore, the hetero interface channel of the Al _y Ga _1-y N barrier layer / GaN channel layer is ON at Vg = 0V, that is, normally ON, between the gate and the ohmic electrode and immediately below the ohmic electrode.

  The preferred structures for obtaining normally-off characteristics in the GaN-MISFET have been described above by classifying into cases A, B, and C.

In Case B, GaN was used for the buffer layer, and the channel layer or buffer layer was doped with p-type impurities to give the GaN-FET normally OFF characteristics. When p-type doped p-GaN is used for the buffer layer, the buffer layer is made conductive by the acceptor. In this case, from the viewpoint of not deteriorating the buffer layer breakdown voltage of the FET, it is preferable that the p-type impurity concentration of the buffer layer is not too high. In addition, when p-type doped p-GaN is used for the channel layer, the channel electrons at the heterointerface between the Al _y Ga _1-y N barrier layer and the p-GaN channel layer are scattered by impurities due to p-type impurities. Therefore, it is preferable that the p-type impurity concentration is not too high from the viewpoint that the concentration does not decrease.

In Case C, we explained a device structure that gives a GaN-FET normally OFF characteristics using an InGaN cap structure. Note that in this structure, the combination of the above layers (GaN for the buffer layer, GaN for the channel layer, and Al _y Ga _1-y N (0 <y ≦ 1) for the barrier layer) It is easy to generate holes in the electron band. In particular, in the off state where the gate voltage V _g is V _g ≦ 0 V, holes are easily generated in the InGaN cap layer. To prevent the formation of holes in an In _z Ga _1-z N cap _{layer, In z Ga 1-z N} In composition ratio z of the cap layer is preferably 3% or less (z ≦ 0.03), 1% or less ( z ≦ 0.01) is more preferable. However, if the In composition ratio z is reduced, the absolute amount of negative polarization charge in the epi is reduced, so that a thicker gate insulating film is required to obtain the same threshold voltage. Alternatively, generation of holes in the InGaN cap layer may be prevented by appropriately changing the composition of each layer (buffer layer, channel layer, barrier layer). Also note that layers containing In like InGaN are more difficult to form than GaN and AlGaN due to epi growth, and that the surface of InGaN is more susceptible to damage than the surface of GaN or AlGaN during the manufacturing process. To manufacture.

In the above cases A to C, the case A (structure based on the AlGaN buffer structure) is particularly preferable as the actual device structure that gives the FET a normally OFF characteristic. In this case, the basic profile of epi structure (composition of each layer) is Al _x Ga _1-x N (0 <x <1) with Al composition ratio x as described in A- (2). The barrier layer is Al _y Ga _1-y N (x <y ≦ 1) where the Al composition ratio y is larger than x, and the cap layer is Al _z Ga _1-z N where the Al composition ratio z is smaller than x. (0 ≦ z <x). However, as described above, these are examples, and the present invention is not limited to these. For example, in the cases A to C, a combination in which the buffer layer is AlGaN or GaN, the channel layer is GaN, and the barrier layer is AlGaN is described. Each layer is formed of another group III nitride semiconductor as described above. May be.

Next, conditions for suppressing the accumulation of electrons in the MIS (MOS) channel during device operation when the original semiconductor heterojunction interface channel (2DEG604 in FIG. 1) is in the on state will be described. If no electron accumulation occurs in the MIS (MOS) channel, it is possible to prevent the phenomenon that the semiconductor heterojunction interface channel is not modulated even if the gate voltage _Vg is increased in the positive direction. Hereinafter, the case of the AlGaN buffer structure of case A will be described.

First, in order to prevent electron accumulation in the MIS (MOS) channel at the gate voltage (that is, the threshold voltage) V _g = V _{th at} which the device starts to turn on, the conduction band potential qV _{mis at the} MIS channel interface is positive. There must be. That is, the following formula (21) needs to be satisfied for qV _mis shown in FIG.

qV _mis = ΔEc1-ΔEc2 + (q / ε _o ) (σ _h -σ _c ) T _h / ε _h- (q / ε _o ) (σ _s + σ _c -σ _h ) T _s / ε _s > 0 (21 )

When the buffer layer is Al _x Ga _1-x N, the channel layer is GaN, the barrier layer is Al _y Ga _1-y N, and the cap layer is GaN, σ _h = σ _c , ΔEc1 = ΔEc2 The equation (21) is simplified and expressed as the following equation (22).

qV _mis = (q / ε _o ) (σ _h -σ _c ) T _h / ε _h- (q / ε _o ) σ _c T _s / ε _s > 0 (22)

Furthermore, when V _g is applied positively to turn on the semiconductor heterojunction channel and the electrons accumulated in the channel become saturated, the conditions for preventing the accumulation of electrons in the MIS (MOS) channel are: Approximately, it can be expressed by the following formula (23).

qV _mis = (q / ε _o ) (σ _h -σ _c ) T _h / ε _h- (q / ε _o ) σ _c T _s / ε _s ≥ΔEc1 (23)

Here, each polarization charge density depends on the Al composition ratio of the layer, σ _c /q=5.25×10 ¹⁷ x [m ⁻² ], σ _h /q=5.25×10 ¹⁷ (yx) [m ⁻² ], and σ _s /q=5.25×10 ¹⁷ (yx) [m ⁻² ]. Furthermore, since the relative dielectric constants of the respective semiconductor layers are substantially equal, when the relative dielectric constants of the respective semiconductor layers are all set to ε _r , the following formula (24) is obtained.

5.25 × 10 ¹⁷ (q ² / ε _o ε _r ) [(y-2x) T _h -xT _s ] ≧ ΔEc1 (24)

The larger the left side of the equation (24), the more effective it is to suppress the MIS (MOS) channel electron accumulation. In order to increase the left side of the formula (24) as much as possible, the Al composition ratio x of the buffer layer should not be increased so much, the cap layer thickness T _s should be as thin as possible, and the Al composition ratio y of the barrier layer should be of and more than twice the Al composition ratio x, it can be seen it is effective to increase the barrier layer thickness T _h. The Al composition ratio x of the buffer layer is, for example, about 10% (x≈0.1) for reasons of crystal growth such as suppression of epi warping. In this case, Al composition ratio y of the barrier layer is preferably greater than 20% that (y> 0.2), further, it is preferable to thicker barrier layer thickness T _h.

Furthermore, as described above, the first or second FET of the present invention can be manufactured without forming a gate recess. According to this, since the cap layer thickness T _s is defined by epi growth regardless of the recess depth, it can be made extremely thin, for example, T _s = 2 nm. Thereby, it is possible to effectively suppress the accumulation of electrons in the MIS (MOS) channel when the FET is turned on. Furthermore, any chance, even the gate voltage V _g as the application of a device operating voltage increased beyond the positive direction, for the cap layer is thin, the sheet amount of electric charge stored in the MIS (MOS) channel can be suppressed as much as possible It is. However, considering not only suitable conditions for suppressing MIS (MOS) channel electron accumulation, but also suitable conditions for increasing the threshold voltage _Vth , etc., the composition, thickness, etc. of each component (for example, It is preferable to appropriately select a barrier layer thickness, an Al composition ratio of the barrier layer, an Al composition ratio of the buffer layer, and the like.

  In addition, suitable conditions, such as a composition of each said component based on said theoretical calculation, thickness, are demonstrated below based on the graph of FIGS.

FIG. 11 shows an example of the calculation result of the gate voltage dependence of the carrier concentration formed in the channel layer 603 in the case A FET. In the figure, the horizontal axis indicates the gate voltage (V). The vertical axis represents the carrier concentration (cm ⁻² ) in the channel 604 and is a calculated value at the interface between the GaN channel layer 603 and the AlN barrier layer 605. Here, as an example, the Al composition ratio of the buffer layer 602 is x = 0.1, the Al composition ratio of the channel layer 603 is u = 0.0, the Al composition ratio of the barrier layer 605 is y = 1.0, and the Al composition ratio of the cap layer 606 is The results when z = 0.0 and the material of the gate insulating film 607 is Al ₂ O ₃ are shown. The thickness of each layer was calculated assuming that the AlGaN buffer layer 602 was 1 μm, the GaN channel layer 603 was 25 nm, the AlN barrier layer 605 was 2 nm, and the GaN cap layer 606 was 5 nm. The film thickness of the Al ₂ O ₃ gate insulating film 607 was changed in the range of 30 nm to 70 nm.

As shown in FIG. 11, due to the internal electric field generated in the gate insulating film 607, _Vth moves to the positive side as the gate insulating film thickness increases, and + 2V or higher in the gate insulating film thickness of 30 nm or more. It can be seen that V _th is obtained. On the other hand, as the gate insulating film thickness increases, the intrinsic gate capacitance decreases and the mutual conductance (gm) decreases. Thus, from the viewpoint of maintaining forward breakdown voltage and maintaining gm, the thickness of the gate insulating film 607 is preferably 5 nm or more and 200 nm or less. The thickness of the gate insulating film is more preferably 30 nm or more and 70 nm or less. Thereby, it is possible to further optimize _Vth .

FIG. 12 shows an example of the calculation result of the dependence of the carrier concentration accumulated in the channel layer 603 and the cap layer 606 on the film thickness of the GaN cap layer 606 in the case A FET. In the figure, the horizontal axis represents the GaN cap layer 606 thickness (nm). The vertical axis represents the carrier concentration (cm ⁻² ) in the channel 604 and is a calculated value at the interface between the GaN channel layer 603 and the AlN barrier layer 605. The parameters other than that the thickness of the Al ₂ O ₃ gate insulating film 607 is fixed at 30 nm and the thickness of the GaN spacer layer are the same as the values used in the calculation of FIG.

  As shown in FIG. 12, it can be seen that the smaller the film thickness of the cap layer 606, the higher the carrier concentration accumulated in the channel layer and the lower the carrier concentration accumulated in the cap layer 606. Thus, from the viewpoint of accumulating certain carriers in the channel, the cap layer thickness below the gate electrode (under the gate) is preferably 0.5 nm or more and 20 nm or less. The thickness of the spacer layer below the gate electrode (under the gate) is more preferably 0.5 nm or more and 10 nm or less. For example, in FIG. 12, if the thickness of the cap layer 606 is 0.5 nm or more and 10 nm or less, about 50% or more of the carriers are accumulated in the channel, and the on-resistance is further improved.

FIG. 13 shows an example of a calculation result of the dependence of the carrier concentration accumulated in the channel layer and the cap layer on the Al composition ratio (y) of the AlGaN barrier layer 605 in the case A FET. In the figure, the horizontal axis represents the Al composition ratio of the barrier layer 605. The vertical axis represents the carrier concentration (cm ⁻² ) in the channel 604 and is a calculated value at the interface between the GaN channel layer 603 and the AlN barrier layer 605. Here, parameters other than the Al ₂ O ₃ gate insulating film 607 having a fixed film thickness of 30 nm and the Al composition ratio of the barrier layer 605 are the same as the values used in the calculation of FIG.

  As shown in FIG. 13, it can be seen that as the Al composition ratio y of the barrier layer 605 increases, the carrier concentration accumulated in the channel layer 603 increases and the carrier concentration accumulated in the cap layer 606 decreases. This is because an increase in the Al composition ratio of the barrier layer increases the conduction band offset at the interface with the barrier layer and increases the polarization electric field generated in the barrier layer, thereby improving carrier confinement in the channel layer. . In FIG. 13, it can be seen that when the Al composition ratio of the barrier layer 605 is 40% (0.4) or more, carrier confinement and on-resistance are further improved.

FIG. 14 shows an example of the calculation result of the dependence of the carrier concentration accumulated in the channel layer 603 and the cap layer 606 on the film thickness of the AlN barrier layer 605 in the case A FET. In the figure, the horizontal axis indicates the thickness (nm) of the AlN barrier layer 605. The vertical axis represents the carrier concentration (cm ⁻² ) in the channel 604 and is a calculated value at the interface between the GaN channel layer 603 and the AlN barrier layer 605. Here, the parameters other than the thickness of the Al ₂ O ₃ gate insulating film 607 fixed at 30 nm and the barrier layer thickness are the same as those used in the calculation of FIG.

  As shown in FIG. 14, as the barrier layer thickness increases, carrier confinement in the channel layer is improved, the carrier concentration accumulated in the channel layer is increased, and the carrier concentration accumulated in the spacer layer is decreased. I understand. On the other hand, if the thickness of the AlN barrier layer is 10 nm or less, it is considered that the lattice strain is relatively small and dislocations are not easily generated. That is, in FIG. 14, it can be seen that when the AlN barrier layer thickness is 1 nm or more and 10 nm or less, carrier confinement is further improved and the crystal quality of the barrier layer is easily maintained.

FIG. 15 shows an example of the calculation result of the gate voltage dependence of the carrier concentration formed in the channel layer 603 in the case B FET. In the figure, the horizontal axis indicates the gate voltage (V). The vertical axis represents the carrier concentration (cm ⁻² ) in the channel 604 and is a calculated value at the interface between the GaN channel layer 603 and the AlN barrier layer 605. Here, as an example, the Al composition ratio of the buffer layer 602 and the channel layer 603 is x = 0.0, the Al composition ratio of the barrier layer 605 is y = 1.0, the Al composition ratio of the cap layer 606 is z = 0.0, and the gate insulating film The result when the material of 607 is Al ₂ O ₃ is shown. The thickness of each layer was calculated assuming that the GaN buffer layer 602 was 1 μm, the GaN channel layer 603 was 160 nm, the AlN barrier layer 605 was 2 nm, and the GaN cap layer 606 was 5 nm. The film thickness of the Al ₂ O ₃ gate insulating film 607 was changed in the range of 30 nm to 70 nm.

As shown in FIG. 15, due to the internal electric field generated in the gate insulating film 607, V _th moves to the positive side as the gate insulating film thickness increases, and + 4V or higher in the gate insulating film thickness of 30 nm or more. It can be seen that V _th is obtained. On the other hand, as the gate insulating film thickness increases, the intrinsic gate capacitance decreases and the mutual conductance (gm) decreases. Thus, from the viewpoint of maintaining forward breakdown voltage and maintaining gm, the thickness of the gate insulating film 607 is preferably 5 nm or more and 200 nm or less. The thickness of the gate insulating film is more preferably 30 nm or more and 70 nm or less. Thereby, it is possible to further optimize _Vth .

FIG. 16 shows an example of the calculation result of the dependency of the carrier concentration accumulated in the channel layer 603 and the cap layer 606 on the film thickness of the GaN cap layer 606 in the case B FET. In the figure, the horizontal axis represents the GaN cap layer 606 thickness (nm). The vertical axis represents the carrier concentration (cm ⁻² ) in the channel 604 and is a calculated value at the interface between the GaN channel layer 603 and the AlN barrier layer 605. The values are the same as those used in the calculation of FIG. 15 except that the thickness of the Al ₂ O ₃ gate insulating film 607 is fixed at 30 nm and parameters other than the GaN spacer layer thickness.

  As shown in FIG. 16, it can be seen that the carrier concentration accumulated in the channel layer increases and the carrier concentration accumulated in the cap layer 606 decreases as the thickness of the cap layer 606 decreases. Thus, from the viewpoint of accumulating certain carriers in the channel, the cap layer thickness below the gate electrode (under the gate) is preferably 0.5 nm or more and 20 nm or less. The thickness of the spacer layer below the gate electrode (under the gate) is more preferably 0.5 nm or more and 7 nm or less. For example, in FIG. 16, when the thickness of the cap layer 606 is 0.5 nm or more and 7 nm or less, about 50% or more of the carriers are accumulated in the channel, and the on-resistance is further improved.

FIG. 17 shows an example of the calculation result of the dependence of the carrier concentration accumulated in the channel layer and the cap layer on the Al composition ratio (y) of the AlGaN barrier layer 605 in the case B FET. In the figure, the horizontal axis represents the Al composition ratio of the barrier layer 605. The vertical axis represents the carrier concentration (cm ⁻² ) in the channel 604 and is a calculated value at the interface between the GaN channel layer 603 and the AlN barrier layer 605. Here, the parameters other than the Al ₂ O ₃ gate insulating film 607 fixed at 30 nm and the Al composition ratio of the barrier layer 605 are the same as the values used in the calculation of FIG.

  As shown in FIG. 17, it can be seen that as the Al composition ratio y of the barrier layer 605 increases, the carrier concentration accumulated in the channel layer 603 increases and the carrier concentration accumulated in the cap layer 606 decreases. This is because an increase in the Al composition ratio of the barrier layer increases the conduction band offset at the interface with the barrier layer and increases the polarization electric field generated in the barrier layer, thereby improving carrier confinement in the channel layer. . In FIG. 17, it can be seen that when the Al composition ratio of the barrier layer 605 is 40% (0.4) or more, carrier confinement and on-resistance are further improved.

FIG. 18 shows an example of the calculation result of the dependence of the carrier concentration accumulated in the channel layer 603 and the cap layer 606 on the film thickness of the AlN barrier layer 605 in the case B FET. In the figure, the horizontal axis indicates the thickness (nm) of the AlN barrier layer 605. The vertical axis represents the carrier concentration (cm ⁻² ) in the channel 604 and is a calculated value at the interface between the GaN channel layer 603 and the AlN barrier layer 605. Here, the parameters other than the thickness of the Al ₂ O ₃ gate insulating film 607 fixed at 30 nm and the barrier layer thickness are the same as the values used in the calculation of FIG.

  As shown in FIG. 18, as the barrier layer thickness increases, carrier confinement in the channel layer is improved, the carrier concentration accumulated in the channel layer is increased, and the carrier concentration accumulated in the spacer layer is decreased. I understand. On the other hand, if the thickness of the AlN barrier layer is 10 nm or less, it is considered that the lattice strain is relatively small and dislocations are not easily generated. That is, in FIG. 18, it can be seen that when the AlN barrier layer thickness is 1 nm or more and 10 nm or less, carrier confinement is further improved and the crystal quality of the barrier layer is easily maintained.

[Embodiment 2]
The cross-sectional view of FIG. 6 schematically shows the structure of another embodiment of the FET of the present invention. In the FET of the figure, the barrier layer is formed of a two-layer structure of a non-doped spacer layer 623 and an n-doped electron supply layer 624. The spacer layer 623 and the electron supply layer 624 are stacked on the channel layer in the above order, and the ohmic electrodes (the source electrode 609 and the drain electrode 610) are disposed so as to contact the upper surface of the electron supply layer 624. The formation material and composition of the spacer layer 623 and the electron supply layer 624 are not particularly limited, and may be, for example, AlGaN or another group III nitride semiconductor described above. Except for these, the structure of the FET of FIG. 6 is the same as the FET of FIG. In FIG. 6, the buffer layer is represented by reference numeral 621, the channel layer is represented by reference numeral 622, the cap layer is represented by reference numeral 626, and the gate insulating film is represented by reference numeral 627. The gate electrode is represented by reference numeral 628, and the surface protective film is represented by reference numeral 629.

In FIG. 6, since the ohmic electrodes (609, 610) are in direct contact with the n-doped electron supply layer 624, good ohmic contact can be obtained without separately performing ion implantation of n-type impurities. Can do. In particular, if the surface of the electron supply layer 624 contains a large amount of n-type impurities before the electronic state is sufficiently degenerated, the ohmic contact can be formed non-alloyed. The n-type impurity concentration is not particularly limited, but for example, 1 × 10 ¹⁷ (1E17) cm ⁻³ or more, preferably 1 × 10 ¹⁸ (1E18) cm ⁻³ or more, more preferably 1 × 10 ¹⁹ (1E19 ) Cm ^-3 or more. The upper limit value of the n-type impurity concentration is not particularly limited, but is, for example, 1 × 10 ²³ (1E23) cm ⁻³ or less. The non-doped spacer layer 623 is an electron traveling in the channel layer 622 (strictly speaking, it is a wave function of electrons and has a certain extent in the vertical direction). It prevents impurities from being scattered by impurities and prevents the electron mobility of channel electrons from decreasing.

  The structure of the FET of this embodiment can be applied to both the first and second FETs of the present invention. The manufacturing method of the FET of this embodiment is not particularly limited, and can be manufactured in the same manner as the FET of FIG.

[Embodiment 3]
The cross-sectional view of FIG. 7 schematically shows the structure of still another embodiment of the FET of the present invention. In the FET of FIG. 7, the barrier layer has a three-layer structure of a spacer layer 623, an electron supply layer 624, and a stopper layer 625. The spacer layer 623 and the electron supply layer 624 are stacked on the channel layer 622 in the above order. Similar to the second embodiment, the spacer layer 623 is non-doped, and the electron supply layer 624 is n-doped. The formation material and composition of the spacer layer 623 and the electron supply layer 624 are the same as those in the second embodiment. The ohmic electrodes (source electrode 609 and drain electrode 610) are disposed so as to be in contact with the upper surface of the electron supply layer 624. The stopper layer 625 is not particularly limited, and is made of, for example, very thin (about 1 nm) AlN. The stopper layer 625 is disposed on the electron supply layer 624 in a region between the source electrode 609 and the drain electrode 610, and is sandwiched between the electron supply layer 624, the cap layer 626, and the surface protective film 640. . Except for these, the structure of the FET of FIG. 7 is the same as the FET of FIG. 6 (Embodiment 2). In FIG. 7, the gate insulating film is denoted by reference numeral 630, and the surface protective film is denoted by reference numeral 640. The gate insulating film 630 may be formed of, for example, a silicon oxide film, and the surface protective film 640 may be formed of, for example, alumina, but is not limited thereto. The surface protective film 640 is preferably formed of alumina because, for example, negative polarization charges generated on the upper surface of the barrier layer (that is, the upper surface of the AlN stopper layer 625) can be compensated.

  The stopper layer 625 in the FET of FIG. 7 functions to increase the etching selectivity with respect to the cap layer 626 in the manufacturing process. The manufacturing method itself of the FET of FIG. 7 is not particularly limited. For example, except that the barrier layer is formed by the above three-layer structure and the stopper layer 625 in the ohmic electrode formation region is selectively removed prior to the formation of the ohmic electrode (source electrode 609, drain electrode 610). It can be manufactured in the same manner as the FETs of the first and second embodiments. More specifically, for example, it may be manufactured by the manufacturing method of Example 3 described later. Further, the structure of the FET of this embodiment can be applied to both the first and second FETs of the present invention.

Example 1
An FET having the structure shown in FIG. 1 was manufactured and its performance was verified. Each semiconductor layer (multilayer epitaxial film) and gate insulating film in the FET of this example had the compositions and thicknesses (thicknesses) shown in Table 3 below. Note that 1 mm is equal to 10 ⁻¹⁰ m, that is, 0.1 nm.

The FET of this example was manufactured as follows. That is, first, a nucleation layer (200 nm, not shown) composed of a superlattice in which undoped AlN and undoped GaN are alternately stacked on a (111) -plane silicon (Si) substrate 601, and an undoped Al _0.08 Ga _0.92 N A buffer layer 602 (1 μm), a channel layer 603 made of undoped GaN, a barrier layer 605 made of undoped Al _0.28 Ga _0.72 N, and an undoped GaN cap layer 606 were grown in this order (semiconductor layer stacking step). In this embodiment, this step is performed by a metalorganic chemical vapor deposition (abbreviated as MOCVD) method, but other methods may be used. The crystal growth was Ga plane (Al plane) growth perpendicular to the (0001) crystal axis.

  Although not performed in this example, when the ohmic contact is further improved, an n-type impurity such as Si is selectively ion-implanted into a region where an ohmic electrode is formed after the semiconductor layer stacking step. For example, activation annealing may be performed at about 1200 degrees for about 5 minutes.

Next, Al ₂ O ₃ to be the gate insulating film 607 was deposited using an atomic layer deposition (ALD) method (gate insulating film material forming step). Next, polysilicon was deposited for use as the gate electrode 608 (gate electrode material forming step).

Further, the polysilicon layer, the Al ₂ O ₃ layer, and the undoped GaN cap layer 606 were removed by recess etching in a portion other than the gate electrode formation region. More specifically, it is as follows.

That is, in order to form the gate electrode 608, patterning was performed so that the upper surface of the gate portion (portion serving as the gate electrode) of the polysilicon layer was covered with a resist and the portions other than the gate portion were opened. Thereafter, using a magnetron RIE apparatus, a portion other than the gate portion in the polysilicon layer was selectively etched away with a chlorine-based gas to form a gate electrode 608 (gate electrode forming step). Further, a portion other than the gate portion in the alumina (Al ₂ O ₃ ) layer was selectively removed by wet etching using hydrofluoric acid to form a gate insulating film 607 (gate insulating film forming step). Further, selective etching of the undoped GaN cap layer 606 with respect to the AlGaN barrier layer 605 is performed by ICP dry etching using a mixed gas of BCl ₃ and SF ₆ , and a portion other than the gate portion in the undoped GaN cap layer 606 is selectively used. (Cap layer partial removal step). In this selective etching, Al _0.28 Ga _0.72 N (barrier layer 605) having an Al composition ratio of 28% and GaN (cap layer 606) can achieve an etching rate selection ratio of 1:35.

  Further, on the AlGaN barrier layer 605, titanium (Ti) / aluminum (Al) / nickel (Ni) / gold (Au) is deposited and alloyed to form a source electrode 609 and a drain electrode 610, respectively. Ohmic contact with the channel layer 603 was taken (source electrode and drain electrode formation step).

Then, a surface protective film 611 made of silicon nitride (Si ₃ N ₄ ) was deposited by 50 nm using a plasma-enhanced chemical vapor deposition (abbreviated as PECVD) method. In this embodiment, this process is performed by a plasma-enhanced chemical vapor deposition (abbreviated as PECVD) method, but may be performed by another method. Further, the material of the surface protective film is not particularly limited, and may be another insulator, for example, and the thickness is not limited to the above-described thickness, and can be set as appropriate. Further, the surface protective film in the electrode portion (the upper surfaces of the gate electrode 608, the source electrode 609, and the drain electrode 610) was etched away using sulfur hexafluoride (SF ₆ ) to form an opening. In this embodiment, sulfur hexafluoride (SF ₆ ) is used, but other reactive gas may be used. The FET of this example was manufactured as described above.

  As described above, the FET of this embodiment can make full use of selective etching, and has a high affinity with the Si-MOSFET mass production process (the gate-first process) (the formation of the gate electrode precedes the formation of the ohmic electrode). Can be manufactured by a process performed in This manufacturing method is an example of the first or second manufacturing method of the present invention.

FIG. 3 shows the calculation results of the conduction band energy and the valence band energy in the direction perpendicular to the main surface of the substrate below the gate electrode 608 in the FET of this example. In the figure, the horizontal axis indicates the distance [Å] perpendicular to the main surface of the substrate from the lowermost end of the gate electrode 608 downward. Note that 1 mm is equal to 10 ⁻¹⁰ m, that is, 0.1 nm. The vertical axis represents the energy level Ec [eV]. Here, the thickness of the gate insulating film 607 using alumina was set to 300 mm (30 nm) as described in Table 3 above. As shown in the drawing, a threshold voltage (V _th ) of about 3 V was obtained in the FET of this example. This threshold voltage was verified by experiment.

FIG. 4 shows a plot of calculation results of the conduction band energy and the carrier electron concentration between the gate and ohmic and immediately below the ohmic electrode (below the ohmic electrode) at the gate voltage Vg = 0V. In the figure, the horizontal axis indicates the distance [Å] perpendicular to the main surface of the substrate from the lowermost end of the gate electrode 608 downward. Note that 1 mm is equal to 10 ⁻¹⁰ m, that is, 0.1 nm. The vertical axis represents the conductor lower end energy Ec [eV]. As shown in the figure, according to the FET of this example, generation of high-concentration carrier electrons is observed at the semiconductor heterojunction interface, and on-resistance reduction is realized. The sheet channel electron concentration at the on time was 7 × 10 ¹² [cm ⁻² ], the maximum drain current density was 900 mA / mm, and the on current density was 720 mA / mm or more. All these numerical values were verified by experiments. Furthermore, the channel electron mobility was confirmed to be a high value of 1800 [cm ² / Vs] by experiments.

As described above, the field effect transistor (FET) of this example could be manufactured without forming a gate recess. Therefore, the threshold voltage (V _th ) did not vary due to variations in the recess etching depth. Further, since no gate recess is formed, the roughness of the semiconductor on the bottom surface of the recess does not increase, and the stoichiometry is not disturbed. This makes it difficult for interface states to be formed between the gate insulating film 607 and the semiconductor interface 606, and electron traps and emission are difficult to occur. Therefore, the hysteresis of the IV characteristics of the FET and the shift of the gate voltage in the plus / minus direction were suppressed, and IV and CV characteristics very close to the ideal characteristics were obtained.

Further, in the FET of this embodiment, since the cap layer 606 does not exist except for the gate electrode portion, a parallel conduction path is not formed even if the gate voltage Vg is increased, and this secondary channel conducts parallel conduction. It never happened. Furthermore, in the FET structure of this example, since it is not necessary to form a gate recess, the thickness of the cap layer 606 can be made extremely thin (2 nm) as described above by controlling the film thickness during epi growth. As a result, it was possible to suppress the accumulation of electrons in the MIS (MOS) channel when the FET was turned on. Therefore, in the FET of this example, the channel is only the two-dimensional electron gas 604 at the semiconductor heterojunction interface (605/603), and the high channel electron mobility 1800 [cm ² / Vs] inherent to the HEMT structure is realized. This is suitable, for example, for realizing a reduction in switching loss and a reduction in size of the device by using the FET (HEMT) power supply device of this embodiment. Furthermore, even if the gate voltage Vg greatly exceeds the device operating voltage and is applied in the positive direction, the FET of this embodiment has a small cap layer thickness, so the sheet charge amount accumulated in the MIS (MOS) channel is reduced. It is possible to suppress to the limit.

Further, FIG. 5 plots changes in the experimental value of the threshold voltage Vth when the thickness of the gate insulating film 607 (alumina) is changed from 200 to 700 mm. As shown in the figure, in the case of the FET of the present example (structure shown in Table 3), a high _{Vth of} about 7 V was realized with the thickness of the gate insulating film 607 (alumina) being 700 mm. This value is sufficient to replace the Si-IGBT.

  In the present example, a manufacturing method (manufacturing process) of an FET having an epi structure based on an AlGaN buffer structure (case A of the first embodiment) has been described. An FET having an epi structure based on a GaN buffer structure (case B of the first embodiment) can also be manufactured by a manufacturing method using an out-gate recess as in this example.

(Example 2)
An FET having the structure shown in FIG. 6 was manufactured. Each semiconductor layer and gate insulating film in the FET of this example had the composition and thickness (thickness) shown in Table 4 below. Note that 1 mm is equal to 10 ⁻¹⁰ m, that is, 0.1 nm. In the FET of this example, the barrier layer has a two-layer structure of an n-doped n-Al _0.28 Ga _0.72 N electron supply layer 624 and a non-doped Al _0.28 Ga _0.72 N spacer layer 623 (n-Al _0.28 Ga _0.72 N / i-Al _0.28 Ga _0.72 N) makes it easy to make ohmic contact with the ohmic electrode.

  The FET of this example could be manufactured in the same manner as the FET of Example 1 except that the barrier layer was formed with the two-layer structure shown in FIG. 6 and Table 4.

In the FET of this example, the ohmic electrode (609, 610) was formed so as to be in direct contact with the n-doped n-Al _0.28 Ga _0.72 N electron supply layer 624, and therefore, n-type impurity ion implantation was performed separately. Even without this, good ohmic contact could be obtained.

In this example, the n-Al _0.28 Ga _0.72 N electron supply layer 624 was doped with ²⁸ Si as an n-type impurity at a high concentration of 5 × 10 ¹⁹ (5E19) cm ⁻³ . Therefore, the electronic state of the surface of the n-Al _0.28 Ga _0.72 N electron supply layer 624 was sufficiently degenerated, and an ohmic contact could be formed in a non-alloy. In addition, an i-Al _0.28 Ga _0.72 N spacer layer 623 is inserted between the n-Al _0.28 Ga _0.72 N electron supply layer 624 and the GaN channel layer 622. This spacer layer 623 is an impurity of the n-Al _0.28 Ga _0.72 N electron supply layer 624, which is an electron traveling in the channel layer 622 (specifically, it is a wave function of electrons and has a certain extent in the vertical direction). Prevents impurities from being scattered and prevents the electron mobility of channel electrons from decreasing.

In the FET of this example, when the gate insulating film 627 (alumina) thickness is 600 mm, the threshold voltage V _th has achieved a high value of about 6V. The above values are experimentally verified values.

Example 3
An FET having the structure shown in FIG. 7 was manufactured. Each semiconductor layer and gate insulating film in the FET of this example had the composition and thickness (thickness) shown in Table 5 below. As shown in Table 5 below, the barrier layer has a three-layer structure including a very thin (about 1 nm) AlN stopper layer 625, an n-Al _0.28 Ga _0.72 N electron supply layer 624, and an i-Al _0.28 Ga _0.72 N spacer layer 623. Formed from.

The FET of this example was manufactured as follows. That is, first, on a (111) plane silicon (Si) substrate 601, a nucleation layer (200 nm, not shown) made of a superlattice in which undoped AlN and undoped GaN are alternately stacked, a buffer layer 621, a channel layer 622, The spacer layer 623, the electron supply layer 624, the stopper layer 625, and the cap layer 626 were grown in the above order (semiconductor layer stacking step). In this semiconductor layer stacking step, metal organic chemical vapor deposition (abbreviated as MOCVD) is the same as in Example 1 except that the structure, composition and thickness of each semiconductor layer are as shown in Table 5 above. Done by law. The crystal growth was Ga plane (Al plane) growth perpendicular to the (0001) crystal axis. A 40 nm thick SiO ₂ film to be the gate insulating film 630 was deposited on the epitaxial wafer thus fabricated by using an atomic layer deposition (ALD) method (gate insulating film material forming step).

Further, polysilicon was deposited on the SiO ₂ for use as the gate electrode 608 (gate electrode material forming step). Further, in order to form the gate electrode 608, the upper surface of the gate part (gate electrode formation region) was covered with a resist, and patterning was performed so that the part other than the gate part was an opening. Thereafter, using a magnetron RIE apparatus, polysilicon other than the gate portion was selectively etched away with respect to SiO ₂ with a chlorine-based gas (gate electrode forming step). Further, SiO ₂ other than the gate portion was selectively removed by dry etching using a fluorine-based gas (gate insulating film forming step). Further, selective etching of the GaN cap layer 626 with respect to the AlN stopper layer 625 was performed by ICP dry etching using a mixed gas of BCl ₃ and SF ₆ to selectively remove the GaN cap layer 626 other than the gate portion ( Cap layer partial removal step). In this selective etching of the GaN cap layer 626 with respect to the AlN stopper layer 625, an etching rate selection ratio of 1: 115, which is more than two orders of magnitude, was achieved.

When the ohmic electrode (609, 610) is directly formed on the AlN stopper layer 625, the ohmic contact resistance is increased. For this reason, the ohmic electrode forming region is patterned with a resist so that the upper surface becomes an opening, and the AlN stopper layer 625 in the ohmic electrode forming region is removed by wet etching with an aqueous potassium hydroxide (KOH) solution to remove n-Al _0.28 Ga _0.72 The upper surface of the N electron supply layer 624 was exposed. Further, on the top surface of the n-Al _0.28 Ga _0.72 N electron supply layer 624, titanium (Ti) / aluminum (Al) / nickel (Ni) / gold (Au) is deposited and alloyed to obtain a source electrode 609, A drain electrode 610 was formed, and ohmic contact with the channel layer 622 was made (source electrode and drain electrode forming step). Furthermore, a surface protective film 640 made of alumina was deposited by 15 nm using the ALD method. Thereafter, the surface protective film (alumina) on the electrode portions (the upper surfaces of the gate electrode 608, the source electrode 609, and the drain electrode 610) was removed by wet etching using hydrofluoric acid to form openings. As described above, the FET of this example could be manufactured.

FIG. 8A shows calculated values of conduction band energy and valence band energy in a direction perpendicular to the main surface of the substrate below the gate electrode in the FET of this example. In the figure, the horizontal axis indicates the distance [Å] perpendicular to the main surface of the substrate from the lowermost end of the gate electrode 608 downward. Note that 1 mm is equal to 10 ⁻¹⁰ m, that is, 0.1 nm. The vertical axis represents the electron energy Ec [eV]. FIG. 8B shows an enlarged view of the channel portion (distance 300 to 600 mm from the lowermost end of the gate electrode) in FIG. 8A. As shown in the drawing, according to the FET of this example, a high value of 7.5 V could be obtained as the threshold voltage. This value was verified by experiment.

FIG. 9 shows the conduction band energy and carrier electron concentration between the gate and ohmic of the FET of this example. In the figure, the horizontal axis indicates the distance [Å] perpendicular to the main surface of the substrate from the lowermost end of the gate electrode 608 downward. Note that 1 mm is equal to 10 ⁻¹⁰ m, that is, 0.1 nm. The vertical axis represents the conductor lower end energy Ec [eV]. As shown in the figure, at V _g = 0V, high concentration carrier electrons are generated in the GaN channel layer. FIG. 10 shows the conduction band energy and carrier electron concentration immediately below the ohmic electrode of the FET of this example. In the figure, the horizontal axis indicates the distance [Å] perpendicular to the main surface of the substrate from the lowermost end of the gate electrode 608 downward. One inch is equal to 10 ⁻¹⁰ m or 0.1 nm. The vertical axis represents the conductor lower end energy Ec [eV]. As shown in the figure, it can be seen that high-concentration carrier electrons are generated in the GaN channel layer even immediately under the ohmic electrode. As shown in FIG. 9, since there is an AlN stopper layer 625 on the surface between the gate and the ohmic, the conduction band potential on the surface is remarkably raised, and this will hinder the formation of a good ohmic contact. There is a fear. However, as shown in FIG. 10, since the AlN stopper layer 625 is removed in the ohmic electrode forming portion, the conduction band potential on the surface is close to the Fermi level, and a good ohmic contact can be formed. I understand. For this reason, the FET of this structure can obtain a sufficiently low on-resistance, the channel sheet electron concentration is 7 × 10 ¹² [cm ^-2 ] at V _g = 12 V, and the maximum drain current density is 900 mA. / mm, on-current density was over 720mA / mm. The numerical values of the channel / sheet electron concentration, the maximum drain current density, and the on-current density were all verified by experiments.

The field effect transistor (FET) of this example could be manufactured without forming a gate recess. Therefore, the threshold voltage (V _th ) did not vary due to variations in the recess etching depth. Further, since no gate recess is formed, the roughness of the semiconductor on the bottom surface of the recess does not increase, and the stoichiometry is not disturbed. This makes it difficult for interface states to be formed between the gate insulating film 607 and the semiconductor interface 606, and electron traps and emission are difficult to occur. Therefore, the hysteresis of the IV characteristics of the FET and the shift of the gate voltage in the plus / minus direction were suppressed, and IV and CV characteristics very close to the ideal characteristics were obtained.

Furthermore, in the FET of this embodiment, since the cap layer 626 does not exist except for the gate electrode portion, a parallel conduction path is not formed even when the gate voltage Vg is increased, and this secondary channel conducts parallel conduction. It never happened. Furthermore, in the FET structure of this example, since it is not necessary to form a gate recess, the thickness of the cap layer 626 can be made extremely thin (2 nm) as described above by controlling the film thickness during epi growth. As a result, it was possible to suppress the accumulation of electrons in the MIS (MOS) channel when the FET was turned on. Therefore, in the FET of this example, the channel is only the two-dimensional electron gas 604 at the semiconductor heterojunction interface (623/622), and the HEMT structure inherent high channel electron mobility 1800 [cm ² / Vs] is realized. This is suitable, for example, for realizing a reduction in switching loss and a reduction in size of the device by using the FET (HEMT) power supply device of this embodiment. Furthermore, even if the gate voltage Vg greatly exceeds the device operating voltage and is applied in the positive direction, the FET of this embodiment has a small cap layer thickness, so the sheet charge amount accumulated in the MIS (MOS) channel is reduced. It is possible to suppress to the limit.

As mentioned above, although this invention was demonstrated based on each said embodiment and each said Example, this invention is not limited to these, A various change is possible. For example, in each of the embodiments and the examples, each semiconductor layer has been mainly described as an undoped layer. However, for example, the semiconductor layer may be p-type or n-type having an impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ or less. May be. However, the channel layer is preferably non-doped (undoped) from the viewpoint of preventing channel electrons from being subjected to impurity scattering and reducing electron mobility.

  In the present invention, Si or the like can be used as the n-type impurity, and magnesium (Mg) or the like can be used as the p-type impurity, but is not limited thereto.

In each of the embodiments and the examples, Si is used as a substrate, but other substrates such as silicon carbide (SiC), sapphire (Al ₂ O ₃ ), GaN, diamond (C) may be used. .

  In each of the embodiments and the examples, a superlattice of AlN and GaN is used as the nucleation layer, but a single layer such as AlN, AlGaN, or GaN may be used.

  In each of the above embodiments and each of the above examples, GaN or AlGaN is mainly used as the buffer layer material. However, other group III nitrides such as indium gallium nitride (InGaN), indium aluminum nitride (InAlN), and InAlGaN are used. A semiconductor may be used.

  In each of the embodiments and the examples, GaN or AlGaN is mainly used as a material for the channel layer and the cap layer, but other group III nitride semiconductors having a smaller band gap than the buffer layer may be used. . Specifically, for example, InGaN, InAlN, InAlGaN, InN, or the like may be used. The Al composition ratio of the channel layer and the cap layer is not particularly limited, but is preferably 10% or less from the viewpoint of preventing alloy scattering (alloy scattering).

  In each of the embodiments and the examples, AlGaN is used as the barrier layer material, but another group III nitride semiconductor having a larger band gap than the buffer layer may be used. The barrier layer material may be, for example, InGaN, InAlN, InAlGaN, GaN, AlN, or the like. When a binary material such as GaN or AlN is used, alloy scattering (alloy scattering) received by channel electrons can be suppressed, and reduction in channel electron mobility due to scattering can be suppressed.

In each embodiment and each example, Al ₂ O ₃ or silicon oxide (SiO ₂ ) is used as the gate insulating film, but silicon nitride (Si ₃ N ₄ ), hafnium oxide (HfO ₂ ), etc. Alternatively, the insulator may be used. In addition, as the gate insulating film, ferroelectric thin films such as lead zirconate titanate and Pb (Zr, Ti) O ₃ , high dielectrics such as barium strontium titanate and (Ba _x Sr _1-x ) TiO ₃ A rate film may be used. When a ferroelectric thin film or a high dielectric constant thin film is used for the gate insulating film, if the dielectric polarization vector in the thin film is oriented from the device surface to the back surface, the threshold value Vth of the element is made more positive. Has the effect of shifting. In the FET of the present invention, the “device surface” is the surface opposite to the substrate (the side on which the buffer layer, the channel layer, the barrier layer, and the cap layer are stacked on the substrate). The “back surface (device back surface)” means a surface on the substrate side (surface opposite to the device surface). When further using a ferroelectric thin film or a high dielectric constant thin film on the gate insulating film, an intrinsic gate capacitance C _g due to its high dielectric constant is increased. Since the mutual conductance (transconductance) g _m has a relationship of g _{m to} C _g ν _peak when the peak velocity of the channel electrons is ν _peak , the increase in the intrinsic gate capacitance C _g causes the mutual conductance g _m to increase. There are increasing benefits. This is particularly advantageous when the FET of the present invention (the first or second FET) is used for information communication.

In each of the embodiments and the examples, Si ₃ N ₄ or Al ₂ O ₃ is used as the surface protective film (passivation film), but other insulators such as SiO ₂ may be used.

  In each of the embodiments and the examples, Ti / Al / Nb / Au is used as a material for the source electrode and the drain electrode, but Ti / Al, Ti / Al / molybdenum (Mo) / Au, Ti / Al Other materials such as / Niobium (Nb) / Au may be used.

  In each of the embodiments and the examples, polysilicon is used as the material of the gate electrode. However, Ni / Au, Ni / Palladium (Pd) / Au, Ni / Platinum (Pt) / Au, Ti / Au Other materials such as metals such as Ti / Pd / Au and Ti / Pt / Au may be used.

  As described above, according to the present invention, there are provided a field effect transistor that can achieve both a high threshold voltage and a low on-resistance, and that can suppress parallel conduction, a method for manufacturing the field effect transistor, and an electronic device. can do. Other effects and applications of the field effect transistor of the present invention are as follows, for example. However, the following are exemplifications, and the field effect transistor of the present invention is not limited only to those having the following effects or used for the following uses.

  Since the field effect transistor (FET) of the present invention is an element using a wide band gap material called a group III nitride semiconductor, it can realize high withstand voltage characteristics and has good reliability. Therefore, the field effect transistor (FET) of the present invention can be used as a power semiconductor element for power control such as a switching power supply and an inverter circuit. According to the present invention, for example, it is possible to obtain an FET that can operate stably even at a severe temperature increase of around 200 ° C. in an engine room of an automobile.

  Furthermore, the FET of the present invention has a high channel mobility due to the HEMT structure, so that the switching speed, that is, the speed of calculating information can be increased. The FET of the present invention can be effectively used as an FET for information communication applications such as communication and computation. That is, it is also suitable for information communication applications. The FET of the present invention can also obtain a high output power in a high frequency region such as a microwave and a millimeter wave. Such a characteristic is an advantage when used for information communication together with the high breakdown voltage characteristic.

  Further, the FET of the present invention has, for example, a normally OFF (enhancement) characteristic, so that a negative power supply is unnecessary, and the power supply system of the electronic device can be simplified, reduced in size, and reduced in cost. Furthermore, since the FET of the present invention has a MIS (MOS) structure in which a gate insulating film is applied to the gate electrode, the gate leakage current can be suppressed to an extremely low level. Therefore, according to the present invention, it is also possible to obtain an FET with a significantly reduced noise figure (Noise Figure, NF). The FET of the present invention is suitable for application to a communication device terminal or the like because, for example, the noise figure is greatly reduced. Further, unlike the GaAs element, the FET of the present invention does not require a harmful substance such as arsenic (As). For this reason, even if the FET of the present invention is used in, for example, a communication device terminal, the load on the environment is small.

  In addition to being a group III nitride field effect transistor, the FET of the present invention can achieve both a high threshold voltage and a low on-resistance as described above, and can suppress parallel conduction. For this reason, the FET of the present invention is also suitable for the purpose of energy saving.

  As described above, the field effect transistor (FET) of the present invention can be widely used in various electronic devices (electronic devices). As described above, the electronic device of the present invention is characterized by including the field effect transistor of the present invention. Applications of the electronic device of the present invention are not particularly limited. For example, a power control device, a motor control device (for example, for an electric vehicle, for an air conditioner), a power supply device (for example, for a computer), inverter lighting, a high-frequency power generation device ( For example, it can be widely used for an image display device, an information recording / reproducing device, a communication device, a computing device (for example, including the FET of the present invention as a computing element), etc.

101 Semi-insulating silicon carbide (SiC) substrate
102 Gallium nitride (GaN) buffer
103 2D electron gas
104 n-type aluminum gallium nitride (AlGaN)
105 3 layer cap
106 n-type gallium nitride (GaN)
107 Aluminum nitride (AlN)
108 n-type gallium nitride (GaN)
109 Aluminum oxide (Al ₂ O ₃ )
110 Gate electrode
111 Source electrode
112 Drain electrode
113 Parallel conduction path
601 Substrate (Si etc.)
602 buffer layer (Al _x Ga _1-x N etc.)
603 channel layer (GaN, etc.)
604 2D electron gas
605 barrier layer (Al _y Ga _1-y N [x <y ≦ 1] etc.)
606 Cap layer (GaN, etc.)
607 Gate insulation film (alumina, etc.)
608 Gate electrode (polysilicon, etc.)
609 Source electrode
610 Drain electrode
611 Surface protective film (silicon nitride film, SiN, etc.)
621 Buffer layer (Al _0.08 Ga _0.92 N)
622 channel layer (GaN)
623 Spacer layer (i-Al _0.28 Ga _0.72 N)
624 Electron supply layer (n-Al _0.28 Ga _0.72 N)
625 Stopper layer (AlN)
626 Cap layer (GaN)
627 Gate insulation film (alumina)
628 Gate electrode (polysilicon)
629 Surface protective film (silicon nitride film)
630 Gate insulation film (silicon oxide film)
640 Surface protective film (alumina)

Claims (25)

Including substrate, buffer layer, channel layer, barrier layer, cap layer, gate insulating film, gate electrode, source electrode, and drain electrode,
The buffer layer is formed of lattice-relaxed Al _x Ga _1-x N (0 ≦ x <1),
The channel layer is Al _u Ga _1-u N (0 ≦ u <x) having an Al composition ratio smaller than that of the buffer layer, and Al _x Ga _1-x N (0 ≦ x <1) having the same composition as the buffer layer. Or formed from InGaN,
The barrier layer is made of Al _y Ga _1-y N (x <y ≦ 1) having a larger Al composition ratio than the buffer layer,
The cap layer is formed of Al _z Ga _1-z N (0 ≦ z <y) having a smaller Al composition ratio than the barrier layer,
The upper surface of the buffer layer, the upper surface of the channel layer, the upper surface of the barrier layer, and the upper surface of the cap layer are respectively a Ga plane or an Al plane perpendicular to the (0001) crystal axis,
The buffer layer, the channel layer, and the barrier layer are stacked in the order on the substrate,
The cap layer is formed in a partial region on the barrier layer;
The gate insulating film and the gate electrode are stacked in the order on the cap layer,
The field effect transistor according to claim 1, wherein the source electrode and the drain electrode are formed on a region of the barrier layer where the cap layer is not formed. Al composition ratio x in the buffer layer satisfies 0 <x <1,
The channel layer is made of Al _u Ga _1-u N (0 ≦ u <x) or InGaN having a smaller Al composition ratio than the buffer layer,
2. The field effect transistor according to claim 1, wherein the Al composition ratio z of the cap layer is smaller than the Al composition ratio x of the buffer layer (0 ≦ z <x).   3. The field effect transistor according to claim 2, wherein the channel layer is made of GaN.   4. The field effect transistor according to claim 2, wherein the cap layer is made of GaN. The channel layer is formed of Al _x Ga _1-x N (0 ≦ x <1) or InGaN having the same composition as the buffer layer;
2. The field effect transistor according to claim 1, wherein at least one of the semiconductor layers formed below the gate electrode is a p-type layer.   6. The field effect transistor according to claim 5, wherein at least one of the buffer layer and the channel layer is the p-type layer. The buffer layer is formed of lattice-relaxed GaN;
7. The field effect transistor according to claim 5, wherein the channel layer is made of GaN or InGaN.   8. The field effect transistor according to claim 7, wherein the channel layer is made of GaN.   9. The field effect transistor according to claim 5, wherein the cap layer contains an n-type impurity or a p-type impurity.   The field effect transistor according to claim 5, wherein the cap layer is made of GaN. In the p-type layer, the surface density of the ionized p-type impurity (ξ _c / q [cm ⁻² ]) and the Al composition ratio y of the barrier layer satisfy the following formula (A): The field effect transistor according to claim 10.

ξ _c /q<5.25×10 ¹³ y (A) Including substrate, buffer layer, channel layer, barrier layer, cap layer, gate insulating film, gate electrode, source electrode, and drain electrode,
The buffer layer, the channel layer, the barrier layer, and the cap layer are each formed of a group III nitride semiconductor,
The upper surface of the buffer layer, the upper surface of the channel layer, the upper surface of the barrier layer, and the upper surface of the cap layer are each a group III atomic plane perpendicular to the (0001) crystal axis,
The buffer layer is lattice-relaxed;
The barrier layer has tensile strain;
The channel layer and the cap layer both have compressive strain, or the channel layer is lattice relaxed and the cap layer has tensile strain;
The buffer layer, the channel layer, and the barrier layer are stacked in the order on the substrate,
The cap layer is formed in a partial region on the barrier layer;
The gate insulating film and the gate electrode are stacked in the order on the cap layer,
The field effect transistor according to claim 1, wherein the source electrode and the drain electrode are formed on a region of the barrier layer where the cap layer is not formed.   13. The field effect transistor according to claim 12, wherein both the channel layer and the cap layer have compressive strain.   14. The field effect transistor according to claim 13, wherein the buffer layer is made of GaN, AlGaN, InGaN, InAlN, or InAlGaN. The channel layer is formed of InGaN, InAlN, InAlGaN, or InN; and
The field effect transistor according to claim 13 or 14, wherein the channel layer forming material has a band gap smaller than that of the buffer layer forming material. The barrier layer is formed of AlGaN, AlN, InGaN, InAlN, InAlGaN, or GaN; and
The field effect transistor according to any one of claims 13 to 15, wherein a material for forming the barrier layer has a larger band gap than a material for forming the buffer layer. The cap layer is formed of InGaN, InAlN, InAlGaN, or InN; and
The field effect transistor according to any one of claims 13 to 16, wherein a material for forming the cap layer has a smaller band gap than a material for forming the buffer layer. The channel layer is lattice relaxed;
The cap layer has tensile strain;
13. The field effect transistor according to claim 12, wherein at least one of the semiconductor layers formed below the gate electrode is a p-type layer.   The field effect transistor according to claim 18, wherein the buffer layer is formed of GaN, AlGaN, InGaN, InAlN, InAlGaN, or InN.   The field effect transistor according to claim 18 or 19, wherein the channel layer is formed of GaN, AlGaN, InGaN, InAlN, InAlGaN, or InN. The barrier layer is formed of AlGaN, AlN, InGaN, InAlN, InAlGaN, or GaN; and
21. The field effect transistor according to claim 18, wherein a material for forming the barrier layer has a larger band gap than a material for forming the buffer layer. The cap layer is formed of GaN, AlGaN, InGaN, InAlN, InAlGaN, or InN; and
The field effect transistor according to any one of claims 18 to 21, wherein a material for forming the cap layer has a smaller band gap than a material for forming the barrier layer. A semiconductor layer laminating step of laminating a buffer layer, a channel layer, a barrier layer, and a cap layer in the above order on a substrate;
A gate insulating film material forming step of forming a gate insulating film material on the cap layer;
A gate electrode material forming step of forming a gate electrode material on the gate insulating film material;
Forming a gate electrode by removing a part of the gate electrode material; and
A gate insulating film forming step of forming a gate insulating film by removing a part of the gate insulating film material;
A cap layer partial removal step of removing a part of the cap layer;
Forming a source electrode and a drain electrode on the barrier layer on the region where the cap layer has been removed,
In the semiconductor layer stacking step, the buffer layer, the channel layer, the barrier layer, and the cap layer are each grown on a group III atomic plane perpendicular to the (0001) crystal axis,
The buffer layer is formed of lattice-relaxed Al _x Ga _1-x N (0 ≦ x <1),
The channel layer is made of Al _u Ga _1-u N (0 ≦ u <x) having an Al composition ratio smaller than that of the buffer layer, Al _x Ga _1-x N (0 ≦ x <1) having the same composition as the buffer layer. Or formed from InGaN,
The barrier layer is formed of Al _y Ga _1-y N (x <y ≦ 1) having a higher Al composition ratio than the buffer layer,
A method of manufacturing a field effect transistor, wherein the cap layer is formed of Al _z Ga _1-z N (0 ≦ z <y) having an Al composition ratio smaller than that of the barrier layer. A semiconductor layer laminating step of laminating a buffer layer, a channel layer, a barrier layer, and a cap layer in the above order on a substrate;
A gate insulating film material forming step of forming a gate insulating film material on the cap layer;
A gate electrode material forming step of forming a gate electrode material on the gate insulating film material;
Forming a gate electrode by removing a part of the gate electrode material; and
A gate insulating film forming step of forming a gate insulating film by removing a part of the gate insulating film material;
A cap layer partial removal step of removing a part of the cap layer;
Forming a source electrode and a drain electrode on the barrier layer on the region where the cap layer has been removed,
In the semiconductor layer stacking step, the buffer layer, the channel layer, the barrier layer, and the cap layer are each grown on a group III atomic plane perpendicular to the (0001) crystal axis,
Forming the buffer layer so as to be lattice-relaxed;
Forming the barrier layer to have tensile strain;
Forming the channel layer and the cap layer so that both the channel layer and the cap layer have compressive strain, or the channel layer is lattice-relaxed and the cap layer has tensile strain. A method for manufacturing a field effect transistor, which is characterized.   An electronic device comprising the field effect transistor according to any one of claims 1 to 22, or the field effect transistor manufactured by the manufacturing method according to claim 23 or 24.

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