WO2014002672A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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WO2014002672A1
WO2014002672A1 PCT/JP2013/064851 JP2013064851W WO2014002672A1 WO 2014002672 A1 WO2014002672 A1 WO 2014002672A1 JP 2013064851 W JP2013064851 W JP 2013064851W WO 2014002672 A1 WO2014002672 A1 WO 2014002672A1
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electrode
semiconductor device
dielectric structure
dielectric
gan
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PCT/JP2013/064851
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French (fr)
Japanese (ja)
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佐藤　義浩
堤　岳志
三千矢 山田
亮 田中
康真 佐々木
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次世代パワーデバイス技術研究組合
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device having a group III-V nitride compound semiconductor used for power electronics devices and the like, and a method for manufacturing the same.
  • the group III nitride semiconductor has a high dielectric breakdown electric field of about 3.3 MV / cm, and it is considered that a power semiconductor device having the same performance can be produced with a smaller chip area than a conventional Si device.
  • a group III nitride semiconductor uses an insulating substrate such as sapphire or a conductive substrate such as a Si substrate, the resistance is increased by using AlN in the buffer layer on the substrate. Elements are mainstream. Therefore, when a diode or a transistor is manufactured, electrodes to which a high voltage is applied exist on the same plane.
  • each electrode has a comb-teeth electrode structure, and a source electrode and a drain electrode having a voltage difference of 600 V are alternately arranged on the same plane at an interval of about 10 ⁇ m. .
  • both the width of the source electrode and the drain electrode as the wiring are increased, and the distance between these electrodes is reduced to several ⁇ m. For this reason, the electric field between electrodes reaches several MV / cm by an average electric field, and becomes still higher locally.
  • Si devices have been filled with polyimide between the electrodes. This is because the breakdown electric field of Si is 0.3 MV / cm, whereas that of polyimide is 4 to 5 MV / cm, and the dielectric breakdown electric field has a difference of about 10 times.
  • the dielectric breakdown electric field of GaN is 3.3 MV / cm, which is about the same as that of polyimide, so there is no problem with the average electric field, but at the electric field concentration point such as the corner of the electrode, the dielectric breakdown electric field of polyimide is reduced. There is a possibility of exceeding.
  • the dielectric breakdown electric field of polyimide may be exceeded. Therefore, if the space between the electrodes is simply filled with polyimide as in the prior art, there is a problem that polyimide causes dielectric breakdown.
  • Patent Document 1 a dielectric structure in which the withstand voltage of an insulating film between wirings is higher than air and lower than GaN has been proposed.
  • Patent Document 1 a dielectric structure in which the withstand voltage of an insulating film between wirings is higher than air and lower than GaN has been proposed.
  • Patent Document 1 the insulating film yields before GaN, and a high voltage device cannot be manufactured.
  • Patent Document 2 a dielectric structure in which an emitter electrode covers an element upper portion through an interlayer insulating film has been proposed (Patent Document 2).
  • the breakdown voltage of the interlayer insulating film between the collector electrode and the electrode extending from the emitter electrode seems to be a problem, but since the dielectric breakdown voltage of Si is low, it still remains around the collector electrode. Electric field concentration is considered to be a problem. For this reason, an insulating layer having a shape that bites into the semiconductor layer is provided near the collector electrode to prevent electric field concentration.
  • the insulating layer is Si, it is considered that the breakdown voltage of the interlayer insulating film is not a problem because the breakdown voltage of Si is low.
  • lateral IGBTs have a structure in which a collector electrode and an emitter electrode to which a high voltage is applied intersect (Patent Document 3).
  • Patent Document 3 the electric field concentration in the semiconductor portion is considered, but the interlayer insulating film itself is not considered.
  • the low voltage part covers the periphery of the high voltage part in the Si device, and the high voltage MOSFET is connected between them to devise the structure.
  • a high electric field is generated in the insulating film. This is because the Si device can adopt not only a horizontal structure but also a vertical structure, and can have a withstand voltage in the vertical direction. Further, in a configuration in which a high electric field is generated in the interlayer insulating film (see FIG. 17), an electric field is not generated between the opposing electrodes as in a GaN device, and the electric field strength in the interlayer insulating film is lower than that of GaN. it is conceivable that.
  • An object of the present invention is to provide a semiconductor device capable of improving reliability even in the case where a high electric field is generated between electrodes in a semiconductor device having a lateral structure, and a method for manufacturing the same.
  • a semiconductor device is a semiconductor device having a lateral structure, a substrate, a first semiconductor layer stacked on the substrate and containing a GaN-based compound, and the first semiconductor.
  • a second semiconductor layer including another GaN-based compound laminated on the layer and heterojunction with the GaN-based compound; a first electrode and a second electrode formed on the surface of the second semiconductor layer at a predetermined interval;
  • a first dielectric structure made of a first material having a predetermined dielectric constant and integrally covering the opposing surfaces of the first electrode and the second electrode and the surface of the second semiconductor layer.
  • a second dielectric structure comprising a second material on the first dielectric structure and formed between the first electrode and the second electrode and having a dielectric constant equal to or higher than that of the first material And a half characterized by comprising Body device.
  • the first material is preferably SiO 2
  • the second material is preferably a material having a dielectric constant equal to or higher than that of polyimide.
  • the second material is preferably SiO 2 .
  • first electrode and the second electrode may form a comb electrode structure.
  • the one dielectric structure may be formed to cover at least a part of the upper surface of the first electrode and at least a part of the upper surface of the second electrode.
  • the first dielectric structure may be formed to cover the entire upper surface of the first electrode and the upper surface of the second electrode.
  • the semiconductor device may be composed of a diode or a transistor.
  • a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having a lateral structure, the step of forming a first semiconductor layer containing a GaN-based compound on a substrate, and on the first semiconductor layer, Forming a second semiconductor layer including another GaN-based compound heterojunction with the GaN-based compound, and forming a first electrode and a second electrode at a predetermined interval on a surface of the second semiconductor layer.
  • a first dielectric structure that integrally covers the opposing surfaces of the first electrode and the second electrode and the surface of the second semiconductor layer is formed of a first material having a predetermined dielectric constant. Forming a second dielectric structure on the first dielectric structure and between the first electrode and the second electrode, using a material having a dielectric constant equal to or higher than that of the first material And a step of And wherein the door.
  • the first material and the second material are SiO 2
  • the second dielectric structure is integrally formed with the first dielectric structure by a cathode coupling type PECVD method. .
  • the first dielectric structure may be formed to cover at least part of the upper surface of the first electrode and at least part of the upper surface of the second electrode.
  • the first dielectric structure is formed so as to integrally cover the opposing surfaces of the first electrode and the second electrode and the surface of the second semiconductor layer, And it consists of the 1st material which has a predetermined dielectric constant.
  • the second dielectric structure is formed of a second material on the first dielectric structure and formed between the first electrode and the second electrode, and having a dielectric constant equal to or higher than that of the first material. Become. That is, between the first electrode and the second electrode, a layer of the first material is formed in the vicinity of each electrode where electric field concentration is likely to occur, and the remaining material has the same dielectric constant as that of the first material or more dielectric.
  • the layer of the second material having a high rate is formed, it is possible to prevent the dielectric breakdown that easily occurs in the vicinity of each electrode, and to prevent the dielectric structure from cracking. Accordingly, reliability can be improved even when a high electric field is generated between the electrodes.
  • the first dielectric structure formed of SiO 2 by forming the second dielectric structure with a high dielectric constant than SiO 2 polyimide, dielectric constant and low but SiO 2 high dielectric breakdown voltage, dielectric constant
  • the gap between the electrodes is embedded with polyimide which is high and does not easily crack. Therefore, it is possible to prevent a dielectric breakdown that easily occurs in the vicinity of each electrode, and it is possible to manufacture a highly reliable dielectric structure that does not cause cracks.
  • FIG. 1 is a plan view schematically showing a configuration of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a partial cross-sectional view of the semiconductor device taken along line AA in FIG. 1.
  • FIG. 3 is a cross-sectional view showing the dielectric structure of FIG. 2, wherein (a) shows a first dielectric structure and (b) shows a second dielectric structure.
  • FIG. 6 is a partial cross-sectional view showing a modification of the semiconductor device of FIG. 2.
  • FIG. 10 is a partial cross-sectional view showing another modification of the semiconductor device of FIG. 2.
  • FIG. 1 shows a semiconductor device according to this embodiment, for example, a diode having an AlGaN / GaN heterojunction structure.
  • this semiconductor device 1 is a semiconductor device having a lateral structure having comb-shaped electrodes, and is formed on a laminate 2 including a group III-V nitride semiconductor and on the surface of the laminate.
  • a comb-shaped Schottky electrode 3 and an ohmic electrode 4 are provided.
  • Each of these electrodes 3 and 4 has a plurality of comb teeth extending from the side of each electrode, and by alternately arranging a plurality of comb teeth provided on these electrodes, High density is realized.
  • FIG. 2 is a partial cross-sectional view of the semiconductor device 1 taken along line AA in FIG.
  • the semiconductor device 1 includes a substrate 11 made of Si, a buffer layer 12 formed on the substrate, a GaN layer 13 (first semiconductor layer) stacked on the buffer layer 12, and a GaN layer 13.
  • the semiconductor device 1 is formed so as to integrally cover the opposing surfaces of the Schottky electrode 3 and the ohmic electrode 4 and the surface 14a of the AlGaN layer 14, and is a dielectric structure 5 (first material) made of SiO 2 (first material).
  • the Schottky electrode 3 and the ohmic electrode 4 have, for example, a substantially rectangular cross section, and the opposing surfaces of the Schottky electrode 3 and the ohmic electrode 4 constitute inner side surfaces 3a and 4a, respectively.
  • the Schottky electrode 3 and the ohmic electrode 4 are made of a highly conductive material.
  • the Schottky electrode 3 is, for example, in order from the semiconductor layer side, Ni (100 nm), Au (100 nm), Al or Al alloy (5 to 10 ⁇ m).
  • the ohmic electrode 4 is made of, for example, Ti (25 nm), Al (300 nm), Al, or an Al alloy (5 to 10 ⁇ m) in this order from the semiconductor layer side.
  • the Schottky electrode 3 and the ohmic electrode 4 are formed with a width of 10 ⁇ m, for example.
  • the dielectric structure 5 includes a bottom surface portion 5 a formed on the surface 14 a of the AlGaN layer 14, and a side surface portion 5 b that covers the inner surface 3 a of the Schottky electrode 3.
  • the dielectric structure 5 is made of, for example, SiO 2 and has a thickness T1 of, for example, 2.0 ⁇ m.
  • the dielectric structure 6 has a layer thickness portion 6a formed on the bottom surface portion 5a and thin layer portions 6b and 6c formed on the top surface portions 5d and 5e. ing.
  • the layer thickness portion 6 a is formed so as to be embedded between the Schottky electrode 3 and the ohmic electrode 4.
  • the thin layer portions 6b and 6c are formed so as to cover the entire upper surfaces 50d and 50e, respectively.
  • the dielectric structure 6 is made of an organic film having a dielectric constant higher than that of SiO 2 , for example, a high dielectric constant polyimide having a dielectric constant of 4.0 or more, and the width D of the layer thickness portion 6a is about 6.0 ⁇ m. It is. By using such a material, the electric field in the organic film can be set to ⁇ 1 / ⁇ 2 ( ⁇ 1 : dielectric constant of SiO 2 , ⁇ 2 : dielectric constant of the organic film). Can be extended.
  • the dielectric structures 5 and 6 are used. Since the charges are the same because of the series capacitor, the lower the dielectric constant, the higher the electric field applied. Therefore, by adjusting the thickness of the dielectric structures 5 and 6 between the electrodes, it is possible to realize a long life without generating an excessive voltage in the low breakdown voltage dielectric. Specifically, when the dielectric structure 5 made of the first material is formed with the minimum necessary thickness and the remaining portion is embedded with the second material, an electric field is generated in the dielectric structure 5 having a relatively low dielectric constant. It will take. For this reason, it is possible to prevent dielectric breakdown due to high voltage while preventing cracking due to thickening.
  • a two-dimensional electron gas layer is generated by the piezoelectric effect on the GaN layer 13 side of the AlGaN / GaN heterojunction interface.
  • the ohmic electrode 4 is electrically connected to the Schottky electrode 3 through the AlGaN / GaN layer on which the two-dimensional electron gas layer 13a having a high carrier concentration is formed.
  • the two-dimensional electron gas layer serves as a carrier and the AlGaN / GaN layer has low resistance and high mobility, the on-resistance of the semiconductor device 1 can be reduced and a low on-voltage can be realized. Yes.
  • the dielectric structure 5 integrally forms the opposing surfaces of the Schottky electrode and the ohmic electrode and the surface of the second semiconductor layer. And is made of SiO 2 having a predetermined dielectric constant.
  • the dielectric structure 6 is made of polyimide which is on the dielectric structure 5 and is formed between the Schottky electrode and the ohmic electrode and has a dielectric constant equal to or higher than that of SiO 2 .
  • an SiO 2 layer is formed in the vicinity of each electrode where electric field concentration is likely to occur, and a polyimide layer having a higher dielectric constant than SiO 2 is formed for the remaining part. It is possible to prevent dielectric breakdown that is likely to occur in the vicinity of each electrode, and to prevent cracking of the dielectric structure. Moreover, even if it is difficult to form the entire dielectric structure with only SiO 2 , it can be easily manufactured by using the two materials having the above relationship, and the degree of freedom in design can be improved. it can.
  • the dielectric breakdown voltage between the electrodes can be improved, even when the comb-shaped electrodes are arranged at a high density, dielectric breakdown can be prevented from occurring between the electrodes, and a low on-resistance and high breakdown voltage can be prevented. It is possible to manufacture a simple semiconductor device.
  • FIG. 4 is a partial cross-sectional view showing a modification of the semiconductor device of FIG.
  • the semiconductor device of FIG. 2 has dielectric structures 5 and 6, but the semiconductor device of FIG. 4 is different in that it has an integrally formed dielectric structure 20.
  • the semiconductor device of FIG. 2 is demonstrated.
  • the dielectric structure 20 is formed so as to integrally cover the opposing surfaces of the Schottky electrode 3 and the ohmic electrode 4 and the surface 14 a of the AlGaN layer 14, and the Schottky electrode 3. Are arranged so as to be buried between the ohmic electrodes 4. That is, the dielectric structure 20 of this modification is obtained by integrally molding the semiconductor structures 5 and 6 of FIG. 2 with SiO 2 .
  • the dielectric structure 20 has a layer thickness portion 20a formed on the surface 14a of the AlGaN layer 14 and thin layer portions 20b and 20c formed on the upper surfaces 3b and 4b.
  • the dielectric structure needs to be embedded between the Schottky electrode 3 and the ohmic electrode 4. Therefore, the thickness of the dielectric structure depends on the thickness of each electrode formed on the AlGaN layer 14, and in particular, when the thickness of each electrode is increased to about 10 ⁇ m, the thickness of the anode coupling type PECVD is increased. When a normal CVD method is used, the entire dielectric structure may not be formed with only SiO 2 .
  • the thickness T2 of the dielectric structure 20 (distance from the surface in contact with the surface 14a of the AlGaN layer 14 to the upper surface) is larger than the thickness (height) of the Schottky electrode 3 or the ohmic electrode 4. Is done.
  • the dielectric structure 20 is formed by, for example, a cathode coupling type PECVD method.
  • Cathode coupling type PECVD is a type of CVD in which charged particles ionized by plasma are incident on a film to be formed. Since the SiO 2 network is divided by the incident particles, the internal stress is relieved, and as a result, it is presumed that a thick SiO 2 film can be formed as compared with ordinary CVD. Therefore, even when the thickness of each electrode is large, the dielectric structure 20 made of SiO 2 can be formed between the electrodes by adopting the cathode coupling type PECVD method. Further high breakdown voltage can be realized.
  • FIG. 5 is a partial cross-sectional view showing a modification of the semiconductor device of FIG.
  • the dielectric structure 30 has a layer thickness portion 30a formed on the surface 14a of the AlGaN layer 14, and layer thin portions 30b and 30c formed on the upper surfaces 3b and 4b. Yes.
  • the thin layer portion 30b is formed so as to cover a part of the upper surface 3b
  • the thin layer portion 30c is formed so as to cover a part of the upper surface 4b. That is, in the dielectric structure 20, the upper surface 3 b of the Schottky electrode 3 and a part of the ohmic electrode 4 are exposed.
  • the dielectric structure 30 As described above, by not forming the dielectric structure 30 at a position where no electric field is generated on the upper surface of the electrode, the residual stress of the dielectric structure 30 can be reduced, and cracking of the dielectric structure 30 is surely prevented. can do.
  • the invention made by the present inventor has been specifically described based on the embodiment.
  • the present invention is not limited to the above embodiment, and can be changed without departing from the gist thereof.
  • the electronic device is a diode having a group III nitride semiconductor, but is not limited thereto, and may be a transistor having a group III nitride semiconductor.
  • the present invention can be applied to an insulating film between a source electrode and a drain electrode. Further, it may be an SOI diode or an SOI transistor.
  • an ohmic electrode drain electrode
  • a Schottky electrode gate electrode
  • the SiO 2 which is an interlayer insulating film formed by plasma CVD method or a thermal CVD method, and opening the SiO 2 by etching the necessary portion of the ohmic electrode and the Schottky electrode by photolithography and hydrofluoric acid.
  • pure Al or Al alloy AlSi, AlCu, etc.
  • AlSi, AlCu, etc. pure Al or Al alloy
  • polyimide dielectric constant 4.0
  • the coating thickness was applied under the condition that the bare silicon substrate on which no pattern was formed was 20 ⁇ m so that polyimide was also formed on the upper surface of the electrode. Thereafter, a resist was applied and the polyimide was patterned, followed by curing at 380 ° C.
  • Example 2 instead of the polyimide of Example 1, an organic film having a dielectric constant higher than that of polyimide was used.
  • the dielectric constant of SiO 2 was 3.9 and the dielectric constant between the organic films was X, the charge was 3.9 / X times, so a lower voltage was applied to the organic film than in the case of polyimide.
  • Example 3 It was produced in the same manner as in Example 1 until the aluminum wiring was formed.
  • a SiO 2 film having a thickness of 5000 nm was formed by cathode-coupled PECVD.
  • the raw materials at that time were TEOS and oxygen.
  • the pad portion was opened with buffered hydrofluoric acid containing ethylene glycol.
  • polyimide was applied.
  • the coating thickness was applied on a bare silicon substrate on which no pattern was formed under the condition of 20 ⁇ m.
  • a resist was applied and the polyimide was patterned, followed by curing at 380 ° C.

Abstract

Provided is a semiconductor device with a horizontal structure, wherein the device can have improved reliability even if a high electric field arises between electrodes. A semiconductor device (1) is provided with the following: a silicon substrate (11); a buffer layer (12) formed on the substrate; a GaN layer (13) layered on top of the buffer layer (12); an AlGaN layer (14) that is layered on top of the GaN layer (13) and that comprises another GaN-based compound hetero-bonded to the GaN; and a Schottky electrode (3) and an ohmic electrode (4) formed at a prescribed distance apart from each other on the surface (14a) of the AlGaN layer (14). Moreover, the semiconductor device (1) is provided with a dielectric structure (5) that comprises SiO2 and that integrally covers the opposing surfaces (3a, 4a) of the electrodes (3, 4) and the surface (14a) of the AlGaN layer (14), and a dielectric structure (6) that is disposed on top of the dielectric structure (5) and between the electrodes (3, 4) and that comprises a material with a dielectric constant at least that of SiO2.

Description

半導体デバイスおよびその製造方法Semiconductor device and manufacturing method thereof
　本発明は、パワーエレクトロニクス用デバイス等に用いられるＩＩＩ－Ｖ族窒化物系化合物半導体を有する半導体デバイスおよびその製造方法に関する。 The present invention relates to a semiconductor device having a group III-V nitride compound semiconductor used for power electronics devices and the like, and a method for manufacturing the same.
　ＩＩＩ族窒化物半導体は、およそ３．３ＭＶ／ｃｍの高い絶縁破壊電界を有しており、従来のＳｉデバイスに比べて小さいチップ面積で同じ性能のパワー半導体装置が作製できると考えられている。しかし、ＩＩＩ族窒化物半導体は、サファイヤなどの絶縁基板上やＳｉ基板等の導電基板を使用しても、基板上のバッファ層内にＡｌＮを使用することで高抵抗化していることから、横型素子が主流である。そのため、ダイオードやトランジスタを作製する場合、高電圧が印加される電極が同一平面に存在することになる。特に、素子の高密度化を図った場合、各電極が櫛歯型電極構造となり、電圧差が６００Ｖのソース電極とドレイン電極が１０μｍ程度の間隔で、交互に同一平面に配置されることになる。特に、配線抵抗を低減するためには配線幅を広げる必要があることから、配線としてのソース電極とドレイン電極の双方の幅が広げられ、これら電極間の距離が数μｍまで縮小される。このため、電極間電界は平均電界で数ＭＶ／ｃｍに達し、局所的には更に高くなる。 The group III nitride semiconductor has a high dielectric breakdown electric field of about 3.3 MV / cm, and it is considered that a power semiconductor device having the same performance can be produced with a smaller chip area than a conventional Si device. However, even if a group III nitride semiconductor uses an insulating substrate such as sapphire or a conductive substrate such as a Si substrate, the resistance is increased by using AlN in the buffer layer on the substrate. Elements are mainstream. Therefore, when a diode or a transistor is manufactured, electrodes to which a high voltage is applied exist on the same plane. In particular, when increasing the density of elements, each electrode has a comb-teeth electrode structure, and a source electrode and a drain electrode having a voltage difference of 600 V are alternately arranged on the same plane at an interval of about 10 μm. . In particular, since it is necessary to increase the wiring width in order to reduce the wiring resistance, both the width of the source electrode and the drain electrode as the wiring are increased, and the distance between these electrodes is reduced to several μm. For this reason, the electric field between electrodes reaches several MV / cm by an average electric field, and becomes still higher locally.
　従来、Ｓｉデバイスでは電極間にポリイミドを充填していた。これは、Ｓｉの絶縁破壊電界が０．３ＭＶ／ｃｍであるのに対し、ポリイミドは４～５ＭＶ／ｃｍであり、絶縁破壊電界に１０倍程度の差があることによる。しかし、ＧａＮの絶縁破壊電界は３．３ＭＶ／ｃｍであり、ポリイミドと同程度であることから、平均電界では問題ないが、電極の角隅部など電界集中点においては、ポリイミドの絶縁破壊電界を超す可能性がある。 Traditionally, Si devices have been filled with polyimide between the electrodes. This is because the breakdown electric field of Si is 0.3 MV / cm, whereas that of polyimide is 4 to 5 MV / cm, and the dielectric breakdown electric field has a difference of about 10 times. However, the dielectric breakdown electric field of GaN is 3.3 MV / cm, which is about the same as that of polyimide, so there is no problem with the average electric field, but at the electric field concentration point such as the corner of the electrode, the dielectric breakdown electric field of polyimide is reduced. There is a possibility of exceeding.
　さらに配線抵抗を下げるために配線幅を広げ、配線間距離が狭くなると、ポリイミドの絶縁破壊電界を超える可能性がある。そのため、従来のように電極間を単にポリイミドで充填していたのでは、ポリイミドが絶縁破壊を起こす問題があった。 If the wiring width is increased to further reduce the wiring resistance and the distance between the wirings is narrowed, the dielectric breakdown electric field of polyimide may be exceeded. Therefore, if the space between the electrodes is simply filled with polyimide as in the prior art, there is a problem that polyimide causes dielectric breakdown.
　例えば、配線間の絶縁膜の耐圧が空気より高く、ＧａＮより低くなっている誘電体構造が提案されている（特許文献１）。しかしながら、本構成では、ＧａＮより先に絶縁膜が降伏してしまい、高耐圧素子を作製することはできない。 For example, a dielectric structure in which the withstand voltage of an insulating film between wirings is higher than air and lower than GaN has been proposed (Patent Document 1). However, in this configuration, the insulating film yields before GaN, and a high voltage device cannot be manufactured.
　また、横型ＩＧＢＴ（Insulated Gate Bipolar Transistor）において、エミッタ電極が、素子上部を層間絶縁膜を介して覆っている誘電体構造が提案されている（特許文献２）。本構成では、必然的にコレクタ電極の上面が覆われることになる。このような構造の場合、コレクタ電極とエミッタ電極から延びた電極との間の層間絶縁膜の耐圧が問題になると思われるが、Ｓｉの絶縁破壊耐圧が低い為、それ依然に、コレクタ電極周辺の電界集中が問題になると考えられる。このため、コレクタ電極近傍に半導体層に食い込む形状の絶縁層を設けて、電界集中を防いでいる。このように、絶縁層がＳｉの場合には、Ｓｉの絶縁破壊耐圧が低い為、層間絶縁膜の耐圧は問題にならないと考えられる。 Also, in a lateral IGBT (Insulated Gate Bipolar Transistor), a dielectric structure in which an emitter electrode covers an element upper portion through an interlayer insulating film has been proposed (Patent Document 2). In this configuration, the upper surface of the collector electrode is necessarily covered. In such a structure, the breakdown voltage of the interlayer insulating film between the collector electrode and the electrode extending from the emitter electrode seems to be a problem, but since the dielectric breakdown voltage of Si is low, it still remains around the collector electrode. Electric field concentration is considered to be a problem. For this reason, an insulating layer having a shape that bites into the semiconductor layer is provided near the collector electrode to prevent electric field concentration. Thus, when the insulating layer is Si, it is considered that the breakdown voltage of the interlayer insulating film is not a problem because the breakdown voltage of Si is low.
　また、他の横型ＩＧＢＴは、高電圧のかかるコレクタ電極とエミッタ電極が交差している構造を有している（特許文献３）。この横型ＩＧＢＴでは、特許文献２の構成と同様、半導体部の電界集中について考慮しているものの、層間絶縁膜自体については考慮していない。 Further, other lateral IGBTs have a structure in which a collector electrode and an emitter electrode to which a high voltage is applied intersect (Patent Document 3). In this lateral IGBT, like the configuration of Patent Document 2, the electric field concentration in the semiconductor portion is considered, but the interlayer insulating film itself is not considered.
　特許文献４では、ＨＶ ＩＣ（High Voltage Integrated Circuit）の一例として、Ｓｉデバイスにおいて高圧部の周辺を低圧部が覆うようにして、かつその間を高耐圧ＭＯＳＦＥＴで繋ぎ、その構造を工夫することで層間絶縁膜に高い電界が生じるようにしている。これはＳｉデバイスが横型構造のみならず縦型構造を採用することができ、縦方向で耐圧を持たせることが可能となっている。また、層間絶縁膜に高い電界が発生する構成では（図１７参照）、ＧａＮのデバイスのように対向する電極間で電界が生じる訳ではなく、層間絶縁膜での電界強度はＧａＮに比べて低いと考えられる。このように、ＳｉのＨＶ ＩＣ等においても、横型の対向する配線間の耐圧を考慮する必要が無いと考えられる。また、この特許文献４におけるトレンチ分離部の作製方法では（図４参照）、トレンチをエッチングして熱酸化しているが、本方法はＳｉであるが故に実行できるのであり、ＧａＮで実行するのは本質的に困難である。 In Patent Document 4, as an example of HV IC (High Voltage Integrated Circuit), the low voltage part covers the periphery of the high voltage part in the Si device, and the high voltage MOSFET is connected between them to devise the structure. A high electric field is generated in the insulating film. This is because the Si device can adopt not only a horizontal structure but also a vertical structure, and can have a withstand voltage in the vertical direction. Further, in a configuration in which a high electric field is generated in the interlayer insulating film (see FIG. 17), an electric field is not generated between the opposing electrodes as in a GaN device, and the electric field strength in the interlayer insulating film is lower than that of GaN. it is conceivable that. Thus, it is considered that it is not necessary to consider the breakdown voltage between the horizontal opposing wirings even in a Si HV IC. Further, in the method of manufacturing the trench isolation part in this Patent Document 4 (see FIG. 4), the trench is etched and thermally oxidized, but this method can be executed because it is Si, and is performed with GaN. Is inherently difficult.
特開２０１１－１４６４４６号公報JP 2011-146446 A 特開２０１１－１０８８００号公報JP 2011-108800 A 特開２００１－５７４３１号公報JP 2001-57431 A 特許第４７８８７４９号公報Japanese Patent No. 4778849
　本発明の目的は、横型構造の半導体デバイスにおいて、電極間に高電界が生じる場合であっても信頼性を向上することができる半導体デバイスおよびその製造方法を提供することにある。 An object of the present invention is to provide a semiconductor device capable of improving reliability even in the case where a high electric field is generated between electrodes in a semiconductor device having a lateral structure, and a method for manufacturing the same.
　上記目的を達成するために、本発明に係る半導体デバイスは、横型構造の半導体デバイスであって、基板と、前記基板上に積層され、ＧａＮ系化合物を含む第１半導体層と、前記第１半導体層上に積層され、前記ＧａＮ系化合物とヘテロ接合された他のＧａＮ系化合物を含む第２半導体層と、前記第２半導体層の表面に所定間隔で形成された第１電極および第２電極と、前記第１電極および前記第２電極のそれぞれの対向面と、前記第２半導体層の表面とを一体的に覆って形成され、所定の誘電率を有する第１材料からなる第１誘電体構造と、前記第１誘電体構造上であり且つ前記第１電極および第２電極の間に形成され、前記第１材料と同じかそれ以上の誘電率を有する第２材料からなる第２誘電体構造と、を備えることを特徴とする半導体デバイス。 In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a lateral structure, a substrate, a first semiconductor layer stacked on the substrate and containing a GaN-based compound, and the first semiconductor. A second semiconductor layer including another GaN-based compound laminated on the layer and heterojunction with the GaN-based compound; a first electrode and a second electrode formed on the surface of the second semiconductor layer at a predetermined interval; A first dielectric structure made of a first material having a predetermined dielectric constant and integrally covering the opposing surfaces of the first electrode and the second electrode and the surface of the second semiconductor layer. A second dielectric structure comprising a second material on the first dielectric structure and formed between the first electrode and the second electrode and having a dielectric constant equal to or higher than that of the first material And a half characterized by comprising Body device.
　前記第１材料はＳｉＯ２であるのが好ましく、また、前記第２材料は、ポリイミドと同じかそれ以上の誘電率を有する材料であるのが好ましい。 The first material is preferably SiO 2 , and the second material is preferably a material having a dielectric constant equal to or higher than that of polyimide.
　また、前記第２材料がＳｉＯ２であるのが好ましい。 The second material is preferably SiO 2 .
　また、前記第１電極および前記第２電極が櫛歯型電極構造を形成してもよい。 In addition, the first electrode and the second electrode may form a comb electrode structure.
　さらに、前記１誘電体構造が、前記第１電極の上面の少なくとも一部と、前記第２電極の上面の少なくとも一部とを覆って形成されてもよい。 Furthermore, the one dielectric structure may be formed to cover at least a part of the upper surface of the first electrode and at least a part of the upper surface of the second electrode.
　また、前記第１誘電体構造が、前記第１電極の上面および前記第２電極の上面の全面を覆って形成されてもよい。 The first dielectric structure may be formed to cover the entire upper surface of the first electrode and the upper surface of the second electrode.
　また、前記半導体デバイスがダイオードまたはトランジスタで構成されてもよい。 Further, the semiconductor device may be composed of a diode or a transistor.
　本発明に係る半導体デバイスの製造方法は、横型構造の半導体デバイスの製造方法であって、基板上に、ＧａＮ系化合物を含む第１半導体層を形成するステップと、前記第１半導体層上に、前記ＧａＮ系化合物とヘテロ接合された他のＧａＮ系化合物を含む第２半導体層を形成するステップと、前記第２半導体層の表面に、第１電極および第２電極を所定の間隔で形成するステップと、前記第１電極および前記第２電極のそれぞれの対向面と、前記第２半導体層の表面とを一体的に覆う第１誘電体構造を、所定の誘電率を有する第１材料で形成するステップと、前記第１誘電体構造上であり且つ前記第１電極と前記第２電極との間に、前記第１材料と同じかそれ以上の誘電率を有する材料で第２誘電体構造を形成するステップと、を備えることを特徴とする。 A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a lateral structure, the step of forming a first semiconductor layer containing a GaN-based compound on a substrate, and on the first semiconductor layer, Forming a second semiconductor layer including another GaN-based compound heterojunction with the GaN-based compound, and forming a first electrode and a second electrode at a predetermined interval on a surface of the second semiconductor layer. And a first dielectric structure that integrally covers the opposing surfaces of the first electrode and the second electrode and the surface of the second semiconductor layer is formed of a first material having a predetermined dielectric constant. Forming a second dielectric structure on the first dielectric structure and between the first electrode and the second electrode, using a material having a dielectric constant equal to or higher than that of the first material And a step of And wherein the door.
　また、前記第１材料および前記第２材料がＳｉＯ２であり、前記第２誘電体構造は、カソードカップリング型ＰＥＣＶＤ法にて、前記第１誘電体構造と一体的に成形されるのが好ましい。 In addition, it is preferable that the first material and the second material are SiO 2 , and the second dielectric structure is integrally formed with the first dielectric structure by a cathode coupling type PECVD method. .
　また、前記第１誘電体構造が、前記第１電極の上面の少なくとも一部と、前記第２電極の上面の少なくとも一部とを覆って形成されてもよい。 The first dielectric structure may be formed to cover at least part of the upper surface of the first electrode and at least part of the upper surface of the second electrode.
　本発明によれば、横型構造の半導体デバイスにおいて、第１誘電体構造が、第１電極および第２電極のそれぞれの対向面と、第２半導体層の表面とを一体的に覆って形成され、かつ、所定の誘電率を有する第１材料からなる。また、第２誘電体構造が、第１誘電体構造上であり且つ第１電極および第２電極の間に形成され、かつ、第１材料と同じかそれ以上の誘電率を有する第２材料からなる。すなわち、第１電極と第２電極の間で、電界集中の生じ易い各電極の近傍には第１材料の層が形成され、残りの部分については第１材料と誘電率が同じ、またはより誘電率の高い第２材料の層が形成されるので、各電極の近傍で生じ易い絶縁破壊を防止することができ、加えて誘電体構造の割れを防止することができる。したがって、電極間に高電界が生じる場合であっても信頼性を向上することができる。 According to the present invention, in the semiconductor device having a lateral structure, the first dielectric structure is formed so as to integrally cover the opposing surfaces of the first electrode and the second electrode and the surface of the second semiconductor layer, And it consists of the 1st material which has a predetermined dielectric constant. Further, the second dielectric structure is formed of a second material on the first dielectric structure and formed between the first electrode and the second electrode, and having a dielectric constant equal to or higher than that of the first material. Become. That is, between the first electrode and the second electrode, a layer of the first material is formed in the vicinity of each electrode where electric field concentration is likely to occur, and the remaining material has the same dielectric constant as that of the first material or more dielectric. Since the layer of the second material having a high rate is formed, it is possible to prevent the dielectric breakdown that easily occurs in the vicinity of each electrode, and to prevent the dielectric structure from cracking. Accordingly, reliability can be improved even when a high electric field is generated between the electrodes.
　また、第１誘電体構造をＳｉＯ２で形成し、第２誘電体構造をＳｉＯ２より誘電率の高いポリイミドで形成することで、誘電率は低いが絶縁破壊耐圧の高いＳｉＯ２と、誘電率が高く、割れを生じにくいポリイミドとで電極間が埋め込まれる。したがって、各電極の近傍で生じ易い絶縁破壊を防止できると共に、割れ等が生じない信頼性の高い誘電体構造を作製することができる。 Further, the first dielectric structure formed of SiO 2, by forming the second dielectric structure with a high dielectric constant than SiO 2 polyimide, dielectric constant and low but SiO 2 high dielectric breakdown voltage, dielectric constant The gap between the electrodes is embedded with polyimide which is high and does not easily crack. Therefore, it is possible to prevent a dielectric breakdown that easily occurs in the vicinity of each electrode, and it is possible to manufacture a highly reliable dielectric structure that does not cause cracks.
本発明の実施形態に係る半導体デバイスの構成を概略的に示す平面図である。1 is a plan view schematically showing a configuration of a semiconductor device according to an embodiment of the present invention. 図１の線Ａ－Ａに沿う半導体デバイスの部分断面図である。FIG. 2 is a partial cross-sectional view of the semiconductor device taken along line AA in FIG. 1. 図２の誘電体構造を示す断面図であり、（ａ）は第１誘電体構造、（ｂ）は第２誘電体構造を示す。FIG. 3 is a cross-sectional view showing the dielectric structure of FIG. 2, wherein (a) shows a first dielectric structure and (b) shows a second dielectric structure. 図２の半導体デバイスの変形例を示す部分断面図である。FIG. 6 is a partial cross-sectional view showing a modification of the semiconductor device of FIG. 2. 図２の半導体デバイスの他の変形例を示す部分断面図である。FIG. 10 is a partial cross-sectional view showing another modification of the semiconductor device of FIG. 2.
　以下、本発明の実施の形態を図面を参照しながら詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
　図１は、本実施形態に係る半導体デバイスで、例えば、ＡｌＧａＮ／ＧａＮのヘテロ接合構造を有するダイオードである。この半導体デバイス１は、図１に示すように、櫛歯型電極を有する横型構造の半導体デバイスであって、ＩＩＩ－Ｖ族窒化物半導体を含む積層体２と、積層体の表面に形成された櫛歯型のショットキー電極３およびオーミック電極４とを備えている。これらの電極３，４は、各電極の側方から延出する複数の櫛歯部をそれぞれ有しており、これら電極に設けられた複数の櫛歯部を交互に配置することで、素子の高密度化を実現している。 FIG. 1 shows a semiconductor device according to this embodiment, for example, a diode having an AlGaN / GaN heterojunction structure. As shown in FIG. 1, this semiconductor device 1 is a semiconductor device having a lateral structure having comb-shaped electrodes, and is formed on a laminate 2 including a group III-V nitride semiconductor and on the surface of the laminate. A comb-shaped Schottky electrode 3 and an ohmic electrode 4 are provided. Each of these electrodes 3 and 4 has a plurality of comb teeth extending from the side of each electrode, and by alternately arranging a plurality of comb teeth provided on these electrodes, High density is realized.
　図２は、図１の線Ａ－Ａに沿う半導体デバイス１の部分断面図である。 FIG. 2 is a partial cross-sectional view of the semiconductor device 1 taken along line AA in FIG.
　半導体デバイス１は、Ｓｉからなる基板１１と、該基板上に形成されたバッファ層１２と、バッファ層１２上に積層されたＧａＮ層１３（第１半導体層）と、ＧａＮ層１３上に積層され、ＧａＮとヘテロ接合された他のＧａＮ系化合物を含むＡｌＧａＮ層１４（第２半導体層）と、ＡｌＧａＮ層１４の表面１４ａに所定間隔で形成されたショットキー電極３（第１電極）およびオーミック電極４（第２電極）とを備えている。また半導体デバイス１は、ショットキー電極３およびオーミック電極４のそれぞれの対向面とＡｌＧａＮ層１４の表面１４ａとを一体的に覆って形成され、ＳｉＯ２（第１材料）からなる誘電体構造５（第１誘電体構造）と、誘電体構造５上であり且つショットキー電極３およびオーミック電極４の間に、ＳｉＯ２と同じかそれ以上の誘電率を有する材料（第２材料）からなる誘電体構造６（第２誘電体構造）とを備えている。 The semiconductor device 1 includes a substrate 11 made of Si, a buffer layer 12 formed on the substrate, a GaN layer 13 (first semiconductor layer) stacked on the buffer layer 12, and a GaN layer 13. AlGaN layer 14 (second semiconductor layer) containing other GaN compound heterojunction with GaN, Schottky electrode 3 (first electrode) and ohmic electrode formed on surface 14a of AlGaN layer 14 at predetermined intervals 4 (second electrode). Further, the semiconductor device 1 is formed so as to integrally cover the opposing surfaces of the Schottky electrode 3 and the ohmic electrode 4 and the surface 14a of the AlGaN layer 14, and is a dielectric structure 5 (first material) made of SiO 2 (first material). A dielectric made of a material (second material) having a dielectric constant equal to or higher than that of SiO 2 between the first dielectric structure) and the dielectric structure 5 and between the Schottky electrode 3 and the ohmic electrode 4 Structure 6 (second dielectric structure).
　ショットキー電極３およびオーミック電極４は、例えば断面略矩形であり、ショットキー電極３とオーミック電極４の対向面が、それぞれ内側面３ａ，４ａを構成している。これらショットキー電極３およびオーミック電極４は、高導電性の材料からなり、ショットキー電極３は例えば、半導体層側から順に、Ｎｉ（１００ｎｍ）、Ａｕ（１００ｎｍ）、ＡｌもしくはＡｌ合金（５～１０μｍ）からなり、オーミック電極４は例えば、半導体層側から順に、Ｔｉ（２５ｎｍ）、Ａｌ（３００ｎｍ）、ＡｌもしくはＡｌ合金（５～１０μｍ）からなる。また、このショットキー電極３およびオーミック電極４は、例えば幅１０μｍで形成される。 The Schottky electrode 3 and the ohmic electrode 4 have, for example, a substantially rectangular cross section, and the opposing surfaces of the Schottky electrode 3 and the ohmic electrode 4 constitute inner side surfaces 3a and 4a, respectively. The Schottky electrode 3 and the ohmic electrode 4 are made of a highly conductive material. The Schottky electrode 3 is, for example, in order from the semiconductor layer side, Ni (100 nm), Au (100 nm), Al or Al alloy (5 to 10 μm). The ohmic electrode 4 is made of, for example, Ti (25 nm), Al (300 nm), Al, or an Al alloy (5 to 10 μm) in this order from the semiconductor layer side. The Schottky electrode 3 and the ohmic electrode 4 are formed with a width of 10 μm, for example.
　誘電体構造５は、具体的には、図３（ａ）に示すように、ＡｌＧａＮ層１４の表面１４ａに形成された底面部５ａと、ショットキー電極３の内側面３ａを覆う側面部５ｂと、ショットキー電極３の上面３ｂを覆う上面部５ｄと、オーミック電極４の内側面４ａを覆う側面部５ｃと、オーミック電極４の上面４ｂを覆う上面部５ｅとを有している。この誘電体構造５は、例えばＳｉＯ２からなり、その厚さＴ１が、例えば２．０μｍとなるように形成されている。 Specifically, as shown in FIG. 3A, the dielectric structure 5 includes a bottom surface portion 5 a formed on the surface 14 a of the AlGaN layer 14, and a side surface portion 5 b that covers the inner surface 3 a of the Schottky electrode 3. The upper surface portion 5 d that covers the upper surface 3 b of the Schottky electrode 3, the side surface portion 5 c that covers the inner surface 4 a of the ohmic electrode 4, and the upper surface portion 5 e that covers the upper surface 4 b of the ohmic electrode 4. The dielectric structure 5 is made of, for example, SiO 2 and has a thickness T1 of, for example, 2.0 μm.
　誘電体構造６は、図３（ｂ）に示すように、底面部５ａ上に形成された層厚部６ａと、上面部５ｄ，５ｅ上に形成された層薄部６ｂ，６ｃとを有している。層厚部６ａは、ショットキー電極３およびオーミック電極４の間に埋設するように形成されている。また、層薄部６ｂ，６ｃは、それぞれ上面５０ｄ，５０ｅの全体を覆って形成されている。この誘電体構造６は、具体的には、ＳｉＯ２より誘電率の高い有機膜、例えば誘電率が４．０以上の高誘電率ポリイミドからなり、層厚部６ａの幅Ｄは約６．０μｍである。このような材料を用いることによって、有機膜中の電界をε1／ε2（ε1：ＳｉＯ２の誘電率、ε2：有機膜の誘電率）にすることができるため、有機膜の寿命を延ばすことが可能となる。 As shown in FIG. 3B, the dielectric structure 6 has a layer thickness portion 6a formed on the bottom surface portion 5a and thin layer portions 6b and 6c formed on the top surface portions 5d and 5e. ing. The layer thickness portion 6 a is formed so as to be embedded between the Schottky electrode 3 and the ohmic electrode 4. The thin layer portions 6b and 6c are formed so as to cover the entire upper surfaces 50d and 50e, respectively. Specifically, the dielectric structure 6 is made of an organic film having a dielectric constant higher than that of SiO 2 , for example, a high dielectric constant polyimide having a dielectric constant of 4.0 or more, and the width D of the layer thickness portion 6a is about 6.0 μm. It is. By using such a material, the electric field in the organic film can be set to ε 1 / ε 2 (ε 1 : dielectric constant of SiO 2 , ε 2 : dielectric constant of the organic film). Can be extended.
　また、本実施形態において、誘電体構造５を形成する材料を第１材料、誘電体構造６を形成する材料を、第１材料より耐圧の大きい第２材料としたとき、誘電体構造５，６は直列コンデンサの関係より、その電荷が同じになるため、誘電率の低いもの程、高電界がかかる。よって、電極間における誘電体構造５，６の厚さを調整することで、低耐圧な誘電体に過剰な電圧が生じず、長寿命を実現することも可能である。具体的には、第１材料からなる誘電体構造５を必要最低限の厚さで形成し、残りの部分を第２材料で埋め込むと、相対的に誘電率の低い誘電体構造５に電界がかかることになる。このため、厚膜化による割れを防止しつつ、高電圧による絶縁破壊を防止することができる。 In the present embodiment, when the material forming the dielectric structure 5 is the first material and the material forming the dielectric structure 6 is the second material having a higher breakdown voltage than the first material, the dielectric structures 5 and 6 are used. Since the charges are the same because of the series capacitor, the lower the dielectric constant, the higher the electric field applied. Therefore, by adjusting the thickness of the dielectric structures 5 and 6 between the electrodes, it is possible to realize a long life without generating an excessive voltage in the low breakdown voltage dielectric. Specifically, when the dielectric structure 5 made of the first material is formed with the minimum necessary thickness and the remaining portion is embedded with the second material, an electric field is generated in the dielectric structure 5 having a relatively low dielectric constant. It will take. For this reason, it is possible to prevent dielectric breakdown due to high voltage while preventing cracking due to thickening.
　上記のようなＡｌＧａＮ／ＧａＮヘテロ接合構造を有する半導体デバイス１では、ＡｌＧａＮ／ＧａＮヘテロ接合界面のＧａＮ層１３側に、ピエゾ効果によって２次元電子ガス層が発生している。そして、高キャリア濃度の２次元電子ガス層１３ａが形成されたＡｌＧａＮ／ＧａＮ層を介して、オーミック電極４がショットキー電極３と電気的に接続される。このとき、２次元電子ガス層がキャリアとなってＡｌＧａＮ／ＧａＮ層が低抵抗、高移動度となるため、半導体デバイス１のオン抵抗を小さくし、低オン電圧を実現することが可能となっている。 In the semiconductor device 1 having the AlGaN / GaN heterojunction structure as described above, a two-dimensional electron gas layer is generated by the piezoelectric effect on the GaN layer 13 side of the AlGaN / GaN heterojunction interface. The ohmic electrode 4 is electrically connected to the Schottky electrode 3 through the AlGaN / GaN layer on which the two-dimensional electron gas layer 13a having a high carrier concentration is formed. At this time, since the two-dimensional electron gas layer serves as a carrier and the AlGaN / GaN layer has low resistance and high mobility, the on-resistance of the semiconductor device 1 can be reduced and a low on-voltage can be realized. Yes.
　本実施形態によれば、櫛歯型電極を有する横型構造の半導体デバイス１において、誘電体構造５が、ショットキー電極およびオーミック電極のそれぞれの対向面と、第２半導体層の表面とを一体的に覆って形成され、かつ、所定の誘電率を有するＳｉＯ２からなる。また、誘電体構造６が、誘電体構造５上であり且つショットキー電極およびオーミック電極の間に形成され、かつ、ＳｉＯ２と同じかそれ以上の誘電率を有するポリイミドからなる。すなわち、ショットキー電極とオーミック電極の間で、電界集中の生じ易い各電極の近傍にはＳｉＯ２層が形成され、残りの部分についてはＳｉＯ２より誘電率の高いポリイミド層が形成されるので、各電極の近傍で生じ易い絶縁破壊を防止することができ、加えて誘電体構造の割れを防止することができる。また、ＳｉＯ２のみでは誘電体構造全体を形成し難い場合であっても、上記関係を有する２つの材料を使用することで容易に作製することが可能となり、設計の自由度を向上させることができる。 According to this embodiment, in the semiconductor device 1 having a lateral structure having a comb-shaped electrode, the dielectric structure 5 integrally forms the opposing surfaces of the Schottky electrode and the ohmic electrode and the surface of the second semiconductor layer. And is made of SiO 2 having a predetermined dielectric constant. The dielectric structure 6 is made of polyimide which is on the dielectric structure 5 and is formed between the Schottky electrode and the ohmic electrode and has a dielectric constant equal to or higher than that of SiO 2 . That is, between the Schottky electrode and the ohmic electrode, an SiO 2 layer is formed in the vicinity of each electrode where electric field concentration is likely to occur, and a polyimide layer having a higher dielectric constant than SiO 2 is formed for the remaining part. It is possible to prevent dielectric breakdown that is likely to occur in the vicinity of each electrode, and to prevent cracking of the dielectric structure. Moreover, even if it is difficult to form the entire dielectric structure with only SiO 2 , it can be easily manufactured by using the two materials having the above relationship, and the degree of freedom in design can be improved. it can.
　さらに、電極間の絶縁破壊耐圧を向上することができるため、櫛歯型電極を高密度に配置した場合でも、電極間で絶縁破壊が生じるのを防止することができ、低オン抵抗で高耐圧な半導体デバイスを作製することが可能となる。 Furthermore, since the dielectric breakdown voltage between the electrodes can be improved, even when the comb-shaped electrodes are arranged at a high density, dielectric breakdown can be prevented from occurring between the electrodes, and a low on-resistance and high breakdown voltage can be prevented. It is possible to manufacture a simple semiconductor device.
　図４は、図２の半導体デバイスの変形例を示す部分断面図である。図２の半導体デバイスは誘電体構造５，６を有しているが、図４の半導体デバイスは、一体成形された誘電体構造２０を有している点で異なる。以下、図２の半導体デバイスと異なる部分を説明する。 FIG. 4 is a partial cross-sectional view showing a modification of the semiconductor device of FIG. The semiconductor device of FIG. 2 has dielectric structures 5 and 6, but the semiconductor device of FIG. 4 is different in that it has an integrally formed dielectric structure 20. Hereinafter, a different part from the semiconductor device of FIG. 2 is demonstrated.
　図４の半導体デバイスにおいて、誘電体構造２０は、ショットキー電極３およびオーミック電極４のそれぞれの対向面と、ＡｌＧａＮ層１４の表面１４ａとを一体的に覆って形成され、かつ、ショットキー電極３とオーミック電極４の間に埋設するように配置されている。すなわち、本変形例の誘電体構造２０は、図２の半導体構造５，６をＳｉＯ２にて一体的に成形したものである。この誘電体構造２０は、ＡｌＧａＮ層１４の表面１４ａ上に形成された層厚部２０ａと、上面３ｂ，４ｂ上に形成された層薄部２０ｂ，２０ｃとを有している。 In the semiconductor device of FIG. 4, the dielectric structure 20 is formed so as to integrally cover the opposing surfaces of the Schottky electrode 3 and the ohmic electrode 4 and the surface 14 a of the AlGaN layer 14, and the Schottky electrode 3. Are arranged so as to be buried between the ohmic electrodes 4. That is, the dielectric structure 20 of this modification is obtained by integrally molding the semiconductor structures 5 and 6 of FIG. 2 with SiO 2 . The dielectric structure 20 has a layer thickness portion 20a formed on the surface 14a of the AlGaN layer 14 and thin layer portions 20b and 20c formed on the upper surfaces 3b and 4b.
　ここで、誘電体構造はショットキー電極３とオーミック電極４との間に埋め込んで形成する必要がある。したがって、誘電体構造の厚さはＡｌＧａＮ層１４上に形成される各電極の厚さに依存することとなり、とりわけ、各電極の厚さが１０μｍ程度まで大きくなると、アノードカップリング型ＰＥＣＶＤのような通常のＣＶＤ法を用いた場合にＳｉＯ２のみでは誘電体構造全体を形成できない場合がある。 Here, the dielectric structure needs to be embedded between the Schottky electrode 3 and the ohmic electrode 4. Therefore, the thickness of the dielectric structure depends on the thickness of each electrode formed on the AlGaN layer 14, and in particular, when the thickness of each electrode is increased to about 10 μm, the thickness of the anode coupling type PECVD is increased. When a normal CVD method is used, the entire dielectric structure may not be formed with only SiO 2 .
　本実施形態では、誘電体構造２０の厚さＴ２（ＡｌＧａＮ層１４の表面１４ａと接する面から上面までの距離）が、ショットキー電極３あるいはオーミック電極４の厚さ（高さ）よりも大きく形成される。このとき、誘電体構造２０は、例えばカソードカップリング型ＰＥＣＶＤ法にて形成される。カソードカップリング型ＰＥＣＶＤとは、成膜される膜にプラズマでイオン化された荷電粒子が入射してくるタイプのＣＶＤである。入射する粒子により、ＳｉＯ２のネットワークが分断されるので内部応力が緩和され、その結果通常のＣＶＤと比較して厚いＳｉＯ２が成膜できると推察される。したがって、各電極の厚さが大きい場合であっても、カソードカップリング型ＰＥＣＶＤ法を採用することにより、電極間にＳｉＯ２からなる誘電体構造２０を形成することができ、誘電体構造２０の更なる高耐圧を実現することができる。 In the present embodiment, the thickness T2 of the dielectric structure 20 (distance from the surface in contact with the surface 14a of the AlGaN layer 14 to the upper surface) is larger than the thickness (height) of the Schottky electrode 3 or the ohmic electrode 4. Is done. At this time, the dielectric structure 20 is formed by, for example, a cathode coupling type PECVD method. Cathode coupling type PECVD is a type of CVD in which charged particles ionized by plasma are incident on a film to be formed. Since the SiO 2 network is divided by the incident particles, the internal stress is relieved, and as a result, it is presumed that a thick SiO 2 film can be formed as compared with ordinary CVD. Therefore, even when the thickness of each electrode is large, the dielectric structure 20 made of SiO 2 can be formed between the electrodes by adopting the cathode coupling type PECVD method. Further high breakdown voltage can be realized.
　図５は、図４の半導体デバイスの変形例を示す部分断面図である。 FIG. 5 is a partial cross-sectional view showing a modification of the semiconductor device of FIG.
　図５に示すように、誘電体構造３０は、ＡｌＧａＮ層１４の表面１４ａ上に形成された層厚部３０ａと、上面３ｂ，４ｂ上に形成された層薄部３０ｂ，３０ｃとを有している。そして、層薄部３０ｂは上面３ｂの一部を覆って形成され、層薄部３０ｃは上面４ｂの一部を覆って形成されている。すなわち、誘電体構造２０では、ショットキー電極３の上面３ｂとオーミック電極４の一部が露出している。 As shown in FIG. 5, the dielectric structure 30 has a layer thickness portion 30a formed on the surface 14a of the AlGaN layer 14, and layer thin portions 30b and 30c formed on the upper surfaces 3b and 4b. Yes. The thin layer portion 30b is formed so as to cover a part of the upper surface 3b, and the thin layer portion 30c is formed so as to cover a part of the upper surface 4b. That is, in the dielectric structure 20, the upper surface 3 b of the Schottky electrode 3 and a part of the ohmic electrode 4 are exposed.
　このように、電極の上面において、電界が生じない位置には誘電体構造３０を形成しないことにより、誘電体構造３０の残留応力を減少させることができ、誘電体構造３０の割れを確実に防止することができる。 As described above, by not forming the dielectric structure 30 at a position where no electric field is generated on the upper surface of the electrode, the residual stress of the dielectric structure 30 can be reduced, and cracking of the dielectric structure 30 is surely prevented. can do.
　以上、本発明者によってなされた発明を実施形態に基づいて具体的に説明したが、本発明は上記実施形態に限定されるものではなく、その要旨を逸脱しない範囲で変更可能である。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and can be changed without departing from the gist thereof.
　例えば、本実施形態では電子デバイスはＩＩＩ族窒化物半導体を有するダイオードであるが、これに限らず、ＩＩＩ族窒化物半導体を有するトランジスタであってもよい。トランジスタの場合はソース電極とドレイン電極間の絶縁膜について本願発明を適用できる。また、ＳＯＩダイオードまたはＳＯＩトランジスタであってもよい。 For example, in this embodiment, the electronic device is a diode having a group III nitride semiconductor, but is not limited thereto, and may be a transistor having a group III nitride semiconductor. In the case of a transistor, the present invention can be applied to an insulating film between a source electrode and a drain electrode. Further, it may be an SOI diode or an SOI transistor.
　以下、本発明の実施例を説明する。 Hereinafter, examples of the present invention will be described.
　（実施例１）
　先ず、基板としてＳｉ（１１１）を準備し、この基板をＭＯＣＶＤ装置内に導入して結晶成長を行う。具体的には、ＡｌＮ層１００ｎｍを成長後、ＡｌＮ／ＧａＮ＝２０／２００ｎｍを１２回繰り返してバッファ層を成長させた。次に、炭素濃度が１×１０19ｃｍ-3以上の高抵抗ＧａＮ層を１０００ｎｍ成長させ、その後、炭素濃度が１×１０17ｃｍ-3以下の低抵抗ＧａＮ層を１００ｎｍ成長させた。次いで、Ａｌ組成２５％のＡｌＧａＮ層を２５ｎｍ成長させ、ヘテロ接合界面を形成した。 (Example 1)
First, Si (111) is prepared as a substrate, and this substrate is introduced into an MOCVD apparatus for crystal growth. Specifically, after growing an AlN layer of 100 nm, AlN / GaN = 20/200 nm was repeated 12 times to grow a buffer layer. Next, a high resistance GaN layer having a carbon concentration of 1 × 10 19 cm −3 or more was grown to 1000 nm, and then a low resistance GaN layer having a carbon concentration of 1 × 10 17 cm −3 or less was grown to 100 nm. Next, an AlGaN layer having an Al composition of 25% was grown to 25 nm to form a heterojunction interface.
　その後、オーミック電極（ドレイン電極）とショットキー電極（ゲート電極）とを、フォトリソグラフィーとスパッタリング、リフトオフ、アニール等の工程を経て形成した。 Thereafter, an ohmic electrode (drain electrode) and a Schottky electrode (gate electrode) were formed through processes such as photolithography, sputtering, lift-off, and annealing.
　その後、層間絶縁膜であるＳｉＯ２をプラズマＣＶＤ法や熱ＣＶＤ法により形成し、オーミック電極とショットキー電極の必要部をフォトリソグラフィーとフッ酸によるエッチングによりＳｉＯ２を開口した。 Thereafter, the SiO 2 which is an interlayer insulating film formed by plasma CVD method or a thermal CVD method, and opening the SiO 2 by etching the necessary portion of the ohmic electrode and the Schottky electrode by photolithography and hydrofluoric acid.
　次に、純ＡｌやＡｌ合金（ＡｌＳｉ、ＡｌＣｕ等）を１０μｍ成膜させ、その後、フォトリソグラフィーと塩素系ドライエッチングによりアルミをエッチングして、アルミ配線をパターンニングした。 Next, pure Al or Al alloy (AlSi, AlCu, etc.) was formed to a thickness of 10 μm, and then aluminum was etched by photolithography and chlorine-based dry etching to pattern the aluminum wiring.
　次いで、アノードカップリング型ＰＥＣＶＤを用いてＳｉＯ２を２μｍ成膜したのち、ポリイミド（誘電率４．０）を塗布した。塗布厚は電極上面にもポリイミドが形成されるように、パターンを形成していないベアシリコン基板で２０μｍとなるような条件で塗布した。その後、レジストを塗って、ポリイミドをパターンニングした後、３８０℃でキュアを行った。 Next, after 2 μm of SiO 2 was formed using anode coupling type PECVD, polyimide (dielectric constant 4.0) was applied. The coating thickness was applied under the condition that the bare silicon substrate on which no pattern was formed was 20 μm so that polyimide was also formed on the upper surface of the electrode. Thereafter, a resist was applied and the polyimide was patterned, followed by curing at 380 ° C.
　（実施例２）
　実施例１のポリイミドに代えて、ポリイミドより誘電率の高い有機膜を使用した。ＳｉＯ２の誘電率が３．９であり、有機膜間の誘電率がＸの場合、電荷は３．９／Ｘ倍となることから、ポリイミドの場合よりも低い電圧が有機膜にかかった。 (Example 2)
Instead of the polyimide of Example 1, an organic film having a dielectric constant higher than that of polyimide was used. When the dielectric constant of SiO 2 was 3.9 and the dielectric constant between the organic films was X, the charge was 3.9 / X times, so a lower voltage was applied to the organic film than in the case of polyimide.
　（実施例３）
　アルミ配線を形成するまでは、実施例１と同様に作製した。 (Example 3)
It was produced in the same manner as in Example 1 until the aluminum wiring was formed.
　その後、カソードカップル型ＰＥＣＶＤでＳｉＯ２を５０００ｎｍ成膜した。そのときの原料はＴＥＯＳと酸素であった。その後、パット部分をエチレングリコール含有の緩衝フッ酸で開口した。 Thereafter, a SiO 2 film having a thickness of 5000 nm was formed by cathode-coupled PECVD. The raw materials at that time were TEOS and oxygen. Thereafter, the pad portion was opened with buffered hydrofluoric acid containing ethylene glycol.
　（比較例）
　アルミ配線を形成するまでは、実施例１と同様に作製した。 (Comparative example)
It was produced in the same manner as in Example 1 until the aluminum wiring was formed.
　その後、ポリイミドを塗布した。塗布厚はパターンを形成していないベアシリコン基板で２０μｍとなるような条件で塗布した。その後、レジストを塗って、ポリイミドをパターンニングした後、３８０℃でキュアを行った。 Thereafter, polyimide was applied. The coating thickness was applied on a bare silicon substrate on which no pattern was formed under the condition of 20 μm. Thereafter, a resist was applied and the polyimide was patterned, followed by curing at 380 ° C.
　上記のように作製した半導体デバイスの耐圧性を検証した結果、実施例１～３の場合、電極間に高電圧が生じる場合であっても、電極間での絶縁破壊を防止することができ、高耐圧な半導体デバイスを作製できることが分かった。 As a result of verifying the pressure resistance of the semiconductor device fabricated as described above, in Examples 1 to 3, even when a high voltage is generated between the electrodes, dielectric breakdown between the electrodes can be prevented, It was found that a semiconductor device with a high breakdown voltage can be produced.
　１　半導体デバイス
　２　積層体
　３　ショットキー電極
　３ａ，４ａ　対向面
　３ｂ，４ｂ　上面
　４　オーミック電極
　５ａ　底面部
　５ｂ　側面部
　５ｃ　側面部
　５ｄ　上面部
　５ｅ　上面部
　６ａ　層厚部
　６ｂ，６ｃ　層薄部
　１１　基板
　１２　バッファ層
　１３　ＧａＮ層
　１３ａ　２次元電子ガス層
　１４　ＡｌＧａＮ層
　１４ａ　表面
　５　誘電体構造
　６　誘電体構造
　２０　誘電体構造
　２０ａ　層厚部
　２０ｂ，２０ｃ　層薄部
　３０　誘電体構造
　３０ａ　層厚部
　３０ｂ，３０ｃ　層薄部
　５０ｄ，５０ｅ　上面 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Laminated body 3 Schottky electrode 3a, 4a Opposite surface 3b, 4b Upper surface 4 Ohmic electrode 5a Bottom surface part 5b Side surface part 5c Side surface part 5d Upper surface part 5e Upper surface part 6a Layer thickness part 6b, 6c Layer thin part 11 Substrate 12 Buffer layer 13 GaN layer 13a Two-dimensional electron gas layer 14 AlGaN layer 14a Surface 5 Dielectric structure 6 Dielectric structure 20 Dielectric structure 20a Layer thick part 20b, 20c Layer thin part 30 Dielectric structure 30a Layer thick part 30b, 30c layer Thin section 50d, 50e Top surface

Claims (11)

  1. 　横型構造の半導体デバイスであって、
    　基板と、
    　前記基板上に積層され、ＧａＮ系化合物を含む第１半導体層と、
    　前記第１半導体層上に積層され、前記ＧａＮ系化合物とヘテロ接合された他のＧａＮ系化合物を含む第２半導体層と、
    　前記第２半導体層の表面に所定間隔で形成された第１電極および第２電極と、
    　前記第１電極および前記第２電極のそれぞれの対向面と、前記第２半導体層の表面とを一体的に覆って形成され、所定の誘電率を有する第１材料からなる第１誘電体構造と、
    　前記第１誘電体構造上であり且つ前記第１電極および第２電極の間に形成され、前記第１材料と同じかそれ以上の誘電率を有する第２材料からなる第２誘電体構造と、
    を備えることを特徴とする半導体デバイス。     A semiconductor device having a lateral structure,
    A substrate,
    A first semiconductor layer stacked on the substrate and containing a GaN-based compound;
    A second semiconductor layer including another GaN-based compound laminated on the first semiconductor layer and heterojunction with the GaN-based compound;
    A first electrode and a second electrode formed on the surface of the second semiconductor layer at predetermined intervals;
    A first dielectric structure made of a first material having a predetermined dielectric constant and integrally covering the opposing surfaces of the first electrode and the second electrode and the surface of the second semiconductor layer; ,
    A second dielectric structure formed of a second material on the first dielectric structure and formed between the first electrode and the second electrode and having a dielectric constant equal to or higher than the first material;
    A semiconductor device comprising:
  2. 　前記第１材料はＳｉＯ２であることを特徴とする請求項１記載の半導体デバイス。 The semiconductor device according to claim 1, wherein the first material is SiO 2 .
  3. 　前記第２材料は、ポリイミドと同じかそれ以上の誘電率を有する材料であることを特徴とする、請求項１記載の半導体デバイス。 2. The semiconductor device according to claim 1, wherein the second material is a material having a dielectric constant equal to or higher than that of polyimide.
  4. 　前記第２材料がＳｉＯ２であることを特徴とする請求項１記載の半導体デバイス。 The semiconductor device according to claim 1, wherein the second material is SiO 2 .
  5. 　前記第１電極および前記第２電極が櫛歯型電極構造を形成することを特徴とする請求項１乃至４のいずれか１項に記載の半導体デバイス。 The semiconductor device according to any one of claims 1 to 4, wherein the first electrode and the second electrode form a comb-shaped electrode structure.
  6. 　前記第１誘電体構造が、前記第１電極の上面の少なくとも一部と、前記第２電極の上面の少なくとも一部とを覆って形成されることを特徴とする、請求項１乃至５のいずれか１項に記載の半導体デバイス。 The first dielectric structure is formed so as to cover at least part of the upper surface of the first electrode and at least part of the upper surface of the second electrode. 2. A semiconductor device according to claim 1.
  7. 　前記第１誘電体構造が、前記第１電極の上面および前記第２電極の上面の全面を覆って形成されることを特徴とする、請求項１乃至６のいずれか１項に記載の半導体デバイス。 The semiconductor device according to claim 1, wherein the first dielectric structure is formed so as to cover an entire upper surface of the first electrode and an upper surface of the second electrode. .
  8. 　前記半導体デバイスが、ダイオードまたはトランジスタで構成されることを特徴とする、請求項１乃至７のいずれか１項に記載の半導体デバイス。 The semiconductor device according to claim 1, wherein the semiconductor device is configured by a diode or a transistor.
  9. 　横型構造の半導体デバイスの製造方法であって、
    　基板上に、ＧａＮ系化合物を含む第１半導体層を形成するステップと、
    　前記第１半導体層上に、前記ＧａＮ系化合物とヘテロ接合された他のＧａＮ系化合物を含む第２半導体層を形成するステップと、
    　前記第２半導体層の表面に、第１電極および第２電極を所定の間隔で形成するステップと、
    　前記第１電極および前記第２電極のそれぞれの対向面と、前記第２半導体層の表面とを一体的に覆う第１誘電体構造を、所定の誘電率を有する第１材料で形成するステップと、
    　前記第１誘電体構造上であり且つ前記第１電極と前記第２電極との間に、前記第１材料と同じかそれ以上の誘電率を有する材料で第２誘電体構造を形成するステップと、
    を備えることを特徴とする半導体デバイスの製造方法。     A method of manufacturing a semiconductor device having a lateral structure,
    Forming a first semiconductor layer containing a GaN-based compound on a substrate;
    Forming a second semiconductor layer including another GaN-based compound heterojunctioned with the GaN-based compound on the first semiconductor layer;
    Forming a first electrode and a second electrode at a predetermined interval on a surface of the second semiconductor layer;
    Forming a first dielectric structure integrally covering the opposing surfaces of the first electrode and the second electrode and the surface of the second semiconductor layer with a first material having a predetermined dielectric constant; ,
    Forming a second dielectric structure with a material having a dielectric constant equal to or higher than that of the first material on the first dielectric structure and between the first electrode and the second electrode; ,
    A method for manufacturing a semiconductor device, comprising:
  10. 　前記第１材料および前記第２材料がＳｉＯ２であり、
    　前記第２誘電体構造は、カソードカップリング型ＰＥＣＶＤ法にて、前記第１誘電体構造と一体的に成形されることを特徴とする、請求項９記載の製造方法。     The first material and the second material are SiO 2 ;
    10. The manufacturing method according to claim 9, wherein the second dielectric structure is formed integrally with the first dielectric structure by a cathode coupling type PECVD method.
  11. 　前記第１誘電体構造が、前記第１電極の上面の少なくとも一部と、前記第２電極の上面の少なくとも一部とを覆って形成されることを特徴とする、請求項９または１０に記載の製造方法。 The said 1st dielectric structure is formed covering at least one part of the upper surface of the said 1st electrode, and at least one part of the upper surface of the said 2nd electrode, The Claim 9 or 10 characterized by the above-mentioned. Manufacturing method.
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