JP6584987B2 - Semiconductor device - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor device.

  Since nitride-based semiconductor materials have high breakdown field strength and high electron mobility, they are expected to be applied to power electronics semiconductor devices and high-frequency power semiconductor devices.

  In a lateral power electronics semiconductor device, it is desirable to increase the gate width in order to drive it with a large current. At this time, a multi-finger structure is preferably used. Here, the lateral power electronics semiconductor device having a multi-finger structure is required to be downsized because the gate width is increased and the size of the semiconductor device is increased.

JP 2009-12002 A

  A miniaturized semiconductor device is provided.

A semiconductor device according to an embodiment includes a substrate having a first surface and a second surface provided on the opposite side of the first surface, and a first nitride semiconductor provided on the first surface. A plurality of source electrodes provided on the first nitride semiconductor layer, a plurality of drain electrodes provided between the plurality of source electrodes on the first nitride semiconductor layer, A plurality of gate electrodes provided between each of the plurality of source electrodes and the plurality of drain electrodes on the one nitride semiconductor layer, and in contact with the second surface; The first wiring connected, the second wiring provided on the active region electrically connected to the plurality of drain electrodes, and the second surface provided in contact with the plurality of gate electrodes. Provided between the first interconnect and the first nitride semiconductor layer and the second interconnect An interlayer insulating film, provided between the plurality of gate electrodes and the third wiring, and a plurality of third connecting portion for electrically connecting each of the third wirings of the plurality of gate electrodes, the Prepare.

1 is a schematic top view of a semiconductor device 100 according to a first embodiment. 1 is a schematic cross-sectional view of a main part of a semiconductor device 100 according to a first embodiment. 3 is a schematic top view showing a first connecting part 22 and a third connecting part 24 of the semiconductor device 100 of the first embodiment. FIG. 1 is a schematic top view of a semiconductor package 1000 using a semiconductor device 100 of a first embodiment. It is a schematic cross section of the principal part of the semiconductor device 800 used as a comparison with the first embodiment. It is a model top view of the semiconductor package 8000 using the semiconductor device 800 used as the comparison of 1st Embodiment. It is a schematic cross section of the principal part of the semiconductor device 200 of 2nd Embodiment. It is a schematic cross section of the principal part of the semiconductor device 300 of 3rd Embodiment. It is a schematic cross section of the principal part of the semiconductor device 400 of 4th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  In this specification, in order to show the positional relationship of components and the like, the upward direction of the drawing is described as “up” and the downward direction of the drawing is described as “down”. In the present specification, the concepts of “upper” and “lower” are not necessarily terms indicating the relationship with the direction of gravity.

(First embodiment)
The semiconductor device of this embodiment includes a substrate having a first surface and a second surface provided on the opposite side of the first surface, and a first nitride provided on the first surface. A semiconductor layer, a plurality of source electrodes provided on the first nitride semiconductor layer, a plurality of drain electrodes provided on each of the first nitride semiconductor layers and between the plurality of source electrodes; A plurality of gate electrodes provided between the plurality of source electrodes and the plurality of drain electrodes on the first nitride semiconductor layer, respectively, in contact with the second surface and electrically connected to the plurality of source electrodes A first wiring connected to the plurality of drain electrodes, a second wiring electrically connected to the plurality of drain electrodes, provided on the active region, provided in contact with the second surface, and connected to the plurality of gate electrodes. The third wiring electrically connected, and the first wiring between the first nitride semiconductor layer and the second wiring. Comprising an interlayer insulating film which is, a.

  FIG. 1 is a schematic top view of the semiconductor device 100 of this embodiment. FIG. 1A is a schematic top view showing the positional relationship among the substrate 10, the first wiring 24, the second wiring 34, and the third wiring 44 of the semiconductor device 100 of this embodiment. FIG. 1B is a schematic diagram showing the electrode structure of the semiconductor device 100 of this embodiment. FIG. 2 is a schematic cross-sectional view of a main part of the semiconductor device 100 of the present embodiment.

  The semiconductor device of this embodiment is a HEMT (High Electron Mobility Transistor) using a nitride semiconductor such as GaN (gallium nitride), AlGaN (aluminum gallium nitride), and InGaN (indium gallium nitride). Moreover, the electrode structure of the semiconductor device 100 of this embodiment is a multi-finger structure.

  The semiconductor device 100 includes a first nitride semiconductor layer 6, a second nitride semiconductor layer 4, a gate insulating film 8, a substrate 10, a source electrode 20, a first connecting portion 22, Wiring 24, drain electrode 30, second connecting portion 32, second wiring 34, gate electrode 40, third connecting portion 42, third wiring 44, and interlayer insulating film 60. , An element isolation region 62, an insulating layer 66, and an active region 68.

  The substrate 10 has a first surface 12 and a second surface 14 provided on the opposite side of the first surface. For example, a Si (silicon) substrate. In addition to the Si substrate, for example, a sapphire substrate or a silicon carbide (SiC) substrate can be used.

  The first nitride semiconductor layer 6 is provided on the first surface 12. The first nitride semiconductor layer 6 includes a first semiconductor layer 6a and a second semiconductor layer 6b provided on the first semiconductor layer 6a. The band gap of the second semiconductor layer 6b is larger than the band gap of the first semiconductor layer 6a.

The first semiconductor layer 6a is, for example, undoped Al _X Ga _1-X N (0 ≦ X <1). More specifically, undoped GaN. The film thickness of the first semiconductor layer 6a is, for example, not less than 0.5 μm and not more than 3 μm. The second semiconductor layer 6b is, for example, undoped Al _Y Ga _1-Y N (0 <Y ≦ 1, X <Y). More specifically, it is undoped Al _0.2 Ga _0.8 N. The film thickness of the second semiconductor layer 6b is, for example, 15 nm or more and 50 nm or less.

  A heterojunction interface is formed between the first semiconductor layer 6a and the second semiconductor layer 6b. When the semiconductor device 100 is turned on, a two-dimensional electron gas (2DEG) is formed at the heterojunction interface and becomes a carrier.

The second nitride semiconductor layer (buffer layer) 4 is provided between the substrate 10 and the first nitride semiconductor layer 6. By providing the second nitride semiconductor layer 4, the lattice mismatch between the substrate 10 and the first nitride semiconductor layer 6 is relaxed, and the first nitride semiconductor layer 6 having high crystallinity is formed. . Thereby, a high-performance semiconductor device is realized. The second nitride semiconductor layer 4 has, for example, a multilayer structure of aluminum gallium nitride (Al _W Ga _1-W N (0 <W <1)).

  The semiconductor device 100 includes a plurality of source electrodes 20 provided on the first nitride semiconductor layer 6 (second semiconductor layer 6b) and a plurality of drain electrodes provided on the first nitride semiconductor layer 6. 30 and a plurality of gate electrodes 40 provided on the first nitride semiconductor layer 6. The plurality of drain electrodes 30 are provided between the plurality of source electrodes 20. The plurality of gate electrodes 40 are provided between the plurality of source electrodes 20 and the plurality of drain electrodes 30, respectively.

  The plurality of source electrodes 20 are preferably connected to the substrate 10 to have the same potential as the substrate 2 in order to alleviate electric field concentration and suppress current collapse during voltage application.

  The first wiring 24 is provided in contact with the second surface 14. The first wiring 24 is electrically connected to the plurality of source electrodes 20. In the semiconductor device 100 of this embodiment, for example, when “the first wiring 24 is provided in contact with the second surface 14”, the first wiring 24 and the second surface 14 are directly connected. A case where the first wiring 24 and the second surface 14 are indirectly in contact with each other by providing an intermediate layer or the like between the first wiring 24 and the second surface 14. ,including.

  FIG. 3 is a schematic top view showing the first connecting portion 22 and the third connecting portion 24 of the semiconductor device 100 of the first embodiment.

  The first connecting portion 22 is provided between the first wiring 24 and the plurality of source electrodes 20. The first connecting portion 22 electrically connects the first wiring 24 and the plurality of source electrodes 20. Here, in the case where a plurality of wirings electrically connected to the plurality of source electrodes 20 are provided, the wiring that can draw the largest inscribed circle in a plane parallel to the first nitride semiconductor layer 6 Is a first wiring 24. The other wiring is the first connecting portion 22.

  The plurality of first coupling portions 22 may be provided separately from each other between the plurality of source electrodes 20 and the first wiring 24. Note that one first connection portion 22 may be provided between the plurality of source electrodes 20 and the first wiring 24.

  The second wiring 34 is provided on the active region 68. The second wiring 34 is electrically connected to the plurality of drain electrodes 30. The active region 68 is a region where a transistor is formed. Specifically, the active region refers to a region where a transistor operates where the source electrode 20, the drain electrode 30, or the gate electrode 40 is disposed.

  The second wiring 34 may be reduced in size by providing the second wiring 34 on a part of the active region 68 instead of on the whole. By reducing the size of the second wiring 34, the parasitic capacitance generated between the nitride semiconductor layer and the second wiring 34 can be reduced. The second wiring 34 may be provided on the entire active region 68.

  The second connecting portion 32 is provided between the second wiring 34 and the plurality of drain electrodes 30. The second connecting portion 32 electrically connects the second wiring 34 and the plurality of drain electrodes 30. Here, when a plurality of wirings electrically connected to the plurality of drain electrodes 30 are provided, the wiring that can draw the largest inscribed circle in a plane parallel to the first nitride semiconductor layer 6 Is the second wiring 34. The other wiring is the second connecting portion 32.

  The plurality of second coupling portions 32 may be provided separately from each other between the plurality of drain electrodes 30 and the second wiring 34. One second connecting portion 32 may be provided between the plurality of drain electrodes 30 and the second wiring 34.

  The third wiring 44 is provided in contact with the second surface 14. The third wiring 44 is electrically connected to the plurality of gate electrodes 40.

  The third connection portion 42 is provided between the third wiring 44 and the plurality of gate electrodes 40. The third connecting portion 42 electrically connects the third wiring 44 and the plurality of gate electrodes 40. Here, when a plurality of wirings electrically connected to the plurality of gate electrodes 40 are provided, the wiring that can draw the largest inscribed circle in a plane parallel to the first nitride semiconductor layer 6 Is a third wiring 44. The other wirings are referred to as third connection portions 42.

  The plurality of third connecting portions 42 may be provided separately from each other between the plurality of gate electrodes 40 and the third wiring 44. One third connecting portion 42 may be provided between the plurality of gate electrodes 40 and the third wiring 44.

  The plurality of source electrodes 20 and the plurality of drain electrodes 30 preferably include a laminated structure of Ti (titanium) and Al (aluminum), for example. For example, TiN (titanium nitride), MoN (molybdenum nitride), WN (tungsten nitride), TaN (tantalum nitride) Ni (nickel) is preferably used for the plurality of gate electrodes 40. It is preferable that the 1st connection part 22, the 2nd connection part 32, and the 3rd connection part 42 consist of a laminated structure of Ti and Al, for example. Moreover, it is preferable that the 1st wiring 24, the 2nd wiring 34, and the 3rd wiring 44 consist of Al, Cu (copper), or Au (gold), for example.

  The interlayer insulating film 60 includes a first nitride semiconductor layer 6, a plurality of source electrodes 20, a first connection portion 22, a first wiring 24, a plurality of drain electrodes 30, and a second connection portion. 32, the second wiring 34, the plurality of gate electrodes 40, the third connecting portion 42, and the third wiring 44. Alternatively, the interlayer insulating film 60 is provided between the first nitride semiconductor layer 6 and the second wiring 34. The interlayer insulating film 60 is preferably made of a polyimide film or a BCB (benzocyclobutene) film because the relative dielectric constant is small and the parasitic capacitance between the substrate and the source electrode can be reduced.

The insulating layer 66 is provided between the third connecting portion 42 and the substrate 10. The insulating layer 66 insulates the third connecting portion 42 (third wiring) and the substrate 10. As the material of the insulating layer 66, for example, SiN (silicon nitride), AlN (aluminum nitride), SiO ₂ (silicon oxide) or Al ₂ O ₃ (aluminum oxide) is preferably used.

The gate insulating film 8 is provided between the plurality of gate electrodes 40 and the first nitride semiconductor layer 6. As a material of the gate insulating film 8, for example, SiN (silicon nitride), AlN (aluminum nitride), SiO ₂ (silicon oxide) or Al ₂ O ₃ (aluminum oxide) is preferably used. Note that the gate insulating film 8 may be omitted.

  The semiconductor device 100 may be provided with an element isolation boundary 64. At this time, the element isolation region 62 is provided on the nitride semiconductor layer outside the element isolation boundary 64. The element isolation region 62 is produced, for example, by Ar ion implantation into the nitride semiconductor layer. Alternatively, the element isolation region 62 may be manufactured by embedding an insulator material such as a polyimide film having a low relative dielectric constant or a BCB (benzocyclobutene) film in the nitride semiconductor layer. An active region 68 is provided inside the element isolation boundary 64.

The film thickness t ₁ of the first wiring 24 is preferably larger than the film thickness t ₂ of the second wiring 34.

The ratio of the first dielectric constant epsilon _f of the nitride semiconductor layer _6, when the film thickness d _{f, d} and dielectric constant of the interlayer insulating film 60 _epsilon, the film thickness was d _d, epsilon _f and d _f Is preferably larger than the ratio of ε _d and d _d , in other words, (ε _f / d _f )> (ε _d / d _d ). Further, in the present embodiment, _a relative dielectric constant of the second nitride semiconductor layer 4 _epsilon, film thickness d _a, the dielectric constant epsilon _b of the first semiconductor layer _6a, the film thickness d _b , the relative dielectric constant of the second semiconductor layer epsilon _c, a film thickness when a _{d c, (ε a ε b} ε c / (d a ε b ε c + d b ε a ε c + d c ε a ε _b ))> (ε _d / d _d ).

  FIG. 4 is a schematic top view of a semiconductor package 1000 using the semiconductor device 100 of the present embodiment.

  The semiconductor package 1000 includes a semiconductor device 100, a source terminal (first terminal) 70, a drain terminal (second terminal) 72, a gate terminal (third terminal) 74, and a first bonding wire 76. , A second bonding wire 78 and a package substrate 82. The source terminal 70, the drain terminal 72, and the gate terminal 74 are provided on the package substrate 82.

  The semiconductor device 100 is disposed on the package substrate 82 such that the second wiring 34 is in contact with and electrically connected to the drain terminal 72. Thus, the first wiring 24 and the third wiring 44 are arranged on the upper surface of the semiconductor package 1000. A conductive paste or the like may be provided between the second wiring 34 and the drain terminal 72. The first wiring 24 and the source terminal 70 are electrically connected by a first bonding wire 76. The third wiring 44 and the gate terminal 74 are electrically connected by a second bonding wire 78. Note that means for electrically connecting the first wiring 24 and the source terminal 70 or the third wiring 44 and the gate terminal 74 is not limited to the bonding wire.

  Next, the effect of this embodiment is described.

  FIG. 5 is a schematic cross-sectional view of a main part of a semiconductor device 800 for comparison with this embodiment. FIG. 6 is a schematic top view of a semiconductor package 8000 using the semiconductor device 800 as a comparison with the present embodiment.

  In the semiconductor device 800, the second wiring 34 and the third wiring 44 are provided on the active region 68, and the first wiring 24 is in contact with the second surface. Therefore, in the semiconductor package 8000 as shown in FIG. 6, the drain terminal 74 and the second wiring 34 are connected by the third bonding wire 80 on the upper surface of the semiconductor package 8000. A large voltage is applied to the drain electrode during driving of the semiconductor device. Therefore, when a semiconductor package is manufactured, the insulating properties of the second wiring 34, the first wiring 24, and the third wiring 44 that are electrically connected to the drain electrode must be maintained.

  In the semiconductor device 100 of this embodiment, the second wiring 34 is provided on the active region 68, and the first wiring 24 and the third wiring 34 are in contact with the second surface 14. That is, since the first wiring 24 and the third wiring 34 are provided on different surfaces from the second wiring, the insulating properties of the second wiring 34, the first wiring 24, and the third wiring 44 are provided. Thus, a highly safe semiconductor device 100 is provided.

  In addition, since the second wiring 34 is provided on the active region 68, the semiconductor device 100 that is smaller than the case where the second wiring 34 is disposed on the element isolation region 62 is provided. .

  Since the source electrode 20 is preferably at the same potential as the substrate 10, the large source-drain capacitance of the lateral power electronic semiconductor device having a multi-finger structure has a plurality of drain electrodes 30, the second connecting portion 32, and the second This is mainly due to the parasitic capacitance between the wiring 34 and the substrate 10. In particular, since the second wiring 34 has a large area, the contribution to the parasitic capacitance is large.

  Semiconductor devices are expected to be applied to high-frequency power semiconductor devices. However, in high-frequency operation, there is a problem that switching loss due to charging / discharging of the parasitic capacitance is increased, and a semiconductor device that makes use of high breakdown electric field strength and high electron mobility cannot be provided.

  In the semiconductor device 100 of this embodiment, the second wiring 34 is provided with the interlayer insulating film 60 sandwiched between the substrates 10. Therefore, the parasitic capacitance generated between the second wiring 34 and the substrate 10 is reduced.

Incidentally, thereby the first nitride semiconductor layer 6 and the longer second distance d ₂ of the wire 34, as a result, the drain resistance since the second coupling portion 32 is long increases. However, in the semiconductor device 100, for high-speed operation, it is preferable to reduce the parasitic capacitance between the second wiring 34 and the substrate 10 rather than reducing the drain resistance.

On the other hand, in order to drive a semiconductor device with a large current, it is preferable to reduce the source resistance. By making the film thickness t ₁ of the first wiring 24 larger than the film thickness t ₂ of the second wiring 34, the source resistance can be reduced.

(Ε _f / d _f )> (ε _d / d _d ) means that the contribution of the parasitic capacitance between the second wiring 34 and the substrate 10 is smaller than the contribution of the capacitance caused by the nitride semiconductor layer. This is preferable.

  According to the semiconductor device of this embodiment, a miniaturized semiconductor device is provided.

(Second Embodiment)
The semiconductor device of this embodiment includes a substrate having a first surface and a second surface provided on the opposite side of the first surface, and a first nitride provided on the first surface. A semiconductor layer, a plurality of source electrodes provided on the first nitride semiconductor layer, a plurality of drain electrodes provided on each of the first nitride semiconductor layers and between the plurality of source electrodes; A plurality of gate electrodes provided between the plurality of source electrodes and the plurality of drain electrodes on the first nitride semiconductor layer, respectively, in contact with the second surface and electrically connected to the plurality of source electrodes A first wiring connected to the plurality of drain electrodes, a second wiring provided on the active region and opposite to the second wiring of the first nitride semiconductor layer Provided in contact with the first nitride semiconductor layer and electrically connected to the plurality of gate electrodes. Comprising 3 wires and, the, the interlayer insulating film provided between the first nitride semiconductor layer and the second wiring.

  The semiconductor device of this embodiment is different from the semiconductor device 100 of the first embodiment in that there is no substrate 10 near the third wiring 44 and the third wiring 44 is in direct contact with the nitride semiconductor layer. Yes. Here, the description overlapping with the first embodiment is omitted.

  FIG. 7 is a schematic cross-sectional view of a main part of the semiconductor device 200 of the present embodiment.

  As in the semiconductor device 200 of the present embodiment, the third connecting portion 42 (third wiring) and the substrate 10 can be insulated from each other even when the substrate 10 in the vicinity of the third wiring 44 is not provided. .

  According to the semiconductor device 200 of the present embodiment, a miniaturized semiconductor device is provided.

(Third embodiment)
The semiconductor device of this embodiment is different from the first and second embodiments in that the interlayer insulating film 60 includes a plurality of insulating films. Here, the description overlapping with the first and second embodiments is omitted.

  FIG. 8 is a schematic cross-sectional view of the semiconductor device 300 of this embodiment.

  In the semiconductor device 300 according to the present embodiment, the interlayer insulating film 60 includes the first insulating film 60a between the first nitride semiconductor layer 6 and the second wiring 34, the first insulating film 60a, and the second insulating film 60a. A second insulating film 60 b provided between the second wirings 34 and a third insulating film 60 c provided between the second insulating film 60 b and the second wiring 34.

  According to the semiconductor device 300 of the present embodiment, since the interlayer insulating film can be formed by dividing into a plurality of processes, the manufacture of the semiconductor device 300, in particular, the electrode and the connecting portion becomes easy.

  According to the semiconductor device 300 of the present embodiment, a semiconductor device that is downsized and easy to manufacture is provided.

(Fourth embodiment)
In the semiconductor device 400 of this embodiment, one end is electrically connected to the gate electrode 40, and the other end is disposed between the gate electrode 40 and the drain electrode 30, and is provided apart from the first nitride semiconductor layer 6. One end of the gate field plate electrode 90 is electrically connected to the source electrode 20 and the other end is separated from the first nitride semiconductor layer 6 and is separated from the first nitride semiconductor layer 6. This is different from the first to third embodiments in that it further includes a source field plate electrode 92 provided between the electrodes 30. Here, the description overlapping with the first to third embodiments is omitted.

  FIG. 9 is a schematic cross-sectional view of the semiconductor device 400 of the present embodiment.

  The gate field plate electrode 90 and the source field plate electrode 92 are used to relieve electric field concentration in the semiconductor device 100 and suppress current collapse by an electric field generated from each.

  According to the semiconductor device 400 of the present embodiment, a semiconductor device that is reduced in size and suppressed in current collapse is provided.

  According to the semiconductor device of at least one embodiment described above, a substrate having a first surface and a second surface provided on the opposite side of the first surface, and provided on the first surface. Provided on the first nitride semiconductor layer, the plurality of source electrodes provided on the first nitride semiconductor layer, and between the plurality of source electrodes on the first nitride semiconductor layer. A plurality of drain electrodes, a plurality of gate electrodes provided between the plurality of source electrodes and the plurality of drain electrodes on the first nitride semiconductor layer, and in contact with the second surface, A first wiring electrically connected to the plurality of source electrodes; a second wiring electrically connected to the plurality of drain electrodes; provided on the active region; and provided in contact with the second surface. A third wiring electrically connected to the plurality of gate electrodes, and a first nitridation An interlayer insulating film provided between the semiconductor layer and the second wiring, by providing, it is possible to provide a parasitic capacitance small semiconductor device.

  Although several embodiments and examples of the present invention have been described, these embodiments and examples have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

4 Second nitride semiconductor layer (buffer layer)
6 1st nitride semiconductor layer 6a 1st semiconductor layer 6b 2nd semiconductor layer 8 Gate insulating film 10 Substrate 12 1st surface 14 2nd surface 20 Source electrode 22 1st connection part 24 1st wiring 30 drain electrode 32 second connection portion 34 second wiring 40 gate electrode 42 third connection portion 44 third wiring 60 interlayer insulating film 62 element isolation region 64 element isolation boundary 66 insulating layer 68 active region 70 source terminal ( First terminal)
72 Gate terminal (second terminal)
74 Drain terminal (third terminal)
76 First bonding wire 78 Second bonding wire 80 Third bonding wire 82 Package substrate 90 Gate field plate electrode 92 Source field plate electrode 100 Semiconductor device 200 Semiconductor device 300 Semiconductor device 400 Semiconductor device 1000 Semiconductor package 8000 Semiconductor package

Claims (21)

A substrate having a first surface and a second surface provided on the opposite side of the first surface;
A first nitride semiconductor layer provided on the first surface;
A plurality of source electrodes provided on the first nitride semiconductor layer;
A plurality of drain electrodes provided between each of the plurality of source electrodes on the first nitride semiconductor layer;
A plurality of gate electrodes provided between the plurality of source electrodes and the plurality of drain electrodes on the first nitride semiconductor layer;
A first wiring provided in contact with the second surface and electrically connected to the plurality of source electrodes;
A second wiring provided on the active region and electrically connected to the plurality of drain electrodes;
A third wiring provided in contact with the second surface and electrically connected to the plurality of gate electrodes;
An interlayer insulating film provided between the first nitride semiconductor layer and the second wiring;
A plurality of third coupling portions that are provided between the plurality of gate electrodes and the third wiring and electrically connect each of the plurality of gate electrodes and the third wiring;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein a film thickness of the first wiring is larger than a film thickness of the second wiring.   The ratio of the relative dielectric constant of the first nitride semiconductor layer to the film thickness of the first nitride semiconductor layer is greater than the ratio of the relative dielectric constant of the interlayer insulating film to the film thickness of the interlayer insulating film. Alternatively, the semiconductor device according to claim 2. 4. The device according to claim 1, further comprising: a first coupling portion that is provided between the plurality of source electrodes and the first wiring and electrically connects the plurality of source electrodes and the first wiring. the semiconductor equipment according to any one claim.   The semiconductor device according to claim 4, further comprising a plurality of the first coupling portions, wherein the plurality of first coupling portions are electrically connected to the plurality of source electrodes.   2. The device according to claim 1, further comprising: a second connecting portion provided between the plurality of drain electrodes and the second wiring and electrically connected to the plurality of drain electrodes and the second wiring. Item 6. The semiconductor device according to any one of Items 5. The semiconductor device according to claim 1 , further comprising an insulator provided between the substrate and the third connecting portion. The first nitride semiconductor layer includes:
A first semiconductor layer;
A second semiconductor layer provided on the first semiconductor layer and having a band gap larger than that of the first semiconductor layer;
The semiconductor device of any one of claims 1 to claim 7 having a. The semiconductor device of the second nitride further comprises a semiconductor layer according to claim 1, wherein any one of claims 8 provided between said substrate and said first nitride semiconductor layer. The interlayer insulating film semiconductor device according to claim 1 or any one of claims 9 having a plurality of insulating films. A substrate having a first surface and a second surface provided on the opposite side of the first surface;
A first nitride semiconductor layer provided on the first surface;
A plurality of source electrodes provided on the first nitride semiconductor layer;
A plurality of drain electrodes provided between each of the plurality of source electrodes on the first nitride semiconductor layer;
A plurality of gate electrodes provided between the plurality of source electrodes and the plurality of drain electrodes on the first nitride semiconductor layer;
A first wiring provided in contact with the second surface and electrically connected to the plurality of source electrodes;
A second wiring provided on the active region and electrically connected to the plurality of drain electrodes;
A third wiring provided on a side opposite to the second wiring of the first nitride semiconductor layer, in contact with the first nitride semiconductor layer, and electrically connected to the plurality of gate electrodes;
An interlayer insulating film provided between the first nitride semiconductor layer and the second wiring;
A semiconductor device comprising: The semiconductor device according to claim 11, wherein a film thickness of the first wiring is larger than a film thickness of the second wiring. The ratio between the relative dielectric constant of the first nitride semiconductor layer and the film thickness of the first nitride semiconductor layer is greater than the ratio between the relative dielectric constant of the interlayer insulating film and the film thickness of the interlayer insulating film. A semiconductor device according to claim 12. 14. A first connecting portion provided between the plurality of source electrodes and the first wiring, which electrically connects the plurality of source electrodes and the first wiring. The semiconductor device according to any one of claims. The semiconductor device according to claim 14, further comprising a plurality of the first coupling portions, wherein the plurality of first coupling portions are electrically connected to each of the plurality of source electrodes. 12. The device according to claim 11, further comprising a second coupling portion provided between the plurality of drain electrodes and the second wiring and electrically connected to the plurality of drain electrodes and the second wiring. Item 15. The semiconductor device according to any one of Items 15. 17. The device according to claim 11, further comprising a third coupling portion that is provided between the plurality of gate electrodes and the third wiring and electrically connects the plurality of gate electrodes and the third wiring. The semiconductor device according to any one of claims. The semiconductor device according to claim 17, further comprising a plurality of third connection portions, wherein the plurality of third connection portions are electrically connected to each of the plurality of gate electrodes. The first nitride semiconductor layer includes:
A first semiconductor layer;
A second semiconductor layer provided on the first semiconductor layer and having a band gap larger than that of the first semiconductor layer;
The semiconductor device according to claim 11, comprising: 20. The semiconductor device according to claim 11, further comprising a second nitride semiconductor layer provided between the substrate and the first nitride semiconductor layer. The semiconductor device according to claim 11, wherein the interlayer insulating film includes a plurality of insulating films.

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