JPH065758B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an electrode structure for realizing high performance of a semiconductor device, particularly a lateral field effect transistor (FET).

[Conventional technology]

Conventionally, as this kind of device, IEEE TRANSACTIONS ON MIC
ROWAVE THEORY AND TECHNIQUES VOL MTT−29 No.6 JUNE
3 and 4 shown in 1981 (IV-IV 'in FIG. 3)
The cross-sectional view) is shown. In these figures,
(1) is FET, (2) is semi-insulating substrate, (3) is semi-insulating substrate (2)
Is an operating layer formed by ion implantation or the like, (4) and (5) are source and drain electrodes, and (6) is a gate electrode formed so as to make a Schottky contact. Reference numerals (7) and (8) denote drain and gate lead wires for connecting to an external circuit (not shown), respectively. Source electrode
(4) is electrically connected to the back surface electrode (10) through a via hole (9) penetrating the semi-insulating substrate (2) and the operating layer (3).

For example, in the case of an n-channel FET, the source electrode (4) is grounded via the via hole (9) and the back surface electrode (10). The gate electrode (6) is connected to an external circuit via a gate lead wire (8) as a high frequency signal input side, and a negative voltage is applied as a DC bias. The drain electrode (5) is connected to an external circuit via a drain lead wire (7) as a high frequency signal output side, and a positive voltage is applied as a DC bias.

As described above, the high frequency signal is input to the gate electrode (6), and the high frequency signal amplified by the drain electrode (5) is output.
FETs are often used as so-called high-frequency amplifiers.

Here, in order to increase the gain of the amplifier, it is particularly necessary to reduce the source resistance and the source inductance. Directly grounding the source electrode (4) through the vice hole (9) without using a lead wire effectively contributes to the reduction of the source resistance and the source inductance.

[Problems to be solved by the invention]

The FET (1) having the vise hole (9) has a vise hole structure in which a hole is opened from the back surface of the semiconductor substrate and the source electrode (4) in the direction is penetrated. On the other hand, considering the high-frequency transmission loss, the thicker the semiconductor substrate, the smaller the loss and
The original performance can be obtained. However, as the thickness of the semiconductor substrate increases, in the conventional vise hole structure, the opening area of the back surface of the semiconductor substrate increases, and the area of the vise hole portion in the chip increases. This was a disadvantage for integration.

The present invention provides a high gain due to the low source resistance and low source inductance of the vice-hole structure, and further,
It is an object of the present invention to obtain a semiconductor device capable of reducing transmission loss and achieving high integration at that time by using a thick semiconductor substrate. Further, it is another object of the present invention to provide a semiconductor device which can reduce thermal or electrical variation in the chip by using a bridging electrode together and can obtain high reliability.

[Means for solving problems]

This invention utilizes a surface through hole formed in the surface of at least one or more island-shaped source electrode portions from the surface and a back surface through hole formed on the back surface corresponding thereto as a vice hole of the source electrode, The back surface of the above is used as a source electrode terminal, and each source electrode on the front surface is connected by a bridge electrode.

[Action]

By adopting the front and back vise hole structure in the present invention, without lowering the low source resistance and low source inductance of the vise hole, it is possible to integrate and by connecting each source electrode on the surface with a bridge electrode, Mitigates thermal or electrical variations within the chip.

Example of Invention

An embodiment of the present invention will be described below with reference to FIG. 1 and FIG.
II-II 'line sectional view). In these figures,
Reference numeral (11) is a front surface through hole of the island-shaped source electrode (4) and is electrically connected to the back surface electrode (10) through the back surface through hole (12). Further, each source electrode (4) is electrically connected by a bridging electrode (13).

In the drawings, the same symbols as those in FIGS. 3 and 4 indicate the same or corresponding portions.

In the vise hole having the structure shown in such an embodiment, when each of the front surface through hole (11) or the back surface through hole (12) has the same opening area as that of the conventional vise hole, it is twice as large as the conventional one. It can be applied to semiconductor substrate thickness. Similarly, if the semiconductor substrate has the same thickness, a vice hole can be formed with an opening area that is half that of a conventional one, which is effective for integration.

Therefore, it can be applied to a thick semiconductor substrate with little high-frequency transmission loss without impairing the low source resistance and low source inductance of the vice-hole structure, so that a high-performance FET can be realized.

Further, even if the die bonding is insufficient and thermal or electrical variation occurs in the chip, the variation can be mitigated by the bridging electrode (13), and high reliability can be obtained.

In addition, although the case where the number of island-shaped source electrodes (4) is two is described in the above-mentioned embodiment, the present invention can be applied even when a plurality of island-shaped source electrodes are arranged as in a power FET. I can.

In the case of a power FET, a heat dissipation effect can be expected by forming the back electrode of the FET with a thick plating.

〔The invention's effect〕

As described above, according to the present invention, the island-shaped source electrode is configured to be grounded to the back surface electrode through the front surface through hole and the back surface through hole, so that the integration degree is high and the performance is high.
FET can be realized.

In addition, the bridging electrode is configured to reduce thermal or electrical variations in the chip, so that a highly reliable FE
Can realize T.

[Brief description of drawings]

1 is a top view of an FET showing an embodiment of the present invention, FIG. 2 is a sectional view taken along the line II-II 'of FIG. 1, and FIG. 3 is a top view of a conventional FET. FIG. 4 is a sectional view taken along the line IV-IV 'in FIG. Where (1) is a FET, (2) is a semi-insulating substrate, (3) is an operating layer,
(4) is a source electrode, (5) is a drain electrode, (6) is a gate electrode, (7) is a drain lead wire, (8) is a gate lead wire,
(9) is a conventional via hole, (10) is a back surface electrode, (11) is a front surface through hole, (12) is a back surface through hole, and (13) is a bridge electrode. The same reference numerals in the drawings indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makio Komaru 4-1-1 Mizuhara, Itami-shi, Hyogo Prefecture LS Electric Co., Ltd. LSE Research Institute (72) Yoshinobu Sasaki 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation LSI Research Center

Claims (1)

[Claims] 1. In a lateral field effect transistor having a drain electrode / gate electrode and an island-shaped source electrode on one main surface, at least one source electrode portion has a surface through-hole formed from the one main surface and There is a back surface through hole formed in the corresponding other main surface, the back surface electrode and the source electrode formed in the other main surface are electrically connected by the front surface through hole and the back surface through hole portion, and A semiconductor device, wherein the one main surface is electrically insulated from the gate electrode and the drain electrode, and all the island-shaped source electrodes on the one main surface are electrically connected.