JP2010182741A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device composed of a group III-V nitride semiconductor that reduces loss of a high-frequency signal caused on a substrate, and improves high-frequency output and linearity of output electric power. <P>SOLUTION: The semiconductor device composed of the group III-V nitride semiconductor includes a cover 116 for packaging, a ground conductor layer 118 formed on a bottom surface of the cover 116 for packaging, a high dielectric constant film 114 formed on the ground conductor layer 118, a back electrode 113 formed on the high dielectric constant film 114 and being not in contact with the ground conductor layer 118, the substrate 101 arranged on the back electrode 113 and made of silicon, a channel layer 103 and a Schottky layer 104 formed on the substrate 101, and a bias electrode 119 formed on the bottom surface of the cover 116 for packaging and being not in contact with the ground conductor layer 118, wherein the back electrode 113 is electrically connected to a bias electrode 119. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device made of a group III-V nitride semiconductor, and more particularly to a technique for mounting a high-frequency semiconductor chip.

The III-V nitride semiconductor has physical characteristics of a wide band gap and a direct transition type band structure, which are its physical characteristics. Specifically, a general formula such as gallium nitride (GaN), aluminum nitride (AlN), and indium nitride (InN) is Al _x Ga _{1 -xy} In _y N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ This is the mixed crystal represented by 1). Due to the above characteristics, this material system is being studied for application to electronic devices because of its high breakdown electric field and saturation electron velocity, as well as to short wavelength optical elements.

In particular, a two-dimensional electron gas (hereinafter referred to as 2 Dimensional Electron Gas: 2DEG) appearing at the interface between an Al _x Ga _1-x N layer (where 0 <x ≦ 1) and a GaN layer epitaxially grown sequentially on a semi-insulating substrate. Hetero-junction field effect transistors (hereinafter referred to as HFETs) that use a heterojunction field effect transistor (hereinafter referred to as HFET) are being developed as high-power devices and high-frequency devices. In this HFET, in addition to the supply of electrons from the carrier supply layer (n-type AlGaN Schottky layer), there is charge supply due to the polarization effect consisting of spontaneous polarization and piezo polarization, so the electron density is 10 ¹³ cm ⁻² . Exceed. This is about one digit larger than that of the AlGaAs / GaAs HFET. As described above, an HFET using a III-V nitride semiconductor can be expected to have a higher drain current density than a GaAs HFET, and an element having a maximum drain current exceeding 1 A / mm has been reported (Non-Patent Document). 1). Further, the group III-V nitride semiconductor exhibits high breakdown voltage characteristics due to a wide band gap (for example, the band gap of GaN is 3.4 eV). Therefore, in the HFET using the III-V nitride semiconductor, the breakdown voltage between the gate and the drain can be set to 100 V or more (see Non-Patent Document 1). As described above, application of HFETs using III-V nitride semiconductors with high breakdown voltage and high current density is being studied as high-frequency elements and as elements capable of handling high power with smaller design dimensions than conventional ones.

  Furthermore, in recent years, with the progress of film formation technology for epitaxial growth, not only silicon carbide (SiC) and sapphire, which are easily lattice-matched, but also technology development for epitaxial growth on inexpensive silicon (Si) substrates has been vigorously conducted. . Here, a conventional FET which is a high-power element on a Si substrate will be described.

  FIG. 11 is a structural cross-sectional view of a semiconductor device having a conventional via hole (substrate through hole) structure. A semiconductor device 500 shown in the figure is an HFET, and includes a conductive substrate 501 made of Si, a buffer layer 502 formed on the conductive substrate 501, and a III− formed on the buffer layer 502. A channel layer 503 made of a group V nitride semiconductor and a Schottky layer 504 made of a group III-V nitride semiconductor formed on the channel layer 503 are provided. On the Schottky layer 504, a gate electrode 508, ohmic source and drain electrodes 507 and 506 located on both sides thereof, and an insulating layer 505 are formed. A via hole 509 is selectively formed in a part of the conductive substrate 501 and the semiconductor layer located under the source electrode 507. A back electrode 510 is formed on the back surface of the conductive substrate 501. The back electrode 510 is connected to a ground power source by filling the via hole 509 with a conductor.

  As described above, the HFET in which the source electrode 507 is grounded via the back electrode 510 and the via hole 509 can reduce the source inductance as compared with the HFET having a configuration in which the source electrode is grounded by a wire. It has been reported that the improvement is seen (see Non-Patent Document 2).

  As another conventional example, a structure in which a source electrode or an emitter electrode is connected to a conductive p + type substrate grounded via a via hole is known (see Patent Document 1). In order to obtain this structure, for example, Patent Document 2 reports a technique in which a substrate is thinly polished and a via hole is formed by etching from the back surface of the polished substrate.

  However, the conventional semiconductor device using the Si substrate has a problem that the high-frequency loss of the substrate at the time of applying a high frequency is large and the high-frequency output is lower than that of the semiconductor element using the SiC substrate from the following viewpoints. .

(1) The insulating property of the Si substrate is inferior to that of the SiC substrate (the specific resistance of the substrate is low).
(2) The crystallinity at the interface between the Si substrate and the semiconductor layer epitaxially grown on the Si substrate is inferior to the crystallinity at the interface between the SiC substrate and the semiconductor layer epitaxially grown on the SiC substrate, resulting in a low resistance layer at the interface. End up.

  The low resistance layer affects the drain current flowing through the channel layer 503 and attenuates the high frequency output. In order to suppress the attenuation of the high-frequency output, a method of changing the low resistance layer to an insulating layer by applying a DC bias voltage to the substrate and controlling the charge distribution at the interface is employed.

FIG. 12 is a graph showing the substrate bias voltage dependency of the saturation output power of the conventional semiconductor device. In the figure, the vertical axis indicates the power (Psat) at which the high-frequency output is saturated and the power (P3 dB) when the gain is compressed by 3 dB. The horizontal axis indicates the DC substrate bias voltage applied to the substrate. It can be seen that Psat and P3 dB increase as the substrate bias voltage is applied in the positive direction. This is because the low resistance layer described above is insulated as the substrate bias voltage increases. As described above, in the conventional semiconductor device, the high frequency output power is improved and the linearity is improved by applying the substrate bias voltage.
JP 2006-86398 A Yuji Ando and five others, “Evaluation of High Voltage AlGaN / GaN Heterojunction FET”, IEICE Technical Report, October 2002, ED2002-214, CPM2002-105, p. 29-34 Masumi Fukuda, 1 other, “Basics of GaAs Field Effect Transistor”, IEICE, 1992, p. 214

  However, the conventional semiconductor device requires the lead-out wiring for applying the substrate bias voltage described above. Parasitic inductance occurs in the lead-out wiring. This parasitic inductance affects the high-frequency input signal applied to the gate electrode and the high-frequency output signal generated between the drain and the source, and makes the transistor operation unstable. In addition, as a result, a problem such as the oscillation of the transistor may occur.

  As a result, even if a substrate bias voltage is applied, a desired high-frequency output and output power linearity cannot be obtained.

  The present invention has been made in view of the above problems, and provides a low-cost semiconductor device capable of reducing the loss of a high-frequency signal on a substrate and improving the linearity of high-frequency output and output power. For the purpose.

  In order to solve the above problems, a semiconductor device of the present invention is a semiconductor device having a transistor element that operates at a high frequency, the substrate, the transistor element formed on the surface of the substrate, and the back surface of the substrate. A first conductor layer for grounding formed thereon, a dielectric layer formed on the first conductor layer, and a second conductor layer formed on the dielectric layer and insulated from the first conductor layer. And a conductor layer.

  According to this configuration, since the dielectric layer and the conductor layer formed on the back surface of the substrate are formed directly under the substrate, even if there is a parasitic inductance due to the lead-out wiring for applying the substrate bias voltage, the inductance Unnecessary high frequency components generated by the components are eliminated directly under the substrate. Therefore, even if a substrate bias voltage is applied, the high frequency input signal and the high frequency output signal are not affected by unnecessary high frequency components, and the transistor operation does not become unstable. Can be improved.

  The substrate is preferably a silicon substrate, and the transistor element is preferably made of a group III-V nitride semiconductor.

  From the viewpoint of epitaxially growing a group III-V semiconductor, silicon carbide having a high degree of lattice matching with the group III-V semiconductor is used as the substrate. However, the use of a silicon substrate can reduce the material cost. In addition, a III-V nitride semiconductor having physical characteristics such as a wide band gap and a direct transition band structure is useful for a high-frequency device, and is also useful for a high-power device because it has a high breakdown voltage and a high current density. .

  Further, a lid for packaging the transistor element may be provided, and an inner surface of the lid may be bonded onto the second conductor layer.

  Thereby, since the substrate is connected to the lid through the dielectric layer, unnecessary high-frequency components generated by the parasitic inductance component described above are eliminated from the back of the substrate through the lid. In addition, since the bypass capacitor is formed inside the lid, it is possible to reduce the size and increase the output.

  The lid includes a third conductor layer formed on the inner surface and insulated from the second conductor layer, and the first conductor layer is connected to be electrically connected to the third conductor layer. It is preferable.

  As a result, the third conductor layer can be used as a wiring for applying a substrate bias voltage. Since the third conductor layer is formed so as not to be electrically connected to the second conductor layer on the inner surface of the lid body, the above-described removal of unnecessary high-frequency components and application of the substrate bias voltage with a small parasitic inductance component are applied to the lid. Realized inside the body.

  Further, the second conductor layer is disposed at least in a recess formed on the inner surface of the lid, and the third conductor layer is disposed on a part of the inner surface other than the recess, One conductor layer has at least one outer periphery in the plane direction longer than the outer periphery of the recess in the same direction as the outer periphery, and the dielectric layer has all the outer periphery in the plane direction the same as the outer periphery. The direction is preferably shorter than the outer periphery of the recess.

  As a result, the second conductor layer and the dielectric layer are connected to the lid in the recess of the lid. Further, since the first conductor layer is not inserted into the recess of the lid, the first conductor layer and the third conductor layer are connected outside the recess. Therefore, the second conductor layer functioning as a part of the path for removing unnecessary high-frequency components and the third conductor layer functioning as wiring for applying the DC substrate bias voltage are insulated, thereby reducing the size and increasing the output. Figured.

  The lid has a side wall surrounding the substrate and the semiconductor die composed of the transistor element, and the second conductor layer and the third conductor layer are formed to the inner surface of the side wall and a part of the edge, respectively. The semiconductor device further includes a packaging substrate that covers the semiconductor die together with the lid by contacting the edge of the lid, and the packaging substrate includes an upper surface of the lid. Conductor layer electrodes are formed in accordance with the pattern positions of the second conductor layer and the third conductor layer formed on the semiconductor element, and semiconductor layer electrodes are aligned with the pattern positions of the plurality of electrodes of the transistor element. The formed semiconductor layer electrode may be connected to the plurality of electrodes by bumps.

  Thereby, the structure which removes an unnecessary high frequency component and the structure which applies a substrate bias voltage to the inside covered with the lid and the packaging substrate are realized. In addition, since the packaging substrate and the plurality of electrodes are connected by bumps, it is possible to reduce the distance between the packaging substrate and the plurality of electrodes as compared to the case where they are connected by wire bonding. Become. Therefore, it is possible to achieve downsizing, cost reduction, high performance, and high output as a packaged product on which a semiconductor die is mounted.

The lid may be formed using a semiconductor as a base material.
Thereby, the following methods are mentioned as a method of manufacturing the semiconductor device which mounted the semiconductor die and its cover. First, on both surfaces of a wafer substrate, a semiconductor element wafer on which a transistor element and a bypass capacitor are manufactured and a lid wafer made of a semiconductor and processed on a lid are bonded at a wafer level. Thereafter, dicing is cut into individual packages according to the dicing lane. According to this method, since there are many processes at the wafer level and few processes at the individual piece level, it is possible to realize a mass production process that is simplified and reduced in cost.

  Further, a ground potential is applied to the second conductor layer, a substrate bias potential is applied to the third conductor layer, and the semiconductor device further includes a bias potential application circuit that applies the substrate bias potential. A detection circuit for detecting high-frequency power output from the transistor element, and a bias potential adjustment circuit for adjusting the substrate bias potential based on an output signal from the detection circuit may be provided.

  As a result, the high frequency signal output from the packaged product on which the semiconductor die is mounted can be optimized, so that high functionality can be achieved.

  According to the semiconductor device of the present invention, since the transistor operation does not become unstable due to the inductance component of the wiring to which the substrate bias voltage is applied, the high frequency output and the linearity of the output power can be improved. In addition, since the conductor layer and the dielectric layer formed between the silicon substrate and the bottom surface of the lid are used as a configuration for achieving the above-described effect, the size and cost can be reduced.

(Embodiment 1)
The semiconductor device in the present embodiment includes a transistor element formed on the surface of a silicon substrate, a first conductor layer formed on the back surface of the silicon substrate, and a dielectric layer formed on the first conductor layer. A second conductor layer formed on the dielectric layer, a lid bonded to the second conductor layer for packaging the transistor element, and a second conductor formed on the inner surface of the lid The first conductor layer and the third conductor layer are electrically connected to each other. As a result, the third conductor layer is used as a wiring for applying a substrate bias voltage, and even if there is a parasitic inductance, an unnecessary high-frequency component is generated by the first conductor layer, the dielectric layer, and the second conductor layer. Is removed from the back surface of the substrate through the lid. Therefore, it becomes possible to improve the linearity of the high frequency output and the output power.

Hereinafter, Embodiment 1 of the present invention will be described in detail with reference to the drawings.
FIG. 1A is a top perspective view showing the structure of the semiconductor device according to the first embodiment of the present invention. FIG. 1B is a structural cross-sectional view taken along the line AA ′ in FIG. 2 is a structural cross-sectional view taken along line BB ′ of FIG. FIG. 3 is a structural cross-sectional view taken along the line CC ′ of FIG. A semiconductor device 10 described in FIGS. 1B, 2, and 3 includes a substrate 101, a buffer layer 102, a channel layer 103, a Schottky layer 104, insulating layers 106 and 111, and a source electrode 107. The drain electrode 108, the gate electrode 109, the bump 110, the back electrode 113, the high dielectric constant film 114, the ground conductor layers 115 and 118, the packaging lid 116, the bias electrode 119, and the packaging. Substrate 120.

  The semiconductor chip described in FIGS. 1 to 3 has a simplified structure having a hetero-junction field effect transistor (hereinafter referred to as HFET) function in order to explain the mounting structure of the present invention. It is described. 4A is a top view showing a configuration of a multi-finger type transistor chip included in the semiconductor device of the present invention, and FIG. 4B is a diagram of a T-shaped gate lead-out type transistor chip included in the semiconductor device of the present invention. It is a top view which shows a structure. The transistors shown in both figures are HFETs each including a gate electrode and gate pad 127, a source electrode and source pad 128, and a drain electrode and drain pad 129. In the multi-finger type transistor chip shown in FIG. 4A, unit structures represented by a gate electrode, a source electrode and a drain electrode are connected in parallel. In this case, the total gate width (Wg) representing the transistor size is defined by the number of units (Nf) × unit finger length (Lf). Further, in the T-shaped gate lead-out type transistor chip shown in FIG. 4B, the gate electrode has a T-shape, and Wg is equivalent to two unit fingers. In both transistor chips, the gate pad 127 and the source pad 128 are drawn out in the same direction on the main surface on which the transistor is formed, and the drain pad 129 is drawn out in the opposite direction.

  The semiconductor chips shown in FIGS. 1, 2 and 3 are all shown only in the unit parts of the gate electrode, the source electrode and the drain electrode.

  Even if the semiconductor device of the present invention includes a semiconductor chip in which unit portions are arranged in parallel, such as the multi-finger type transistor chip shown in FIG. The same effects as those of the semiconductor device described in (1) can be obtained.

Hereinafter, the configuration and function of the semiconductor device described in FIGS. 1 to 3 will be described.
The semiconductor device 10 constitutes an HFET. First, the structure and function of the main components of the HFET will be described. In the cross-sectional views of the semiconductor chip shown in FIG. 1B, FIG. 2 and FIG. 3, the surface of the substrate 101 is disposed on the lower side and the back surface of the substrate 101 is disposed on the upper side. With respect to the stacking relationship of the layers on the surface of the substrate 101, the stacking in the lower direction in FIG. 1 is expressed as being stacked on the lower layer. In addition, regarding the stacking relationship of the layers on the back surface of the substrate 101, the stacking in the upper direction in FIG. 1 is expressed as being stacked on the lower layer.

  The substrate 101 is, for example, a high resistance substrate made of silicon (Si) and having a thickness of 500 μm. Here, the “high resistance” is used to mean that no current flows during normal operation of the HFET, and a so-called semi-insulating layer is also called a high resistance layer.

The buffer layer 102 is laminated on the substrate 101, and is a layer having a thickness of 500 nm made of, for example, high-resistance aluminum gallium nitride (Al _x Ga _1-x N (0 <x ≦ 1)). The buffer layer 102 is formed to alleviate lattice mismatch between the substrate 101 and the channel layer 103 and Schottky layer 104.

  The channel layer 103 is stacked on the buffer layer 102 and is a semiconductor layer having a thickness of 1000 nm made of, for example, undoped gallium nitride (GaN). GaN is a group III-V nitride semiconductor having a large band gap.

Schottky layer 104 is laminated on the channel layer 103, for example, a semiconductor layer having a thickness of 25nm made of n-type aluminum gallium nitride _{(Al y Ga 1-y N} (0 <y ≦ 1)). Al _y Ga _1-y N is a group III-V nitride semiconductor having a larger band gap than that of GaN, which is a component of the lower layer.

The channel layer 103 induces a two-dimensional electron gas (hereinafter referred to as 2DEG) having a high sheet carrier concentration on the order of 10 ¹³ (cm ⁻² ) at the interface with the Schottky layer 104. Further, the Schottky layer 104 functions as an electron supply layer that supplies electrons to the interface.

  The insulating layer 106 is stacked on the Schottky layer 104 and is a layer having a thickness of 100 nm made of, for example, silicon nitride (SiN). The insulating layer 106 is provided with a plurality of openings that are separated from each other.

A source electrode 107, a drain electrode 108, and a gate electrode 109 are provided as electrode portions in the plurality of openings, respectively. The gate electrode 109 is made of, for example, a stacked body of nickel (Ni) and gold (Au) so as to exhibit Schottky properties with respect to the Schottky layer 104 made of n-type Al _y Ga _1-y N. Further, the source electrode 107 and the drain electrode 108 are formed of, for example, a laminate of titanium (Ti) and aluminum (Al) so as to exhibit ohmic properties with respect to the Schottky layer 104.

  The insulating layer 111 is formed on the insulating layer 106 and around each electrode. Note that the electrode pads of the source electrode 107, the drain electrode 108, and the gate electrode 109 are provided on the insulating layer 111, and the bumps 110 are formed using a technique such as gold plating. The height of the bump 110 is, for example, 15 μm or more. The bumps 110 may be formed in advance on a packaging substrate 120 described later, instead of being formed on each of the electrode pads.

  The channel layer 103, the Schottky layer 104, the source electrode 107, the drain electrode 108, and the gate electrode 109 constitute a transistor element.

  With the above configuration, the semiconductor device 10 functions as a high-power field effect transistor. For example, when the voltage applied to the gate electrode 109 is increased in the positive direction at a threshold voltage or higher, the drain current flowing through the channel layer 103 increases.

Note that the buffer layer 102 includes a conductive layer 105 at an interface with the substrate 101. This is a low resistance layer generated at the interface due to lattice mismatch between the substrate 101 made of Si and the buffer layer 102 made of Al _y Ga _1-y N. The low resistance layer affects the drain current flowing through the channel layer 103 and attenuates the drain current that is a high-frequency output. In order to suppress the attenuation of the high-frequency output, a method of changing the low resistance layer to an insulating layer by applying a DC bias voltage to the substrate and controlling the charge distribution at the interface is employed.

  Below, the structure and function for improving the high frequency output performance by the main component of HFET mentioned above are demonstrated.

  The substrate 101, the buffer layer 102, the channel layer 103, the Schottky layer 104, the insulating layers 106 and 111, and the electrodes, which are the main components of the HFET described above, constitute a semiconductor die.

  The back electrode 113 is, for example, a laminated body of titanium (Ti) and gold (Au) or a laminated body of chromium (Cr) and gold (Au) on the back surface of the semiconductor die, that is, the back surface of the substrate 101. It is the 1st conductor layer currently formed as. In the semiconductor die and the back electrode 113, at least one outer periphery in the direction of the laminated surface is longer than the outer periphery of the recess 117 of the packaging lid 116 in the same direction as the outer periphery. As a result, the semiconductor die and back electrode 113 are not inserted into the recess 117 region of the packaging lid 116.

  The high dielectric constant film 114 is a dielectric layer formed on the back electrode 113 and on the side opposite to the substrate 101, and is formed so as to fit in a recess 117 of a packaging lid 116 described later. For example, a material such as barium / strontium / titanium compound (BST) or strontium / titanium / oxide (STO) is applied to the high dielectric constant film 114. These are formed by a spin coat method or the like. In order to realize the above-described positional relationship between the recess 117 of the packaging lid 116 and the back electrode 113 and the high dielectric constant film 114, the high dielectric constant film 114 is formed on the entire surface of the back electrode 113, and then the high dielectric constant is formed. The rate film 114 may be patterned. Further, the high dielectric constant film 114 may be formed by a lift-off method so as to have a desired shape.

  The ground conductor layer 115 is a conductor layer formed on the high dielectric constant film 114 on the side opposite to the back electrode 113. Here, the ground conductor layer 115 and the back electrode 113 are not in contact with each other and are insulated. The ground conductor layer 115 is made of, for example, titanium (Ti) and gold (Au).

  The sandwich structure of the back electrode 113, the high dielectric constant film 114, and the ground conductor layer 115 forms a metal-insulator-metal (MIM) type capacitor structure. This capacitor structure is formed directly on the back surface of the substrate 101 and functions as a bypass capacitor for applying a substrate bias voltage.

  Next, the packaging structure and function of the semiconductor die and the bypass capacitor will be described. The semiconductor device 10 includes a packaging lid 116 and a packaging substrate 120 as components of the packaging structure.

  The packaging lid 116 is a lid body made of, for example, ceramic, insulating resin or the like, and includes a bottom plate and a side wall, and a recess 117 is formed in a part of the bottom plate. The recess 117 is formed in accordance with the pattern of the high dielectric constant film 114 and the ground conductor layer 115 constituting the bypass capacitor.

  The ground conductor layer 118 is a second conductor layer formed on the inner surface of the packaging lid 116 and in an inner region of the recess 117 and a partial outer region of the recess 117. Here, the ground conductor layer 118 is bonded to the ground conductor layer 115 in the recess 117 and is not in contact with the back electrode 113 and is insulated. The ground conductor layer 118 is made of, for example, titanium (Ti) and gold (Au). The ground conductor layer 118 is subjected to desired patterning for electrical connection with the packaging substrate 120.

  The ground conductor layer 115 may not be formed, and the ground conductor layer 118 may be directly bonded to the high dielectric constant film 114. In this case, the MIM type capacitor formed immediately below the substrate 101 is formed by a sandwich structure of the back electrode 113, the high dielectric constant film 114, and the ground conductor layer 118.

  The bias electrode 119 is a third conductor layer formed on the inner surface of the packaging lid 116 and in a partial external region of the recess 117, and is a wiring for applying a DC bias voltage to the back surface of the substrate 101. Function as. Further, the bias electrode 119 is insulated from the ground conductor layer 118 and is electrically connected by being joined outside the region of the back electrode 113 and the recess 117. For example, in the layout illustrated in FIG. 1A, the bias electrode 119 and the ground conductor layer 118 are formed so as not to intersect on the inner surface of the packaging lid 116.

  The bias electrode 119 is subjected to desired patterning for electrical connection with the packaging substrate 120. Therefore, the bias electrode 119 may be formed not only on the bottom surface of the packaging lid 116 but also on the inner surface of the side wall of the packaging lid 116.

  In addition, although the bias electrode 119 described in FIG. 1A is formed on both the left and right sides of the semiconductor die, that is, at a plurality of locations, only one of them may be formed.

  The packaging substrate 120 is made of, for example, ceramic or insulating resin. On the surface of the packaging substrate 120, a packaging substrate upper electrode 121 is formed in accordance with the pattern of the bump 110, the ground conductor layer 118, and the bias electrode 119. The bonding between the packaging lid 116 and the packaging substrate 120 is performed by heating to a temperature at which the bump 110, the ground conductor layer 118, and the bias electrode 119 are melted, for example. Further, when the packaging lid 116 and the packaging substrate 120 are bonded, the bias electrode 119 and the back electrode 113 may be bonded simultaneously.

  An external terminal as a package is realized by forming a through hole 122 in the packaging substrate 120 and forming a packaging substrate back surface electrode 123 on the back surface of the packaging substrate 120.

  The above structure has a bias application structure in which a semiconductor die is flip-chip mounted and a bypass capacitor is provided between the back surface of the substrate 101 and the recess 117 of the packaging lid 116. According to this structure, the mounting area can be reduced and the cost can be reduced by reducing the number of parts compared to the case where the bypass capacitor is mounted and used externally.

  In addition, downsizing by packaging using flip-chip mounting and stabilization of high-frequency operation by applying a substrate bias voltage through the package terminal can be achieved, and high performance (reliability improvement) can be achieved. .

  The packaging lid 116 may be formed using a semiconductor as a base material. Thus, the following method can be used as a method for manufacturing a semiconductor device on which the semiconductor die and the packaging lid 116 are mounted.

  First, a semiconductor element wafer in which the transistor element is formed on the front surface of the wafer substrate and the bypass capacitor is formed on the back surface is bonded to a lid wafer made of a semiconductor and processed into a lid body at a wafer level. Thereafter, dicing is cut into individual packages according to the dicing lane. According to this method, since there are many processes at the wafer level and few processes at the individual piece level, it is possible to realize a mass production process that is simplified and reduced in cost.

  In the above configuration, the main components of the semiconductor device according to the embodiment of the present invention include a semiconductor die having a capacitor structure on the back surface, and a packaging lid (or cap) for mounting and packaging the semiconductor die. Lid) and a packaging substrate. That is, a configuration in which a bypass capacitor necessary for applying a bias voltage to the back surface of the substrate of the semiconductor die is incorporated in the package is applied. The effect obtained by this configuration will be described with reference to FIG.

  FIG. 5A is an equivalent circuit diagram of the semiconductor device of the present invention, and FIG. 5B is an equivalent circuit diagram of the conventional semiconductor device. As shown in the equivalent circuit diagram of the conventional semiconductor device shown in FIG. 5B, when the bypass capacitor is loaded at a distance away from the bias application point P on the substrate, the bias application point P and the bypass capacitor An inductance component is generated between them. In this case, the inductance component impairs the stability of the transistor during high-frequency operation and causes unnecessary noise in the transistor.

  On the other hand, as shown in the equivalent circuit diagram of the semiconductor device of the present invention described in FIG. 5A, a bypass capacitor is disposed in the vicinity of the bias application point P on the transistor substrate, so that the high frequency of the transistor can be obtained. In addition to ensuring stability during operation, unnecessary noise can be removed.

  As described above, the semiconductor device of this embodiment has (1) the recess 117 on the bottom surface of the packaging lid 116 on which the semiconductor die is mounted and stored, and the ground conductor layer 118 formed inside the recess 117 and The high dielectric constant film 114 formed between the backside electrode 113 of the semiconductor die functions as a bypass capacitor for applying a backside bias of the semiconductor die. Here, the ground conductor layer 118 formed inside the recess 117 is kept at the ground potential.

  (2) Further, the back surface electrode 113 of the semiconductor die is exposed in a region other than the concave portion 117 on the bottom surface of the packaging lid 116, that is, a region where the ground conductor layer 118 and the high dielectric constant film 114 are not formed. The back electrode 113 is electrically connected to a bias electrode 119 formed in a region other than the recess 117 on the bottom surface of the packaging lid 116. Here, the bias electrode 119 is kept at the substrate bias potential.

  With the above structure, even if parasitic inductance exists in the wiring for applying the substrate bias voltage, an unnecessary high frequency component is eliminated immediately under the substrate by the bypass capacitor formed immediately below the substrate. Therefore, it becomes possible to improve the linearity of the high frequency output and the output power.

  By changing the substrate bias voltage to be applied to the semiconductor device 10 described above, output power (gain) as a high frequency amplifier can be controlled. In order to realize this, a packaged semiconductor device 10, a circuit for detecting power output from the semiconductor device 10, and a circuit for controlling the substrate bias potential based on a signal from the circuit to be detected are required. . As a result, it is possible to give added value and contribute to higher functionality when mounted on a set of communication devices such as mobile phones. Hereinafter, this configuration and function will be described with reference to FIG.

  FIG. 6A is a functional block diagram of a semiconductor device showing a first modification according to the first embodiment of the present invention. FIG. 6B is a circuit configuration diagram of the power monitor unit. The semiconductor device illustrated in FIG. 6A includes an RF unit 134, an IF signal processing unit 135, an antenna 137, a feedback control unit 143, a baseband unit 149, a CPU memory unit 150, and a power supply unit 151. With.

  The parts related to the transmission / reception of high-frequency signals and signal processing are an RF unit 134, an IF signal processing unit 135, and a baseband unit 149.

  The RF unit 134 includes an antenna 137, an antenna duplexer, or a switch 124 used for transmission / reception of a high-frequency signal, and a front end unit 139. The front end unit 139 further includes a transmission unit 140 and a reception unit 141. Have

  The transmission unit 140 includes a transmission mixer (up-converter) that converts an intermediate frequency (IF) signal transmitted from the modulator into a high-frequency signal, a voltage-controlled oscillator (VCO) thereof, and a power amplifier (here, amplifying the high-frequency signal). Mainly composed of small-signal high-frequency amplifiers). Here, the front-stage high-frequency amplifier 144 and the final-stage power amplifier 145 of the transmission unit 140 include the semiconductor device 10 of the present invention.

  The receiving unit 141 is a low noise amplifier (LNA) that amplifies the high frequency signal sent from the antenna 137 and a reception mixer (down) that converts the high frequency signal into a low frequency IF signal so that the signal processing can be performed by the IC. Converter). Here, the low noise amplifier 148 of the receiving unit 141 includes the semiconductor device 10 of the present invention.

  The IF signal processing unit 135 mainly includes a baseband signal modulation unit of the transmission unit and a part (mixer, IF amplifier) that further converts and amplifies the IF signal from the front end unit of the reception unit.

  In communication equipment consisting of such blocks, when the output power differs depending on the communication method and modulation method used, or when the transmission / reception status of high-frequency signals is changing, the output power is changed or kept constant. There is a need. For this reason, as a function of the power amplifier for transmission, a gain control function for maintaining and stabilizing a constant output power is essential. For reception, it is useful to have a gain control function to obtain an appropriate signal level that can be received and detected according to the strength of the received signal when the received signal from the antenna is amplified by a low noise amplifier. is there.

  The baseband unit 149 is a codec for encoding / decoding audio, data, and video signals in a digital system, a codec for channel selection for a transmission multiplexing system, a baseband signal modulation unit, and an IF signal It is mainly composed of the demodulator. The analog system mainly includes a demodulator, a modulator, voice, data, and a signal processor. The baseband unit handles either analog signals or digital signals depending on the communication method, and either an analog dedicated processing IC or a digital signal dedicated processing IC is used separately, or an integrated type that performs analog / digital signal processing. IC is used.

  In addition, there is a CPU memory unit 150 and a power supply unit 151 for controlling the above-described units. The CPU memory unit 150 controls the RF unit 134, the IF signal processing unit 135, and the baseband unit 149 according to a desired communication method. The power supply unit 151 generates a positive power source or a negative power source according to the operating voltage of the circuit of each unit using a DC-DC converter, a regulator, or the like from a battery, a commercial power source, or the like.

Next, a method for controlling the semiconductor device illustrated in FIG.
On the transmitting side, the output power of the power amplifier is monitored by the power monitor unit 142, and the voltage signal is applied to the substrate bias of the semiconductor device 10 included in the front-stage high-frequency amplifier 144 or the final-stage power amplifier 145 via the feedback control unit 143. The output power can be controlled by feeding back to the terminal. For example, a circuit described in FIG. 6B is used as the output power monitor circuit. The power level obtained at the isolation port of the directional coupler 146 is capacitively coupled, converted into a DC voltage by the detection diode 147, and sent to the feedback control unit 143.

  On the other hand, in order to obtain an appropriate signal level that can be received and detected by the IF signal processing unit 135 and an appropriate signal level in the baseband unit 149, the receiving side is configured in multiple stages via the feedback control unit 143 on the receiving side. The output level, that is, the gain, is adjusted by feeding back to the substrate bias application terminal of the semiconductor device 10 located downstream of the low noise amplifier 148.

  With the above configuration and function, the high-frequency signal output from each amplifier including the semiconductor device 10 can be optimized, so that the semiconductor device can be improved in function.

(Embodiment 2)
Hereinafter, the semiconductor device according to the second embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 7 is a structural cross-sectional view of the semiconductor device according to the second embodiment of the present invention. The semiconductor device 20 shown in the figure includes a substrate 101, a buffer layer 102, a channel layer 103, a Schottky layer 104, insulating layers 106, 111 and 131, a source electrode 107, and a drain not shown. Electrode 108, gate electrode 109, bump 110, back electrode 113, high dielectric constant film 114, ground conductor layers 115, 118 and 132, packaging lid 116, bias electrode 119, and packaging A substrate 120 and a through hole 130 are provided. The semiconductor device 20 shown in FIG. 2 is different from the semiconductor device 10 shown in FIG. 2 only in that the source electrode 107 is connected to the ground conductor layer on the back surface of the substrate through the through hole 130. The structure is different. Hereinafter, description of the same points as those of the semiconductor device 10 is omitted, and only different points will be described.

  Hereinafter, the configuration and function for improving the high-frequency output performance by the main components of the HFET described above will be described.

  The ground conductor layer 132 is, for example, a laminated body of titanium (Ti) and gold (Au) or a laminated body of chromium (Cr) and gold (Au) on the back surface of the semiconductor die, that is, the back surface of the substrate 101. It is formed.

  In the through hole 130, an insulating layer 131 is formed on the inner wall in order to maintain insulation from the substrate 101, the buffer layer 102, the channel layer 103, and the Schottky layer 104. The through-hole 130 is filled with a conductor inside the inner wall on which the insulating layer 131 is formed.

  The source electrode 107 is electrically connected to the ground conductor layer 132 through the through hole 130.

  The ground conductor layer 132 is formed in a region including a region immediately below the source electrode 107, and is formed with a space electrically insulated from the back electrode 113 and the bias electrode 119 for applying a substrate bias voltage.

  The above structure can also be applied to the configuration of the semiconductor chip shown in FIG. FIG. 8A is a top view showing a configuration of a multi-finger type transistor chip included in the semiconductor device according to the second embodiment of the present invention, and FIG. 8B is a diagram according to the second embodiment of the present invention. It is a top view which shows the structure of the T-shaped gate lead-out type transistor chip which a semiconductor device has. The transistors shown in both figures are HFETs each including a passive element circuit 133, a gate electrode and gate pad 127, a source electrode and source pad 128, a drain electrode and drain pad 129.

  This is a case where a passive element circuit 133 for input impedance matching is formed so as to be electrically connected to the gate pad 127, and the passive element circuit 133 functions as a microstrip line structure using the ground conductor layer 132 as a ground electrode. Here, the ground conductor layer 132 is formed in a region including the region immediately below the gate pad 127 and the passive element circuit 133. A similar passive element circuit configuration is possible on the drain side by pulling the source pad to the drain pad 129 side.

  As a result, it is possible to have a high-frequency composite function in the same semiconductor chip, so that it is possible to improve the functionality of the semiconductor device.

  Further, in the first embodiment, a structure is shown in which a through hole that electrically connects each electrode of the semiconductor die and the back surface of the substrate is not formed. However, as in the present embodiment, the through hole is formed in the semiconductor die. Also in the structure in which is formed, the same effect as the semiconductor device 10 according to the first embodiment is obtained.

(Embodiment 3)
Hereinafter, the semiconductor device according to the third embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 9 is a structural sectional view of a semiconductor device according to the third embodiment of the present invention. The semiconductor device 30 shown in the figure includes a substrate 101, a buffer layer 102, a channel layer 103, a Schottky layer 104, insulating layers 106 and 111, a source electrode 107, and a drain electrode (not shown). 108, gate electrode 109, bump 110, back electrode 113, high dielectric constant film 114, ground conductor layers 115 and 118, packaging lid 116, bias electrode 119, and packaging substrate 120. Is provided. The semiconductor device 30 shown in the figure is different in structure from the semiconductor device 10 shown in FIG. 2 only in that no recess is formed on the bottom surface of the packaging lid 116. Hereinafter, description of the same points as those of the semiconductor device 10 is omitted, and only different points will be described.

  The packaging lid 116 is a lid body made of, for example, ceramic, insulating resin, etc., and provided with a bottom plate and side walls. In addition, no recess is formed on the bottom surface of the packaging lid 116.

  As shown in FIG. 9, the film thickness of the bias electrode 119 formed on the bottom surface of the packaging lid 116 and the total film thickness of the high dielectric constant film 114 and the ground conductor layers 115 and 118 are adjusted to the same extent. By doing so, it is possible to have the same function as the semiconductor device 10 according to the first embodiment. Here, the back electrode 113 and the bias electrode 119 are electrically connected, and the bias electrode 119 and the ground conductor layers 115 and 118 are electrically insulated.

  The semiconductor device 30 according to the present embodiment also has the same effect as the semiconductor device 10 according to the first embodiment.

(Embodiment 4)
Hereinafter, a semiconductor device according to Embodiment 4 of the present invention will be described in detail with reference to the drawings.

  FIG. 10B is a top perspective view showing the structure of the semiconductor device according to the fourth embodiment of the present invention. FIG. 10A is a structural cross-sectional view taken along line B-B ′ of FIG. The semiconductor device 40 shown in the figure includes a substrate 101, a buffer layer 102, a channel layer 103, a Schottky layer 104, insulating layers 106 and 111, a source electrode 107, and a drain electrode (not shown). 108, gate electrode 109, bonding wires 155, 156 and 157, back electrode 113, high dielectric constant film 114, ground conductor layers 115 and 162, packaging lid 116, bias electrode 161, and package And a substrate 160 for cleaning. Compared to the semiconductor device 10 shown in FIG. 2, the semiconductor device 40 shown in FIG. 2 has no recess on the bottom surface of the packaging lid 116 and is formed on the back surface of the substrate of the semiconductor die. The structure differs in that the bypass capacitor is connected to a recess 167 formed in the packaging substrate 160. Further, in the first to third embodiments, the bump 110 is formed and packaging is performed using flip chip mounting. In this embodiment, instead of the bump, the transistor gate, source, and drain electrode pads are used. The difference is that bonding wires are connected to each other. Hereinafter, description of the same points as those of the semiconductor device 10 is omitted, and only different points will be described.

  In the cross-sectional view of the semiconductor chip shown in FIG. 10B, the surface of the substrate 101 is disposed on the upper side, and the back surface of the substrate 101 is disposed on the lower side. Regarding the stacking relationship of the layers on the surface of the substrate 101, the stacking in the upper direction in FIG. 1 is expressed as being stacked on the lower layer. In addition, regarding the stacking relationship of the layers on the back surface of the substrate 101, the stack in the lower direction in FIG. 1 is expressed as being stacked on the lower layer.

  A source electrode pad 152 connected to the source electrode 107, a drain electrode pad 154 connected to the drain electrode 108, and a gate electrode pad 153 connected to the gate electrode 109 are provided on the insulating layer 111, respectively. ing. For example, gold bonding wires 155, 157 and 156 are bonded to each pad.

  The bonding wire 155 bonded to the source electrode 107 is bonded to the grounding conductor layer 162 on the inner surface of the packaging substrate 160 and is electrically connected to the packaging substrate back surface electrode 123 functioning as a ground via the through hole 122. Connected to.

  The bonding wire 156 bonded to the gate electrode 109 is bonded to the packaging substrate upper electrode 158 and is electrically connected to the packaging substrate back electrode 123 functioning as a gate terminal through the through hole 122. .

  The bonding wire 157 bonded to the drain electrode 108 is bonded to the packaging substrate upper electrode 159 and is electrically connected to the packaging substrate rear surface electrode 123 functioning as a drain terminal through the through hole 122. .

  With the above configuration, the semiconductor device 40 functions as a high-power field effect transistor. For example, when the voltage applied to the gate electrode 109 is increased in the positive direction at a threshold voltage or higher, the drain current flowing through the channel layer 103 increases.

Note that the buffer layer 102 includes a conductive layer 105 at an interface with the substrate 101. This is a low resistance layer generated at the interface due to lattice mismatch between the substrate 101 made of Si and the buffer layer 102 made of Al _y Ga _1-y N. The low resistance layer affects the drain current flowing through the channel layer 103 and attenuates the drain current that is a high-frequency output. In order to suppress the attenuation of the high-frequency output, a method of changing the low resistance layer to an insulating layer by applying a DC bias voltage to the substrate and controlling the charge distribution at the interface is employed.

  Hereinafter, the configuration and function for improving the high-frequency output performance by the main components of the HFET described above will be described.

  The substrate 101, the buffer layer 102, the channel layer 103, the Schottky layer 104, the insulating layers 106 and 111, and the electrodes, which are the main components of the HFET described above, constitute a semiconductor die.

  The back electrode 113 is, for example, a laminated body of titanium (Ti) and gold (Au) or a laminated body of chromium (Cr) and gold (Au) on the back surface of the semiconductor die, that is, the back surface of the substrate 101. It is the 1st conductor layer currently formed as. In the semiconductor die and the back electrode 113, at least one outer periphery in the direction of the laminated surface is longer than the outer periphery of the recess 167 of the packaging substrate 160 in the same direction as the outer periphery. As a result, the semiconductor die and back electrode 113 are not inserted into the recess 167 region of the packaging substrate 160.

  The high dielectric constant film 114 is a dielectric layer formed on the back electrode 113 and on the side opposite to the substrate 101, and is formed so as to be accommodated in the recess 167 of the packaging substrate 160. For example, a material such as barium / strontium / titanium compound (BST) or strontium / titanium / oxide (STO) is applied to the high dielectric constant film 114. These are formed by a spin coat method or the like. In order to realize the positional relationship between the recess 167 of the packaging substrate 160 and the back electrode 113 and the high dielectric constant film 114 described above, the high dielectric constant film 114 is formed on the entire surface of the back electrode 113 and then the high dielectric constant. The rate film 114 may be patterned. Further, the high dielectric constant film 114 may be formed by a lift-off method so as to have a desired shape.

  The ground conductor layer 115 is a conductor layer formed on the high dielectric constant film 114 on the side opposite to the back electrode 113. Here, the ground conductor layer 115 and the back electrode 113 are not in contact with each other and are insulated. The ground conductor layer 115 is made of, for example, titanium (Ti) and gold (Au).

  The sandwich structure of the back electrode 113, the high dielectric constant film 114, and the ground conductor layer 115 forms a metal-insulator-metal (MIM) type capacitor structure. This capacitor structure is formed directly on the back surface of the substrate 101 and functions as a bypass capacitor for applying a substrate bias voltage.

  Next, the packaging structure and function of the semiconductor die and the bypass capacitor will be described. The semiconductor device 40 includes a packaging lid 116 and a packaging substrate 160 as components of the packaging structure.

  The packaging lid 116 is made of, for example, ceramic or insulating resin, and includes a bottom plate and side walls.

  The packaging substrate 160 is a lid made of, for example, a ceramic, insulating resin, a lead frame made of a metal material, or the like. A recess 167 is formed on a part of the inner surface of the packaging substrate 160. The recess 167 is formed in accordance with the pattern of the high dielectric constant film 114 and the ground conductor layer 115 constituting the bypass capacitor.

  The ground conductor layer 162 is a second conductor layer formed on the inner surface of the packaging substrate 160 and in an inner region of the recess 167 and a partial outer region of the recess 167. Here, the ground conductor layer 162 is bonded to the ground conductor layer 115 in the recess 167 and is not in contact with the back electrode 113 and is insulated. The ground conductor layer 162 is made of, for example, titanium (Ti) and gold (Au). The ground conductor layer 162 is subjected to desired patterning for electrical connection with the packaging substrate 160.

  The ground conductor layer 115 may not be formed, and the ground conductor layer 162 may be directly bonded to the high dielectric constant film 114. In this case, the MIM type capacitor formed immediately below the substrate 101 is formed by a sandwich structure of the back electrode 113, the high dielectric constant film 114, and the ground conductor layer 162.

  The bias electrode 161 is a third conductor layer formed on the inner surface of the packaging substrate 160 and in a part of the outer region of the recess 167, and is a wiring for applying a DC bias voltage to the back surface of the substrate 101. Function as. Furthermore, the bias electrode 161 is insulated from the ground conductor layer 162 and is electrically connected by being joined outside the region of the back electrode 113 and the recess 167. For example, in the layout illustrated in FIG. 10B, the bias electrode 161 and the ground conductor layer 162 are formed so as not to intersect on the inner surface of the packaging substrate 160.

  The bias electrode 161 is subjected to desired patterning for electrical connection with the packaging substrate 160.

  Note that the bias electrode 161 illustrated in FIG. 10B is formed on both the left and right sides of the semiconductor die, that is, at a plurality of locations, but only one of them may be formed.

  An external terminal as a package is realized by forming a through hole 122 in the packaging substrate 160 and forming a packaging substrate back surface electrode 123 on the outer surface of the packaging substrate 160.

  Note that when the packaging lid 116 and the packaging substrate 160 are heat bonded, the bias electrode 161 and the back electrode 113 of the semiconductor die may be bonded.

  The above structure has a bias application structure in which a semiconductor die is mounted by wire bonding and a bypass capacitor is provided between the back surface of the substrate 101 and the recess of the packaging substrate 160. According to this structure, the mounting area can be reduced and the cost can be reduced by reducing the number of parts compared to the case where the bypass capacitor is mounted and used externally.

  The packaging lid 116 may be formed using a semiconductor as a base material. As a result, the wafer-like packaging substrate 160 on which the semiconductor die having the bypass capacitor is mounted and the wafer made of semiconductor and packaged are bonded at the wafer level. Thereafter, dicing is cut into individual packages according to the dicing lane. According to this method, since there are many processes at the wafer level and few processes at the individual piece level, it is possible to realize a mass production process that is simplified and reduced in cost.

  With the above structure, even if parasitic inductance exists in the wiring for applying the substrate bias voltage, an unnecessary high frequency component is eliminated immediately under the substrate by the bypass capacitor formed immediately below the substrate. Therefore, it becomes possible to improve the linearity of the high frequency output and the output power.

  As described above, the semiconductor device of the present invention has been described based on the embodiment, but the semiconductor device according to the present invention is not limited to the above embodiment. In the range which does not deviate from the main point of this invention with respect to another embodiment implement | achieved combining the arbitrary components in Embodiment 1-4 and its modification, Embodiment 1-4, and its modification. Modifications obtained by making various modifications conceivable by those skilled in the art and various apparatuses incorporating the semiconductor device according to the present invention are also included in the present invention.

  For example, the semiconductor devices 20, 30 and 40 according to the second to fourth embodiments may be applied to the semiconductor device showing the first modification according to the first embodiment. That is, the first-stage high-frequency amplifier 144, the last-stage power amplifier 145, and the low-noise amplifier 148 illustrated in FIG. 6A include any one of the semiconductor devices 20 to 40 in the first embodiment according to the first embodiment. The same effects as those of the semiconductor device according to the modified example are obtained.

  In the semiconductor device 40 according to the fourth embodiment, the recess 167 may not be formed on the inner surface of the packaging substrate 160. In this case, by adjusting the film thickness of the bias electrode 161 formed on the bottom surface of the packaging substrate 160 and the total film thickness of the high dielectric constant film 114 and the ground conductor layers 115 and 162 to the same extent, It is possible to have a function similar to that of the semiconductor device. Here, the back electrode 113 and the bias electrode 161 are electrically connected, and the bias electrode 161 and the ground conductor layers 115 and 162 are electrically insulated.

  The present invention is useful when mounting a group III-V nitride semiconductor, and is particularly suitable for use in a GaN-based power device that requires small size, low cost, and high performance.

FIG. 3A is a top perspective view showing the structure of the semiconductor device according to the first embodiment of the present invention. FIG. 2B is a structural cross-sectional view taken along the line A-A ′ in FIG. FIG. 2 is a structural cross-sectional view taken along line B-B ′ of FIG. FIG. 2 is a structural cross-sectional view taken along the line C-C ′ of FIG. (A) is a top view which shows the structure of the multi-finger type transistor chip which the semiconductor device of this invention has. (B) is a top view showing a configuration of a T-shaped gate lead-out type transistor chip included in the semiconductor device of the present invention. (A) is an equivalent circuit diagram of the semiconductor device of this invention. (B) is an equivalent circuit diagram of a conventional semiconductor device. (A) is a functional block diagram of the semiconductor device which shows the 1st modification based on Embodiment 1 of this invention. (B) is a circuit block diagram of an electric power monitor part. It is a structure sectional view of the semiconductor device concerning Embodiment 2 of the present invention. (A) is a top view which shows the structure of the multi-finger type transistor chip which the semiconductor device which concerns on Embodiment 2 of this invention has. (B) is a top view which shows the structure of the T-shaped gate drawer type transistor chip which the semiconductor device which concerns on Embodiment 2 of this invention has. It is a structure sectional view of a semiconductor device concerning Embodiment 3 of the present invention. (A) is sectional drawing cut | disconnected along the B-B 'line | wire of FIG.10 (b). (B) is a top perspective view showing the structure of the semiconductor device according to the fourth embodiment of the present invention. It is a structural sectional view of a semiconductor device having a conventional via hole (substrate through hole) structure. It is a graph which shows substrate bias voltage dependence, such as saturation output electric power, about the conventional semiconductor device.

10, 20, 30, 40 Semiconductor device 101 Substrate 102 Buffer layer 103 Channel layer 104 Schottky layer 105 Conductive layer 106, 111, 131 Insulating layer 107 Source electrode 108 Drain electrode 109 Gate electrode 110 Bump 113 Back electrode 114 High dielectric constant film 115, 118, 132, 162 Grounding conductor layer 116 Packaging lid 117, 167 Recess 119, 161 Bias electrode 120 Packaging substrate 121 Packaging substrate upper electrode 122 Through hole 123 Packaging substrate back electrode 124 Switch 127 Gate Pad 128 Source pad 129 Drain pad 130 Through-hole 133 Passive element circuit 134 RF unit 135 IF signal processing unit 137 Antenna 139 Front end unit 140 Transmitting unit 141 Reception Unit 142 Power Monitor Unit 143 Feedback Control Unit 144 Previous Stage High Frequency Amplifier 145 Final Stage Power Amplifier 146 Directional Coupler 147 Detector Diode 148 Low Noise Amplifier 149 Baseband Unit 150 CPU Memory Unit 151 Power Supply Unit 152 Source Electrode Pad 153 Gate Electrode pad 154 Drain electrode pad 155, 156, 157 Bonding wire 158, 159 Packaging substrate electrode 160 Packaging substrate

Claims (8)

A semiconductor device having a transistor element that operates at a high frequency,
A substrate,
The transistor element formed on the surface of the substrate;
A first conductor layer for grounding formed on the back surface of the substrate;
A dielectric layer formed on the first conductor layer;
A semiconductor device comprising: a second conductor layer formed on the dielectric layer and insulated from the first conductor layer. The substrate is a silicon substrate;
The semiconductor device according to claim 1, wherein the transistor element is made of a group III-V nitride semiconductor. further,
A lid for packaging the transistor element;
The semiconductor device according to claim 1, wherein an inner surface of the lid is bonded on the second conductor layer. The lid is
A third conductor layer formed on the inner surface and insulated from the second conductor layer;
The semiconductor device according to claim 3, wherein the first conductor layer is connected to be electrically connected to the third conductor layer. The second conductor layer is disposed at least in a recess formed on the inner surface of the lid,
The third conductor layer is disposed on a part of the inner surface other than the recess;
The first conductor layer has at least one outer periphery in the plane direction longer than the outer periphery of the recess in the same direction as the outer periphery,
The semiconductor device according to claim 4, wherein the dielectric layer has an outer periphery in the plane direction that is shorter than an outer periphery of the recess in the same direction as the outer periphery. The lid has a side wall surrounding a semiconductor die composed of the substrate and the transistor element,
The second conductor layer and the third conductor layer are formed up to the inner surface of the side wall and a part of the edge, respectively.
The semiconductor device further includes:
A packaging substrate that covers the semiconductor die together with the lid by contacting the edge of the lid,
The packaging substrate is provided with conductor layer electrodes that match the pattern positions of the second conductor layer and the third conductor layer formed on the edge of the lid, and the transistor element. A semiconductor layer electrode is formed in accordance with the pattern position of a plurality of electrodes having,
The semiconductor device according to claim 4, wherein the semiconductor layer electrode is connected to the plurality of electrodes by bumps. The semiconductor device according to claim 1, wherein the lid is formed using a semiconductor as a base material. A ground potential is applied to the second conductor layer,
A substrate bias potential is applied to the third conductor layer,
The semiconductor device further includes:
A bias potential application circuit for applying the substrate bias potential;
A detection circuit for detecting high-frequency power output from the transistor element;
The semiconductor device according to claim 4, further comprising: a bias potential adjustment circuit that adjusts the substrate bias potential based on an output signal from the detection circuit.

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