JP2010212524A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device in which resin sealing is carried out for a chip size package and the high-frequency characteristic of an integrated circuit is hardly deteriorated. <P>SOLUTION: The semiconductor device is equipped with a substrate 101, an integrated circuit 105 which is formed on an element forming surface of the substrate 101 and contains an active element, rear face wiring 108 which is formed at an opposite side of the element forming surface of the substrate 101, a penetration via 106 which penetrates the substrate 101 and electrically connects the integrated circuit 105 and the rear face wiring 108, a film 109 which covers the integrated circuit 105 so as to form a hollow region 114 above the integrated circuit 105, and sealing resin 110 formed on the film 109. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device used for high frequency applications and a manufacturing method thereof.

  In recent years, semiconductor chips have been miniaturized and integrated, and research and development of a chip size package (CSP) having a chip size package (CSP) that is equivalent to the chip size or the chip itself is a package (for example, patents). See reference 1.)

  CSP is a very inexpensive packaging method that can reduce the assembly cost of a semiconductor chip package and greatly reduce the number of components. For example, after forming an insulating film, a rewiring, a sealing resin film, and a forming post on a wafer, a bump (solder ball) is bonded to the forming post, and the wafer is diced into chips to form a CSP. realizable. In particular, wafer level packaging, which can be packaged in a wafer state, is the ultimate packaging method.

  The CSP is assumed to be mounted on a mounting board such as a printed board by flip chip mounting. In the case of flip chip mounting, the connection distance between the chip and the mounting substrate is very short. For this reason, in high-frequency chips where the chip characteristics greatly affect the terminal connection state, indeterminate wire connection can be avoided and terminal connection loss can be minimized. This is an effective implementation method.

  A chip for flip chip mounting generally has a coplanar wiring structure in which signal wiring and ground are formed on the same plane. However, the coplanar wiring requires a large ground area on the chip surface, which is not preferable from the viewpoint of chip area utilization. On the other hand, a semiconductor chip having a microstrip line structure in which a ground is formed on the back surface of the chip can greatly improve the chip area utilization rate. However, when flip chip mounting is performed, the distance between the ground of the mounting substrate and the ground surface of the semiconductor chip becomes long. For this reason, since the ground is likely to be in a floating state and becomes unstable, the high frequency characteristics are extremely deteriorated.

  In order to improve high frequency characteristics in a semiconductor chip having a microstrip line structure, a chip structure in which a circuit terminal is output to the back surface of a chip using a through via penetrating the chip has been proposed (see, for example, Patent Document 2). .) In addition, a method has been proposed in which the sealing resin layer is made into two layers and a sealing resin having a low dielectric constant is used for embedding the high-frequency circuit to prevent deterioration of the high-frequency characteristics (see, for example, Patent Document 3). .

On the other hand, gallium nitride (GaN), aluminum nitride (AlN) and indium nitride (InN) and the general formula is (In _x Al _1-x ) _y Ga _1-y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) Nitride semiconductors, which are mixed crystals represented by the above, are not only applied to optical elements utilizing their wide band gap and direct transition type band structure, which are their physical characteristics, but also have a high breakdown electric field and saturated electron velocity. Applications to electronic devices using the features are also being studied. In particular, a heterojunction field effect transistor (Heterojunction) using a two-dimensional electron gas (2DEG) appearing at the interface between Al _x Ga _1-x N and GaN epitaxially grown on a semi-insulating substrate. Field Effect Transistor (hereinafter abbreviated as HFET) is being developed as a high-power high-frequency device. Monolithic microwave integrated circuit in which HFET is integrated with matching circuit and bias circuit formed on sapphire substrate using microstrip line to use HFET using nitride semiconductor as a device for high frequency applications such as high-speed communication. MMIC) is disclosed (for example, see Non-Patent Document 1).
JP 9-64236 A JP 2002-9193 A JP-A-6-29430 2008 IEEE MTT-S Int. Microwave Symp, Dig. P.1293-1296

  However, in the conventional technique, it is necessary to seal an integrated circuit that operates at a high frequency with a resin. For this reason, for example, the peripheral portion of the gate electrode of the field effect transistor, which is an active element constituting the integrated circuit, is filled with resin, and the parasitic capacitance increases in the gate electrode and the peripheral portion thereof. Due to the increase in parasitic capacitance, the high frequency characteristics of the field effect transistor are deteriorated, and the input / output impedance fluctuates. In addition, even in a transmission line that connects elements in an integrated circuit, the signal line and its periphery are covered with resin, so that transmission loss may increase.

  An object of the present invention is to realize a resin-encapsulated semiconductor device as a chip size package without deteriorating the high-frequency characteristics of an integrated circuit.

  In order to achieve the above object, according to the present invention, a semiconductor device is provided with a film for forming a cavity between an integrated circuit and a sealing resin.

  Specifically, a semiconductor device according to the present invention includes a substrate, an integrated circuit formed on an element formation surface of the substrate and including an active element, a backside wiring formed on a surface opposite to the element formation surface of the substrate, A through via that penetrates the substrate and electrically connects the integrated circuit and the backside wiring, a film that covers the integrated circuit so as to form a hollow region on the integrated circuit, and a sealing resin that is formed on the film It is characterized by having.

  The semiconductor device of the present invention includes a film covering the integrated circuit so as to form a hollow region on the integrated circuit. For this reason, an interval can be provided between the sealing resin and the integrated circuit, and an increase in parasitic capacitance due to the sealing resin can be suppressed. Therefore, it is possible to realize a semiconductor device in which high-frequency characteristics are hardly deteriorated by the sealing resin. In addition, a back surface wiring electrically connected to the integrated circuit through the through via is provided. For this reason, in the case of the microstrip line structure, there is an advantage that the ground of the chip and the ground of the mounting substrate can be brought close to each other.

  In the semiconductor device of the present invention, the active element is a field effect transistor having a gate electrode, and a hollow region may be formed between the gate electrode and the film.

  In the semiconductor device of the present invention, the integrated circuit may include a wiring, and at least a part of the wiring may be higher than the gate electrode.

  The semiconductor device of the present invention may further include a support column that is formed on the element formation surface of the substrate and supports the film. In addition, a frame body that surrounds the integrated circuit and supports the film may be further provided on the element formation surface of the substrate.

  In the semiconductor device of the present invention, the hollow region may be filled with an inert gas or nitrogen.

  In the semiconductor device of the present invention, the active element may be formed of a group III nitride semiconductor.

  In the semiconductor device of the present invention, the substrate may be sapphire, silicon carbide, silicon, aluminum nitride, gallium nitride, or a laminate including two or more thereof.

  In the semiconductor device of the present invention, the film may be a resin film having a base material and an adhesive layer formed on one surface of the base material.

  In the semiconductor device of the present invention, the sealing resin may be conductive.

  The semiconductor device of the present invention may further include a metal film formed between the sealing resin and the film or a metal film formed on the sealing resin.

  In the semiconductor device of the present invention, the operating frequency band of the integrated circuit may be a quasi-millimeter wave band or higher.

  The method of manufacturing a semiconductor device according to the present invention includes a step (a) of forming an integrated circuit on a main surface of a substrate, a step (b) of forming a via hole in the substrate, and a surface on the opposite side to the entire model surface of the substrate. A step (c) of forming a back surface wiring electrically connected to the integrated circuit through a via hole; a step (d) of covering the integrated circuit with a film so as to form a hollow region on the integrated circuit; A step (e) of forming a sealing resin on the substrate and a step (f) of dividing the substrate into chips after the step (e).

  The method for manufacturing a semiconductor device of the present invention includes a step of covering the integrated circuit with a film so as to form a hollow region on the integrated circuit, and forming a sealing resin on the film. For this reason, a space | interval can be provided between sealing resin and an integrated circuit. Therefore, it is possible to realize a semiconductor device in which high-frequency characteristics are hardly deteriorated by the sealing resin. Further, after forming the sealing resin, the substrate is divided into chips. For this reason, the man-hour concerning packaging can be reduced significantly.

  The semiconductor device according to the present invention can realize a semiconductor device that is resin-sealed as a chip size package and has little deterioration in high-frequency characteristics of an integrated circuit.

(One embodiment)
FIG. 1 shows a cross-sectional structure of a semiconductor device according to an embodiment. The semiconductor device of this embodiment has an integrated circuit including active elements and wirings formed on an element formation surface of a substrate, a through via that penetrates the substrate, and a back electrode that is connected to the integrated circuit by the through via. is doing. Specifically, it includes a sapphire substrate 101 and an integrated circuit 105 including a heterojunction field effect transistor (HFET) 103 and a wiring 104 which are active elements formed on an element formation surface of the sapphire substrate 101. The integrated circuit 105 of this embodiment is an integrated circuit for high frequency applications, and the wiring 104 includes a transmission line. On the sapphire substrate 101, a semiconductor layer 102 is formed by epitaxially growing a GaN layer, an AlGaN layer, or the like. The HFET 103 has a gate electrode 103A using, for example, a conductive layer generated at the interface between the GaN layer and the AlGaN layer as a current path (channel). An interlayer insulating film 107 is formed to cover the upper surface of the semiconductor layer 102 and the gate electrode 103A. Note that the upper portion of the gate electrode 103A does not need to be covered with the interlayer insulating film 107.

  A back surface wiring 108 is formed on the surface (back surface) opposite to the element formation surface of the sapphire substrate 101. The back surface wiring 108 includes a back surface signal wiring 108A, a back surface ground wiring 108B, and the like. The back wiring 108 and the wiring 104 are electrically connected by a through via 106 that penetrates the sapphire substrate 101. A microstrip line may be formed by at least a part of the wiring 104 and the back surface wiring 108.

  The semiconductor device 100 is mounted on the mounting substrate 200, and the back surface wiring 108 is connected to the mounting substrate wiring 202. The mounting board wiring 202 includes a signal wiring 202A, a ground wiring 202B, and the like, and the back surface ground wiring 108B is connected to the ground wiring 202B.

  A film 109 is formed on the element formation surface of the sapphire substrate 101 so as to cover the integrated circuit 105. By forming the gate electrode 103 </ b> A to be lower than the wiring 104, the film 109 can be supported by the wiring 104. Therefore, a hollow region 114 is formed between the integrated circuit 105 and the film 109 in the vicinity of the gate electrode 103A. A sealing resin 110 is formed on the film 109, and the semiconductor device 100 is resin-sealed.

  If the element formation surface on which the integrated circuit is formed is directly sealed with a sealing resin, the integrated circuit and the sealing resin come into contact with each other, and the parasitic capacitance of the integrated circuit increases. However, in the semiconductor device 100 of this embodiment, the sealing resin 110 is formed on the film 109 that covers the integrated circuit 105. In addition, a hollow region 114 is formed between the film 109 and the integrated circuit 105. For this reason, an increase in parasitic capacitance can be suppressed, and deterioration in high-frequency characteristics can be suppressed. In particular, when the gate electrode 103A and the sealing resin 110 are close to each other, the parasitic capacitance is remarkably increased. For this reason, the hollow region 114 is preferably formed in the region where the gate electrode 103A is formed. In order to obtain such a structure, it is preferable that the thickness of the wiring 104 be larger than the height of the gate electrode 103A. In this way, the film 109 is supported by the wiring 104 in the vicinity of the gate electrode 103A, and the hollow region 114 can be formed.

  Below, the manufacturing method of the semiconductor device of this embodiment is demonstrated. FIG. 2 shows the manufacturing process of the semiconductor device of this embodiment in the order of steps. First, as shown in FIG. 2A, a GaN layer, an AlGaN layer, and the like are epitaxially grown on the sapphire substrate 101 by a metal organic chemical vapor deposition (MO-CVD) method or the like. Thereby, the semiconductor layer 102 having a heterojunction of AlGaN and GaN is formed. Subsequently, an HFET 103 having a gate electrode 103A, a wiring 104 including a transmission line, and the like are formed on the semiconductor layer 102. Thereby, the integrated circuit 105 is formed. Further, the back surface wiring 108 is formed on the back surface of the sapphire substrate 101, and the through via 106 that connects the wiring 104 and the back surface wiring 108 is formed.

  Next, as shown in FIG. 2B, the integrated circuit 105 is covered with a film 109. The film 109 may be a resin film having a polyolefin base material and an adhesive layer, for example. The thickness of the film 109 may be about 1 μm to 100 μm. The adhesive layer may be rubber, acrylic, silicon or urethane. The adhesive layer may be a resin such as an epoxy resin that can be bonded by applying ultraviolet rays or heat.

  The step of covering the integrated circuit 105 with the film 109 may be performed in a gas atmosphere that is chemically inert and does not contain moisture, such as nitrogen or helium, argon, or neon. In this way, since the hollow region 114 is filled with nitrogen gas or the like, it is possible to suppress deterioration due to oxidation or the like of the semiconductor and electrode material included in the integrated circuit 105. In addition, the film 109 and the interlayer insulating film 107 are preferably in close contact with each other outside the region where the integrated circuit 105 is formed. Therefore, the adhesion between the film 109 and the interlayer insulating film 107 may be improved by applying pressure, heat, ultraviolet light, or a combination thereof to the film 109 outside the region where the integrated circuit 105 is formed. Note that depending on the type of the semiconductor device, the film 109 may be in close contact with the semiconductor layer 102 or the film 109 may be in direct contact with the substrate 101. Alternatively, the film 109 may be a film that is cured by ultraviolet rays or heat. In this case, if the film 109 is cured by ultraviolet irradiation or heat treatment after the integrated circuit 105 is coated, the film 109 is hardly deformed when the sealing resin 110 is formed in a later step.

  Next, as shown in FIG. 2C, a sealing resin 110 is filled on the film 109, and dicing is performed to divide each chip.

  The semiconductor device according to the present embodiment does not require a lid or the like that matches the dimensions of the integrated circuit and does not require alignment in the sealing operation, so that packaging can be performed easily and at low cost. Can do.

(Modification of one embodiment)
FIG. 3 shows a cross-sectional structure of a semiconductor device according to a modification of the embodiment. In FIG. 3, the same components as those in FIG. The semiconductor device 100A of this modification has a configuration in which a support column 301 that supports the film 109 is added to the semiconductor device 100 of one embodiment. The height of the column 301 is preferably higher than that of the wiring 104. For example, a metal that can be formed by plating such as Au or Cu may be used.

  By forming the pillars 301 higher than the wiring 104, not only the distance between the gate electrode of the HFET 103 and the sealing resin 110, which is the main part that determines the high-frequency characteristics of the active element, but also the wiring 104 that is a transmission line and the sealing The distance from the resin 110 can be increased. For this reason, not only can the deterioration of the high frequency characteristics of the active element be suppressed, but also the high frequency loss of the transmission line can be reduced.

  FIG. 4 shows a result obtained by simulation of the relationship between the distance between the sealing resin 110 and the integrated circuit 105 and the insertion loss of the transmission line. The length of the transmission line was 6 mm, and the frequencies were 30 GHz and 60 GHz. As shown in FIG. 4, the insertion loss greatly decreased until the distance between the sealing resin and the transmission line was about 30 μm, and became substantially constant thereafter. From this, it can be seen that in order to reduce the loss due to the sealing resin, it is preferable to set the height of the column 301 to 30 μm or more. Moreover, the effect of reducing the insertion loss by widening the interval between the sealing resin and the transmission line increases as the frequency increases.

  The support column 301 only needs to ensure the hollow region 114 between the film 109 and the integrated circuit 105. Therefore, it may be arranged in a region where the integrated circuit 105 is formed as shown in FIG. 5A, or may be a frame 302 surrounding the integrated circuit 105 as shown in FIG. Further, a plurality of support columns may be formed so as to surround the integrated circuit 105 instead of a continuous frame. You may combine the support | pillar arrange | positioned in the area | region in which the integrated circuit 105 was formed, the frame surrounding the periphery of the integrated circuit 105, etc. FIG.

  In one embodiment and its modification, the sealing resin 110 may be insulative or conductive. By making the sealing resin 110 conductive, an effect of absorbing unnecessary electromagnetic radiation from the integrated circuit 105 and preventing malfunction of the integrated circuit 105 can be obtained. In order to impart conductivity to the sealing resin 110, the conductivity may be imparted by, for example, dispersing conductive filler or the like in the sealing resin 110. In addition, instead of making the sealing resin 110 conductive, unnecessary electromagnetic radiation from the integrated circuit 105 is formed by a method of forming a metal film between the film 109 and the sealing resin 110 or on the sealing resin 110. May be absorbed.

  The film 109 may be any film as long as the hollow region 114 can be secured when the sealing resin 110 is formed without affecting the operation of the integrated circuit 105. For example, not only those based on polyolefin but also those based on plastic materials such as polyethylene terephthalate (PET) resin may be used.

  Although the substrate is sapphire, it is not limited to this, and may be a substrate made of sapphire, silicon carbide, silicon, aluminum nitride, or gallium nitride. Moreover, the laminated substrate which laminated | stacked two or more of these may be sufficient.

  Although an example in which the active element of the integrated circuit is a nitride-based HFET has been shown, an integrated circuit having an element made of a GaAs-based or Si-based material may be used. Also, a semiconductor element other than HFET may be used. The integrated circuit 105 is particularly effective when the operating frequency band is an integrated circuit having a quasi-millimeter wave band or higher.

  The semiconductor device according to the present invention can realize a semiconductor device that is resin-sealed as a chip size package and has little deterioration in high-frequency characteristics of an integrated circuit, and is very effective as a semiconductor device used for a high-power and high-frequency wireless communication device. is there.

It is sectional drawing which shows the semiconductor device which concerns on one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention to process order. It is sectional drawing which shows the semiconductor device which concerns on the modification of one Embodiment of this invention. It is a graph showing the result of having calculated | required the relationship between the space | interval of sealing resin and a transmission line, and the insertion loss of a transmission line by the electromagnetic field simulation. (A) And (b) is a top view which shows the semiconductor device which concerns on the modification of one Embodiment of this invention.

DESCRIPTION OF SYMBOLS 100 Semiconductor device 100A Semiconductor device 101 Sapphire substrate 102 Semiconductor layer 103 Heterojunction field effect transistor 103A Gate electrode 104 Wiring 105 Integrated circuit 106 Through-via 107 Interlayer insulating film 108 Back surface wiring 108A Back surface signal wiring 108B Back surface ground wiring 109 Film 110 Sealing resin 114 Hollow region 200 Mounting substrate 202 Mounting substrate wiring 202A Signal wiring 202B Ground wiring 301 Support column 302 Frame body

Claims (13)

A substrate,
An integrated circuit formed on an element forming surface of the substrate and including an active element;
A backside wiring formed on a surface opposite to the element forming surface of the substrate;
A through via that penetrates the substrate and electrically connects the integrated circuit and the backside wiring;
A film covering the integrated circuit to form a hollow region on the integrated circuit;
And a sealing resin formed on the film. The active element is a field effect transistor having a gate electrode;
The semiconductor device according to claim 1, wherein the hollow region is formed between the gate electrode and the film. The integrated circuit has wiring;
The semiconductor device according to claim 2, wherein at least a part of the wiring is higher than the gate electrode.   The semiconductor device according to claim 1, further comprising a support column formed on an element formation surface of the substrate and supporting the film.   5. The semiconductor device according to claim 1, further comprising a frame body that is formed on an element formation surface of the substrate so as to surround the integrated circuit and supports the film.   The semiconductor device according to claim 1, wherein the hollow region is filled with an inert gas or nitrogen.   The semiconductor device according to claim 1, wherein the active element is formed of a group III nitride semiconductor.   The said board | substrate is a laminated body which consists of sapphire, silicon carbide, silicon, aluminum nitride, or gallium nitride, or consists of two or more thereof. Semiconductor device.   The semiconductor device according to claim 1, wherein the film is a resin film having a base material and an adhesive layer formed on one surface of the base material.   The semiconductor device according to claim 1, wherein the sealing resin is conductive.   The metal film formed between the sealing resin and the film or the metal film formed on the sealing resin is further provided. The semiconductor device described.   The semiconductor device according to claim 1, wherein the integrated circuit has an operating frequency band equal to or higher than a quasi-millimeter wave band. Forming an integrated circuit on the element forming surface of the substrate;
Forming a via hole in the substrate (b);
Forming a back surface wiring electrically connected to the integrated circuit via the via hole on the surface opposite to the element forming surface of the substrate;
Covering the integrated circuit with a film (d);
Forming a sealing resin on the film (e);
A method of manufacturing a semiconductor device, comprising a step (f) of dividing the substrate into chips after the step (e).

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