JP5734727B2 - Semiconductor device - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor device.

  Conventionally, a resin sealing type and an airtight sealing type are known as packaging of a semiconductor element. The resin-encapsulated type has a structure in which the semiconductor element mounted on the lead frame is directly embedded in the resin by transfer molding, etc., and is advantageous for low cost, suitable for mass production, and miniaturization. Widely adopted. The hermetic sealing type has a structure in which a semiconductor element mounted on a base made of an insulator such as ceramic is hollow and hermetically held. The cost is higher than that of a resin-sealed semiconductor device, but the hermeticity is excellent. Therefore, it is adopted when high reliability is required. In the hermetically sealed package, an example is known in which a semiconductor element is directly mounted on a heat radiator made of metal, and the input / output terminal portion has a convex feedthrough structure.

  Systems have emerged in which the difference between two frequencies input to an amplifier is several hundred MHz. An example of such a system is SNG (Satellite News Gathering). SNG is a broadcasting program material collection system such as television news using an artificial satellite (communication satellite). In SNG, the difference frequency between the video frequency and the audio frequency is several hundred MHz. Another example of the system is MIMO (Multiple Input Multiple Output). MIMO is a wireless communication technology that combines a plurality of antennas, transmits and receives different data at the same time, and combines them at the time of reception to broaden the bandwidth in a pseudo manner. For example, a communication performance of 108 Mbps is obtained, and it is applied to speeding up of a wireless local area network (LAN).

JP 2000-183222 A

http://www.excelics.com/MFET%20APP%20NOTE.pdf: “Recommendations for the Handling, Mounting and Biasing of High Power GaAs FETs” Steven Sea Clips, “RF Power Amplifiers for Wireless Communications”, 11.3, Bias Supply Modulation Effects, Steven C. Cripps, “RF Power Amplifiers for Wireless Communications”, 11.3 Bias Supply Modulation Effects. ARTECH HOUSE

  When two frequencies are input to one high frequency amplifying element, a difference frequency component is generated. When the difference frequency is several MHz, by connecting a capacitor of 100 μF or more near the RF output terminal, the output terminal voltage and the chip end face voltage are smoothed.

  However, when the differential frequency is several hundred MHz, a capacitor attached near the RF output terminal cannot smooth the voltage at the chip end face because a matching circuit is interposed between the chip end face and the capacitor.

  The problem to be solved by the present embodiment is to provide a semiconductor device in which the voltage at the drain end face of the high-frequency semiconductor chip is smoothed even when the differential frequency Δf is several hundred MHz.

The semiconductor device of this embodiment includes a high-frequency semiconductor chip, an input-side distribution circuit, an output-side distribution circuit, a high-frequency input terminal, a high-frequency output terminal, a smoothing capacitor, and a smoothing capacitor connecting bonding wire. . The input side distribution circuit is arranged on the input side of the high frequency semiconductor chip. The output side distribution circuit is arranged on the output side of the high frequency semiconductor chip. The high frequency input terminal is connected to the input side distribution circuit. The high frequency output terminal is connected to the output side distribution circuit. The smoothing capacitor is disposed in the vicinity of the drain terminal electrode of the high-frequency semiconductor chip. The smoothing capacitor connecting bonding wire connects the drain terminal electrode of the high-frequency semiconductor chip and the smoothing capacitor, and also directly and directly connects to the smoothing capacitor. Here, the high frequency semiconductor chip, the input side distribution circuit, the output side distribution circuit, and the smoothing capacitor are housed in one package. Also, assuming that the smoothing capacitor value is C _BR , the current amplitude value is I _PK , the allowable ripple voltage value is ΔV, and the differential frequency value is Δf, the smoothing capacitor has C _BR = I _PK × It has a value of (1 / 2πΔf) / ΔV or more.

1 is a schematic bird's-eye view configuration of a package mounting a semiconductor device according to a first embodiment, wherein (a) a metal cap, (b) a metal seal ring, (c) a metal wall, (d) a conductor base plate, and an insulating layer. FIG. 2 is a schematic configuration diagram of a strip line disposed on an insulating layer and a feedthrough upper layer portion disposed on the insulating layer. 1 is a schematic plan configuration diagram of a semiconductor device according to a first embodiment. FIG. 2A is a schematic cross-sectional configuration of the semiconductor device according to the first embodiment, and is a schematic cross-sectional structure diagram taken along the line II of FIG. 2, and FIG. 2B is a detailed schematic cross-section of the smoothing capacitor portion. Structural drawing. FIG. 3 is a schematic circuit configuration diagram including an input matching unit, an output matching unit, and a smoothing capacitor of the semiconductor device according to the first embodiment. In the semiconductor device according to the first embodiment, the simulation shows the relationship between the value C _BR ripple voltage ΔV and a bypass capacitor to the value I _PK of current amplitude parameter results. In the semiconductor device according to the first embodiment, the simulation results showing the relationship between the value C _BR ripple voltage ΔV and the bypass capacitor for the difference frequency Δf as a parameter. The typical plane block diagram of the semiconductor device which concerns on 2nd Embodiment. FIG. 8 is a schematic cross-sectional configuration diagram of the semiconductor device according to the second embodiment, which is taken along line II-II in FIG. 7. The typical plane block diagram of the semiconductor device which concerns on 3rd Embodiment. FIG. 10 is a schematic cross-sectional configuration diagram of the semiconductor device according to the third embodiment, which is taken along line III-III in FIG. 9. FIG. 9 is a schematic circuit configuration diagram including an input matching unit, an output matching unit, a smoothing capacitor, and an auxiliary smoothing capacitor of a semiconductor device according to a third embodiment. The typical plane block diagram of the semiconductor device which concerns on 4th Embodiment. FIG. 14 is a schematic cross-sectional configuration diagram of the semiconductor device according to the fourth embodiment, which is taken along line IV-IV in FIG. 12. (A) The typical plane block diagram of the semiconductor device which concerns on the comparative example explaining the case where the arrangement space of a smoothing capacitor is narrow, (b) The dimension figure of the arrangement space of a smoothing capacitor. FIG. 10 is a schematic plan configuration diagram of a semiconductor device according to a fifth embodiment. FIG. 15A is a schematic cross-sectional structure diagram taken along the line VV in FIG. 15, and FIG. 15B is a detailed schematic cross-sectional structure diagram of the smoothing capacitor portion. FIG. 16 is a schematic sectional view taken along line VI-VI in FIG. 15. FIG. 10 is a schematic plan configuration diagram of a semiconductor device according to a sixth embodiment. FIG. 19 is a schematic cross-sectional structure diagram taken along line VII-VII in FIG. 18. FIG. 10 is a schematic plan configuration diagram of a semiconductor device according to a seventh embodiment. FIG. 21 is a schematic sectional view taken along line VIII-VIII in FIG. 20. (A) In the semiconductor device according to the embodiment, an enlarged view of a schematic planar pattern configuration of a high-frequency semiconductor chip, (b) an enlarged view of a portion J in FIG. FIG. 23 is a schematic cross-sectional structure diagram taken along the line IX-IX in FIG. 22B, which is a structure example 1 of the high-frequency semiconductor chip applied to the semiconductor device according to the embodiment. FIG. 23 is a schematic cross-sectional structure diagram taken along the line IX-IX in FIG. 22B, which is a structural example 2 of the high-frequency semiconductor chip applied to the semiconductor device according to the embodiment. FIG. 23 is a schematic cross-sectional structure diagram taken along the line IX-IX in FIG. 22B, which is a structural example 3 of the high-frequency semiconductor chip applied to the semiconductor device according to the embodiment. FIG. 23 is a schematic cross-sectional structure diagram taken along line IX-IX in FIG. 22B, which is a fourth example of the structure of the high-frequency semiconductor chip applied to the semiconductor device according to the embodiment.

  Next, embodiments will be described with reference to the drawings. In the following, the same elements are denoted by the same reference numerals to avoid duplication of explanation and to simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The embodiment described below exemplifies an apparatus and a method for embodying the technical idea, and the embodiment does not specify the arrangement of each component as described below. This embodiment can be modified in various ways within the scope of the claims.

(First embodiment)
(Package structure)
As shown in FIGS. 1A to 1D, a package for mounting the semiconductor device 1 according to the embodiment includes a metal cap 10, a metal seal ring 14a, a metal wall 16, and a conductor base plate 200. The feedthrough lower layer portions 20a and 20b arranged on the conductor base plate 200, the input stripline 19a and the output stripline 19b arranged on the feedthrough lower layer portions 20a and 20b, and the feedthrough lower layer portions 20a and 20b The feedthrough upper layer portions 22 and 22 are provided.

  The conductor base plate 200 is made of, for example, a conductive metal such as molybdenum or a copper molybdenum alloy. Furthermore, a plated conductor such as Au, Ni, Ag, Ag—Pt alloy, or Ag—Pd alloy may be formed on the surface of the conductor base plate 200. The conductor base plate 200 may have a laminated structure such as a Cu / Mo / alumina substrate.

  For example, the metal wall 16 is made of a conductive metal such as aluminum, molybdenum, or copper molybdenum alloy.

  A solder metal layer (not shown) for soldering is formed on the upper surface of the metal wall 16 via a metal seal ring 14a. The solder metal layer can be formed from, for example, a gold germanium alloy, a gold tin alloy, or the like.

  The metal wall 16 is disposed on the conductor base plate 200 via an insulating or conductive adhesive. The insulating adhesive can be formed from, for example, an epoxy resin or glass, and the conductive adhesive can be formed from, for example, a gold germanium alloy or a gold-tin alloy. In addition, the metal wall 16 is arrange | positioned on the convex feedthrough upper layer part 22 (refer FIG. 1 and FIG. 3) in a feedthrough part. The convex feedthrough upper layer portion 22 is disposed on the feedthrough lower layer portions 20a and 20b and is formed of an insulating layer.

  As shown in FIG. 1A, the metal cap 10 has a flat plate shape.

  The metal cap 10 is disposed on the metal wall 16 via the metal seal ring 14a.

(Semiconductor device)
As shown in FIGS. 1 to 3, the semiconductor device 1 according to the first embodiment includes a high-frequency semiconductor chip 24, an input-side distribution circuit 17 disposed on the input side of the high-frequency semiconductor chip 24, and a high-frequency semiconductor chip. The output side distribution circuit 18 arranged on the output side of the output 24, the high frequency input terminal 21 a connected to the input side distribution circuit 17, the high frequency output terminal 21 b connected to the output side distribution circuit 18, and the high frequency semiconductor chip 24 And smoothing capacitors 34a and 34b disposed in the vicinity of the drain terminal electrode. Here, the high frequency semiconductor chip 24, the input side distribution circuit 17, the output side distribution circuit 18, and the smoothing capacitors 34a and 34b are housed in one package.

  Further, as shown in FIG. 3B, the smoothing capacitor 34 is disposed on the first capacitor electrode layer 42, the capacitor insulating layer 44 disposed on the first capacitor electrode layer 42, and the capacitor insulating layer 44. The second capacitor electrode layer 40 is provided. Further, the smoothing capacitor 34 is disposed on the conductor base plate 200 as shown in FIG.

  Further, as shown in FIG. 2, the semiconductor device 1 according to the first embodiment has a smoothing capacitor connecting bonding wire that connects between the drain terminal electrode of the high-frequency semiconductor chip 24 and the smoothing capacitors 34a and 34b. 23a and 23b.

Further, as shown in FIG. 2, the smoothing capacitors 34a and 34b are arranged at both ends of the high-frequency semiconductor chip 24, and the smoothing capacitor connecting bonding wires 23a and 23b are drain terminals of the high-frequency semiconductor chip 24 at the operating frequency. It has a length that is sufficiently larger than the impedance in the vicinity of the electrode D. Here, for example, the impedance value in the vicinity of the drain terminal electrode D is about 2.4Ω in the high-frequency semiconductor chip 24 having the current amplitude value I _PK = 10A and the voltage Vds = 24V. On the other hand, for example, the wire lengths of the smoothing capacitor connecting bonding wires 23a and 23b are determined so that the impedance is 10 times or more. For example, when the operating frequency f = 14 GHz, the impedance L of the smoothing capacitor connecting wires 23a and 23b may be 0.03 nH or more because the impedance Z = 2πf · L> 2.4Ω.

  1 to 3, the semiconductor device 1 according to the embodiment is disposed on the input side of the high-frequency semiconductor chip 24 on the conductor base plate 200 and the high-frequency semiconductor chip 24 disposed on the conductor base plate 200. And the output circuit board 28 arranged on the output side of the high-frequency semiconductor chip 24 on the conductor base plate 200.

  The input side distribution circuit 17 is arranged on the input circuit board 26, and the output side distribution circuit 18 is arranged on the output circuit board 28.

  Further, as shown in FIG. 2, an input strip line 19 a connected to the input side distribution circuit 17 and an output strip line 19 b connected to the output side distribution circuit 18 are provided. Here, the high frequency input terminal 21a is connected to the gate terminal electrode G of the high frequency semiconductor chip 24 through the input strip line 19a, and the high frequency output terminal 21b is connected to the drain terminal electrode of the high frequency semiconductor chip 24 through the output strip line 19b. Connected to D.

  Further, as shown in FIG. 2, the semiconductor device 1 according to the first embodiment includes an input circuit board 26 on which the input-side distribution circuit 17 is mounted and an output circuit board 28 on which the output-side distribution circuit 18 is mounted. Prepare.

  Further, as shown in FIG. 2, the semiconductor device 1 according to the first embodiment includes an input matching capacitor substrate 30 and an output circuit substrate 28 arranged between the input circuit substrate 26 and the high-frequency semiconductor chip 24. And an output matching capacitor substrate 32 disposed between the semiconductor chip 24 and the high-frequency semiconductor chip 24.

  2 and 3, the input strip line 19a and the input side distribution circuit 17 are connected by a bonding wire 11, and the input side distribution circuit 17 and the input matching capacitor substrate 30 are not connected. The input matching capacitor substrate 30 and the high frequency semiconductor chip 24 are connected by the bonding wire 12, and the high frequency semiconductor chip 24 and the output matching capacitor substrate 32 are connected by the bonding wire 14. The output matching capacitor substrate 32 and the output side distribution circuit 18 are connected by a bonding wire 19, and the output side distribution circuit 18 and the output strip line 19 b are connected by a bonding wire 15. .

The semiconductor device input matching unit 50 of 1 according to the first embodiment, a schematic circuit configuration including the output matching unit 60, and smoothing capacitor C _B is expressed as shown in FIG.

  As shown in FIG. 4, the input matching unit 50 includes an input side distribution circuit 17 and an input side lumped constant circuit connected between the input side distribution circuit 17 and the gate terminal electrode G of the high frequency semiconductor chip 24. The lumped constant circuit on the input side includes inductances L1a and L1b and a capacitance C1. The output matching unit 60 includes an output side distribution circuit 18 and an output side lumped constant circuit connected between the output side distribution circuit 18 and the drain terminal electrode D of the high frequency semiconductor chip 24. The output side lumped constant circuit includes inductances L2a and L2b and a capacitance C2.

Further, the semiconductor device 1 according to the embodiment, as shown in FIGS. 2 and 4, and the drain terminal electrode D of the high-frequency semiconductor chip 24 via the inductance L _B based on the smoothing capacitor connected bonding wires 23a · 23b bypass reservoir capacitor connected between a ground potential (bypass reservoir capacitor) (hereinafter, referred to as a bypass capacitor or smoothing capacitor) a C _B. Here, assuming that the value of the smoothing capacitor C _B is C _BR , the current amplitude value is I _PK , the allowable ripple voltage value is ΔV, and the difference frequency value is Δf, the value C _BR of the smoothing capacitor C _B is , C _BR = I _PK × (1 / 2πΔf) / ΔV or more.

  In the semiconductor device 1 according to the embodiment, as shown in FIGS. 2 and 4, smoothing capacitors 34 a and 34 b are provided, and the smoothing capacitors 34 a and 34 b and the drain terminal electrode D of the high-frequency semiconductor chip 24 are smoothed. Connection is made through capacitor connecting bonding wires 23a and 23b. As shown in FIG. 3B, the smoothing capacitors 34a and 34b have a single plate parallel plate capacitor structure. In this connection, since the output side distribution circuit 18 is not passed, the voltage of the drain terminal electrode D of the high-frequency semiconductor chip 24 is smoothed even when the difference frequency Δf is several hundred MHz.

In the semiconductor device 1 according to the embodiment, the simulation shows the relationship between the value C _BR ripple voltage ΔV and the bypass capacitor (smoothing capacitor) C _B to a value I _PK of current amplitude parameter results are shown in FIG. 5 It is expressed as follows. FIG. 5 is an example of the difference frequency Δf = 300 MHz.

As shown in FIG. 5, for example, in order to suppress the ripple voltage ΔV to 0.1 V or less, when the difference frequency Δf = 300 MHz and the current amplitude value I _PK = 1.0 A, the bypass capacitor value C _BR = 0 .005 μF or more, difference frequency Δf = 300 MHz, current amplitude value I _PK = 3.0 A, bypass capacitor C _B value C _BR = 0.015 μF or more, difference frequency Δf = 300 MHz, current amplitude value I _PK = At 10.0 A, a value of bypass capacitor value C _BR = 0.05 μF or more is required.

Further, the simulation results showing the relationship between the ripple voltage ΔV and the bypass capacitor (smoothing capacitor) values C _BR of C _B that the difference frequency Δf and parameters is expressed as shown in FIG. FIG. 6 shows an example of the current amplitude value I _PK = 10A.

As shown in FIG. 6, for example, in order to suppress the ripple voltage ΔV to 0.1 V or less, the value C _BR = 0 of the bypass capacitor C _B when the current amplitude value I _PK = 10 A and the difference frequency Δf = 100 MHz. When the current amplitude value I _PK = 10 A · differential frequency Δf = 300 MHz, the bypass capacitor C _B value C _BR = 0.05 μF or more, the current amplitude value I _PK = 10 A · differential frequency Δf = 500 MHz At this time, the value C _BR of the bypass capacitor C _B = 0.03 μF or more is required.

For example, when the difference frequency Δf is 300 MHz, if the current amplitude value I _PK is about 3 A, this charge amount is supplied within a period of 300 MHz, and is necessary to make the ripple voltage ΔV within 0.1 V. The value C _BR of the bypass capacitor C _B can be expressed as C _BR = Q / ΔV. Here, Q = I _PK ∫ (0 to T / 2) sin ωtdt = I _PK ∫ (0 to π / ω) sin ωtdt. Therefore, the value of Q is about 3 × (1 / 2πΔf) = 1.5 × 10 ⁻⁹ (C), and from the ripple voltage ΔV = 0.1 V, C _BR = 0.015 μF.

  According to the first embodiment, it is possible to provide a semiconductor device in which the voltage at the drain end face of the high-frequency semiconductor chip is smoothed even when the differential frequency Δf is several hundred MHz.

(Second Embodiment)
In the semiconductor device 1 according to the second embodiment, the smoothing capacitors 34 ₁ , 34 ₂ , 34 ₃ , 34 ₄ are located near the drain terminal electrode D of the high frequency semiconductor chip 24 as shown in FIGS. Several are arranged. Further, the drain terminal electrode D and the smoothing capacitor 34 _1, 34 _2, 34 _3, 34 for ₄ during connecting a smoothing capacitor connected bonding wires 23 _1, 23 _2, 23 _3, 23 ₄ of high-frequency semiconductor chip 24, The operating frequency has a length that is sufficiently larger than the impedance in the vicinity of the drain terminal electrode D of the high-frequency semiconductor chip 24.

In the semiconductor device 1 according to the second embodiment, the smoothing capacitors 34 ₁ , 34 ₂ , 34 _3, and 34 ₄ are arranged in a plurality of chips because the FET cells of the high-frequency semiconductor chip 24 are evenly charged. It is for supplying. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  According to the second embodiment, there is provided a semiconductor device in which the voltage at the drain end face of the high-frequency semiconductor chip is smoothed even when the differential frequency Δf is several hundred MHz.

(Third embodiment)
As shown in FIGS. 9 to 10, the semiconductor device 1 according to the third embodiment includes an auxiliary smoothing capacitor 36 disposed in parallel with the drain terminal electrode D of the high-frequency semiconductor chip 24. Here, the auxiliary smoothing capacitor 36 has a single-plate parallel plate capacitor structure like the smoothing capacitors 34a and 34b.

  Further, as shown in FIGS. 9 to 10, the smoothing capacitors 34 a and 34 b are arranged at both ends of the auxiliary smoothing capacitor 36.

Further, as shown in FIGS. 9 to 10, auxiliary smoothing capacitor connecting bonding wires 37 ₁ , 37 ₂ , 37 ₃ , which connect between the drain terminal electrode D of the high-frequency semiconductor chip 24 and the auxiliary smoothing capacitor 36. equipped with a 37 _4.

  Further, as shown in FIGS. 9 to 10, smoothing capacitor connecting bonding wires 38a and 38b for connecting the auxiliary smoothing capacitor 36 and the smoothing capacitors 34a and 34b are provided.

The auxiliary smoothing capacitor connecting bonding wires 37 ₁ , 37 ₂ , 37 _3, and 37 ₄ have a length that provides an impedance sufficiently larger than the impedance in the vicinity of the drain terminal electrode D of the high-frequency semiconductor chip 24 at the operating frequency. . By connecting the auxiliary smoothing capacitor 36, the auxiliary smoothing capacitor connecting bonding wires 37 ₁ , 37 ₂ , 37 _3, and 37 ₄ are lengthened so that there is no change in the matching state at the operating frequency. Raised.

  Here, the value of the auxiliary smoothing capacitor 36 is about 1/10 of the value of the smoothing capacitors 34a and 34b. For example, the value of the smoothing capacitors 34a and 34b is about 0.05 μF, while the value of the auxiliary smoothing capacitor 36 is about 0.005 μF.

_A schematic circuit configuration including the input matching unit 50, the output matching unit 60, the smoothing capacitor C _B , and the auxiliary smoothing capacitor C _A of the semiconductor device 1 according to the third embodiment is expressed as shown in FIG. Is done.

  As shown in FIG. 11, the input matching unit 50 includes an input-side distribution circuit 17 and an input-side lumped constant circuit connected between the input-side distribution circuit 17 and the gate terminal electrode G of the high-frequency semiconductor chip 24. The lumped constant circuit on the input side includes inductances L1a and L1b and a capacitance C1. The output matching unit 60 includes an output side distribution circuit 18 and an output side lumped constant circuit connected between the output side distribution circuit 18 and the drain terminal electrode D of the high frequency semiconductor chip 24. The output side lumped constant circuit includes inductances L2a and L2b and a capacitance C2.

Further, the semiconductor device 1 according to the third embodiment, as shown in FIGS. 9 and 11, the inductance L _A based on the auxiliary smoothing capacitor connected bonding wires 37 _1, 37 _2, 37 _3, 37 ₄ through comprising a connection auxiliary smoothing capacitor C _a between the drain terminal electrode D of the high-frequency semiconductor chip 24 ground potential. Furthermore, a smoothing capacitor C _B connected between the auxiliary smoothing capacitor 36 and the ground potential is provided via an inductance L _B based on the smoothing capacitor connecting bonding wires 38a and 38b. Here, assuming that the value of the smoothing capacitor C _B is C _BR , the current amplitude value is I _PK , the allowable ripple voltage value is ΔV, and the difference frequency value is Δf, the value C _BR of the smoothing capacitor C _B is , C _BR = I _PK × (1 / 2πΔf) / ΔV or more.

  According to the third embodiment, there is provided a semiconductor device in which the voltage at the drain end face of the high-frequency semiconductor chip is smoothed even when the differential frequency Δf is several hundred MHz.

(Fourth embodiment)
In the semiconductor device 1 according to the fourth embodiment, as shown in FIGS. 12 and 13, the bonding wire 37 for connecting the auxiliary smoothing capacitor from the drain terminal electrode D of the high-frequency semiconductor chip 24 to the auxiliary smoothing capacitor 36. The positions of the auxiliary smoothing capacitor 36 and the output matching capacitor substrate 32 may be interchanged with respect to the smoothing capacitors 34a and 34b so that ₁ · 37 ₂ · 37 ₃ · 37 ₄ are connected long. The other configuration is the same as that of the third embodiment, and a duplicate description is omitted.

  According to the fourth embodiment, there is provided a semiconductor device in which the voltage at the drain end face of the high-frequency semiconductor chip is smoothed even when the differential frequency Δf is several hundred MHz.

(Fifth embodiment)
A schematic planar configuration of a semiconductor device according to a comparative example for explaining the case where the arrangement space of the smoothing capacitors 34a and 34b is narrow is expressed as shown in FIG. 14A, and an enlarged view of the arrangement space of the smoothing capacitors is shown in FIG. This is expressed as shown in FIG. In FIG. 14, the space A in which the smoothing capacitors 34a and 34b are to be arranged has a length D and a width W.

  On the other hand, a schematic planar configuration of the semiconductor device according to the fifth embodiment is expressed as shown in FIG. 15, and a schematic cross-sectional structure taken along line VV of FIG. 15 is shown in FIG. An enlarged schematic cross-sectional structure of the smoothing capacitor 34a is expressed as shown in FIG. Further, a schematic cross-sectional structure taken along line VI-VI in FIG. 15 is expressed as shown in FIG. The fifth embodiment corresponds to the case where the arrangement space of the smoothing capacitors 34a and 34b is narrow in the first embodiment.

  As shown in FIGS. 15 to 17, the semiconductor device 1 according to the fifth embodiment includes a conductor base plate 200 on which the high-frequency semiconductor chip 24 is mounted, and a columnar electrode 94 disposed on the conductor base plate 200. The smoothing capacitors 34 a and 34 b are disposed on the columnar electrode 94.

  Further, as shown in FIG. 16B, the smoothing capacitors 34a and 34b include a first capacitor electrode layer 90b, a capacitor insulating layer 92 disposed on the first capacitor electrode layer 90b, and a capacitor insulating layer 92, respectively. And a second capacitor electrode layer 90a. As shown in FIG. 16B, the smoothing capacitors 34a and 34b are disposed on the columnar electrode 94 via a solder layer 94a. Further, as shown in FIG. 16B, the columnar electrode 94 is disposed on the conductor base plate 200 via a solder layer 200a. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  According to the semiconductor device of the fifth embodiment, by mounting the smoothing capacitor on the metal pillar, the mounting area limitation is avoided and the smoothing capacitor having a relatively large capacity is mounted. be able to.

  According to the fifth embodiment, there is provided a semiconductor device in which the voltage at the drain end face of the high-frequency semiconductor chip is smoothed even when the differential frequency Δf is several hundred MHz.

(Sixth embodiment)
As shown in FIGS. 18 to 19, the semiconductor device 1 according to the sixth embodiment includes a conductor base plate 200 on which the high-frequency semiconductor chip 24 is mounted, and a columnar electrode 94 disposed on the conductor base plate 200. The smoothing capacitors 34 a and 34 b are disposed on the columnar electrode 94. Here, the columnar electrodes 94 are arranged in the same manner as in FIG. 15 of the fifth embodiment, but are not shown in FIG. The sixth embodiment corresponds to the case where the arrangement space of the smoothing capacitors 34a and 34b is narrow in the third embodiment. The other configuration is the same as that of the third embodiment, and a duplicate description is omitted.

  According to the semiconductor device of the sixth embodiment, by mounting the smoothing capacitor on the metal column, the mounting area is not limited and the smoothing capacitor having a relatively large capacity is mounted. be able to.

  According to the sixth embodiment, there is provided a semiconductor device in which the voltage at the drain end face of the high-frequency semiconductor chip is smoothed even when the differential frequency Δf is several hundred MHz.

(Seventh embodiment)
A schematic planar configuration of the semiconductor device 1 according to the seventh embodiment is expressed as shown in FIG. 20, and a schematic cross-sectional structure taken along line VIII-VIII in FIG. 20 is expressed as shown in FIG. The

  As shown in FIGS. 20 to 21, the semiconductor device 1 according to the seventh embodiment includes a conductor base plate 200 on which the high-frequency semiconductor chip 24 is mounted, and a columnar electrode 94 disposed on the conductor base plate 200. The smoothing capacitors 34 a and 34 b are disposed on the columnar electrode 94. Here, the columnar electrodes 94 are arranged in the same manner as in FIG. 15 of the fifth embodiment, but are not shown in FIG. The seventh embodiment corresponds to the case where the arrangement space of the smoothing capacitors 34a and 34b is narrow in the fourth embodiment. The other configuration is the same as that of the fourth embodiment, and a duplicate description is omitted.

  According to the semiconductor device of the seventh embodiment, by mounting the smoothing capacitor on the metal pillar, the mounting area limitation is avoided and the smoothing capacitor having a relatively large capacity is mounted. be able to.

  According to the seventh embodiment, there is provided a semiconductor device in which the voltage at the drain end face of the high-frequency semiconductor chip is smoothed even when the differential frequency Δf is several hundred MHz.

(Configuration of high-frequency semiconductor chip)
An enlarged view of a schematic planar pattern configuration of the high-frequency semiconductor chip 24 applied to the semiconductor device 1 according to the embodiment is represented as shown in FIG. 22A, and an enlarged view of a portion J in FIG. This is expressed as shown in FIG. Moreover, it is the structural examples 1-4 of the high frequency semiconductor chip 24 applied to the semiconductor device 1 which concerns on embodiment, Comprising: Typical sectional structure examples 1-4 along the IX-IX line of FIG.22 (b) are respectively shown. It is expressed as shown in FIGS.

  In the high-frequency semiconductor chip 24 applied to the semiconductor device 1 according to the embodiment, the plurality of FET cells FET1 to FET10 include the semi-insulating substrate 110 and the semi-insulating substrate 110, as shown in FIGS. The gate finger electrode 124, the source finger electrode 120 and the drain finger electrode 122, which are disposed on one surface, each having a plurality of fingers, and the first surface of the semi-insulating substrate 110, the gate finger electrode 124, the source finger electrode 120 A plurality of gate terminal electrodes G1, G2,..., G10 formed by bundling a plurality of fingers for each drain finger electrode 122, a plurality of source terminal electrodes S11, S12, S21, S22,. Electrodes D1, D2, ..., D10, VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 disposed under the terminal electrodes S11, S12, S21, S22,..., S101, S102, and the first surface of the semi-insulating substrate 110. Arranged on the second surface on the side and connected to the source terminal electrodes S11, S12, S21, S22,..., S101, S102 via the VIA holes SC11, SC12, SC21, SC22,. Electrodes (not shown).

  A bonding wire 12 is connected to the gate terminal electrodes G1, G2,..., G10, and a bonding wire 14 is connected to the drain terminal electrodes D1, D2,.

  Barrier metal layers (not shown) formed on the inner walls of the VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102, and a filled metal layer (not shown) formed on the barrier metal layers and filling the VIA holes. The source terminal electrodes S11, S12, S21, S22,..., S101, S102 are connected to the ground electrode.

  The semi-insulating substrate 110 is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or One of the diamond substrates.

―Structure Example 1―
As a schematic cross-sectional configuration along the line IX-IX in FIG. 22B, the structure example 1 of the FET cell of the high-frequency semiconductor chip 24 applied to the semiconductor device 1 according to the embodiment is as shown in FIG. Insulating substrate 110, nitride-based compound semiconductor layer 112 disposed on semi-insulating substrate 110, and an aluminum gallium nitride layer (Al _x Ga _1-x N) disposed on nitride-based compound semiconductor layer 112 (0.1 ≦ x ≦ 1) 118 and source finger electrode 120, gate finger electrode 124, and aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 A drain finger electrode 122. A two-dimensional electron gas (2DEG) layer is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. 116 is formed. In Structural Example 1 shown in FIG. 23, a heterojunction field effect transistor (HFET) or a high electron mobility transistor (HEMT) is shown.

-Structural example 2-
As a schematic cross-sectional configuration along the line IX-IX in FIG. 22B, the structure example 2 of the FET cell of the high-frequency semiconductor chip 24 applied to the semiconductor device 1 according to the embodiment is as shown in FIG. Insulating substrate 110, nitride-based compound semiconductor layer 112 disposed on semi-insulating substrate 110, source region 126 and drain region 128 disposed on nitride-based compound semiconductor layer 112, and source region 126 A source finger electrode 120 disposed on the gate electrode 124, a gate finger electrode 124 disposed on the nitride-based compound semiconductor layer 112, and a drain finger electrode 122 disposed on the drain region 128. A Schottky contact is formed at the interface between the nitride-based compound semiconductor layer 112 and the gate finger electrode 124. In Structural Example 2 shown in FIG. 24, a metal-semiconductor field effect transistor (MESFET) is shown.

―Structure Example 3―
As a schematic cross-sectional configuration along the line IX-IX in FIG. 22B, the structure example 3 of the FET cell of the high-frequency semiconductor chip 24 applied to the semiconductor device 1 according to the embodiment is shown in FIG. Insulating substrate 110, nitride-based compound semiconductor layer 112 disposed on semi-insulating substrate 110, and an aluminum gallium nitride layer (Al _x Ga _1-x N) disposed on nitride-based compound semiconductor layer 112 (0.1 ≦ x ≦ 1) 118, and source finger electrode 120 and drain finger electrode 122 disposed on aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118, And a gate finger electrode 124 disposed in a recess portion on the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In Structural Example 3 shown in FIG. 25, an HFET or HEMT is shown.

-Structural example 4-
As a schematic cross-sectional configuration along the line IX-IX in FIG. 22B, the structure example 4 of the FET cell of the high-frequency semiconductor chip 24 applied to the semiconductor device 1 according to the embodiment is as shown in FIG. Insulating substrate 110, nitride-based compound semiconductor layer 112 disposed on semi-insulating substrate 110, and an aluminum gallium nitride layer (Al _x Ga _1-x N) disposed on nitride-based compound semiconductor layer 112 (0.1 ≦ x ≦ 1) 118, and source finger electrode 120 and drain finger electrode 122 disposed on aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118, A gate finger electrode 124 disposed in a two-stage recess portion on an aluminum gallium nitride layer (Al _x Ga ₁ -xN) (0.1 ≦ x ≦ 1) 118. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In Structural Example 4 shown in FIG. 26, an HFET or HEMT is shown.

  In Structural Examples 1 to 4, the nitride-based compound semiconductor layer 112 other than the active region is used as an electrically inactive element isolation region. Here, the active region refers to the 2DEG layer 116 immediately below the source finger electrode 120, the gate finger electrode 124, and the drain finger electrode 122, between the source finger electrode 120 and the gate finger electrode 124, and between the drain finger electrode 122 and the gate finger electrode 124. 2 DEG layer 116. In the structural examples 1 to 4, the nitride compound semiconductor layer 112 other than the active region is used as an electrically inactive element isolation region.

As another method for forming the element isolation region, the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a part of the nitride-based compound semiconductor layer 112 in the depth direction are used. It can also be formed by ion implantation. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. The dose accompanying ion implantation is, for example, about 1 × 10 ¹⁴ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV.

A passivation insulating layer (not shown) is formed on the element isolation region and the device surface. As this insulating layer, for example, a nitride film, an alumina (Al ₂ O ₃ ) film, an oxide film (SiO ₂ ), an oxynitride film (SiON) or the like deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) method is formed. be able to.

  The source finger electrode 120 and the drain finger electrode 122 are made of, for example, Ti / Al. The gate finger electrode 124 can be formed of, for example, Ni / Au.

  In the high-frequency semiconductor chip 24 applied to the semiconductor device 1 according to the embodiment, the pattern length in the longitudinal direction of the gate finger electrode 124, the source finger electrode 120, and the drain finger electrode 122 is microwave / millimeter wave / submillimeter wave. As the operating frequency increases, it is set shorter. For example, in the millimeter wave band, the pattern length is about 25 μm to 50 μm.

  Further, the width of the source finger electrode 120 is, for example, about 40 μm, and the width of the source terminal electrodes S11, S12, S21, S22,..., S101, S102 is, for example, about 100 μm. Further, the formation width of the VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 is, for example, about 10 μm to 40 μm.

  According to the embodiment, it is possible to provide a semiconductor device applicable to a microwave / millimeter wave / submillimeter wave high frequency band that amplifies a plurality of frequencies simultaneously.

  According to the embodiment, the voltage at the drain end face of the high-frequency semiconductor chip is smoothed even when the differential frequency Δf is several hundred MHz, and a semiconductor device that can be applied to a microwave / millimeter-wave / submillimeter-wave high-frequency band is provided. Can do.

(Other embodiments)
Although the embodiment has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  Note that the high-frequency semiconductor chip mounted on the semiconductor device according to the embodiment is not limited to the FET and the HEMT, but is also an LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor) or a heterojunction bipolar transistor (HBT). Needless to say, amplifying elements such as bipolar transistors and MEMS (Micro Electro Mechanical Systems) elements are also applicable.

  As described above, various embodiments that are not described herein are included.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10 ... Metal cap 11, 12, 13, 14, 15, 19 ... Bonding wire 14a ... Metal seal ring 16 ... Metal wall 17 ... Input side distributed constant circuit 18 ... Output side distributed constant circuit 19a ... Input strip line 19b ... Output strip line 20a, 20b ... Feed-through lower layer 21a ... High-frequency input terminal 21b ... High-frequency output terminal 22 ... Feed-through upper layer 23a, 23b, 23 ₁ , 23 ₂ , 23 ₃ , 23 ₄ , 38a, 38b Capacitor connection bonding wire 24 ... high frequency semiconductor chip 26 ... input circuit board 28 ... output circuit board 30 ... input matching capacitor board 32 ... output matching capacitor boards 34, 34a, 34b, 34 ₁ , 34 ₂ , 34 ₃ , 34 ₄ ... smoothing capacitor 36 ... auxiliary smoothing capacitors 37, 37 ₁ , 37 ₂ , 37 ₃ , 37 ₄ ... Bonding wires 40, 42, 90 a and 90 b for connecting the auxiliary smoothing capacitor. Capacitor electrode layers 44 and 92... Capacitor insulating layer 50. Electrodes 94a, 200a ... solder layer 110 ... semi-insulating substrate 112 ... nitride compound semiconductor layer (GaN epitaxial growth layer)
116: Two-dimensional electron gas (2DEG) layer 118: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
120 ... Source finger electrode 122 ... Drain finger electrode 124 ... Gate finger electrode 126 ... Source region 128 ... Drain region 200 ... Conductor base plates G, G1, G2, ..., G10 ... Gate terminal electrodes S, S11, S12, ..., S101, S102 ... Source terminal electrodes D, D1, D2, ..., D10 ... Drain terminal electrodes SC11, SC12, ..., SC91, SC92, SC101, SC102 ... VIA hole C _B ... Bypass capacitor (smoothing capacitor)
C _A ... auxiliary smoothing capacitors L _A , L _B ... inductor I _PK ... current amplitude value ΔV ... ripple voltage f ... differential frequency

Claims (18)

A high-frequency semiconductor chip;
An input-side distribution circuit disposed on the input side of the high-frequency semiconductor chip;
An output-side distribution circuit disposed on the output side of the high-frequency semiconductor chip; and
A high-frequency input terminal connected to the input-side distributed circuit;
A high-frequency output terminal connected to the output-side distribution circuit;
A smoothing capacitor disposed in the vicinity of the drain terminal electrode of the high-frequency semiconductor chip ;
A smoothing capacitor connecting bonding wire that connects the drain terminal electrode of the high-frequency semiconductor chip and the smoothing capacitor, and is connected in series and directly to the smoothing capacitor; A chip, the input-side distribution circuit, the output-side distribution circuit, and the smoothing capacitor are housed in one package ;
Assuming that the smoothing capacitor value is C _BR , the current amplitude value is I _PK , the allowable ripple voltage value is ΔV, and the differential frequency value is Δf, the smoothing capacitor has C _BR = I _PK × (1 / 2πΔf) / ΔV or more .   The smoothing capacitor is:
  A first capacitor electrode layer;
  A capacitor insulating layer disposed on the first capacitor electrode layer;
  A second capacitor electrode layer disposed on the capacitor insulating layer;
  The semiconductor device according to claim 1, comprising: The smoothing capacitor is disposed at both ends of the high-frequency semiconductor chip, and the bonding wire for connecting the smoothing capacitor has an impedance of 10 times or more than the impedance in the vicinity of the drain terminal electrode of the high-frequency semiconductor chip at the operating frequency. The semiconductor device according to claim 1, wherein the semiconductor device has a length.   A conductor base plate on which the high-frequency semiconductor chip is mounted;
  A columnar electrode disposed on the conductor base plate;
  The semiconductor device according to claim 1, wherein the smoothing capacitor is disposed on the columnar electrode. A plurality of the smoothing capacitors are arranged in the vicinity of the drain terminal electrode of the high-frequency semiconductor chip, and the bonding wire for connecting the smoothing capacitor is 10 times the impedance near the drain terminal electrode of the high-frequency semiconductor chip at the operating frequency. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a length that provides the above impedance. 2. The semiconductor device according to claim 1, further comprising an auxiliary smoothing capacitor disposed in parallel with the drain terminal electrode of the high-frequency semiconductor chip. 7. The semiconductor device according to claim 6, wherein a length in the length direction of the auxiliary smoothing capacitor is substantially the same as a length in the length direction of the high-frequency semiconductor chip. The semiconductor device according to claim 6, wherein the auxiliary smoothing capacitor is arranged so that a length direction of the auxiliary smoothing capacitor is parallel to a length direction of the high-frequency semiconductor chip. The semiconductor device according to claim 6 , wherein the smoothing capacitor is disposed at both ends of the auxiliary smoothing capacitor. The semiconductor device according to claim 6 , further comprising an auxiliary smoothing capacitor connecting bonding wire that connects the drain terminal electrode of the high-frequency semiconductor chip and the auxiliary smoothing capacitor.   11. The semiconductor device according to claim 10, further comprising a bonding wire for connecting a smoothing capacitor that connects between the auxiliary smoothing capacitor and the smoothing capacitor.   11. The auxiliary smoothing capacitor connecting bonding wire has a length at which an impedance is 10 times or more than an impedance in the vicinity of the drain terminal electrode of the high frequency semiconductor chip at an operating frequency. A semiconductor device according to 1. A conductor base plate on which the high-frequency semiconductor chip is mounted;
The semiconductor device according to claim 6 , further comprising: a columnar electrode disposed on the conductor base plate, wherein the smoothing capacitor is disposed on the columnar electrode. An input strip line connected to the input side distribution circuit;
An output strip line connected to the output-side distributed circuit, the high-frequency input terminal is connected to a gate terminal electrode of the high-frequency semiconductor chip via the input strip line, and the high-frequency output terminal is connected to the output strip The semiconductor device according to claim 1, wherein the semiconductor device is connected to the drain terminal electrode of the high-frequency semiconductor chip via a line. An input circuit board on which the input-side distributed circuit is mounted;
The semiconductor device according to claim 1, further comprising: an output circuit board on which the output-side distributed circuit is mounted. An input matching capacitor substrate disposed between the input circuit substrate and the high-frequency semiconductor chip;
The semiconductor device according to claim 15, further comprising: an output matching capacitor substrate disposed between the output circuit substrate and the high-frequency semiconductor chip. The high-frequency semiconductor chip is
A semi-insulating substrate;
A gate finger electrode, a source finger electrode and a drain finger electrode disposed on the first surface of the semi-insulating substrate, each having a plurality of fingers;
A plurality of gate terminal electrodes arranged on the first surface of the semi-insulating substrate and formed by bundling a plurality of fingers for each of the gate finger electrode, the source finger electrode and the drain finger electrode; A drain terminal electrode;
A VIA hole disposed under the source terminal electrode;
The ground electrode disposed on the second surface opposite to the first surface of the semi-insulating substrate and connected to the source terminal electrode via the VIA hole. The semiconductor device described.   The semi-insulating substrate is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or The semiconductor device according to claim 17, wherein the semiconductor device is any one of a diamond substrate.