JP2012178525A - Package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a package in which warping of a base surface is reduced.SOLUTION: The package comprises a conductive base plate 200; a semiconductor device disposed on the conductive base plate; and a metal wall 16 housing the semiconductor device and arranged on the conductive base plate, the metal wall being composed of material different from the conductive base plate. Since one pair of edge faces 100a and 100b opposing with each other have an arcuate shape and the metal wall also has an arcuate shape, the conductive base plate can suppress occurring of warping at the time of bonding, mounting substrate, or soldering a cap.

Description

  Embodiments of the invention relate to a package.

  Conventionally, resin-sealed semiconductor devices and hermetically sealed semiconductor devices are known as semiconductor devices in which semiconductor elements are packaged.

  The resin-encapsulated type has a structure in which the semiconductor element mounted on the lead frame is directly embedded in the resin by transfer molding, etc., and is advantageous for low cost, suitable for mass production, and miniaturization. Widely adopted.

  The hermetic sealing type has a structure in which a semiconductor element mounted on a base made of an insulator such as ceramic is hollow and hermetically held. The cost is higher than that of a resin-sealed semiconductor device, but the hermeticity is excellent. Therefore, it is adopted when high reliability is required.

  In recent years, semiconductor elements have been increased in size, density, and integration, and the amount of heat generated during the operation of the semiconductor elements has increased rapidly.

  As the hermetically sealed semiconductor device, a hermetically sealed semiconductor device in which a semiconductor element is mounted directly on a heat radiator made of metal is known.

JP 2000-183222 A JP 2011-3718 A

  The conductor base plate is made of copper (Cu), a clad material of Cu and molybdenum (Mo), or a compound material of Cu and Mo, which has high heat dissipation. On the other hand, the metal outer wall is often made of KOVAL which is inexpensive and has high hardness. Here, since the thermal expansion coefficients of the conductor base plate material and KOVAL are different, warping occurs when silver brazing is performed.

  Since the conductor base plate material having a flat initial state and the metal outer wall are joined at a high temperature, a large piece-like or bowl-like warp occurs.

  The problem to be solved by the present invention is to provide a package in which the warpage of the base surface is controlled.

The package according to the present embodiment includes a conductor base plate, a semiconductor device, and a metal wall. The semiconductor device is disposed on the conductor base plate. The metal wall includes the semiconductor device, is disposed on the conductor base plate, and is made of a material different from that of the conductor base plate. The conductor base plate has a gentle arc.

It is a typical bird's-eye view of the package which concerns on embodiment, Comprising: (a) Metal cap 10, (b) Metal seal ring 14a, (c) Metal wall 16, (d) Conductor baseplate 200, Feedthrough lower layer part 20, Input The schematic block diagram of the stripline 19a and the output stripline 19b, and the feedthrough upper layer part 22. FIG. The typical plane pattern block diagram of the package which concerns on embodiment. It is typical sectional structure of the package which concerns on embodiment, Comprising: The typical cross-section figure which follows the II line | wire of FIG. It is typical sectional structure of the package which concerns on embodiment, Comprising: Typical sectional structure drawing which follows the II-II line | wire of FIG. It is typical sectional structure of the package which concerns on embodiment, Comprising: The typical cross-section figure which follows the III-III line | wire of FIG. FIG. 6 is a schematic plan pattern configuration of the package according to the embodiment, and illustrates a C-C ′ direction and an A-A ′ direction of a package having a structure having a warp in the C-C ′ direction in advance. 10A and 10B are diagrams illustrating warpage in a C-C ′ direction of a package according to an embodiment. 8A and 8B illustrate a warpage in an A-A ′ direction in a package according to an embodiment. Explanatory drawing of the structure which is the typical bird's-eye view structure of the package which concerns on embodiment, and has curvature in the C-C 'direction previously. The figure explaining the C-C 'direction and A-A' direction of a package in the typical plane pattern composition of the package concerning a comparative example. The figure explaining the curvature of the C-C 'direction of the package which concerns on a comparative example. The figure explaining the curvature of the A-A 'direction of the package which concerns on a comparative example. (A) In the schematic plane pattern structure of the package which concerns on a comparative example, the figure explaining the direction CC 'and AA' of a piece-shaped curvature, (b) The figure explaining the curvature of an AA 'direction (C) The figure explaining the curvature of a CC 'direction. (A) In the schematic plane pattern structure of the package which concerns on a comparative example, the figure explaining bowl-shaped curvature direction CC ', AA', (b) The figure explaining the curvature of AA 'direction (C) The figure explaining the curvature of a CC 'direction. (A) The enlarged view of the typical plane pattern structure of the semiconductor device mounted in the package which concerns on embodiment, (b) The enlarged view of J part of Fig.15 (a). FIG. 16 is a schematic cross-sectional structure diagram illustrating a configuration example 1 of the semiconductor device mounted on the package according to the embodiment, taken along line IV-IV in FIG. FIG. 16 is a schematic cross-sectional structure diagram illustrating a configuration example 2 of the semiconductor device mounted on the package according to the embodiment, taken along line IV-IV in FIG. FIG. 16 is a schematic cross-sectional structure diagram illustrating a configuration example 3 of the semiconductor device mounted on the package according to the embodiment, taken along line IV-IV in FIG. FIG. 16 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. 15B, which is a configuration example 4 of the semiconductor device mounted on the package according to the embodiment.

  Next, embodiments will be described with reference to the drawings. In the following, the same elements are denoted by the same reference numerals to avoid duplication of explanation and to simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The embodiment described below exemplifies an apparatus and a method for embodying the technical idea, and the embodiment does not specify the arrangement of each component as described below. This embodiment can be modified in various ways within the scope of the claims.

[First embodiment]
(Package structure)
A schematic bird's-eye view configuration describing the package according to the embodiment is represented as shown in FIG. 1A shows a metal cap 10, FIG. 1B shows a metal seal ring 14a, FIG. 1C shows a metal wall 16, FIG. 1D shows a conductor base plate 200, a feedthrough lower layer 20, an input. A schematic configuration of the strip line 19a, the output strip line 19b, and the feedthrough upper layer portion 22 is shown.

  As shown in FIG. 1, the package according to the embodiment includes a metal cap 10, a metal seal ring 14 a, a metal wall 16, a conductor base plate 200, and a feedthrough lower layer portion 20 disposed on the conductor base plate 200. , An input strip line 19 a and an output strip line 19 b disposed on the feedthrough lower layer portion 20, and a feedthrough upper layer portion 22 disposed on the feedthrough lower layer portion 20.

  A schematic planar pattern configuration of the package 1 according to the embodiment is expressed as shown in FIG. Further, a schematic cross-sectional structure taken along line II in FIG. 2 is expressed as shown in FIG.

  2 is represented as shown in FIG. 4, and the schematic sectional structure along the line III-III in FIG. 2 is represented as shown in FIG. .

  As shown in FIGS. 1 to 5, the configuration example of the package 1 according to the embodiment includes a conductor base plate 200, a semiconductor device 24 disposed on the conductor base plate 200, a semiconductor device 24, and a conductor base plate 200. The metal wall 16 disposed above, the through hole 34 provided in the input / output part of the metal wall 16 (see FIG. 1C), and fitted into the through hole 34 and disposed on the conductor base plate 200. The feedthrough lower layer part 20 and the feedthrough upper layer part 22 fitted in the through hole 34 and disposed on the feedthrough lower layer part 20 are provided.

  In addition, as shown in FIGS. 1 to 4, the package 1 according to the embodiment includes an input strip line 19 a disposed between the feedthrough lower layer portion 20 and the feedthrough upper layer portion 22 in the input portion of the metal wall 16. In addition, the output portion of the metal wall 16 may include an output strip line 19b disposed between the feedthrough lower layer portion 20 and the feedthrough upper layer portion 22.

  In addition, as shown in FIGS. 2 to 3, the package 1 according to the embodiment includes an input circuit board 26 and an output circuit disposed adjacent to the semiconductor device 24 on the conductor base plate 200 surrounded by the metal wall 16. A substrate 28, an input matching circuit 17 disposed on the input circuit board 26 and connected to the input stripline 19a, an output matching circuit 18 disposed on the output circuit board 28 and connected to the output stripline 19b, The bonding wire 12 that connects the semiconductor device 24 and the input matching circuit 17 and the bonding wire 14 that connects the semiconductor device 24 and the output matching circuit 18 may be provided.

  In the package 1 according to the embodiment, a gentle arc of about 10 μm is conducted in the direction perpendicular to the long side direction (III-III line direction) of the semiconductor device 24, the input circuit board 26, and the output circuit board 28. The base plate 200 and / or the metal wall 16 is held, and the amount of warpage is suppressed to be flattened by screwing to a heat sink (not shown) using screws 70a and 70b.

  Further, since the semiconductor device 24, the input circuit board 26, and the output circuit board 28 are arranged as shown in FIG. 2, the input strip line to which the RF input terminal 21a is connected in the convex feedthrough 25 portion of the input section. 19 a is connected to the input matching circuit 17 from the short side direction of the input circuit board 26, and the output strip line 19 b to which the RF output terminal 21 b is connected in the convex feedthrough 25 portion of the output section is connected to the output circuit board 28. The output matching circuit 18 is connected from the short side direction.

  Moreover, as shown in FIGS. 1 and 3 to 5, the package 1 according to the embodiment includes a metal seal ring 14 a disposed on the metal wall 16 and a metal cap 10 disposed on the metal seal ring 14 a. And may be provided.

  The conductor base plate 200 is made of, for example, a conductive metal such as molybdenum or a copper molybdenum alloy. Furthermore, a plated conductor such as Au, Ni, Ag, Ag—Pt alloy, or Ag—Pd alloy may be formed on the surface of the conductor base plate 200.

  The metal wall 16 is formed of a conductive metal such as aluminum, molybdenum, or copper molybdenum alloy.

  A solder metal layer (not shown) for soldering is formed on the upper surface of the metal wall 16 via a metal seal ring 14a. The solder metal layer can be formed from, for example, a gold germanium alloy, a gold tin alloy, or the like.

  In the package according to the embodiment, the metal wall 16 is arranged on the conductor base plate 200 via an insulating or conductive adhesive. The insulating adhesive can be formed from, for example, an epoxy resin or glass, and the conductive adhesive can be formed from, for example, a gold germanium alloy or a gold-tin alloy.

  In the configuration example of the package 1 according to the embodiment, as shown in FIG. 3, the thickness W2 of the feedthrough upper layer portion 22 may be formed thicker than the thickness W1 of the metal wall 16.

  In the configuration example of the package 1 according to the embodiment, as shown in FIG. 3, in the convex feedthrough 25 including the feedthrough lower layer portion 20 and the feedthrough upper layer portion 22, the thickness W2 of the feedthrough upper layer portion 22 is made of metal. By forming the wall 16 thicker than the thickness W1, the stress concentration point and the stress generation source (metal wall 16) at the connection portion between the feedthrough lower layer 20 and the feedthrough upper layer 22 can be separated. As a result, the stress is relaxed and the generation of cracks at the stress concentration point can be suppressed.

The feedthrough lower layer 20 and the feedthrough upper layer 22 may be formed of the same material, for example, ceramic. The ceramic material can be formed from, for example, alumina (Al ₂ O ₃ ), aluminum nitride (AlN), beryllium oxide (BeO), or the like.

  As shown in FIG. 1, the metal cap 10 has a flat plate shape. The metal cap 10 is formed of, for example, a conductive metal such as aluminum, molybdenum, or copper molybdenum alloy.

  The metal cap 10 is disposed on the metal wall 16 via the metal seal ring 14a.

  As a result, as shown in FIG. 1, the package according to the embodiment is disposed on the metal wall 16, the metal seal ring 14 a disposed on the metal wall 16, and the metal seal ring 14 a on the metal wall 16. The metal cap 10 is provided.

  As described above, the package 1 according to the embodiment has a warp of about 10 μm in a predetermined direction (a direction along the line III-III in FIG. 2) in advance. That is, FIG. 6 shows the CC ′ direction and the AA ′ direction of the package 1 having a structure having a warp in the CC ′ direction in advance, which is a schematic planar pattern configuration of the package 1 according to the embodiment. It is expressed as follows. Further, the warpage in the CC ′ direction of the package 1 according to the embodiment is represented as shown in FIG. 7, and the shape of the package 1 according to the embodiment in the AA ′ direction is as shown in FIG. It is expressed in In addition, a schematic bird's-eye view structure of the package 1 according to the embodiment, which has a warp in the C-C ′ direction in advance, is expressed as shown in FIG. 9. As is clear from FIGS. 7 and 8, the package 1 according to the embodiment has a warp in the C-C 'direction in advance, but has almost no warp in the A-A' direction.

  As shown in FIGS. 6 to 9, the package 1 according to the embodiment includes the conductor base plate 200, the semiconductor device 24 disposed on the conductor base plate 200, and the semiconductor device 24, and is disposed on the conductor base plate 200. And a metal wall 16 made of a material different from that of the conductor base plate 200, and the conductor base plate 200 has a gentle arc on the base surface.

  In the package 1 according to the embodiment, the metal wall 16 may have a gentle arc as shown in FIG.

  Further, as shown in FIG. 9, the pair of end faces 100a and 100b facing each other of the conductor base plate 200 may have a gentle arc of about 10 μm in the package 1 according to the embodiment.

  In the package 1 according to the embodiment, as shown in FIGS. 6 to 9, the long side of the substrate of the semiconductor device 24 is perpendicular to the long side direction CC ′ of the conductor base plate 200 having a gentle arc. Is arranged.

  Further, in the package 1 according to the embodiment, as illustrated in FIGS. 6 to 9, the input circuit board 26 and the output that are disposed adjacent to the semiconductor device 24 on the conductor base plate 200 surrounded by the metal wall 16. The circuit board 28 may be provided, and the long sides of the input circuit board 26 and the output circuit board 28 may be arranged perpendicular to the long side direction CC ′ of the conductor base plate 200 having a gentle arc.

  In the package 1 according to the embodiment, as shown in a bird's eye view of FIG. 9, the conductor base plate 200 having a warp amount in the short side direction is formed in a press die in advance.

  Here, the pair of opposed end faces 100a and 100b have a moderate arc of about 10 μm. A pair of opposed end faces 100a and 100b have a gentle arc with an opening amount d of about 10 μm between the tangent to the arc.

By providing a gentle arc in the conductor base plate 200 and / or the metal wall 16 in advance, as a result, it is possible to suppress the occurrence of warping during bonding, board mounting, and cap soldering.
Since heat is applied when the board is mounted and when the cap is soldered, warping occurs during cooling due to the difference in linear thermal expansion coefficient between the board and the cap and the package. When the substrate is rectangular, the difference in heat shrinkage in the longitudinal direction is large, and thus warpage tends to occur in the short side direction. In general, an arc-shaped plate has a higher strength than a planar plate in a long side direction in which an arc is not drawn. For this reason, in the package 1 according to the embodiment, as shown in FIG. 9, the conductor base plate 200 has a gentle arc with a warpage amount of about 10 μm in the short side direction on the base surface.

  In the above, the reason why the warpage amount is about 10 μm is a numerical value obtained experimentally because the concentric warpage of the existing package is about 10 μm, and the warpage amount given in advance is the same. This is because more than that is necessary.

  In the package 1 according to the embodiment, since the conductor base plate 200 has a planar structure, warping is likely to occur due to external force (difference in linear thermal expansion from the metal frame). By giving an arc in the direction, strength is given in the long side direction of the conductor base plate 200. This is because even soft paper can be set up with an arc, but strength is born by providing an arc so that it cannot be set up in a flat state. If an arc is also provided in the long side direction of the conductor base plate 200, the strength cannot be obtained.

(Comparative example)
In the schematic planar pattern configuration of the package 1a according to the comparative example, a diagram for explaining the CC ′ direction and the AA ′ direction of the package is expressed as shown in FIG. Further, the warpage in the CC ′ direction of the package 1a according to the comparative example is expressed as shown in FIG. 11, and the warpage in the AA ′ direction is expressed as shown in FIG.

  In the package 1a according to the comparative example, the screw position of the conductor base plate 200 in the direction parallel to the long side direction of the semiconductor device 24, the input circuit board 26, and the output circuit board 28 (the direction along the line CC ′). Are arranged, and the RF input terminal 21a and the RF output terminal 21b are arranged in a direction perpendicular to the long side direction (a direction along the line AA ′).

  Further, since the semiconductor device 24, the input circuit board 26, and the output circuit board 28 are arranged as shown in FIG. 10, the input strip line to which the RF input terminal 21a is connected in the convex feedthrough 25 portion of the input section. 19 a is connected to the input matching circuit 17 from the long side direction of the input circuit board 26, and the output strip line 19 b to which the RF output terminal 21 b is connected in the convex feedthrough 25 portion of the output section is connected to the output circuit board 28. The output matching circuit 18 is connected from the long side direction.

  In the package 1a according to the comparative example shown in FIG. 10, since the warp is in the long side direction of the conductor base plate 200, warping occurs in the C-C 'direction as shown in FIG. Further, in the package 1a according to the comparative example shown in FIG. 10, since the semiconductor device 24, the input circuit board 26, and the output circuit board 28 are arranged as shown in FIG. 10, as shown in FIG. Warping also occurs in the A ′ direction.

  In the schematic planar pattern configuration of the package 1a according to the comparative example, a diagram for explaining the direction CC ′ and AA ′ of the piece-like warpage is expressed as shown in FIG. The warp in the 'direction is expressed as shown in FIG. 13B, and the warp in the CC' direction is expressed as shown in FIG. 13C.

  In the schematic planar pattern configuration of the package 1a according to the comparative example, a diagram for explaining bowl-shaped warping directions CC ′ and AA ′ is expressed as shown in FIG. The warping in the 'direction is expressed as shown in FIG. 14 (b), and the warping in the CC' direction is expressed as shown in FIG. 14 (c).

  Since heat is applied when the board is mounted and when the cap is soldered, warping occurs during cooling due to the difference in linear thermal expansion coefficient between the board and the cap and the package. In the case of a flat surface, since the strength is the same in both the A-A ′ direction and the C-C ′ direction, the directions are almost concentric. Exactly, since it is affected by the shape of the substrate to be mounted, some distortion occurs and warps in a piece shape or bowl shape.

(Semiconductor element structure)
An enlarged view of a schematic planar pattern configuration of the semiconductor device 24 mounted on the package according to the embodiment is represented as shown in FIG. 15A, and an enlarged view of a portion J in FIG. It is expressed as shown in 15 (b). Moreover, it is the structural examples 1-4 of the semiconductor device 24 mounted in the package which concerns on embodiment, Comprising: The typical cross-section structural examples 1-4 along the IV-IV line of FIG.15 (b) are respectively FIG. To be expressed as shown in FIG.

  In the semiconductor device 24 mounted on the package according to the embodiment, the plurality of FET cells FET1 to FET10 include a semi-insulating substrate 110 and a first surface of the semi-insulating substrate 110 as shown in FIGS. The gate finger electrode 124, the source finger electrode 120, and the drain finger electrode 122, each having a plurality of fingers, and the first surface of the semi-insulating substrate 110, the gate finger electrode 124, the source finger electrode 120, and the drain A plurality of gate terminal electrodes G1, G2,..., G10 formed by bundling a plurality of fingers for each finger electrode 122, a plurality of source terminal electrodes S11, S12, S21, S22,..., S101, S102 and a drain terminal electrode D1 , D2,..., D10 and source terminals VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 disposed under the poles S11, S12, S21, S22,..., S101, S102, and the opposite side of the first surface of the semi-insulating substrate 110. Ground electrodes (disposed on the second surface and connected to the source terminal electrodes S11, S12, S21, S22,..., S101, S102 via the VIA holes SC11, SC12, SC21, SC22,. (Not shown).

  The bonding wire 12 is connected to the gate terminal electrodes G1, G2,..., G10, the bonding wire 14 is connected to the drain terminal electrodes D1, D2,..., D10, and the source terminal electrodes S11, S12, S21, S22. ,..., S101, S102, VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 are formed on the inner walls of the VIA holes SC11, SC12, SC21, SC22,. The source terminal electrodes S11, S12, S21, S22,..., S101, S102 are formed on the barrier metal layer (not shown) and the filling metal layer (not shown) that is formed on the barrier metal layer and fills the VIA hole. It is connected to a ground electrode (not shown).

  The semi-insulating substrate 110 is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or One of the diamond substrates.

(Structural example 1)
As shown in FIG. 16, the configuration example 1 of the FET cell of the semiconductor device 24 mounted on the package according to the embodiment includes a semi-insulating substrate 110 and a nitride compound disposed on the semi-insulating substrate 110. Semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride compound semiconductor layer 112, and aluminum gallium nitride layer (Al _x Ga) _1-x N) (0.1 ≦ x ≦ 1) 118, a source finger electrode (S) 120, a gate finger electrode (G) 124, and a drain finger electrode (D) 122. A two-dimensional electron gas (2DEG) layer is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. 116 is formed. In the configuration example 1 shown in FIG. 16, a high electron mobility transistor (HEMT) is shown.

(Structural example 2)
As shown in FIG. 17, the configuration example 2 of the FET cell of the semiconductor device 24 mounted on the package according to the embodiment includes a semi-insulating substrate 110 and a nitride compound disposed on the semi-insulating substrate 110. On semiconductor layer 112, source region 126 and drain region 128 disposed on nitride compound semiconductor layer 112, source finger electrode (S) 120 disposed on source region 126, on nitride compound semiconductor layer 112 A gate finger electrode (G) 124 disposed on the drain region 128 and a drain finger electrode (D) 122 disposed on the drain region 128. A Schottky contact is formed at the interface between the nitride-based compound semiconductor layer 112 and the gate finger electrode (G) 124. In Configuration Example 2 shown in FIG. 17, a metal-semiconductor field effect transistor (MESFET) is shown.

(Structural example 3)
As shown in FIG. 18, the configuration example 3 of the FET cell of the semiconductor device 24 mounted on the package according to the embodiment includes a semi-insulating substrate 110 and a nitride-based compound disposed on the semi-insulating substrate 110. Semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride compound semiconductor layer 112, and aluminum gallium nitride layer (Al _x Ga) _1-x N) (0.1 ≦ x ≦ 1) 118 source finger electrode (S) 120 and drain finger electrode (D) 122, and aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 and a gate finger electrode (G) 124 disposed in a recess portion. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In the configuration example 3 illustrated in FIG. 18, the HEMT is illustrated.

(Structural example 4)
The configuration example 4 of the FET cell of the semiconductor device 24 mounted on the package according to the embodiment includes a semi-insulating substrate 110 and a nitride compound disposed on the semi-insulating substrate 110, as shown in FIG. Semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride compound semiconductor layer 112, and aluminum gallium nitride layer (Al _x Ga) _1-x N) (0.1 ≦ x ≦ 1) 118 source finger electrode (S) 120 and drain finger electrode (D) 122, and aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 and a gate finger electrode 124 disposed in a two-stage recess portion. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In the configuration example 4 illustrated in FIG. 19, the HEMT is illustrated.

  Moreover, in the above configuration examples 1 to 4, the nitride-based compound semiconductor layer 112 other than the active region is used as an electrically inactive element isolation region. Here, the active region refers to the 2DEG layer 116 immediately below the source finger electrode 120, the gate finger electrode 124, and the drain finger electrode 122, between the source finger electrode 120 and the gate finger electrode 124, and between the drain finger electrode 122 and the gate finger electrode 124. 2 DEG layer 116.

As another method for forming the element isolation region, the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a part of the nitride-based compound semiconductor layer 112 in the depth direction are used. It can also be formed by ion implantation. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. The dose accompanying ion implantation is, for example, about 1 × 10 ¹⁴ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV.

A passivation insulating layer (not shown) is formed on the element isolation region and the device surface. As this insulating layer, for example, a nitride film, an alumina (Al ₂ O ₃ ) film, an oxide film (SiO ₂ ), an oxynitride film (SiON) or the like deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) method is formed. be able to.

  The source finger electrode 120 and the drain finger electrode 122 are made of, for example, Ti / Al. The gate finger electrode 124 can be formed of, for example, Ni / Au.

  In the semiconductor device 24 mounted on the package according to the embodiment, the longitudinal pattern lengths of the gate finger electrode 124, the source finger electrode 120, and the drain finger electrode 122 are microwave / millimeter wave / submillimeter wave and the operating frequency. As the value increases, it is set shorter. For example, in the millimeter wave band, the pattern length is about 25 μm to 50 μm.

  Further, the width of the source finger electrode 120 is, for example, about 40 μm, and the width of the source terminal electrodes S11, S12, S21, S22,..., S101, S102 is, for example, about 100 μm. Further, the formation width of the VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 is, for example, about 10 μm to 40 μm.

  According to the package of the present embodiment, the long sides of the circuit board and the semiconductor device are arranged perpendicular to the sides of the conductor base plate and / or the metal wall having a gentle arc.

  According to the package according to the present embodiment, strength is obtained by giving an arc to the conductor base plate and / or the metal wall.

  According to the package according to the present embodiment, by generating a gentle arc in advance in the base plate material and the metal outer wall, it is possible to suppress the occurrence of warping during bonding, board mounting, and cap soldering.

  According to the package according to the present embodiment, the circuit board and the semiconductor device are mounted on the base plate on which the gentle arc is drawn by making the long side of the component mounting the arrangement perpendicular to the side having the gentle arc. The circuit board and the semiconductor device can be prevented from cracking when the package mounted with is screwed to the housing.

  According to this embodiment, a package with less warping of the base surface can be provided.

[Other embodiments]
Although the present embodiment and the modification have been described, the embodiment and the modification are presented as examples, and are not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  The semiconductor device mounted on the package according to the embodiment is not limited to the FET and HEMT, but is also an LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor) or a hetero-junction bipolar transistor (HBT). Needless to say, an amplifying element such as), a MEMS (Micro Electro Mechanical Systems) element, and the like can also be applied.

  As described above, various embodiments that are not described herein are included.

DESCRIPTION OF SYMBOLS 1, 1a ... Package 10 ... Metal cap 11, 12, 14, 15 ... Bonding wire 14a ... Metal seal ring 16 ... Metal wall 17 ... Input matching circuit 18 ... Output matching circuit 19a ... Input strip line 19b ... Output strip line 20 ... Feedthrough lower layer 21a ... RF input terminal 21b ... RF output terminal 22 ... feedthrough upper layer 24 ... Semiconductor device 25 ... convex feedthrough 26 ... input circuit board 28 ... output circuit board 34 ... through holes 70a, 70b ... screw 100a 100b ... end face 110 ... semi-insulating substrate 112 ... nitride compound semiconductor layer (GaN epitaxial growth layer)
116: Two-dimensional electron gas (2DEG) layer 118: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
120 ... Source finger electrode 122 ... Drain finger electrode 124 ... Gate finger electrode 126 ... Source region 128 ... Drain region 200 ... Conductor base plates G, G1, G2, ..., G10 ... Gate terminal electrodes S, S11, S12, ..., S101, S102 ... Source terminal electrodes D, D1, D2, ..., D10 ... Drain terminal electrodes SC11, SC12, ..., SC91, SC92, SC101, SC102 ... VIA holes

Claims (11)

A conductor base plate;
A semiconductor device disposed on the conductor base plate;
And a metal wall made of a material different from that of the conductor base plate, the conductor base plate having a gentle arc on a base surface.   The package of claim 1, wherein the metal wall has a gentle arc.   The package according to claim 1, wherein the pair of opposing end faces of the conductor base plate have a gentle arc of 10 µm.   The package according to claim 1, wherein a long side of the semiconductor substrate is disposed perpendicular to a side having an arc of the conductor base plate having the gentle arc. An input circuit board and an output circuit board disposed adjacent to the semiconductor device on the conductor base plate surrounded by the metal wall;
2. The package according to claim 1, wherein the long sides of the input circuit board and the output circuit board are disposed perpendicular to the sides of the conductor base plate having the gentle arc. A metal seal ring disposed on the metal wall;
The package according to claim 1, further comprising a metal cap disposed on the metal seal ring. A through hole provided in the input / output part of the metal wall;
A feedthrough lower layer portion fitted in the through hole and disposed on the conductor base plate;
The package according to any one of claims 1 to 6, further comprising a feedthrough upper layer part fitted in the through hole and disposed on the feedthrough lower layer part. In the input part of the metal wall, an input strip line arranged between the feedthrough lower layer part and the feedthrough upper layer part,
The package according to claim 7, further comprising: an output strip line disposed between the feedthrough lower layer portion and the feedthrough upper layer portion at the output portion of the metal wall. An input matching circuit disposed on the input circuit board and connected to the input stripline;
An output matching circuit disposed on the output circuit board and connected to the output stripline;
The package according to claim 8, further comprising: a bonding wire that connects the semiconductor device to the input matching circuit and the output matching circuit. The semiconductor device includes:
A semi-insulating substrate;
A gate finger electrode, a source finger electrode and a drain finger electrode disposed on the first surface of the semi-insulating substrate, each having a plurality of fingers;
A plurality of gate terminal electrodes arranged on the first surface of the semi-insulating substrate and formed by bundling a plurality of fingers for each of the gate finger electrode, the source finger electrode and the drain finger electrode; A drain terminal electrode;
A VIA hole disposed under the source terminal electrode;
2. A ground electrode disposed on a second surface opposite to the first surface of the semi-insulating substrate and connected to the source terminal electrode via the VIA hole. 10. The package according to any one of items 9.   The semi-insulating substrate is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or The package according to claim 10, wherein the package is any one of a diamond substrate.