CN112310215A - Enhanced high electron mobility transistor device and method of fabricating the same - Google Patents

Enhanced high electron mobility transistor device and method of fabricating the same Download PDF

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CN112310215A
CN112310215A CN201911004925.2A CN201911004925A CN112310215A CN 112310215 A CN112310215 A CN 112310215A CN 201911004925 A CN201911004925 A CN 201911004925A CN 112310215 A CN112310215 A CN 112310215A
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nitride layer
aluminum nitride
low
temperature aluminum
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CN112310215B (en
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陈智伟
温文莹
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Nuvoton Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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Abstract

The invention provides an enhanced high electron mobility transistor element and a manufacturing method thereof. The enhanced high electron mobility transistor element comprises a channel layer, a barrier layer, a reverse polarization layer, a low-temperature aluminum nitride layer, a P-type gallium nitride layer, a grid electrode, a source electrode and a drain electrode which are sequentially arranged on a substrate. The grid is arranged on the P-type gallium nitride layer, and the source electrode and the drain electrode are arranged on the low-temperature aluminum nitride layers at two sides of the grid.

Description

Enhanced high electron mobility transistor device and method of fabricating the same
Technical Field
The present invention relates to a High Electron Mobility Transistor (HEMT) technology, and more particularly, to an enhanced-mode High Electron Mobility Transistor (HEMT) device and a method of fabricating the same.
Background
In recent years, HEMT devices based on group III-V compound semiconductors have been widely used in the field of high-power electronic devices because of their characteristics such as low resistance, high breakdown voltage, and fast switching frequency. Generally, HEMT devices can be classified into depletion or normally-on transistor devices and enhancement or normally-off transistor devices. Enhancement mode transistor elements have gained considerable attention in the industry because of the added security they provide and because they are easier to control by simple, low cost driver circuits. Recently, P-type GaN enhancement mode HEMT devices have been the focus of research, and it is expected that increasing the doping concentration in P-type GaN will further increase the threshold voltage (Vth) of the devices.
However, the P-type GaN enhancement structure is usually processed at high temperature, and the dopant (e.g., mg) therein diffuses into the channel layer, so that two-dimensional electron gas (2DEG) cannot be generated, thereby causing device characteristics anomalies such as Vth shift, Ron increase and reliability failure.
Disclosure of Invention
The invention provides an enhancement type high electron mobility transistor element, which can inhibit the redistribution (redistribution) of dopants in a P-type gallium nitride layer and maintain the characteristics of the enhancement type element.
The invention also provides a manufacturing method of the enhanced high electron mobility transistor element, which can reduce the mask process and manufacture the HEMT element capable of inhibiting the redistribution of the dopant and maintaining the characteristics of the enhanced element.
The invention relates to an enhanced high electron mobility transistor element, which comprises a channel layer arranged on a substrate, a barrier layer arranged on the channel layer, a reverse polarization layer arranged on the barrier layer, a low-temperature aluminum nitride layer arranged on the reverse polarization layer, a P-type gallium nitride layer arranged on the low-temperature aluminum nitride layer, a grid arranged on the P-type gallium nitride layer, and a source electrode and a drain electrode which are arranged on the low-temperature aluminum nitride layer at two sides of the grid.
In an embodiment of the invention, the thickness of the low temperature aluminum nitride layer is between 1nm and 20 nm.
In an embodiment of the invention, a material of the anti-polarization layer includes InXGa1-XN, and X is 0.15-0.3.
In an embodiment of the invention, the antipolarization layer includes a graded indium doping concentration, and the graded indium doping concentration varies from low to high from a position adjacent to the barrier layer toward the low temperature aluminum nitride layer.
In an embodiment of the invention, a thickness of the anti-polarization layer is greater than 10nm and less than 80 nm.
In an embodiment of the invention, the dopant of the P-type gan layer is, for example, mg.
In an embodiment of the invention, the enhancement mode hemt device may further include a buffer layer between the channel layer and the substrate and a nucleation layer between the buffer layer and the substrate.
The invention relates to a manufacturing method of an enhanced high electron mobility transistor element, which comprises the steps of sequentially forming a channel layer, a barrier layer, a depolarizing layer, a low-temperature aluminum nitride layer and a P-type gallium nitride layer on a substrate by utilizing an epitaxial process, then selectively etching the P-type gallium nitride layer until part of the low-temperature aluminum nitride layer is exposed, forming a grid on the P-type gallium nitride layer, and simultaneously forming a source electrode and a drain electrode on the low-temperature aluminum nitride layer exposed at two sides of the P-type gallium nitride layer.
In another embodiment of the present invention, the temperature for forming the low temperature aluminum nitride layer is between 700 ℃ and 800 ℃.
In another embodiment of the present invention, the temperature for forming the channel layer, the barrier layer, the reverse polarization layer and the P-type gallium nitride layer is above 1000 ℃.
In another embodiment of the present invention, a dopant such as magnesium is used to form the P-type gan layer.
Based on the above, the present invention utilizes the specific structure between the channel layer and the P-type gan layer to suppress the redistribution of the dopant in the P-type gan layer and maintain the characteristics of the enhancement type device. Moreover, because the specific structure can inhibit the dopant in the P-type gallium nitride layer from diffusing out in the subsequent high-temperature process, the metal electrodes (namely the grid electrode, the source electrode and the drain electrode) can be formed in the same (mask) process, thereby greatly reducing the time and the cost of the process.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic cross-sectional view of an enhancement mode hemt device according to an embodiment of the present invention.
FIG. 2 is a diagram showing the band structure of the active region in the simulation comparative examples 1 to 2 and the simulation experimental example 1.
Fig. 3 is a diagram showing an energy band structure and a carrier concentration distribution of an inactive region in simulation experimental example 1.
Fig. 4 is a flow chart illustrating a method of fabricating an enhancement mode hemt device according to another embodiment of the present invention.
Reference numerals:
10: enhanced HEMT element
100: substrate
102: channel layer
104: barrier layer
106: reverse polarization layer
108: low temperature aluminum nitride layer
110: p-type gallium nitride layer
112 a: grid electrode
112 b: source electrode
112 c: drain electrode
114: buffer layer
116: nucleation layer
200 a: active region
200 b: non-active region
400. 402, 404: step (ii) of
Detailed Description
The following embodiments are described in detail with reference to the attached drawings, but the embodiments are not provided to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, like elements in the following description will be described with like reference numerals.
Fig. 1 is a schematic cross-sectional view of an enhancement mode hemt device according to an embodiment of the present invention.
Referring to fig. 1, the enhancement mode hemt 10 includes a substrate 100, a channel layer 102, a barrier layer 104, a counter-polarization layer 106, a low temperature aluminum nitride layer 108, a P-type gallium nitride (GaN) layer 110, a gate 112a, a source 112b and a drain 112 c. In an embodiment, the material of the substrate 100 is, for example, sapphire, silicon (Si), or silicon carbide (SiC), but the present invention is not limited thereto. In one embodiment, the channel layer 102 is a material such as a group III nitride or III-V compound semiconductor material, e.g., GaN. The channel layer 102 may be a doped or undoped layer. In one embodiment, the material of the barrier layer 104 is, for example, a group III nitride, such as a group III-V compound semiconductor material, and may have a single layer or a multi-layer structure. In one embodiment, the barrier layer 104 includes aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum nitride (AlN), or aluminum gallium indium nitride (AlGaInN), or combinations thereof. In one embodiment, the barrier layer 104 may be a doped or undoped layer. The P-type gan layer 110 is a region for forming a two-dimensional electron gas or a region with a relatively low electron density, and thus the material of the P-type gan layer 110 is gan doped with a dopant (e.g., mg).
In fig. 1, in order to suppress the dopant redistribution (redistribution) in the P-type gan layer 110, a low temperature aluminum nitride layer 108 is disposed below the P-type gan layer 110, wherein the thickness of the low temperature aluminum nitride layer 108 is, for example, between 1nm and 20nm, and the thickness of the low temperature aluminum nitride layer 108 is preferably about 10nm in terms of film formation. The term "low temperature" aluminum nitride layer 108 is used herein to refer to an aluminum nitride layer formed using an epitaxial temperature that is lower than the temperature typically used in the epitaxial process for HEMT devices (e.g., one thousand degrees C), such as an aluminum nitride layer formed at an epitaxial temperature between 700℃ and 800℃. In the present embodiment, a counter-polarization layer 106 is required to be disposed between the low temperature aluminum nitride layer 108 and the barrier layer 104 for maintaining the characteristics of an enhancement mode (E-mode) device, wherein the thickness of the counter-polarization layer 106 is greater than 10nm and less than 80nm, for example, between 30nm and 60 nm. In one embodiment, the material of the reverse polarization layer 106 is, for example, InXGa1-XN, and X is 0.15-0.3. In another embodiment, the reverse polarization layer 106 has a graded indium doping concentration, and the graded indium doping concentration is selected fromAdjacent to barrier layer 104, the transition is from high to low towards low temperature aluminum nitride layer 108, but the invention is not limited thereto. The graded indium doping concentration varies from low to high from the point of view of a high lattice match with the low temperature aluminum nitride layer 108 from the point of the adjacent barrier layer 104 toward the low temperature aluminum nitride layer 108.
In addition, a buffer layer 114 may be disposed between the channel layer 102 and the substrate 100 to reduce the lattice constant difference and the thermal expansion coefficient difference between the substrate 100 and the channel layer 102. In one embodiment, the buffer layer 114 is made of a material such as a group III nitride, e.g., a group III-V compound semiconductor material, and may have a single layer or a multi-layer structure. In one embodiment, the material of the buffer layer 114 includes aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium nitride (AlInN), aluminum gallium indium nitride (AlGaInN), or a combination thereof. In addition, a nucleation layer 116 is disposed between the buffer layer 114 and the substrate 100, which further reduces the defect density of the channel layer 102 and facilitates the growth of subsequent layers. In one embodiment, the material of the nucleation layer 116 is, for example, aluminum nitride (AlN).
Referring to fig. 1, the gate 112a is disposed on the P-type gan layer 110, and the source 112b and the drain 112c are disposed on the low temperature aluminum nitride layer 108 at two sides of the gate 112 a. The material of the gate 112a, the source 112b, and the drain 112c may each independently comprise a metal or a metal nitride (e.g., Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al, or combinations thereof), a metal silicide (e.g., WSix), or other material that may form a Schottky contact with a III-V compound semiconductor. In one embodiment, the gate 112a, the source 112b and the drain 112c are the same material.
In order to verify the effects of the present invention, the following simulation experiments were performed for different structures, but the scope of the present invention is not limited to the following experiments.
Experimental example 1 simulation
The simulated structure is shown in FIG. 1, wherein the simulated P-type GaN layer 110 has a thickness of 40nm and a Mg doping concentration of 1E18 cm-3The low temperature aluminum nitride layer 108 has a thickness of 10 angstroms
Figure BDA0002242454780000051
The counter-polarization layer 106 is In with a thickness of 60nm0.15Ga0.85N。
Simulation comparative example 1
The simulation structure is similar to that of simulation experiment example 1, except that there is no low-temperature aluminum nitride layer and no counter-polarization layer, only a P-type gallium nitride layer, and the other conditions are the same.
Simulation comparative example 2
The simulated structure was similar to that of the simulated experimental example 1, except that the low temperature aluminum nitride layer was not present, and the other conditions were the same.
Referring to fig. 1, the band structure (band diagram) from the P-type gan layer 110 to the channel layer 102 is simulated for the active region (active region)200a of the simulation comparative examples 1 to 2 and the simulation experimental example 1 at Vg of 0V, and the result is shown in fig. 2.
As can be seen from FIG. 2, the band contact of comparative example 2 was simulated to 0eV (i.e., E)F) The element is in a continuous conduction state, so that it cannot reach E-mode, and the band of the simulation experiment example 1 does not contact EFIt was confirmed that it can maintain the characteristics of the E-mode element. Further, in the conventional P-GaN, E-mode band diagram is similar to that of comparative example 1, and although the band does not reach Ef, the band is not brought into contact with Ef, but low-temperature AlN is inserted between the P-type gallium nitride layer 110 and the barrier layer 104 to prevent diffusion, and the band contacts 0eV (i.e., E) as in comparative example 2F) Since the channel 2DEG formed cannot maintain the characteristics of the E-mode device, it is necessary to add a polarization-reversing layer 106 between the low-temperature aluminum nitride layer 108 and the barrier layer 104, which has a band far from 0eV (i.e., E) as in the simulation experiment example 1F) Thereby achieving the E-mode device characteristics.
Fig. 3 is a graph further illustrating the band structure and carrier concentration distribution from the low temperature aluminum nitride layer 108 to the channel layer 102 for the inactive region 200b of the simulation example 1. As can be seen from fig. 3, the carrier concentration (Ns) is concentrated in a large amount at the position of the quantum well (where the peak of fig. 3 is located) and moves freely and rapidly in the vertical direction, which means that two-dimensional electron gas is generated, and it is confirmed that the structure of the present invention can suppress the redistribution of dopants in the P-type gan layer 110, but does not affect the two-dimensional electron gas.
Experimental example 2 for simulation
The simulated structure was similar to that of the simulated experimental example 1, except that the thickness of the reverse polarization layer and the doping concentration of indium were changed as shown in table 1 below.
Then, simulation tests were performed on the active region and the inactive region of simulation experimental example 2 to confirm the states thereof, and the results are set forth in table 1.
TABLE 1
Figure BDA0002242454780000061
The E-mode indicates that the simulated high electron mobility transistor element has an E-mode element characteristic.
D-mode indicates that the simulated high electron mobility transistor element has a depletion mode (D-mode) element characteristic.
Thus, In, which is a material for the reverse polarization layer, can be obtained from Table 1XGa1-XWhen X in N is 0.15 to 0.3 and the thickness is more than 10nm and less than 80nm, the E-mode device characteristics can be maintained, and the E-mode device characteristics can be more stably maintained with a thickness of 30nm to 60 nm.
Fig. 4 is a flow chart illustrating a method of fabricating an enhancement mode hemt device according to another embodiment of the present invention.
Referring to fig. 4, a channel layer, a barrier layer, a polarization-reversed layer, a low-temperature aluminum nitride layer, and a P-type gallium nitride layer are sequentially formed on a substrate by an epitaxial process 400, such as Metal Organic Chemical Vapor Deposition (MOCVD). The materials of the substrate, the channel layer and the blocking layer can refer to the previous embodiment, and thus are not described in detail. In one embodiment, the material of the anti-polarization layer is InXGa1-XN (X is 0.15-0.3), the doping concentration of indium in gallium nitride can be controlled during deposition; in one embodiment, the doping concentration of indium in gallium nitride is a fixed value; in another embodiment, the counter-polarization layer has a graded indium doping concentration, e.g., from high to low from adjacent the barrier layer toward the low temperature aluminum nitride layer or from adjacent the barrier layer toward the low temperature aluminum nitride layerThe temperature of the aluminum nitride layer varies from low to high. As for the temperature for forming the low temperature aluminum nitride layer, for example, it is between 700 ℃ and 800 ℃, which is lower than the temperature generally used for the epitaxial process of the HEMT device. That is, the temperature for forming the channel layer, the barrier layer, the reverse polarization layer, and the P-type gallium nitride layer is higher than 800 ℃, for example, 1000 ℃. In addition, a dopant such as magnesium is used to form the P-type GaN layer, and the doping concentration is 1E18 cm-3～1E20 cm-3。
Next, in step 402, the P-type gan layer is selectively etched until a portion of the low temperature aluminum nitride layer is exposed. For example, after forming the P-type gan layer, a patterned mask may be formed on the P-type gan layer to expose a portion of the P-type gan layer; then, the exposed P-type GaN layer is etched by using the low-temperature aluminum nitride layer as a stop layer. The patterned mask may then be removed.
Then, in step 404, a gate, a source and a drain are formed simultaneously. Specifically, the gate is formed on the P-type gan layer, the source and the drain are formed on the low temperature aluminum nitride layer exposed at both sides of the P-type gan layer, and the gate, the source and the drain can be formed by etching or Lift Off (Lift Off). The gate, the source and the drain are made of the same material, and the material type can refer to the previous embodiment, so that the description is omitted.
In summary, in the invention, in addition to the barrier layer, the low temperature aluminum nitride layer and the counter-polarization layer are disposed between the channel layer and the P-type gallium nitride layer, so that the redistribution of dopants in the P-type gallium nitride layer can be suppressed, and the characteristics of the enhancement type device can be maintained. Moreover, because the low-temperature aluminum nitride layer can inhibit the dopant in the P-type gallium nitride layer from diffusing out in the subsequent high-temperature process, the metal electrodes (namely the grid electrode, the source electrode and the drain electrode) needing the high-temperature process can be formed in the same (mask) process, and the time and the cost of the process can be greatly reduced.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (11)

1. An enhancement mode high electron mobility transistor device, comprising:
a channel layer disposed on a substrate;
a blocking layer disposed on the channel layer;
a reverse polarization layer configured on the barrier layer;
a low temperature aluminum nitride layer disposed on the counter-polarization layer;
a P-type gallium nitride layer disposed on the low temperature aluminum nitride layer;
a grid electrode, configured on the P-type gallium nitride layer; and
and the source electrode and the drain electrode are arranged on the low-temperature aluminum nitride layer at two sides of the grid electrode.
2. The enhancement mode hemt of claim 1, wherein said low temperature aluminum nitride layer has a thickness between 1nm and 20 nm.
3. The enhancement mode high electron mobility transistor element according to claim 1, wherein a material of the counter polarization layer comprises InXGa1-XN, and X is 0.15-0.3.
4. The enhancement mode hemt of claim 3, wherein said counter-polarization layer comprises a graded indium doping concentration, said graded indium doping concentration varying from low to high from adjacent said barrier layer towards said low temperature aluminum nitride layer.
5. The enhancement mode hemt of claim 1, wherein said counter polarization layer has a thickness greater than 10nm and less than 80 nm.
6. The enhancement mode hemt of claim 1, wherein said P-type gan layer is doped with mg.
7. The enhancement mode hemt of claim 1, further comprising:
the buffer layer is positioned between the channel layer and the substrate; and
a nucleation layer between the buffer layer and the substrate.
8. A method for fabricating an enhanced HEMT device, comprising:
forming a channel layer, a barrier layer, a reverse polarization layer, a low-temperature aluminum nitride layer and a P-type gallium nitride layer on a substrate in sequence by using an epitaxial process;
selectively etching the P-type gallium nitride layer until part of the low-temperature aluminum nitride layer is exposed; and
and forming a grid electrode on the P-type gallium nitride layer, and simultaneously forming a source electrode and a drain electrode on the low-temperature aluminum nitride layer exposed from two sides of the P-type gallium nitride layer.
9. The method of claim 8, wherein the low temperature aluminum nitride layer is formed at a temperature of between 700 ℃ and 800 ℃.
10. The method according to claim 8, wherein a temperature for forming the channel layer, the barrier layer, the counter-polarization layer, and the P-type gallium nitride layer is 1000 ℃ or higher.
11. The method of claim 8, wherein the dopant used to form the P-type GaN layer is Mg.
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