WO2024011610A1

WO2024011610A1 - Semiconductor device and method for manufacturing thereof

Info

Publication number: WO2024011610A1
Application number: PCT/CN2022/106062
Authority: WO
Inventors: Ronghui Hao; King Yuen Wong
Original assignee: Innoscience (Zhuhai) Technology Co., Ltd.
Priority date: 2022-07-15
Filing date: 2022-07-15
Publication date: 2024-01-18
Also published as: CN117897818A

Abstract

A semiconductor device includes a substrate, an insulating layer, and an epitaxial structure. The first substrate layer is doped with p-type dopants. The second substrate layer is doped with n-type dopants and disposed over the first substrate layer. The insulating layer is disposed over the first substrate layer and makes contact with at least one side surface of the second substrate layer. The insulating layer and the second substrate layer collectively cover a top surface of the first substrate layer. The epitaxial structure is disposed over and makes contact with top surfaces of the second substrate layer and the insulating layer.

Description

[Title established by the ISA under Rule 37.2] SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF

Inventors: Ronghui HAO; King Yuen WONG

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor device. More specifically, the present disclosure relates to a nitride-based semiconductor device having a substrate integrated with a p-n junction/diode and an insulation layer.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a substrate, an insulating layer, and an epitaxial structure. The first substrate layer is doped with p-type dopants. The second substrate layer is doped with n-type dopants and disposed over the first substrate layer. The insulating layer is disposed over the first substrate layer and makes contact with at least one side surface of the second substrate layer. The insulating layer and the second substrate layer collectively cover a top surface of the first substrate layer. The epitaxial structure is disposed over and makes contact with top surfaces of the second substrate layer and the insulating layer.

In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first ion-implanting process is performed on a p-type doped intermediate substrate, such that a top portion of the intermediate substrate is doped to be an n-type doped, and a bottom portion of the intermediate substrate is remained to be p-type doped. The bottom portion serves as a first substrate layer of the substrate and the part of the top portion serves as a second substrate layer of the substrate. A second ion-implanting process is performed on a periphery part of the intermediate substrate, such that at least one of a periphery part of the top portion and a periphery of the bottom portion are formed to be an insulating layer of the substrate. An epitaxial structure is formed on the substrate.

In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a substrate, an implantation structure, and an epitaxial structure. The substrate includes a first portion, a second portion, and an implantation structure. The first portion has a first conductive type. The second portion is disposed over the first portion and has a second conductive type which is opposite to the first conductive type. The implantation structure is disposed over the first portion and located at a side of the second portion. The implantation structure has a resistivity greater than that of any one of the first portion and the second portion. The epitaxial structure is disposed on and making contact with top surfaces of the second substrate layer and the insulating layer.

By the above configuration, in the present disclosure, the substrate includes substrate layers with different conductive type. The second substrate layer having N conductive type is disposed on/over/above the first substrate layer having P conductive type, such that a p-n junction/diode is formed between the first and second substrate layers. As such, a substrate integrated with a p-n diode can be achieved. Such a configuration can elevate withstand voltage of the semiconductor device in a vertical direction. Furthermore, the insulating layer is located on the first substrate layer and makes contact with a side surface of the second substrate layer, thereby blocking leakage current at a side of the substrate. Therefore, the semiconductor device of the present disclosure is adapted for high voltage operation and has a good reliability.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1A is a vertical cross-section view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 1B is an enlarged vertical cross-section view of a region A in FIG. 1A;

FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

FIG. 3 is a vertical cross-section view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 4 is a vertical cross-section view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 5 is a vertical cross-section view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 6 is a vertical cross-section view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 7 is a vertical cross-section view of a semiconductor device according to some embodiments of the present disclosure; and

FIG. 8 is a vertical cross-section view of a semiconductor device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

In order to achieve high voltage device, a silicon substrate with high resistance (HR silicon substrate) can be applied to introduce in a device, so as to improve withstand voltage of the device in a vertical direction. Due to polarization effect, an inversion layer of electrons is formed at an interface between an aluminum nitride buffer layer and the silicon substrate. However, as a high voltage is applied to such the device, leakage current issues will occur across edges of the aluminum nitride buffer layer and the silicon substrate, resulting in leakage current flowing from the inversion layer to the edges and further in poor reliability of the device.

On the other hand, applying a thicker buffer layer to a device can improve withstand voltage of the device in a vertical direction as well. Nevertheless, such a way would make a thickness of the device increase, failing to comply with trend of miniaturization of electronic devices. Additional stress issues would arise due to thick buffer layer.

At least to avoid the aforesaid issue, the present disclosure is to develop a novel structure for semiconductor device. The detailed structure/arrangement will be fully described as follows.

FIG. 1A is a vertical cross-section view of a semiconductor device 1A according to some embodiments of the present disclosure. The semiconductor device 1A includes a substrate 10A and an epitaxial structure 30.

In order to increase withstand voltage of the semiconductor device 1A in a vertical direction, the substrate 10A of the present disclosure adopts a novel structure.

Referring to FIG. 1A, formation of the substrate 10A includes two ion-implanting process. First of all, a first ion-implanting process is performed on a p-type doped intermediate substrate using n-type dopants to form an n-type doped top portion, and a bottom portion thereof is remained to be p-type doped. Therefore, at least one p-n junction/diode PN is formed between the n-type doped top portion and the p-type doped bottom portion.

Then, a second ion-implanting process is performed on a periphery part of the aforesaid intermediate substrate to covert the periphery part thereof into an insulation layer. The ions applied to the second ion-implanting process include a group III element, a group V element, a hydrogen element, an oxygen element, a fluorine element, or combinations thereof. The second ion-implanting process is aimed to destroy the crystal structure of the periphery part, so as to covert such part to an insulating layer 106A.

As such, a substrate 10A including substrate layer 102A, a substrate layer 104A, and an insulating layer 106A, is formed. The substrate layers 102A, 104A and the insulating layer 106A can serve as different portions of the substrate 10A.

The exemplary materials of the substrate 10A can include silicon. The silicon substrate 10A has a <111> orientation. The substrate layer 102A is doped with p-type dopants, in which the p-type dopants can include a group III element, such as boron (B) and gallium (Ga) . The substrate layer 104A is doped with n-type dopants, in which the n-type dopants can include a group V element, such as phosphorus (P) , arsenic (As) , or antimony (Sb) . Thus, the substrate layer 102A is doped to have P conductive type, and the substrate layer 104A is doped to have N conductive type which is opposite to P conductive type. The insulating layer 160 is formed by performing double ion-implanting processes, and thus the insulating layer 160 can be referred to as an implantation structure. After the double ion-implanting processes, the original crystal structure of the periphery part of the p-type doped intermediate substrate is destroyed, and thus the defect density of the periphery part of the intermediate substrate is greater than the other part of the intermediate substrate. The formed insulating layer 160 can referred as to a defect-rich layer. As such, the formed insulating layer 160 has a resistivity greater than that of any one of the substrate layers 102A, 104A. Furthermore, since the substrate layers 104A, 106A and insulation layer 106A are made from the same p-type doped intermediate substrate, the substrate layers 104A, 106A and insulation layer 106A collectively have the same elements, such as silicon and the applied group III element. Also, a top surface 106ts of the insulating layer 106A is coplanar with a top surface 104ts of the substrate layer 104A, since the insulating layer 106A and the substrate layer 104A are made from the same p-type doped intermediate substrate by double ion-implanting processes.

The substrate 102A has a sub-portion with thickness T1 (e.g., central portion) and sub-portions with thickness T2 (e.g., periphery portions) , in which the thickness T1 is greater than the thickness T2. Accordingly, the central portion is called a thicker portion and the periphery portions are called thinner portions. The substrate layer 104A is disposed on/over/above the thicker portion of the substrate layer 102A. The insulating layer 106A is disposed on/over/above thinner portions of the substrate layer 102A. The substrate layer 104A has two opposite outer side surfaces SS1, SS2. The insulating layer 106A makes contact with the outer side surfaces SS1, SS2 of the substrate layer 104A, such that the substrate layer 104A is confined by the insulating layer 106A. Portions of the insulating layer 106A are located at two opposite sides of the substrate layer 104A, respectively. The substrate layer 104A is surrounded by the insulating layer 106A. The insulating layer 106A has opposite inner and outer side surfaces. The inner side surface of the insulating layer 106A is covered by the substrate layers 102A, 104A. The outer side surface of the insulating layer 106A is free from coverage of the substrate layers 102A, 104A. The insulating layer 106A and the substrate layer 104A collectively cover a top surface 102ts of the substrate layer 102A.

The insulating layer 106A extends downward into a thickness of the substrate layer 102A, such that a bottom surface thereof is within a thickness of the substrate layer 102A. The insulating layer 106A extends downward in a vertically manner. A downward extending length of the insulating layer 106A is greater than a thickness of the substrate layer 104A. A width of the insulating layer 106A remains constant along a vertical direction. In the embodiment, the insulating layer 106A can have a rectangular profile. In some embodiments, the profile of the insulating layer 106A can have a square profile. An interface formed between the insulating layer 106A and the substrate 106A can be a flat interface.

The epitaxial structure 30 is disposed on/over/above the substrate layer 104A and the insulating layer 106A. The epitaxial structure 30 makes contact with the substrate layer 104A and the insulating layer 106A. Specifically, the epitaxial structure 30 includes a buffer layer 302, a nitride-based semiconductor layer 304, and a nitride-based semiconductor layer 306.

The buffer layer 302 is disposed on/over/above the insulation layer 106A and the substrate layer 104A. The buffer layer 302 is disposed between the nitride-based semiconductor layer 304 and the substrate layer 104A. The buffer layer 302 makes contact with the top surfaces 104ts, 106ts of the insulation layer 106A and the substrate layer 104A. The buffer layer 302 can be configured to reduce lattice and thermal mismatches between the substrate layer 104A and the nitride-based semiconductor layer 302, thereby curing defects due to the mismatches/difference. The buffer layer 302 may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer 302 can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In the embodiment, the material of the buffer layer 302 can be selected as AlN. As a high voltage is applied to such the semiconductor device 1A, an inversion layer of electrons is formed at an interface between the AlN buffer layer 302 and the silicon substrate layer 104A due to the polarization effect. Since the inversion layer of electrons can act as a parasitic channel, it may raise leakage current issue. One of possible leakage current path is from an inversion layer of electrons to outer sidewalls horizontally. Accordingly, the insulation layer 106A confines the substrate layers 102A and 104A, such that the formed inversion layer is narrowed than the buffer layer 302 and spaced apart from sidewalls of the buffer layer 302. As such, the insulation layer 106 (i.e., current blocking layer) can effectively block leakage current flowing from the inversion layer. Thus, probability of current leakage occurring at a side surface of the substrate 10A can be greatly reduced, and the reliability of the semiconductor device 1A can be improved. The semiconductor device 1A is adapted for high voltage operation.

In some embodiments, the epitaxial structure 30 may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate layer 104A and the buffer layer 302. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate layer 104A and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 304 is disposed on/over/above the buffer layer 302. The nitride-based semiconductor layer 304 makes contact with the buffer layer 302. The nitride-based semiconductor layer 306 is disposed on/over/above the nitride-based semiconductor layer 304. The nitride-based semiconductor layer 306 makes contact with the nitride-based semiconductor layer 304.

The exemplary materials of the nitride-based semiconductor layer 304 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1. The exemplary materials of the nitride-based semiconductor layer 306 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤1.

The exemplary materials of the nitride-based semiconductor layers 304 and 306 are selected such that the nitride-based semiconductor layer 306 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 304, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 304 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 306 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV.

As such, the nitride-based semiconductor layers 304 and 306 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The electrodes E1 and E2 are disposed on/over/above the nitride-based semiconductor layer 306. The electrodes E1 and E2 can make contact with the nitride-based semiconductor layer 306. In some embodiments, the electrode E1 can serve as a source electrode. In some embodiments, the electrode E2 can serve as a drain electrode. In some embodiments, the electrode E1 can serve as a source electrode. In some embodiments, the electrode E2 can serve as a drain electrode. The role of the electrodes E1 and E2 depends on the device design.

In some embodiments, the electrodes E1 and E2 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the electrodes E1 and E2 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. Each of the electrodes E1 and E2 may be a single layer, or plural layers of the same or different composition. The electrodes E1 and E2 form ohmic contacts with the nitride-based semiconductor layer 306. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the electrodes E1 and E2.

In some embodiments, each of the electrodes E1 and E2 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer can include, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The doped nitride-based semiconductor layer 50 is disposed on/over/above the nitride-based semiconductor layer 306. The doped nitride-based semiconductor layer 50 makes contact with the nitride-based semiconductor layer 306. The gate electrode 52 is disposed on/over/above the doped nitride-based semiconductor layer 50 and the nitride-based semiconductor layer 306. The gate electrode 52 makes contact with the doped nitride-based semiconductor layer 50. The doped nitride-based semiconductor layer 50 is disposed between the gate electrode 52 and the nitride-based semiconductor layer 306.

The gate electrode 52 is narrower than the doped nitride-based semiconductor layer 30. In some embodiments, a width of the doped nitride-based semiconductor layer 50 is substantially the same as a width of the gate electrode 52. The profiles of the doped nitride-based semiconductor layer 50 and the gate electrode 52 are the same, for example, both of them are rectangular profiles. In other embodiments, the profiles of the doped nitride-based semiconductor layer 50 and the gate electrode 52 can be different from each other. For example, the profile of the doped nitride-based semiconductor layer 50 can be a trapezoid profile, the profile of the gate electrode 52 can be a rectangular profile.

In the exemplary illustration of FIG. 1B, the semiconductor device 1A is an enhancement mode device, which is in a normally-off state when the gate electrode 52 is at approximately zero bias. Specifically, the doped nitride-based semiconductor layer 50 may create at least one p-n junction with the nitride-based semiconductor layer 306 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the gate electrode 52 has different characteristics (e.g., different electron concentrations) than the remaining portion of the 2DEG region and thus is blocked.

Due to such mechanism, the semiconductor device 1A has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 52 or a voltage applied to the gate electrode 52 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 52) , the zone of the 2DEG region below the gate electrode 52 is kept blocked, and thus no current flows therethrough.

In some embodiments, the doped nitride-based semiconductor layer 50 can be omitted, such that the semiconductor device 1A is a depletion-mode device, which means the semiconductor device 1A in a normally-on state at zero gate-source voltage.

The doped nitride-based semiconductor layer 50 can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped nitride-based semiconductor layer 50 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer 304 includes undoped GaN and the nitride-based semiconductor layer 306 includes AlGaN, and the doped nitride-based semiconductor layer 50 is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the semiconductor device 1A into an off-state condition.

The exemplary materials of the gate electrode 52 may include metals or metal compounds. The gate electrode 52 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.

In the present disclosure, the epitaxial structure 30 is disposed/formed on the substrate 10A integrated with a p-n diode/junction PN, and the epitaxial structure 30 is electrically coupled/connected to the p-n diode/junction PN. In some embodiments, the electrode E1 (serving as a source electrode) and the substrate 10A can be electrically connected to the same ground voltage, and the electrode E2 (serving as a drain electrode) can be electrically connected to a drain voltage higher than the ground voltage. During such the operation, the p-n diode/junction PN is reversed biased, and the p-n diode/junction PN can share a part of voltage when the semiconductor device 1A is in a normally-off state, thereby improving withstand voltage of the semiconductor device 1A.

FIG. 1B is an enlarged vertical cross-section view of a region A in FIG. 1A. Referring to FIG. 1B, the substrate layer 102A and the substrate layer 104A collectively forms a depletion region DPR. In the embodiment, the doping concentration of the p-type dopants of the substrate layer 102A is different from that of the n-type dopants of the substrate layer 104A. As such, a thickness T4 of the depletion region DPR in the substrate layer 102A is different from a thickness T3 of the depletion region DPR in the substrate layer 104A.

For example, the doping concentration of the p-type dopants of the substrate layer 102A is greater than that of the n-type dopants of the substrate layer 104A. Thus, the substrate layer 102A can also be refereed as a p ⁺ substrate layer/region, and the substrate layer 104A can also be refereed as a n ^-substrate layer/region. The thickness T4 is greater than the thickness T3. By adjusting the ratio of the doping concentration of p-type dopants and the n-type dopants, the electrical property of the p-n diode/junction PN in the substrate 10A can be adjusted accordingly so as to get best result.

Different stages of a method for manufacturing the semiconductor device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, a p-type doped intermediate substrate 60 is provided.

Referring to FIG. 2B, a first ion-implanting process is performed on the p-type doped intermediate substrate 60 using n-type dopants, such that a top portion 62 of the intermediate substrate 60 is doped to be an n-type doped and a bottom portion 64 of the intermediate substrate 60 is remained to be p-type doped. Then, a thermal annealing process is performed during the step of the first ion-implanting process, so as to activate the n-type dopants in the top portion 62 and the p-type dopants in the bottom portion 64.

Referring to FIG. 2C, a mask layer ML is provided on the intermediate substrate 60 after the step of performing the first ion-implanting process to expose a periphery part of the intermediate substrate 60. Then, a second ion-implanting process is performed on a periphery part of the intermediate substrate 60, such that at least one of a periphery part of the top portion 62 and a periphery part of the bottom portion 64 are formed to be an insulating layer 106A of the substrate 10A. A part of the bottom portion 64 serves as a substrate layer 102A of the substrate 10A. A part of the top portion serves as a substrate layer 104A of the substrate 10A. The thickness of the substrate layer 102A/104A is controlled by the ion implanting depth of the first ion-implanting process. The thickness of the insulating layer 106A is controlled by the ion implanting depth of the second ion-implanting process. Thus, a substrate 10A including a substrate layer 102A, a substrate layer 104A, and an insulating layer 106A is formed.

Referring to FIG. 2D, an epitaxial structure 30 is formed on/over/above the substrate 10A. Specifically, a buffer layer 302 is formed on/over/above the substrate 10A. A nitride-based semiconductor layer 302 is formed on/over/above the buffer layer 302. A nitride-based semiconductor layer 304 is formed on/over/above the nitride-based semiconductor layer 302. Thereafter, the electrodes E1, E2, doped nitride-based semiconductor layer 50, and a gate electrode 52 are formed. Therefore, the semiconductor device 1A in FIG. 1A can be obtained.

FIG. 3 is a vertical cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure. The semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the thickness of the insulation layer 106B is less than that of the substrate layer 104B, such that a bottom surface of the insulation layer 106B is within a thickness of the substrate layer 104B. During the formation of the semiconductor device 1B, the depth of the insulation layer 106B can be controlled by the implantation energy of the second ion-implanting process, such that the formed insulation layer 106B is shallower than the substrate layer 104B. Such a design can reduce process cost and time.

FIG. 4 is a vertical cross-sectional view of a semiconductor device 1C according to some embodiments of the present disclosure. The semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the insulation layer 106C is located at only one side of the substrate layer 104C. Such a design can simplify the process and still meet a specific electrical requirement. For example, since the occupation of the insulation layer 106C is reduced, the ion-implanting process can get simplified. Further, the “only one side” insulation layer 106C can be set to align a drain electrode so leakage current issue is still improved even a high voltage is applied to the drain.

FIG. 5 is a vertical cross-sectional of a semiconductor device 1D according to some embodiments of the present disclosure. The semiconductor device 1D is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the insulating layer 106D has opposite inner and outer side surfaces. The inner and outer side surfaces of the insulating layer 106D are covered by the substrate layers 102D, 104D. The insulating layer 106D is spaced apart from an edge E of the substrate 10D. Such a design can make process have high tolerance.

FIG. 6 is a vertical cross-sectional of a semiconductor device 1E according to some embodiments of the present disclosure. The semiconductor device 1E is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that the insulating layer 106E extends downward in an inclined manner, such that opposite inner and outer side surfaces thereof are covered by the substrate layers 102E, 104E. During the formation of the semiconductor device 1E, the intermediate substrate can be tilted during performing the second ion-implanting process, thereby forming the inclined insulating layer 106E. The insulating layer 106E can have a parallelogram profile. Such a design can meet a specific electrical requirement.

FIG. 7 is a vertical cross-sectional of a semiconductor device 1F according to some embodiments of the present disclosure. The semiconductor device 1F is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that a width of the insulation layer 106F changes along a vertical direction. Specifically, a width of the insulation layer 106F gradually increases along the vertical direction. An interface IF1 formed between the insulation layer 106F and the substrate layer 102F/104F can be a curved interface, and the shape of the interface can be determined by at least one of recipes of the second ion-implanting process, such as temperature or pressure. Such a design can meet a specific electrical requirement.

FIG. 8 is a vertical cross-sectional of a semiconductor device 1G according to some embodiments of the present disclosure. The semiconductor device 1G is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1A, except that a width of the insulation layer 106G changes along a vertical direction. Specifically, a width of the insulation layer 106G gradually increases along the vertical direction. An interface IF2 formed between the insulation layer 106G and the substrate layer 102G/104G can be an inclined interface. The insulation layer 106G can have a triangle profile. Such a design can meet a specific electrical requirement.

In some embodiments, an interface formed between the insulation layer 106G and the substrate layer 102G/104G can be a combination of a curved interface and a flat interface, so as to achieve a specific electrical requirement.

Based on above, in the present disclosure, by performing double ion-implanting processes in a p-doped intermediate substrate, a p-n diode/junction and an insulation layer can be formed in a substrate. The p-n diode/junction of the substrate can improve withstand voltage of the semiconductor device instead of thickening the buffer layer. The insulation layer can prevent current leakage occurring at a side surface of the substrate. Thus, the semiconductor device of the present disclosure can be adapted for high voltage operation and has good reliability.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A semiconductor device, comprising:

a substrate comprising:

a first substrate layer doped with p-type dopants;

a second substrate layer doped with n-type dopants and disposed over the first substrate layer; and

an insulating layer disposed over the first substrate layer and making contact with at least one side surface of the second substrate layer, wherein the insulating layer and the second substrate layer collectively cover a top surface of the first substrate layer; and

an epitaxial structure disposed over and making contact with top surfaces of the second substrate layer and the insulating layer.
The semiconductor device of claim 1, wherein the second substrate layer has two opposite side surfaces making contact with the insulating layer, respectively, such that the second substrate layer is confined by the insulating layer.
The semiconductor device of claim 1, wherein the insulating layer extends downward into a thickness of the first substrate layer.
The semiconductor device of claim 3, wherein an extending length of the insulating layer is greater than a thickness of the second substrate layer.
The semiconductor device of claim 3, wherein the insulating layer extends downward in a vertically manner.
The semiconductor device of claim 3, wherein the insulating layer extends downward in an inclined manner.
The semiconductor device of claim 1, wherein the insulating layer has opposite inner and outer side surfaces, and the inner and outer side surfaces are covered by the first and the second substrate layers.
The semiconductor device of claim 1, wherein the insulating layer has opposite inner and outer side surfaces, wherein,

the inner side surface is covered by the first and the second substrate layers, and

the outer side surface is free from coverage of first and the second substrate layers.
The semiconductor device of claim 1, wherein the top surface of the insulating layer is coplanar with the top surface of the second substrate layer.
The semiconductor device of claim 1, wherein an interface is formed between the insulation layer and at least one of the first and the second substrate layers, wherein the interface further comprises a flat interface, a curved interface, or a combination thereof.
The semiconductor device of claim 1, wherein a p-n junction is formed between the first and second substrate layers.
The semiconductor device of claim 1, wherein the substrate comprises a silicon substrate.
The semiconductor device of claim 1, wherein the p-type dopants comprise a group III element.
The semiconductor device of claim 13, wherein the n-type dopants comprise a group V element.
The semiconductor device of claim 14, wherein the insulating layer comprises a group III element, a group V element, a hydrogen element, an oxygen element, a fluorine element or a combination thereof.
A manufacturing method of a semiconductor device, comprising:

performing a first ion-implanting process on a p-type doped intermediate substrate, such that a top portion of the intermediate substrate is doped to be an n-type doped, and a bottom portion of the intermediate substrate is remained to be p-type doped, wherein the bottom portion serves as a first substrate layer of the substrate and a part of the top portion serves as a second substrate layer of the substrate;

performing a second ion-implanting process on a periphery part of the intermediate substrate, such that at least one of a periphery part of the top portion and a periphery of the bottom portion are formed to be an insulating layer of the substrate; and

forming an epitaxial structure on the substrate.
The method of claim 16, further comprising:

performing a thermal annealing process during the step of performing first ion-implanting process.
The method of claim 16, wherein the insulating layer is located at least a side of the second substrate layer.
The method of claim 16, wherein the second ion-implanting process is performed on the at least one of the periphery part of the top portion and the periphery of the bottom portion, so as to form the insulating layer.
The method of claim 16, wherein forming the epitaxial structure further comprises:

forming a buffer layer on the substrate;

forming a first nitride-based semiconductor layer on the buffer layer; and

forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap different from that of the first nitride-based semiconductor layer.
A semiconductor device, comprising:

a substrate comprising:

a first portion having a first conductive type;

a second portion disposed over the first portion and having a second conductive type which is opposite to the first conductive type; and

an implantation structure disposed over the first portion and located at a side of the second portion, wherein the implantation structure has a resistivity greater than that of any one of the first portion and the second portion; and

an epitaxial structure disposed on and making contact with top surfaces of the second substrate layer and the insulating layer.
The semiconductor device of claim 21, wherein the first portion and the second portion collectively form a depletion region, and a thickness of the depletion region in the first portion is different from a thickness of the depletion region in the second portion.
The semiconductor device of claim 21, wherein a width of the implantation structure changes along a vertical direction.
The semiconductor device of claim 21, wherein a bottom surface of the implantation structure is within a thickness of the first portion.
The semiconductor device of claim 21, wherein the first portion of the substrate has a first sub-portion and a second sub-portion thinner than the first sub-portion, wherein the second portion of the substrate and the implantation structure of the substrate are disposed over the first and second sub-portions of the first portion, respectively.