WO2023212856A1 - Semiconductor device and method for manufacturing thereof - Google Patents
Semiconductor device and method for manufacturing thereof Download PDFInfo
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- WO2023212856A1 WO2023212856A1 PCT/CN2022/090932 CN2022090932W WO2023212856A1 WO 2023212856 A1 WO2023212856 A1 WO 2023212856A1 CN 2022090932 W CN2022090932 W CN 2022090932W WO 2023212856 A1 WO2023212856 A1 WO 2023212856A1
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Images
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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Definitions
- the present disclosure generally relates to a semiconductor device having a diamond substrate. More specifically, the present disclosure relates to a complementary metal oxide semiconductor (CMOS) device formed on a diamond substrate.
- CMOS complementary metal oxide semiconductor
- III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices.
- devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
- a semiconductor device in accordance with one aspect of the present disclosure, includes a semi-insulating drift layer, a diamond-based transistor, and a nitride-based transistor.
- the semi-insulating drift layer is disposed over a diamond substrate.
- the diamond-based transistor includes a drain and a source electrodes over a top surface of a first portion of the semi-insulating drift layer.
- the top surface of the first portion is hydrogen-terminated such that a two-dimensional hole gas (2DHG) region is formed adjacent to the top surface of the first portion.
- the nitride-based transistor includes a first and a second nitride-based semiconductor layers stacked over a top surface of a second portion of the semi-insulating drift layer.
- the second nitride-based semiconductor layer has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
- 2DEG two-dimensional electron gas
- a semiconductor device in accordance with one aspect of the present disclosure, includes a semi-insulating drift layer, a diamond-based transistor, a buffer layer, and a nitride-based transistor.
- the semi-insulating drift layer is disposed over a diamond substrate.
- the diamond-based transistor is disposed over a top surface of a first portion of the semi-insulating drift layer and includes a drain and a source electrodes over the top surface of a first portion.
- the top surface of the first portion is hydrogen-terminated such that a two-dimensional hole gas (2DHG) region is formed adjacent to the top surface of the first portion.
- the buffer layer is disposed over a top surface of a second portion of the semi-insulating drift layer.
- the nitride-based transistor is disposed over a top surface of the buffer layer.
- the nitride-based transistor includes a first nitride-based semiconductor layer and a second nitride-based semiconductor layer.
- the first nitride-based semiconductor layer is in contact with the top surface of the buffer layer.
- the second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
- a height level of the top surface of the buffer layer is different from a height level of the top surface of the first portion of the first portion of the semi-insulating drift layer, such that the diamond-based transistor and the nitride-based transistor are at different height levels.
- a method for manufacturing a semiconductor device includes steps as follows.
- a semi-insulating drift layer is formed over a diamond substrate.
- An ion implanting process is performed using hydrogen element, such that a top surface of a first portion of the semi-insulating drift layer is hydrogen-terminated, thereby forming a two-dimensional hole gas (2DHG) region adjacent to the top surface of the first portion.
- a diamond-based transistor is formed over the top surface of the first portion of the semi-insulating drift layer.
- a nitride-based transistor is formed over a top surface of a second portion of the semi-insulating drift layer.
- a second portion of the semi-insulating drift layer is separated from the first portion.
- the diamond-based transistor having a 2DHG region i.e., p-channel transistor
- the nitride-based transistor having a 2DEG region i.e., n-channel transistor
- the CMOS device benefits from the high thermal conductivity of diamond substrate; and therefore, the heat dissipation efficiency of the CMOS device can be greatly improved.
- the CMOS device of the present disclosure can be suitable for high temperature applications.
- FIG. 1 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure
- FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, and FIG. 2F show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure
- FIG. 3 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
- FIG. 4 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
- group III-V field-effect transistors such as gallium nitride (GaN) or other group III-V based high mobility electron transistors (HEMTs)
- FETs group III-V field-effect transistors
- GaN gallium nitride
- HEMTs group III-V based high mobility electron transistors
- a CMOS device is conventionally constituted by a n-channel transistor and a p-channel transistor for logic functions.
- the n-channel transistor can be achieved by a GaN-based HEMT transistor.
- the GaN-based HEMT transistor has high electron mobility
- hole mobility of the other types of the p-channel transistor is much less than electron mobility of the GaN-based HEMT transistor, resulting in an imbalance between n-channel and p-channel transistors drivability.
- One way to solve the aforesaid imbalance issue is to increase the size of the n-channel transistor to compensate the disparity between the hole mobility and electron mobility.
- such a configuration is unfavorable to the trend of miniaturization of electronic device.
- FIG. 1 is a vertical cross-sectional of a semiconductor device 1A according to some embodiments of the present disclosure.
- the semiconductor device 1A is, for example, a CMOS device.
- the semiconductor device 1A includes a substrate 10A, a semi-insulating drift layer 20A, a diamond-based transistor 30, a buffer layer 40, and a nitride-based transistor 50.
- the material of the substrate 10A is selected to be a diamond substrate since it owns excellent hole mobility and thermal conductivity.
- the substrate 10A is a semi-insulating diamond substrate.
- the term “semi-insulating” in reference to the semi-insulating diamond material of the present disclosure means that such material has a resistivity in a range from 1*10 -5 ( ⁇ cm) to 1*10 8 ( ⁇ cm) .
- the diamond substrate 10A can have a flat top surface. The detailed configuration of the semiconductor device 1A will be fully described as follows.
- the semi-insulating drift layer 20A is disposed on/over/above on the substrate 10A.
- the semi-insulating drift layer 20A is in contact with the flat top surface of the diamond substrate 10A.
- the semi-insulating drift layer 20A is conformally disposed with the substrate 10A, so the semi-insulating drift layer 20A can have a flat top surface.
- the material of the semi-insulating drift layer 20A can be, for example, diamond.
- the semi-insulating drift layer 20A can be a surface layer of the diamond substrate 10A.
- the semi-insulating drift layer 20A can be p-type doped.
- the p-type doped semi-insulating drift layer 20A is doped with boron (B) .
- the semi-insulating drift layer 20A includes portions 202, 204 and a connecting portion 206.
- the diamond-based transistor 30 i.e., p-channel transistor
- the nitride-based transistor 50 i.e., n-channel transistor
- the connecting portion 206 is located between the portions 202, 204.
- the connecting portion 206 connects the portion 202 to the portion 204.
- the height levels of top surfaces TS1, TS2, TSP of the portions 202, 204 and the connecting portion 206 are substantially the same each other.
- a mask layer is provided to cover the connecting portion 206 and the portion 204 and expose the portion 202. Then, a hydrogen-terminating process is performed on the portion 202 using the hydrogen element, such that the top surface of the portion 202 of the semi-insulating drift layer 20A can be hydrogen-terminated.
- the hydrogen-terminated top surface TS1 of the portion 202 includes/possesses carbon-hydrogen (C-H) bond, such that a two-dimensional hole gas (2DHG) region G1 is formed adjacent to the top surface TS1 of the portion 202.
- a thickness T’ of the hydrogen-terminated portion 202 is thinner/smaller than whole thickness T of the semi-insulating drift layer 20A.
- the connecting portion 206 and the portion 204 are free from the influence of the hydrogen element due to the obstruction of the mask layer; and therefore, top surfaces of the portion 204 and the connecting portion 206 are devoid of carbon-hydrogen bond (or hydrogen element) .
- the portion 202 can be referred to as a hydrogen-terminated portion.
- the portion 204 and the connecting portion 206 can be referred to as non-hydrogen-terminated portions.
- the term “hydrogen-terminated portion” used in the present disclosure refers to a status of a diamond crystal terminated by coupling hydrogen element with dangling bonds (i.e., unoccupied bonds of carbon atoms in the semi-insulating drift layer 20A before the hydrogen-terminating process) .
- the term “non-hydrogen-termination portion” refers to a status of the diamond crystal with its surface not terminated by hydrogen element.
- the density of 2DHG region G1 is positively correlated with the C-H bond density of the portion 202 of the semi-insulating drift layer 20A.
- the diamond-based transistor 30 with different 2DHG densities can be achieved by performing a hydrogen-terminating process to the semi-insulating drift layer 20A with different crystal orientations, thereby realizing different device requirements.
- the carbon density of the semi-insulating drift layer 20A having a (110) crystal orientation is greater than that of the semi-insulating drift layer 20A having a (001) crystal orientation.
- C-H bond density of the portion 202 with a (110) crystal orientation can be greater than that of the portion 202 with a (001) crystal orientation; and therefore, the 2DHG density of the hydrogen-terminated portion 202 with a (110) crystal orientation can be greater than that of the hydrogen-terminated portion 202 with a (001) crystal orientation.
- the semi-insulating drift layer 20A having a (110) crystal orientation can be applied to a device with a higher current density requirement.
- hydrogen element ( 1 H) applied in the hydrogen-terminating process can be replaced by isotope of hydrogen element, such as deuterium ( 2 H) , for achieving different electrical requirements.
- the diamond-based transistor 30 is disposed on/over/above a top surface TS1 of the portion 202 of the semi-insulating drift layer 20A.
- the diamond-based transistor 30 is formed at the portion 202 of the semi- insulating drift layer 20A.
- the diamond-based transistor 30 includes electrodes 303, 304 and a gate structure GS1.
- the electrodes 303 and 304 are disposed on/over/above the portion 202 of the semi-insulating drift layer 20A.
- the electrodes 303 and 304 are in contact with the top surface TS1 of the semi-insulating drift layer 20A.
- the electrodes 303 and 304 are respectively disposed at two opposite sides of the gate structure GS1.
- the electrode 303 can serve as a source electrode.
- the electrode 303 can serve as a drain electrode.
- the electrode 304 can serve as a source electrode.
- the electrode 304 can serve as a drain electrode.
- the role of the electrodes 303 and 304 depends on the device design.
- the electrodes 303 and 304 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof.
- the exemplary materials of the electrodes 303 and 304 can include metal with high work function.
- the high work-function metal can include, for example but are not limited to, Pd, Pt, Au, or combinations thereof.
- Each of the electrodes 303 and 304 may be a single layer, or plural layers of the same or different composition.
- the electrodes 303 and 304 form ohmic contacts with the semi-insulating drift layer 20A.
- a distance between the electrode 303 to the gate structure GS1 can be substantially the same as a distance between the electrode 304 to the gate structure GS1. In some embodiments, the distance between the electrode 303 to the gate structure GS1 can be smaller than the distance between the electrode 304 to the gate structure GS1. The aforementioned distance relationship is also determined by the device design.
- the doped diamond layer 305 has a conductivity type opposite to that of the semi-insulating drift layer 20A.
- the semi-insulating drift layer 20A can be p-type doped, and thus the doped diamond layer 305 can be n-type doped.
- the n-type doped diamond layer 305 is doped with nitrogen (N) , phosphorus (P) , lithium (Li) , sodium (Na) , antimony (Sb) , oxygen (O) , sulfur (S) , or a combination thereof.
- the diamond-based transistor 30 is an enhancement mode transistor, which is in a normally-off state when the gate electrode 306 is at approximately zero bias.
- the n-type doped diamond layer 305 may create at least one p-n junction with the nitride-based semiconductor layer 502 to deplete the 2DHG region G1, such that at least one zone of the 2DHG region G1 corresponding to a position below the corresponding the gate electrode 306 has different characteristics (e.g., different hole concentrations) than the remain portion of the 2DHG region G1 and thus is blocked.
- the diamond-based transistor 30 has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 306 or a voltage applied to the gate electrode 306 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 114) , the zone of the 2DHG region G1 below the gate electrode 306 is kept blocked, and thus no current flows therethrough.
- a threshold voltage i.e., a minimum voltage required to form an inversion layer below the gate electrode 114
- the doped diamond layer 305 can be omitted, such that the diamond-based transistor 30 is a depletion-mode transistor, which means the diamond-based transistor 30 in a normally-on state at zero gate-source voltage.
- the exemplary materials of the gate electrode 306 may include metals or metal compounds.
- the gate electrode 306 may be formed as a single layer, or plural layers of the same or different compositions.
- the exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
- the nitride-based transistor 50 is disposed on/over/above the top surface TS2 of the portion 204 of the semi-insulating drift layer 20A.
- the nitride-based transistor 50 includes nitride-based semiconductor layers 501, 502, electrodes 503, 504 and a gate structure GS2.
- a buffer layer 40 can be formed/located between the portion 204 of the semi-insulating drift layer 20A and the nitride-based semiconductor layer 501 of the nitride-based transistor 50.
- the buffer layer 40 can be configured to reduce lattice and thermal mismatches between the semi-insulating drift layer 20A and the nitride-based semiconductor layer 501 of the nitride-based transistor 50, thereby curing defects due to the mismatches/difference. Therefore, the nitride-based transistor 50 can be compatible with the semi-insulating drift layer 20A.
- the phrase “be compatible with” means that the buffer layer 40 can provide a crystal transition from the semi-insulating drift layer 20A to nitride-based semiconductor layers 501, 502 of the nitride-based transistor 50 by well selecting the material of the buffer layer 40.
- the material character of the semi-insulating drift layer 20A can let an epitaxy layer formed thereon.
- the semi-insulating drift layer 20A can create a condition for formation of a p-channel transistor and provide a platform for another epitaxy layer growing continuously thereon.
- the “another epitaxy layer” can serve as a base for a n-channel transistor, so as to constitute a CMOS device.
- the buffer layer 40 may include a III-V compound.
- the III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof.
- the exemplary materials of the buffer layer 40 can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
- the buffer layer 40 can be omitted for reducing the manufacturing cost of the semiconductor device 1A.
- the buffer layer 40 is disposed on/over/above the top surface TS2 of the portion 204 of the semi-insulating drift layer 20A.
- the buffer layer 40 is in contact with the top surface TS2 of the portion 204 of the semi-insulating drift layer 20A, such that a height level of the top surface TSB of the buffer layer 40 is higher than a height level of the top surface TS2 of the portion 204 of the semi-insulating drift layer 20A. Since height levels of top surfaces TS1, TS2 of the portions 202, 204 are substantially the same, a height level of the top surface TSB of the buffer layer 40 is different from (for example, higher than) a height level of the top surface TS1 of the portion 202 of the semi-insulating drift layer 20A. Therefore, the diamond-based transistor 30 and the nitride-based transistor 50 are at different height levels. To be more specific, the nitride-based transistor 50 can be formed higher than the diamond-based transistor 30.
- the nitride-based semiconductor layers 501, 502 are stacked over the top surface TS2 of the portion 204 of the semi-insulating drift layer 20A.
- the nitride-based semiconductor layer 501 can be disposed on/over/above the top surface TSB of the buffer layer 40.
- the nitride-based semiconductor layer 501 can be in contact with the top surface TSB of the buffer layer 40.
- the buffer layer 40 can be located between the semi-insulating drift layer 20A and the nitride-based semiconductor layer 501 of the nitride-based transistor 50.
- the nitride-based semiconductor layer 502 can be disposed on/over/above the nitride-based semiconductor layer 501.
- the exemplary materials of the nitride-based semiconductor layer 501 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al x Ga (1–x) N where x ⁇ 1.
- the exemplary materials of the nitride-based semiconductor layer 502 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In x Al y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
- the exemplary materials of the nitride-based semiconductor layers 501 and 502 are selected such that the nitride-based semiconductor layer 502 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 501, which causes electron affinities thereof different from each other and forms a heterojunction therebetween.
- the nitride-based semiconductor layer 501 is an undoped GaN layer having a bandgap of approximately 3.4 eV
- the nitride-based semiconductor layer 502 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV.
- the nitride-based semiconductor layers 501 and 502 can serve as a channel layer and a barrier layer, respectively.
- a triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region G2 adjacent to the heterojunction.
- the nitride-based transistor 50 is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
- HEMT high-electron-mobility transistor
- the electrodes 503 and 504 are disposed on/over/above the nitride-based semiconductor layer 502.
- the electrodes 503 and 504 are in contact with a top surface of the nitride-based semiconductor layer 502.
- the electrodes 503 and 504 are respectively disposed at two opposite sides of the gate structure GS2.
- the electrode 503 can serve as a source electrode.
- the electrode 503 can serve as a drain electrode.
- the electrode 504 can serve as a source electrode.
- the electrode 504 can serve as a drain electrode.
- the role of the electrodes 503 and 504 depends on the device design.
- the electrodes 503 and 504 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof.
- the exemplary materials of the electrodes 503 and 504 can include, metal with low work function.
- the low work-function metal can include, for example but are not limited to, Ti, Al, Ta, or combinations thereof.
- Each of the electrodes 503 and 504 may be a single layer, or plural layers of the same or different composition.
- the electrodes 503 and 504 form ohmic contacts with the nitride-based semiconductor layer 502.
- a distance between the electrode 503 to the gate structure GS2 can be substantially the same as a distance between the electrode 504 to the gate structure GS2. In some embodiments, the distance between the electrode 503 to the gate structure GS2 can be smaller than the distance between the electrode 504 to the gate structure GS2. The aforementioned distance relationship is also determined by the device design.
- the gate structure GS2 is disposed/located between the electrodes 503, 504.
- the gate structure GS2 further includes a doped nitride-based semiconductor layer 505 and a gate electrode 506.
- the doped nitride-based semiconductor layer 505 is in contact with a top surface of the nitride-based semiconductor layer 502.
- the gate electrode 506 is disposed on/over/above the doped nitride-based semiconductor layer 505.
- the gate electrode 506 is in contact with the doped nitride-based semiconductor layer 505.
- the nitride-based transistor 50 is an enhancement mode device, which is in a normally-off state when the gate electrode 506 is at approximately zero bias.
- the doped nitride-based semiconductor layer 505 may create at least one p-n junction with the nitride-based semiconductor layer 502 to deplete the 2DEG region G2, such that at least one zone of the 2DEG region G2 corresponding to a position below the corresponding the gate electrode 506 has different characteristics (e.g., different electron concentrations) than the remain portion of the 2DEG region G2 and thus is blocked.
- the nitride-based transistor 50 has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 506 or a voltage applied to the gate electrode 506 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 506) , the zone of the 2DEG region G2 below the gate electrode 506 is kept blocked, and thus no current flows therethrough.
- a threshold voltage i.e., a minimum voltage required to form an inversion layer below the gate electrode 506
- the doped nitride-based semiconductor layer 505 can be omitted, such that the nitride-based transistor 50 is a depletion-mode device, which means the nitride-based transistor 50 in a normally-on state at zero gate-source voltage.
- the doped nitride-based semiconductor layer 505 can be a p-type doped III-V semiconductor layer.
- the exemplary materials of the doped nitride-based semiconductor layer 505 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof.
- the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg.
- the nitride-based semiconductor layer 501 includes undoped GaN and the nitride-based semiconductor layer 502 includes AlGaN, and the doped nitride-based semiconductor layer 505 is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region G2, so as to place the nitride-based transistor 50 into an off-state condition.
- the exemplary materials of the gate electrode 506 may include metals or metal compounds.
- the gate electrode 506 may be formed as a single layer, or plural layers of the same or different compositions.
- the exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
- the connecting portion 206 between the diamond-based transistor 30 and the nitride-based transistor 50 can provide a good insulation due to its high resistivity.
- at least one shallow trench isolation (STI) can be formed in the connecting portion 206 to separate and delineate the diamond transistor 30 and the nitride-based transistor 50.
- the diamond transistor 30 acting as a p-channel transistor and the nitride-based transistor 50 acting as a n-channel transistor can be integrated on the same diamond substrate 10A, so as to constitute a CMOS device.
- Heat generated during the operation period of the semiconductor device 1A can be dissipated rapidly through the diamond substrate 10A due to its high thermal conductivity.
- the semiconductor device 1A can be applied to a high temperature environment.
- the diamond transistor 30 possesses high hole mobility and high current density, which are comparable to the nitride-based transistor 50. Therefore, a more balanced CMOS device in the semiconductor device 1A can be achieved.
- deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
- ALD atomic layer deposition
- PVD physical vapor deposition
- CVD chemical vapor deposition
- MOCVD metal organic CVD
- PECVD plasma enhanced CVD
- LPCVD low-pressure CVD
- plasma-assisted vapor deposition epitaxial growth, or other suitable processes.
- a semi-insulating drift layer 60 is formed on/over/above the diamond substrate 10A.
- a mask layer ML is provided on the semi-insulating drift layer 10A.
- the mask layer ML has an opening OG (aperture) to define the location of the portion 202 of the semi-insulating drift layer 10A.
- a hydrogen-terminating process is performed using hydrogen element, such that a top surface TS1 of the portion 202 of the semi-insulating drift layer 10A is hydrogen-terminated, thereby forming a two-dimensional hole gas (2DHG) region G1 adjacent to the top surface TS1 of the portion 202.
- the remaining portion of the semi-insulating drift layer 10A is devoid of hydrogen element due to obstruction of the mask layer ML.
- a diamond-based transistor 30 is formed on/over/above the top surface TS1 of the portion 202 of the semi-insulating drift layer 20A.
- electrodes 303, 304 of the diamond-based transistor 30 are formed on/over/above the top surface TS1 of the portion 202 of the semi-insulating drift layer 20A.
- a gate structure GS1 of the diamond-based transistor 30 is formed on/over/above the portion 202 of the semi-insulating drift layer 20A and between the electrodes 303, 304.
- a doped diamond layer 305 of the gate structure GS1 is formed on/over/above the top surface TS1 of the portion 202 of the semi-insulating drift layer 20A and between the electrodes 303, 304.
- the doped diamond layer 305 can deplete a zone of the 2DHG region G1 thereunder.
- a gate electrode 306 of the gate structure GS1 is formed on/over/above the doped diamond layer 305.
- a buffer layer 40 is formed to be in contact with a top surface TS2 of the portion 204 of the semi-insulating drift layer 20A.
- a nitride-based transistor 50 is formed over the top surface TS2 of the portion 204 of the semi-insulating drift layer 20A, in which the portion 204 of the semi-insulating drift layer 20A is separated from the portion 202.
- a nitride-based semiconductor layer 501 of the nitride-based transistor 50 is formed to be in contact with the top surface TSB of the buffer layer 40.
- a nitride-based semiconductor layer 502 of the nitride-based transistor 50 is formed on/over/above the nitride-based semiconductor layer 501, in which the nitride-based semiconductor layer 502 has a bandgap greater than that of the nitride-based semiconductor layer 501, so as to form a heterojunction and a 2DEG region G2 adjacent to the heterojunction.
- electrodes 503, 504 of the nitride-based transistor 50 are formed on/over/above the nitride-based semiconductor layer 502.
- a gate structure GS2 of the nitride-based transistor 50 is formed over the nitride-based semiconductor layer 502, such that the gate structure GS2 is formed between the electrodes 503 and 504.
- a doped nitride-based semiconductor layer 505 of the gate structure GS2 is formed on/over/above the nitride-based semiconductor layer 502.
- the doped nitride-based semiconductor layer 505 can deplete a zone of the 2DEG region G2 thereunder.
- a gate electrode 506 of the gate structure GS2 is formed on/over/above the doped nitride-based semiconductor layer 505.
- FIG. 3 is a vertical cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure.
- the semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the diamond substrate 10B can have portions 102, 104 with different thickness, in which a thickness T1 of the portion 102 of the diamond substrate 10B is greater than a thickness T2 of the portion 104 (i.e., recessed portion) of the diamond substrate 10B. That is, a height level of a top surface of the portion 102 of the diamond substrate 10B is higher than a height level of a top surface of the portion 104 of the diamond substrate 10B.
- the semi-insulating drift layer 20B is conformally disposed with the diamond substrate 10, such that the semi-insulating drift layer 20B can have portions 202, 204 at different height levels.
- a height level of the top surface TS1 of the portion 202 of the semi-insulating drift layer 20B is higher than a height level of the top surface TS2 of the portion 104 of the semi-insulating drift layer 20B.
- the connecting portion 206 of the semi-insulating drift layer 20 can vertically extend from the portion 202 to the portion 204.
- the buffer layer 40 is disposed on the top surface TS2 of the portion 204 of the semi-insulating drift layer 20B.
- the buffer layer 40 is in contact with the top surface TS2 of the portion 204 of the semi-insulating drift layer 20B.
- the top surface TSB of the buffer layer 40 is lower than that of the top surface TS1 of the portion 202.
- the buffer layer 40 is within a thickness T1 of the portion 202 of the diamond substrate 10B.
- the nitride-based transistor 50 can be formed lower than the diamond-based transistor 30, and the nitride-based transistor 50 can be formed within a thickness T1 of the portion 202 of the diamond substrate 10B. Accordingly, the semiconductor device 1B can have a reduced thickness compared to the semiconductor device 1A in the FIG. 1A, which is advantageous to meet to the trend of miniaturization of the electronic devices.
- FIG. 4 is a vertical cross-sectional view of a semiconductor device 1C according to some embodiments of the present disclosure.
- the semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the thickness T3 of the portion 202 of the semi-insulating drift layer 20C is greater than the thickness T4 of the portion 204 (i.e., recessed portion) of the semi-insulating drift layer 20C.
- the top surface TS1 of the portion 202 is within a thickness of the buffer layer 40.
- the semiconductor device 1C can have a reduced thickness compared to the semiconductor device 1A in the FIG. 1A, which is advantageous to meet to the trend of miniaturization of the electronic devices.
- a semi-insulating drift layer is formed over a diamond substrate.
- a hydrogen-terminating process using hydrogen element is performed on a portion of the semi-insulating drift layer, such that a 2DHG region is formed adjacent to a top surface of the hydrogen-terminated portion of the semi-insulating drift layer.
- a diamond-based transistor is formed on the hydrogen-terminated portion of the semi-insulating drift layer to serve as a p-channel transistor.
- a buffer layer can be formed on another portion of the semi-insulating drift layer. Thenitride-based transistor is formed on the buffer layer to serve as a n-channel transistor.
- the diamond-based transistor and the nitride-based transistor can be integrated on the same diamond substrate with high thermal conductivity. Hence, the heat dissipation efficiency of the semiconductor device can be enhanced. Moreover, since the value of the carrier mobility/current density of the diamond-based transistor is comparable to that of the nitride-based transistor, the imbalance issue can be alleviated. Thus, a more balanced CMOS device can be achieved.
- the terms “substantially, “ “substantial, “ “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.
- the terms when used in conjunction with a numerical value, can encompass a range of variation of less than or equal to ⁇ 10%of that numerical value, such as less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
- substantially coplanar can refer to two surfaces within micrometers of lying along a same plane, such as within 40 ⁇ m, within 30 ⁇ m, within 20 ⁇ m, within 10 ⁇ m, or within 1 ⁇ m of lying along the same plane.
- a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.
Abstract
A semiconductor device (1A) includes a semi-insulating drift layer (20A), a diamond-based transistor (30), and a nitride-based transistor (50). The semi-insulating drift layer (20A) is disposed over a diamond substrate (10A). The diamond-based transistor (30) includes a drain electrode and a source electrode (303,304) over a top surface (TS1) of a first portion of the semi-insulating drift layer (20A). The top surface (TS1) of the first portion is hydrogen-terminated such that a two-dimensional hole gas (2DHG) region (G1) is formed adjacent to the top surface (TS1) of the first portion. The nitride-based transistor (50) includes a first and a second nitride-based semiconductor layers (501,502) stacked over a top surface (TS2) of a second portion of the semi-insulating drift layer (20A). The second nitride-based semiconductor layer (502) has a bandgap greater than a bandgap of the first nitride-based semiconductor layer (501), so as to form a heterojunction and a two-dimensional electron gas (2DEG) region (G2) adjacent to the heterojunction.
Description
Inventors: Ronghui HAO
Field of the Disclosure:
The present disclosure generally relates to a semiconductor device having a diamond substrate. More specifically, the present disclosure relates to a complementary metal oxide semiconductor (CMOS) device formed on a diamond substrate.
In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .
Summary of the Disclosure:
In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a semi-insulating drift layer, a diamond-based transistor, and a nitride-based transistor. The semi-insulating drift layer is disposed over a diamond substrate. The diamond-based transistor includes a drain and a source electrodes over a top surface of a first portion of the semi-insulating drift layer. The top surface of the first portion is hydrogen-terminated such that a two-dimensional hole gas (2DHG) region is formed adjacent to the top surface of the first portion. The nitride-based transistor includes a first and a second nitride-based semiconductor layers stacked over a top surface of a second portion of the semi-insulating drift layer. The second nitride-based semiconductor layer has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a semi-insulating drift layer, a diamond-based transistor, a buffer layer, and a nitride-based transistor. The semi-insulating drift layer is disposed over a diamond substrate. The diamond-based transistor is disposed over a top surface of a first portion of the semi-insulating drift layer and includes a drain and a source electrodes over the top surface of a first portion. The top surface of the first portion is hydrogen-terminated such that a two-dimensional hole gas (2DHG) region is formed adjacent to the top surface of the first portion. The buffer layer is disposed over a top surface of a second portion of the semi-insulating drift layer. The nitride-based transistor is disposed over a top surface of the buffer layer. The nitride-based transistor includes a first nitride-based semiconductor layer and a second nitride-based semiconductor layer. The first nitride-based semiconductor layer is in contact with the top surface of the buffer layer. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. A height level of the top surface of the buffer layer is different from a height level of the top surface of the first portion of the first portion of the semi-insulating drift layer, such that the diamond-based transistor and the nitride-based transistor are at different height levels.
In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A semi-insulating drift layer is formed over a diamond substrate. An ion implanting process is performed using hydrogen element, such that a top surface of a first portion of the semi-insulating drift layer is hydrogen-terminated, thereby forming a two-dimensional hole gas (2DHG) region adjacent to the top surface of the first portion. A diamond-based transistor is formed over the top surface of the first portion of the semi-insulating drift layer. A nitride-based transistor is formed over a top surface of a second portion of the semi-insulating drift layer. A second portion of the semi-insulating drift layer is separated from the first portion.
By the above configuration, in the present disclosure, the diamond-based transistor having a 2DHG region (i.e., p-channel transistor) and the nitride-based transistor having a 2DEG region (i.e., n-channel transistor) are formed on/over/above a diamond substrate with high thermal conductivity, so as to constitute a CMOS device. The CMOS device benefits from the high thermal conductivity of diamond substrate; and therefore, the heat dissipation efficiency of the CMOS device can be greatly improved. Thus, the CMOS device of the present disclosure can be suitable for high temperature applications.
Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:
FIG. 1 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, and FIG. 2F show different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;
FIG. 3 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure; and
FIG. 4 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.
Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.
Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.
In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.
Since group III-V field-effect transistors (FETs) , such as gallium nitride (GaN) or other group III-V based high mobility electron transistors (HEMTs) , advantageously possess a wide bandgap, a high breakdown electric-field, a large thermal conductivity, HEMTs potentially advantageous for use in power applications. However, the development of the GaN-based HEMT has encountered some bottleneck problems.
For instance, a CMOS device is conventionally constituted by a n-channel transistor and a p-channel transistor for logic functions. The n-channel transistor can be achieved by a GaN-based HEMT transistor. Nevertheless, although the GaN-based HEMT transistor has high electron mobility, hole mobility of the other types of the p-channel transistor is much less than electron mobility of the GaN-based HEMT transistor, resulting in an imbalance between n-channel and p-channel transistors drivability. One way to solve the aforesaid imbalance issue is to increase the size of the n-channel transistor to compensate the disparity between the hole mobility and electron mobility. However, such a configuration is unfavorable to the trend of miniaturization of electronic device.
Furthermore, another issue is heat dissipating issue. High temperature not only reduces the working efficiency of the electronic component, but also may damage or even burnout the CMOS device, thereby limiting the applications of the CMOS device in high temperature environment. Therefore, there is a need to solve the aforesaid issues.
FIG. 1 is a vertical cross-sectional of a semiconductor device 1A according to some embodiments of the present disclosure. The semiconductor device 1A is, for example, a CMOS device. Specifically, the semiconductor device 1A includes a substrate 10A, a semi-insulating drift layer 20A, a diamond-based transistor 30, a buffer layer 40, and a nitride-based transistor 50.
At least for solving the aforesaid issues, in the present disclosure, the material of the substrate 10A is selected to be a diamond substrate since it owns excellent hole mobility and thermal conductivity. Specifically, the substrate 10A is a semi-insulating diamond substrate. As used herein, the term “semi-insulating” in reference to the semi-insulating diamond material of the present disclosure means that such material has a resistivity in a range from 1*10
-5 (Ω·cm) to 1*10
8 (Ω·cm) . In the embodiment, the diamond substrate 10A can have a flat top surface. The detailed configuration of the semiconductor device 1A will be fully described as follows.
The semi-insulating drift layer 20A is disposed on/over/above on the substrate 10A. The semi-insulating drift layer 20A is in contact with the flat top surface of the diamond substrate 10A. The semi-insulating drift layer 20A is conformally disposed with the substrate 10A, so the semi-insulating drift layer 20A can have a flat top surface. The material of the semi-insulating drift layer 20A can be, for example, diamond. In some embodiments, the semi-insulating drift layer 20A can be a surface layer of the diamond substrate 10A. The semi-insulating drift layer 20A can be p-type doped. In some embodiments, the p-type doped semi-insulating drift layer 20A is doped with boron (B) .
The semi-insulating drift layer 20A includes portions 202, 204 and a connecting portion 206. The diamond-based transistor 30 (i.e., p-channel transistor) is to be formed on the portion 202 (i.e., p-channel portion/region) of the semi-insulating drift layer 20A. The nitride-based transistor 50 (i.e., n-channel transistor) is to be formed on the portion 204 (i.e., n-channel portion/region) of the semi-insulating drift layer 20A. The connecting portion 206 is located between the portions 202, 204. The connecting portion 206 connects the portion 202 to the portion 204. In the embodiment, the height levels of top surfaces TS1, TS2, TSP of the portions 202, 204 and the connecting portion 206 are substantially the same each other.
During the formation of the diamond-based transistor 30, a mask layer is provided to cover the connecting portion 206 and the portion 204 and expose the portion 202. Then, a hydrogen-terminating process is performed on the portion 202 using the hydrogen element, such that the top surface of the portion 202 of the semi-insulating drift layer 20A can be hydrogen-terminated. As a result, the hydrogen-terminated top surface TS1 of the portion 202 includes/possesses carbon-hydrogen (C-H) bond, such that a two-dimensional hole gas (2DHG) region G1 is formed adjacent to the top surface TS1 of the portion 202. A thickness T’ of the hydrogen-terminated portion 202 is thinner/smaller than whole thickness T of the semi-insulating drift layer 20A.
On the other hand, the connecting portion 206 and the portion 204 are free from the influence of the hydrogen element due to the obstruction of the mask layer; and therefore, top surfaces of the portion 204 and the connecting portion 206 are devoid of carbon-hydrogen bond (or hydrogen element) .
With respect to the semi-insulating drift layer 20A, the portion 202 can be referred to as a hydrogen-terminated portion. The portion 204 and the connecting portion 206, can be referred to as non-hydrogen-terminated portions. It should be noted that the term “hydrogen-terminated portion” used in the present disclosure refers to a status of a diamond crystal terminated by coupling hydrogen element with dangling bonds (i.e., unoccupied bonds of carbon atoms in the semi-insulating drift layer 20A before the hydrogen-terminating process) . On the other hand, the term "non-hydrogen-termination portion" refers to a status of the diamond crystal with its surface not terminated by hydrogen element.
It is worth mentioning that the density of 2DHG region G1 is positively correlated with the C-H bond density of the portion 202 of the semi-insulating drift layer 20A. The diamond-based transistor 30 with different 2DHG densities can be achieved by performing a hydrogen-terminating process to the semi-insulating drift layer 20A with different crystal orientations, thereby realizing different device requirements.
For example, the carbon density of the semi-insulating drift layer 20A having a (110) crystal orientation is greater than that of the semi-insulating drift layer 20A having a (001) crystal orientation. Thus, after the step of hydrogen-terminating process, C-H bond density of the portion 202 with a (110) crystal orientation can be greater than that of the portion 202 with a (001) crystal orientation; and therefore, the 2DHG density of the hydrogen-terminated portion 202 with a (110) crystal orientation can be greater than that of the hydrogen-terminated portion 202 with a (001) crystal orientation. Thus, the semi-insulating drift layer 20A having a (110) crystal orientation can be applied to a device with a higher current density requirement.
In some embodiments, hydrogen element (
1H) applied in the hydrogen-terminating process can be replaced by isotope of hydrogen element, such as deuterium (
2H) , for achieving different electrical requirements.
The diamond-based transistor 30 is disposed on/over/above a top surface TS1 of the portion 202 of the semi-insulating drift layer 20A. The diamond-based transistor 30 is formed at the portion 202 of the semi- insulating drift layer 20A. The diamond-based transistor 30 includes electrodes 303, 304 and a gate structure GS1.
The electrodes 303 and 304 are disposed on/over/above the portion 202 of the semi-insulating drift layer 20A. The electrodes 303 and 304 are in contact with the top surface TS1 of the semi-insulating drift layer 20A. The electrodes 303 and 304 are respectively disposed at two opposite sides of the gate structure GS1. In some embodiments, the electrode 303 can serve as a source electrode. In some embodiments, the electrode 303 can serve as a drain electrode. In some embodiments, the electrode 304 can serve as a source electrode. In some embodiments, the electrode 304 can serve as a drain electrode. The role of the electrodes 303 and 304 depends on the device design.
In some embodiments, the electrodes 303 and 304 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the electrodes 303 and 304 can include metal with high work function. The high work-function metal can include, for example but are not limited to, Pd, Pt, Au, or combinations thereof. Each of the electrodes 303 and 304 may be a single layer, or plural layers of the same or different composition. The electrodes 303 and 304 form ohmic contacts with the semi-insulating drift layer 20A.
In the embodiment, a distance between the electrode 303 to the gate structure GS1 can be substantially the same as a distance between the electrode 304 to the gate structure GS1. In some embodiments, the distance between the electrode 303 to the gate structure GS1 can be smaller than the distance between the electrode 304 to the gate structure GS1. The aforementioned distance relationship is also determined by the device design.
The doped diamond layer 305 has a conductivity type opposite to that of the semi-insulating drift layer 20A. Specifically, the semi-insulating drift layer 20A can be p-type doped, and thus the doped diamond layer 305 can be n-type doped. In some embodiments, the n-type doped diamond layer 305 is doped with nitrogen (N) , phosphorus (P) , lithium (Li) , sodium (Na) , antimony (Sb) , oxygen (O) , sulfur (S) , or a combination thereof.
In the exemplary illustration of FIG. 1, the diamond-based transistor 30 is an enhancement mode transistor, which is in a normally-off state when the gate electrode 306 is at approximately zero bias. Specifically, the n-type doped diamond layer 305 may create at least one p-n junction with the nitride-based semiconductor layer 502 to deplete the 2DHG region G1, such that at least one zone of the 2DHG region G1 corresponding to a position below the corresponding the gate electrode 306 has different characteristics (e.g., different hole concentrations) than the remain portion of the 2DHG region G1 and thus is blocked.
Due to such mechanism, the diamond-based transistor 30 has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 306 or a voltage applied to the gate electrode 306 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 114) , the zone of the 2DHG region G1 below the gate electrode 306 is kept blocked, and thus no current flows therethrough.
In some embodiments, the doped diamond layer 305 can be omitted, such that the diamond-based transistor 30 is a depletion-mode transistor, which means the diamond-based transistor 30 in a normally-on state at zero gate-source voltage.
The exemplary materials of the gate electrode 306 may include metals or metal compounds. The gate electrode 306 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
The nitride-based transistor 50 is disposed on/over/above the top surface TS2 of the portion 204 of the semi-insulating drift layer 20A. The nitride-based transistor 50 includes nitride-based semiconductor layers 501, 502, electrodes 503, 504 and a gate structure GS2.
It should be noted that the lattice and thermal mismatch issues may arise due to material difference between the nitride-based transistor 50 and the semi-insulating drift layer 20A. In the embodiment, at least for preventing negative impacts resulting from thermal and lattice mismatch, a buffer layer 40 can be formed/located between the portion 204 of the semi-insulating drift layer 20A and the nitride-based semiconductor layer 501 of the nitride-based transistor 50.
The buffer layer 40 can be configured to reduce lattice and thermal mismatches between the semi-insulating drift layer 20A and the nitride-based semiconductor layer 501 of the nitride-based transistor 50, thereby curing defects due to the mismatches/difference. Therefore, the nitride-based transistor 50 can be compatible with the semi-insulating drift layer 20A.
In this regard, the phrase “be compatible with” means that the buffer layer 40 can provide a crystal transition from the semi-insulating drift layer 20A to nitride-based semiconductor layers 501, 502 of the nitride-based transistor 50 by well selecting the material of the buffer layer 40. The material character of the semi-insulating drift layer 20A can let an epitaxy layer formed thereon. As such, the semi-insulating drift layer 20A can create a condition for formation of a p-channel transistor and provide a platform for another epitaxy layer growing continuously thereon. The “another epitaxy layer” can serve as a base for a n-channel transistor, so as to constitute a CMOS device.
For example, the buffer layer 40 may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer 40 can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
In some embodiments, the buffer layer 40 can be omitted for reducing the manufacturing cost of the semiconductor device 1A.
The buffer layer 40 is disposed on/over/above the top surface TS2 of the portion 204 of the semi-insulating drift layer 20A. The buffer layer 40 is in contact with the top surface TS2 of the portion 204 of the semi-insulating drift layer 20A, such that a height level of the top surface TSB of the buffer layer 40 is higher than a height level of the top surface TS2 of the portion 204 of the semi-insulating drift layer 20A. Since height levels of top surfaces TS1, TS2 of the portions 202, 204 are substantially the same, a height level of the top surface TSB of the buffer layer 40 is different from (for example, higher than) a height level of the top surface TS1 of the portion 202 of the semi-insulating drift layer 20A. Therefore, the diamond-based transistor 30 and the nitride-based transistor 50 are at different height levels. To be more specific, the nitride-based transistor 50 can be formed higher than the diamond-based transistor 30.
The nitride-based semiconductor layers 501, 502 are stacked over the top surface TS2 of the portion 204 of the semi-insulating drift layer 20A. The nitride-based semiconductor layer 501 can be disposed on/over/above the top surface TSB of the buffer layer 40. The nitride-based semiconductor layer 501 can be in contact with the top surface TSB of the buffer layer 40. The buffer layer 40 can be located between the semi-insulating drift layer 20A and the nitride-based semiconductor layer 501 of the nitride-based transistor 50. The nitride-based semiconductor layer 502 can be disposed on/over/above the nitride-based semiconductor layer 501.
The exemplary materials of the nitride-based semiconductor layer 501 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In
xAl
yGa
(1–x–y) N where x+y ≤ 1, Al
xGa
(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 502 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In
xAl
yGa
(1–x–y) N where x+y ≤ 1, Al
yGa
(1–y) N where y ≤ 1.
The exemplary materials of the nitride-based semiconductor layers 501 and 502 are selected such that the nitride-based semiconductor layer 502 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 501, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 501 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 502 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 501 and 502 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region G2 adjacent to the heterojunction. Accordingly, the nitride-based transistor 50 is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .
The electrodes 503 and 504 are disposed on/over/above the nitride-based semiconductor layer 502. The electrodes 503 and 504 are in contact with a top surface of the nitride-based semiconductor layer 502. The electrodes 503 and 504 are respectively disposed at two opposite sides of the gate structure GS2. In some embodiments, the electrode 503 can serve as a source electrode. In some embodiments, the electrode 503 can serve as a drain electrode. In some embodiments, the electrode 504 can serve as a source electrode. In some embodiments, the electrode 504 can serve as a drain electrode. The role of the electrodes 503 and 504 depends on the device design.
In some embodiments, the electrodes 503 and 504 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the electrodes 503 and 504 can include, metal with low work function. The low work-function metal can include, for example but are not limited to, Ti, Al, Ta, or combinations thereof. Each of the electrodes 503 and 504 may be a single layer, or plural layers of the same or different composition. The electrodes 503 and 504 form ohmic contacts with the nitride-based semiconductor layer 502.
In the embodiment, a distance between the electrode 503 to the gate structure GS2 can be substantially the same as a distance between the electrode 504 to the gate structure GS2. In some embodiments, the distance between the electrode 503 to the gate structure GS2 can be smaller than the distance between the electrode 504 to the gate structure GS2. The aforementioned distance relationship is also determined by the device design.
The gate structure GS2 is disposed/located between the electrodes 503, 504. The gate structure GS2 further includes a doped nitride-based semiconductor layer 505 and a gate electrode 506. The doped nitride-based semiconductor layer 505 is in contact with a top surface of the nitride-based semiconductor layer 502. The gate electrode 506 is disposed on/over/above the doped nitride-based semiconductor layer 505. The gate electrode 506 is in contact with the doped nitride-based semiconductor layer 505.
In the exemplary illustration of FIG. 1, the nitride-based transistor 50 is an enhancement mode device, which is in a normally-off state when the gate electrode 506 is at approximately zero bias. Specifically, the doped nitride-based semiconductor layer 505 may create at least one p-n junction with the nitride-based semiconductor layer 502 to deplete the 2DEG region G2, such that at least one zone of the 2DEG region G2 corresponding to a position below the corresponding the gate electrode 506 has different characteristics (e.g., different electron concentrations) than the remain portion of the 2DEG region G2 and thus is blocked.
Due to such mechanism, the nitride-based transistor 50 has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 506 or a voltage applied to the gate electrode 506 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 506) , the zone of the 2DEG region G2 below the gate electrode 506 is kept blocked, and thus no current flows therethrough.
In some embodiments, the doped nitride-based semiconductor layer 505 can be omitted, such that the nitride-based transistor 50 is a depletion-mode device, which means the nitride-based transistor 50 in a normally-on state at zero gate-source voltage.
The doped nitride-based semiconductor layer 505 can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped nitride-based semiconductor layer 505 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer 501 includes undoped GaN and the nitride-based semiconductor layer 502 includes AlGaN, and the doped nitride-based semiconductor layer 505 is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region G2, so as to place the nitride-based transistor 50 into an off-state condition.
The exemplary materials of the gate electrode 506 may include metals or metal compounds. The gate electrode 506 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.
The connecting portion 206 between the diamond-based transistor 30 and the nitride-based transistor 50 can provide a good insulation due to its high resistivity. In some embodiments, at least one shallow trench isolation (STI) can be formed in the connecting portion 206 to separate and delineate the diamond transistor 30 and the nitride-based transistor 50.
Based on above description, in the semiconductor device 1A, the diamond transistor 30 acting as a p-channel transistor and the nitride-based transistor 50 acting as a n-channel transistor can be integrated on the same diamond substrate 10A, so as to constitute a CMOS device. Heat generated during the operation period of the semiconductor device 1A can be dissipated rapidly through the diamond substrate 10A due to its high thermal conductivity. Thus, the semiconductor device 1A can be applied to a high temperature environment. Moreover, the diamond transistor 30 possesses high hole mobility and high current density, which are comparable to the nitride-based transistor 50. Therefore, a more balanced CMOS device in the semiconductor device 1A can be achieved.
Different stages of a method for manufacturing the semiconductor device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, and FIG. 2F, as described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
Referring to FIG. 2A, a semi-insulating drift layer 60 is formed on/over/above the diamond substrate 10A.
Referring to FIG. 2B, a mask layer ML is provided on the semi-insulating drift layer 10A. The mask layer ML has an opening OG (aperture) to define the location of the portion 202 of the semi-insulating drift layer 10A. Then, a hydrogen-terminating process is performed using hydrogen element, such that a top surface TS1 of the portion 202 of the semi-insulating drift layer 10A is hydrogen-terminated, thereby forming a two-dimensional hole gas (2DHG) region G1 adjacent to the top surface TS1 of the portion 202. The remaining portion of the semi-insulating drift layer 10A is devoid of hydrogen element due to obstruction of the mask layer ML.
Referring to FIG. 2C, a diamond-based transistor 30 is formed on/over/above the top surface TS1 of the portion 202 of the semi-insulating drift layer 20A. To be more specific, electrodes 303, 304 of the diamond-based transistor 30 are formed on/over/above the top surface TS1 of the portion 202 of the semi-insulating drift layer 20A. A gate structure GS1 of the diamond-based transistor 30 is formed on/over/above the portion 202 of the semi-insulating drift layer 20A and between the electrodes 303, 304. A doped diamond layer 305 of the gate structure GS1 is formed on/over/above the top surface TS1 of the portion 202 of the semi-insulating drift layer 20A and between the electrodes 303, 304. The doped diamond layer 305 can deplete a zone of the 2DHG region G1 thereunder. A gate electrode 306 of the gate structure GS1 is formed on/over/above the doped diamond layer 305.
Referring to FIG. 2D, a buffer layer 40 is formed to be in contact with a top surface TS2 of the portion 204 of the semi-insulating drift layer 20A.
Referring to FIG. 2E, a nitride-based transistor 50 is formed over the top surface TS2 of the portion 204 of the semi-insulating drift layer 20A, in which the portion 204 of the semi-insulating drift layer 20A is separated from the portion 202.
To be more specific, a nitride-based semiconductor layer 501 of the nitride-based transistor 50 is formed to be in contact with the top surface TSB of the buffer layer 40. A nitride-based semiconductor layer 502 of the nitride-based transistor 50 is formed on/over/above the nitride-based semiconductor layer 501, in which the nitride-based semiconductor layer 502 has a bandgap greater than that of the nitride-based semiconductor layer 501, so as to form a heterojunction and a 2DEG region G2 adjacent to the heterojunction.
Referring to FIG. 2F, electrodes 503, 504 of the nitride-based transistor 50 are formed on/over/above the nitride-based semiconductor layer 502. A gate structure GS2 of the nitride-based transistor 50 is formed over the nitride-based semiconductor layer 502, such that the gate structure GS2 is formed between the electrodes 503 and 504. To be more specific, a doped nitride-based semiconductor layer 505 of the gate structure GS2 is formed on/over/above the nitride-based semiconductor layer 502. The doped nitride-based semiconductor layer 505 can deplete a zone of the 2DEG region G2 thereunder. A gate electrode 506 of the gate structure GS2 is formed on/over/above the doped nitride-based semiconductor layer 505. Thus, the semiconductor device 1A as shown in the FIG. 1 is obtained.
FIG. 3 is a vertical cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure. The semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the diamond substrate 10B can have portions 102, 104 with different thickness, in which a thickness T1 of the portion 102 of the diamond substrate 10B is greater than a thickness T2 of the portion 104 (i.e., recessed portion) of the diamond substrate 10B. That is, a height level of a top surface of the portion 102 of the diamond substrate 10B is higher than a height level of a top surface of the portion 104 of the diamond substrate 10B.
The semi-insulating drift layer 20B is conformally disposed with the diamond substrate 10, such that the semi-insulating drift layer 20B can have portions 202, 204 at different height levels. In the embodiment, a height level of the top surface TS1 of the portion 202 of the semi-insulating drift layer 20B is higher than a height level of the top surface TS2 of the portion 104 of the semi-insulating drift layer 20B. The connecting portion 206 of the semi-insulating drift layer 20 can vertically extend from the portion 202 to the portion 204.
The buffer layer 40 is disposed on the top surface TS2 of the portion 204 of the semi-insulating drift layer 20B. The buffer layer 40 is in contact with the top surface TS2 of the portion 204 of the semi-insulating drift layer 20B. The top surface TSB of the buffer layer 40 is lower than that of the top surface TS1 of the portion 202. The buffer layer 40 is within a thickness T1 of the portion 202 of the diamond substrate 10B.
Due to the height level relationship between the top surface TS1 of the portion 202 and the top surface TSB of the buffer layer 40, the nitride-based transistor 50 can be formed lower than the diamond-based transistor 30, and the nitride-based transistor 50 can be formed within a thickness T1 of the portion 202 of the diamond substrate 10B. Accordingly, the semiconductor device 1B can have a reduced thickness compared to the semiconductor device 1A in the FIG. 1A, which is advantageous to meet to the trend of miniaturization of the electronic devices.
FIG. 4 is a vertical cross-sectional view of a semiconductor device 1C according to some embodiments of the present disclosure. The semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the thickness T3 of the portion 202 of the semi-insulating drift layer 20C is greater than the thickness T4 of the portion 204 (i.e., recessed portion) of the semi-insulating drift layer 20C. The top surface TS1 of the portion 202 is within a thickness of the buffer layer 40.
Since the nitride-based transistor 50 is formed the recessed portion 204 of the semi-insulating drift layer 20C, the semiconductor device 1C can have a reduced thickness compared to the semiconductor device 1A in the FIG. 1A, which is advantageous to meet to the trend of miniaturization of the electronic devices.
Based on the above description, in the present disclosure, a semi-insulating drift layer is formed over a diamond substrate. By performing a hydrogen-terminating process using hydrogen element on a portion of the semi-insulating drift layer, such that a 2DHG region is formed adjacent to a top surface of the hydrogen-terminated portion of the semi-insulating drift layer. Then, a diamond-based transistor is formed on the hydrogen-terminated portion of the semi-insulating drift layer to serve as a p-channel transistor. On the other hand, prior to the formation of a nitride-based transistor, a buffer layer can be formed on another portion of the semi-insulating drift layer. Then, the nitride-based transistor is formed on the buffer layer to serve as a n-channel transistor. As such, the diamond-based transistor and the nitride-based transistor can be integrated on the same diamond substrate with high thermal conductivity. Hence, the heat dissipation efficiency of the semiconductor device can be enhanced. Moreover, since the value of the carrier mobility/current density of the diamond-based transistor is comparable to that of the nitride-based transistor, the imbalance issue can be alleviated. Thus, a more balanced CMOS device can be achieved.
The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.
As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.
As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.
Claims (25)
- A semiconductor device comprising:a semi-insulating drift layer disposed over a diamond substrate;a diamond-based transistor comprising a drain and a source electrodes over a top surface of a first portion of the semi-insulating drift layer, wherein the top surface of the first portion is hydrogen-terminated such that a two-dimensional hole gas (2DHG) region is formed adjacent to the top surface of the first portion; anda nitride-based transistor comprising a first and a second nitride-based semiconductor layers stacked over a top surface of a second portion of the semi-insulating drift layer, wherein the second nitride-based semiconductor layer has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
- The semiconductor device of any one of the preceding claims, wherein the semi-insulating drift layer is p-type doped.
- The semiconductor device of any one of the preceding claims, wherein the p-type semi-insulating drift layer is doped with boron (B) .
- The semiconductor device of any one of the preceding claims, wherein the diamond-based transistor further comprises a gate structure disposed between the drain and the source electrodes of the diamond-based transistor.
- The semiconductor device of any one of the preceding claims, wherein the gate structure further comprises a doped diamond layer in contact with the semi-insulating drift layer and a gate electrode disposed over the doped diamond layer.
- The semiconductor device of any one of the preceding claims, wherein the doped diamond layer is n-type doped.
- The semiconductor device of any one of the preceding claims, wherein the n-type doped diamond layer is doped with nitrogen (N) , phosphorus (P) , lithium (Li) , sodium (Na) , antimony (Sb) , oxygen (O) , sulfur (S) , or a combination thereof.
- The semiconductor device of any one of the preceding claims, wherein the nitride-based transistor further comprises a source, a drain electrodes and a gate structure disposed over the second nitride-based semiconductor layer, wherein the gate structure of the nitride-based transistor is located between the source and drain electrodes.
- The semiconductor device of any one of the preceding claims, wherein the gate structure further comprises a doped nitride-based semiconductor layer in contact with the second nitride-based semiconductor layer and a gate electrode disposed over the doped nitride-based semiconductor layer.
- The semiconductor device of any one of the preceding claims, further comprising a buffer layer in contact with the top surface of the second portion of the semi-insulating drift layer and located between the semi-insulating drift layer and the first nitride-based semiconductor layer of the nitride-based transistor.
- The semiconductor device of any one of the preceding claims, wherein the hydrogen-terminated top surface of the first portion comprises carbon-hydrogen bond.
- The semiconductor device of any one of the preceding claims, wherein the top surface of the second portion of the semi-insulating drift layer is devoid of hydrogen element.
- The semiconductor device of any one of the preceding claims, wherein the diamond substrate is a semi-insulating diamond substrate.
- The semiconductor device of any one of the preceding claims, wherein the semi-insulating drift layer further comprises a connecting portion connecting the first portion to the second potion.
- The semiconductor device of any one of the preceding claims, wherein a thickness of the first portion of the semi-insulating drift layer is thinner than whole thickness of the semi-insulating drift layer.
- A method for manufacturing a semiconductor device, comprising:forming a semi-insulating drift layer over a diamond substrate;performing a hydrogen-terminating process using hydrogen element, such that a top surface of a first portion of the semi-insulating drift layer is hydrogen-terminated, thereby forming a two-dimensional hole gas (2DHG) region adjacent to the top surface of the first portion;forming a diamond-based transistor over the top surface of the first portion of the semi-insulating drift layer; andforming a nitride-based transistor over a top surface of a second portion of the semi-insulating drift layer, wherein a second portion of the semi-insulating drift layer is separated from the first portion.
- The manufacturing method of any one of the preceding claims, further comprising:providing a mask layer on the semi-insulating drift layer prior to the step of performing the hydrogen-terminating process, wherein the mask layer has an opening to define the first portion of the semi-insulating drift layer.
- The manufacturing method of any one of the preceding claims, wherein forming the diamond-based transistor further comprises:forming a source and a drain electrodes on the top surface of the first portion of the semi-insulating drift layer; andforming a gate structure on the top surface of the first portion and between the source and the drain electrodes of the diamond-based transistor.
- The manufacturing method of any one of the preceding claims, further comprising:forming a buffer layer in contact with the top surface of the second portion of the semi-insulating drift layer prior to the step of forming the nitride-based transistor.
- The manufacturing method of any one of the preceding claims, wherein forming the nitride-based transistor further comprises:forming a first nitride-based semiconductor layer to be in contact with the top surface of the buffer layer;forming a second nitride-based semiconductor layer over the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a bandgap greater than that of the first nitride-based semiconductor layer;forming a source and a drain electrodes over the second nitride-based semiconductor layer; andforming a gate structure over the second nitride-based semiconductor layer, such that the gate structure is formed between the source and the drain electrodes of the nitride-based transistor.
- A semiconductor device comprising:a semi-insulating drift layer disposed over a diamond substrate;a diamond-based transistor disposed over a top surface of a first portion of the semi-insulating drift layer and comprising a drain and a source electrodes over the top surface of a first portion, wherein the top surface of the first portion is hydrogen-terminated such that a two-dimensional hole gas (2DHG) is formed adjacent to the top surface of the first portion;a buffer layer disposed over a top surface of a second portion of the semi-insulating drift layer; anda nitride-based transistor disposed over a top surface of the buffer layer and comprising:a first nitride-based semiconductor layer in contact with the top surface of the buffer layer; anda second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction and a two-dimensional electron gas (2DEG) region adjacent to the heterojunction;wherein a height level of the top surface of the buffer layer is different from a height level of the top surface of the first portion of the semi-insulating drift layer, such that the diamond-based transistor and the nitride-based transistor are at different height levels.
- The semiconductor device of any one of the preceding claims, wherein the height level of the top surface of the first portion is substantially the same as a height level of the top surface of the second portion, such that the top surface of the buffer layer is higher than that of the top surface of the first portion.
- The semiconductor device of any one of the preceding claims, wherein the nitride-based transistor is higher than the diamond-based transistor.
- The semiconductor device of any one of the preceding claims, wherein the height level of the top surface of the first portion is higher than a height level of the top surface of the second portion, such that the top surface of the buffer layer is lower than that of the top surface of the first portion.
- The semiconductor device of any one of the preceding claims, wherein the nitride-based transistor is lower than the diamond-based transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2022/090932 WO2023212856A1 (en) | 2022-05-05 | 2022-05-05 | Semiconductor device and method for manufacturing thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2022/090932 WO2023212856A1 (en) | 2022-05-05 | 2022-05-05 | Semiconductor device and method for manufacturing thereof |
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|---|---|---|---|---|
| WO2006081348A1 (en) * | 2005-01-26 | 2006-08-03 | Apollo Diamond, Inc. | Gallium nitride light emitting devices on diamond |
| GB2504613A (en) * | 2012-07-17 | 2014-02-05 | Element Six Technologies Us Corp | Integrated diamond p-channel FETs and GaN n-channel FETs |
| US20170018639A1 (en) * | 2015-07-17 | 2017-01-19 | Mitsubishi Electric Research Laboratories, Inc. | Semiconductor Device with Multiple Carrier Channels |
| WO2021142206A1 (en) * | 2020-01-08 | 2021-07-15 | The Board Of Trustees Of The Leland Stanford Junior University. | Methods and apparatuses involving diamond growth on gan |
| CN113659002A (en) * | 2020-05-12 | 2021-11-16 | 内蒙古工业大学 | With AlOXDiamond-based MISFET device of protective layer and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006081348A1 (en) * | 2005-01-26 | 2006-08-03 | Apollo Diamond, Inc. | Gallium nitride light emitting devices on diamond |
| GB2504613A (en) * | 2012-07-17 | 2014-02-05 | Element Six Technologies Us Corp | Integrated diamond p-channel FETs and GaN n-channel FETs |
| US20170018639A1 (en) * | 2015-07-17 | 2017-01-19 | Mitsubishi Electric Research Laboratories, Inc. | Semiconductor Device with Multiple Carrier Channels |
| WO2021142206A1 (en) * | 2020-01-08 | 2021-07-15 | The Board Of Trustees Of The Leland Stanford Junior University. | Methods and apparatuses involving diamond growth on gan |
| CN113659002A (en) * | 2020-05-12 | 2021-11-16 | 内蒙古工业大学 | With AlOXDiamond-based MISFET device of protective layer and preparation method thereof |
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