CN117941056A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN117941056A
CN117941056A CN202280060418.4A CN202280060418A CN117941056A CN 117941056 A CN117941056 A CN 117941056A CN 202280060418 A CN202280060418 A CN 202280060418A CN 117941056 A CN117941056 A CN 117941056A
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nitride
layer
semi
insulating
drift layer
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郝荣晖
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Innoscience Suzhou Semiconductor Co Ltd
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Innoscience Suzhou Semiconductor Co Ltd
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
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    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
    • H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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Abstract

The semiconductor device 1A includes a semi-insulating drift layer 20A, a diamond-based transistor 30, and a nitride-based transistor 50. A semi-insulating drift layer 20A is disposed over the diamond substrate 10A. The diamond based transistor 30 includes drain and source electrodes 303, 304 located over the upper surface of the first portion of the semi-insulating drift layer 20A. The upper surface TS1 of the first section is hydrogen terminated such that a two-dimensional hole gas 2DHG region G1 is formed adjacent to the upper surface TS1 of the first section. The nitride-based transistor 50 includes a first nitride-based semiconductor layer 501 and a second nitride-based semiconductor layer 502 stacked above the upper surface TS2 of the second portion of the semi-insulating drift layer 20A. The second nitride-based semiconductor layer 502 has a band gap greater than that of the first nitride-based semiconductor layer 501 to form a heterojunction and a two-dimensional electron gas 2DEG region G2 adjacent to the heterojunction.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present disclosure relates generally to a semiconductor device having a diamond substrate. More particularly, the present disclosure relates to Complementary Metal Oxide Semiconductor (CMOS) devices formed on diamond substrates.
Background
In recent years, intensive research into High Electron Mobility Transistors (HEMTs) has been very popular, particularly HEMTs for high power switching and high frequency applications. The III-nitride-based HEMT utilizes a heterojunction interface between two different band gap materials to form a structure of a quasi-quantum well, and the structure can accommodate a two-dimensional electron gas (2 DEG) region and meet the requirements of high-power/high-frequency devices. Examples of devices having a heterostructure include Heterojunction Bipolar Transistors (HBTs), heterojunction Field Effect Transistors (HFETs), and modulation doped FETs (MODFETs) in addition to HEMTs.
Disclosure of Invention
According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a semi-insulating drift layer, a diamond-based transistor, and a nitride-based transistor. The semi-insulating drift layer is disposed over a diamond substrate. The diamond-based transistor includes a drain electrode and a source electrode over an upper surface of the first portion of the semi-insulating drift layer. The upper surface of the first portion is hydrogen terminated such that a two-dimensional hole gas (2 DHG) region is formed adjacent the upper surface of the first portion. The nitride-based transistor includes a first nitride-based semiconductor layer and a second nitride-based semiconductor layer stacked over an upper surface of a second portion of the semi-insulating drift layer. The second nitride-based semiconductor layer has a band gap greater than that of the first nitride-based semiconductor layer to form a heterojunction and a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction.
According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a semi-insulating drift layer, a diamond-based transistor, a buffer layer, and a nitride-based transistor. The semi-insulating drift layer is disposed over a diamond substrate. The diamond-based transistor is disposed over an upper surface of a first portion of the semi-insulating drift layer and includes a drain electrode and a source electrode over the upper surface of the first portion. The upper surface of the first portion is hydrogen terminated such that a two-dimensional hole gas (2 DHG) region is formed adjacent the upper surface of the first portion. The buffer layer is disposed over an upper surface of the second portion of the semi-insulating drift layer. The nitride-based transistor is disposed over an upper surface of the buffer layer. The nitride-based transistor includes a first nitride-based semiconductor layer and a second nitride-based semiconductor layer. The first nitride-based semiconductor layer is in contact with an upper surface of the buffer layer. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer and has a band gap greater than that of the first nitride-based semiconductor layer to form a heterojunction and a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction. The height of the upper surface of the buffer layer is different from the height of the upper surface of the first portion of the semi-insulating drift layer such that the diamond-based transistor and the nitride-based transistor are at different heights.
According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method comprises the following steps. A semi-insulating drift layer is formed on the diamond substrate. An ion implantation process is performed using a hydrogen element such that an upper surface of the first portion of the semi-insulating drift layer is capped with hydrogen, thereby forming a two-dimensional hole gas (2 DHG) region adjacent to the upper surface of the semi-insulating drift layer. A diamond-based transistor is formed over an upper surface of the first portion of the semi-insulating drift layer. A nitride-based transistor is formed over an upper surface of the second portion of the semi-insulating drift layer. The second portion of the semi-insulating drift layer is separated from the first portion.
With the above configuration, in the present disclosure, a diamond-based transistor having a 2DHG region (i.e., a p-channel transistor) and a nitride-based transistor having a 2DEG region (i.e., an n-channel transistor) are formed on/over a diamond substrate having high thermal conductivity, thereby constituting a CMOS device. The CMOS device benefits from the high thermal conductivity of the diamond substrate; therefore, the heat dissipation efficiency of the CMOS device can be greatly improved. Thus, the CMOS device of the present disclosure may be suitable for high temperature applications.
Drawings
Aspects of the disclosure can be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Embodiments of the present disclosure are described in more detail below with reference to the attached drawing figures, wherein:
Fig. 1 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
Fig. 2A, 2B, 2C, 2D, 2E, and 2F illustrate different stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure;
fig. 3 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure; and
Fig. 4 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
Detailed Description
Common reference numerals are used throughout the drawings and the detailed description to designate the same or similar components. Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.
Spatial descriptors, such as "above," "below," "upper," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," "higher," "upper," "below," etc., are specified for the orientation of a component shown in the figures relative to a particular component or group of components, or a particular plane of a component or group of components. It should be understood that the spatial descriptors used herein are for illustrative purposes only, and that the actual implementation of the structures described herein may be spatially arranged in any direction or manner so long as such arrangement does not depart from the advantages of the embodiments of the present disclosure.
Further, it should be noted that the actual shape of the various structures depicted as being approximately rectangular may be curved, have rounded edges, have slightly uneven thickness, etc. in an actual device due to device manufacturing conditions. Straight lines and right angles are used for convenience only to represent layers and features.
In the following description, a semiconductor device/die/package, a method of manufacturing the same, and the like are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions, can be made without departing from the scope and spirit of the disclosure. Specific details may be omitted in order not to obscure the disclosure; however, the disclosure is written to enable any person skilled in the art to practice the teachings herein without undue experimentation.
Group III-V Field Effect Transistors (FETs), such as gallium nitride (GaN) or other group III-V based high mobility electron transistors (HEMTs), advantageously have a wide bandgap, high breakdown field, high thermal conductivity, which has potential advantages in power applications. However, the development of GaN-based HEMTs has encountered some bottleneck problems.
For example, CMOS devices are typically composed of n-channel transistors and p-channel transistors for logic functions. The n-channel transistor may be implemented by a GaN-based HEMT transistor. However, while GaN-based HEMT transistors have higher electron mobility, other types of p-channel transistors have much lower hole mobility than GaN-based HEMT transistors, resulting in an imbalance between the n-channel transistor drive capability and the p-channel transistor drive capability. One approach to solving the imbalance problem described above is to increase the size of the n-channel transistor to compensate for the difference between hole mobility and electron mobility. However, such a configuration is disadvantageous in terms of the trend of miniaturization of electronic devices.
In addition, another problem is the problem of heat dissipation. The high temperature not only reduces the operating efficiency of the electronic components, but also may damage or even burn out the CMOS devices, thereby limiting the application of the CMOS devices in high temperature environments. Therefore, it is necessary to solve the above-described problems.
Fig. 1 is a vertical cross-sectional view of a semiconductor device 1A according to some embodiments of the present disclosure. The semiconductor device 1A is, for example, a CMOS device. Specifically, the semiconductor device 1A includes a substrate 10A, a semi-insulating drift layer 20A, a diamond-based transistor 30, a buffer layer 40, and a nitride-based transistor 50.
At least to solve the above-described problems, in the present disclosure, the material of the substrate 10A is selected as a diamond substrate because the diamond substrate has excellent hole mobility and thermal conductivity. Specifically, the substrate 10A is a semi-insulating diamond substrate. As used herein, the term "semi-insulating" in relation to the semi-insulating diamond material of the present disclosure means that such material has a resistivity in the range of 1 x 10 -5 ohm-cm (Ω -cm) to 1 x 10 8 (Ω -cm). In this embodiment, the diamond substrate 10A may have a flat upper surface. The detailed structure of the semiconductor device 1A is described in detail below.
A semi-insulating drift layer 20A is provided on/over/above the substrate 10A. The semi-insulating drift layer 20A is in contact with the planar upper surface of the diamond substrate 10A. The semi-insulating drift layer 20A is disposed conformally with the substrate 10A, so the semi-insulating drift layer 20A may have a flat upper surface. The material of the semi-insulating drift layer 20A may be, for example, diamond. In some embodiments, semi-insulating drift layer 20A may be a surface layer of diamond substrate 10A. The semi-insulating drift layer 20A may be p-type doped. In some embodiments, the p-doped semi-insulating drift layer 20A is doped with boron (B).
The semi-insulating drift layer 20A includes portions 202, 204 and a connection 206. A diamond based transistor 30 (i.e., a p-channel transistor) may be formed on portion 202 (i.e., a p-channel portion/region) of semi-insulating drift layer 20A. Nitride-based transistor 50 (i.e., an n-channel transistor) may be formed on portion 204 (i.e., an n-channel portion/region) of semi-insulating drift layer 20A. A connection 206 is located between the portions 202, 204. Connection 206 connects portion 202 to portion 204. In the present embodiment, the heights of the top surfaces TS1, TS2 of the portions 202, 204 are substantially the same as the height of the top surface TSP of the connection portion 206.
In forming the diamond-based transistor 30, a masking layer is provided to cover the connection portions 206 and portions 204 and to expose portions 202. Then, the portion 202 is subjected to a hydrogen capping process with a hydrogen element so that the upper surface of the portion 202 of the semi-insulating drift layer 20A may be hydrogen capped. As a result, the hydrogen-terminated upper surface TS1 of the portion 202 includes/has carbon-hydrogen (CH) bonds such that a two-dimensional hole gas (2 DHG) region G1 is formed adjacent to the upper surface TS1 of the portion 202. The thickness T' of the hydrogen-terminated portion 202 is thinner/smaller than the total thickness T of the semi-insulating drift layer 20A.
On the other hand, the connection portion 206 and the portion 204 are not affected by the hydrogen element due to the blocking of the mask layer. Thus, the upper surface of portion 204 and the upper surface of connecting portion 206 are free of carbon hydrogen bonds (or hydrogen elements).
With respect to semi-insulating drift layer 20A, portion 202 may be referred to as a hydrogen-terminated portion. Portion 204 and connecting portion 206 may be referred to as non-hydrogen terminated portions. Note that the term "hydrogen capping portion" as used in this disclosure refers to a state in which the diamond crystal is capped by coupling a hydrogen element with dangling bonds (i.e., unoccupied bonds of carbon atoms in the semi-insulating drift layer 20A before the hydrogen capping process). On the other hand, the term "non-hydrogen-terminated portion" refers to a state in which the surface of the diamond crystal is not terminated with hydrogen element.
It is noted that the density of the 2DHG region G1 is positively correlated with the c—h bond density of the portion 202 of the semi-insulating drift layer 20A. By subjecting the semi-insulating drift layer 20A to a hydrogen capping process for different crystal orientations, diamond-based transistors 30 having different 2DHG densities may be obtained, thereby achieving different device requirements.
For example, the semi-insulating drift layer 20A having a (110) crystal orientation has a carbon density that is greater than the carbon density of the semi-insulating drift layer 20A having a (001) crystal orientation. Thus, after the step of hydrogen capping treatment, the C-H bond density of the portion 202 having the (110) crystal orientation may be greater than the C-H bond density of the portion 202 having the (001) crystal orientation. Thus, the 2DHG density of the hydrogen terminated portion 202 having a (110) crystal orientation may be greater than the 2DHG density of the hydrogen terminated portion 202 having a (001) crystal orientation. Therefore, the semi-insulating drift layer 20A having the (110) crystal orientation can be applied to a device requiring high current density.
In some embodiments, the hydrogen element (1 H) used in the hydrogen capping process may be replaced with an isotope of the hydrogen element, such as deuterium (2 H), to achieve different electrical requirements.
The diamond-based transistor 30 is disposed on/over the upper surface TS1 of the portion 202 of the semi-insulating drift layer 20A. The diamond-based transistor 30 is formed at a portion 202 of the semi-insulating drift layer 20A. The diamond-based transistor 30 includes electrodes 303, 304 and a gate structure GS1.
Electrodes 303 and 304 are disposed on/over portion 202 of semi-insulating drift layer 20A. The electrodes 303 and 304 are in contact with the upper surface TS1 of the semi-insulating drift layer 20A. The electrodes 303 and 304 are disposed on opposite sides of the gate structure GS1, respectively. In some embodiments, electrode 303 may serve as a source electrode. In some embodiments, electrode 303 may serve as a drain electrode. In some embodiments, electrode 304 may serve as a source electrode. In some embodiments, electrode 304 may function as a drain electrode. The role of electrodes 303 and 304 depends on the design of the device.
In some embodiments, electrodes 303 and 304 may include, for example, but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. Exemplary materials for electrodes 303 and 304 may include metals having high work functions. Metals having a high work function may include, for example, but are not limited to, pd, pt, au, or combinations thereof. Each of the electrodes 303 and 304 may be a single layer or multiple layers having the same or different compositions. The electrodes 303 and 304 form ohmic contacts with the semi-insulating drift layer 20A.
In this embodiment, the distance between the electrode 303 and the gate structure GS1 may be substantially the same as the distance between the electrode 304 and the gate structure GS 1. In some embodiments, the distance between electrode 303 and gate structure GS1 may be less than the distance between electrode 304 and gate structure GS 1. The distance relationship described above is also determined by the device design.
The doped diamond layer 305 has a conductivity type opposite to that of the semi-insulating drift layer 20A. In particular, the semi-insulating drift layer 20A may be p-type doped, and thus the doped diamond layer 305 may be n-type doped. In some embodiments, the N-doped diamond layer 305 is doped with nitrogen (N), phosphorus (P), lithium (Li), sodium (Na), antimony (Sb), oxygen (O), sulfur (S), or a combination thereof.
In the exemplary illustration of fig. 1, the diamond-based transistor 30 is an enhancement transistor that is normally off when the gate electrode 306 is at about zero bias. In particular, the n-type doped diamond layer 305 may form at least one pn junction with the nitride-based semiconductor layer 502 to deplete the 2DHG region G1 such that at least one region of the 2DHG region G1 corresponding to a location below the corresponding gate electrode 306 has a different characteristic (e.g., a different hole concentration) than the remainder of the 2DHG region G1, and is thus blocked.
Due to this mechanism, the diamond-based transistor 30 has normally-off characteristics. In other words, when no voltage is applied to the gate electrode 306 or the voltage applied to the gate electrode 306 is less than the threshold voltage (i.e., the minimum voltage required to form an inversion layer under the gate electrode 114), the portion of the 2DHG region G1 under the gate electrode 306 remains blocked, and thus no current flows.
In some embodiments, the doped diamond layer 305 may be omitted such that the diamond-based transistor 30 is a depletion transistor, meaning that the diamond-based transistor 30 is in a normally-on state at zero gate-source voltage.
Exemplary materials for the gate electrode 306 may include metals or metal compounds. The gate electrode 306 may be formed as a single layer or multiple layers having the same or different compositions. Exemplary materials for the metal or metal compound may include, for example, but are not limited to W, au, pd, ti, ta, co, ni, pt, mo, tiN, taN, metal alloys or compounds thereof, or other metal compounds.
The nitride-based transistor 50 is disposed on/over the upper surface TS2 of the portion 204 of the semi-insulating drift layer 20A. The nitride-based transistor 50 includes nitride-based semiconductor layers 501, 502, electrodes 503, 504, and a gate structure GS2.
It should be noted that lattice mismatch and thermal mismatch problems may occur due to the material difference between the nitride-based transistor 50 and the semi-insulating drift layer 20A. In this embodiment, the buffer layer 40 may be formed/located between the portion 204 of the semi-insulating drift layer 20A and the nitride-based semiconductor layer 501 of the nitride-based transistor 50 at least in order to prevent negative effects caused by thermal and lattice mismatch.
The buffer layer 40 may be configured to reduce lattice mismatch and thermal mismatch between the semi-insulating drift layer 20A and the nitride-based semiconductor layer 501 of the nitride-based transistor 50, thereby eliminating defects due to mismatch/difference. Therefore, the nitride-based transistor 50 can be compatible with the semi-insulating drift layer 20A.
In this regard, the phrase "compatible" means that the buffer layer 40 can provide a crystalline transition from the semi-insulating drift layer 20A to the nitride-based semiconductor layers 501, 502 of the nitride-based transistor 50 by appropriately selecting the material of the buffer layer 40. The material properties of the semi-insulating drift layer 20A may be such that an epitaxial layer is formed thereon. Thus, semi-insulating drift layer 20A may provide for the formation of a p-channel transistor and provide a platform for another epitaxial layer to be grown continuously thereon. The "further epitaxial layer" may be the basis of an n-channel transistor, thus constituting a CMOS device.
For example, buffer layer 40 may include a III-V compound. The III-V compounds may include, for example, but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Thus, exemplary materials for buffer layer 40 may also include, for example, but are not limited to GaN, alN, alGaN, inAlGaN or combinations thereof.
In some embodiments, the buffer layer 40 may be omitted to reduce the manufacturing cost of the semiconductor device 1A.
The buffer layer 40 is disposed on/over/on the upper surface TS2 of the portion 204 of the semi-insulating drift layer 20A. The buffer layer 40 is in contact with the upper surface TS2 of the portion 204 of the semi-insulating drift layer 20A such that the height of the upper surface TSB of the buffer layer 40 is higher than the height of the upper surface TS2 of the portion 204 of the semi-insulating drift layer 20A. Since the heights of the upper surfaces TS1, TS2 of the portions 202, 204 are substantially the same, the height of the upper surface TSB of the buffer layer 40 is different (e.g., higher) than the height of the upper surface TS1 of the portion 202 of the semi-insulating drift layer 20A. Thus, the diamond-based transistor 30 and the nitride-based transistor 50 are at different heights. More specifically, the nitride-based transistor 50 may be formed higher than the diamond-based transistor 30.
Nitride-based semiconductor layers 501, 502 are stacked on top of upper surface TS2 of portion 204 of semi-insulating drift layer 20A. The nitride-based semiconductor layer 501 may be disposed on/over the upper surface TSB of the buffer layer 40. The nitride-based semiconductor layer 501 may be in contact with the upper surface TSB of the buffer layer 40. The buffer layer 40 may be located between the semi-insulating drift layer 20A and the nitride-based semiconductor layer 501 of the nitride-based transistor 50. The nitride-based semiconductor layer 502 may be disposed on/over/above the nitride-based semiconductor layer 501.
Exemplary materials for nitride-based semiconductor layer 501 may include, for example, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inN, in x Al y Ga(1-x-y) N, where x+y.ltoreq.1, al x Ga(1-x) N, where x.ltoreq.1. Exemplary materials for nitride-based semiconductor layer 502 may include, for example, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inN, in x Al y Ga(1–x–y) N, where x+y.ltoreq.1, al y Ga(1–y) N, where y.ltoreq.1.
The exemplary materials of the nitride-based semiconductor layers 501 and 502 are selected such that the band gap (i.e., the forbidden band width) of the nitride-based semiconductor layer 502 is greater/higher than the band gap of the nitride-based semiconductor layer 501, which results in their electron affinities being different from each other and forming a heterojunction therebetween. For example, when the nitride-based semiconductor layer 501 is an undoped GaN layer having a band gap of about 3.4eV, the nitride-based semiconductor layer 502 may be selected to be an AlGaN layer having a band gap of about 4.0 eV. In this way, the nitride-based semiconductor layers 501 and 502 can function as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the bonding interface between the channel layer and the barrier layer such that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2 DEG) region G2 in the vicinity of the heterojunction. Thus, the nitride-based transistor 50 may include at least one GaN-based High Electron Mobility Transistor (HEMT).
Electrodes 503 and 504 are provided on/over/above the nitride-based semiconductor layer 502. The electrodes 503 and 504 are in contact with the upper surface of the nitride-based semiconductor layer 502. Electrodes 503 and 504 are disposed on opposite sides of the gate structure GS2, respectively. In some embodiments, electrode 503 may serve as a source electrode. In some embodiments, electrode 503 may serve as a drain electrode. In some embodiments, electrode 504 may serve as a source electrode. In some embodiments, electrode 504 may serve as a drain electrode. The role of electrodes 503 and 504 depends on the device design.
In some embodiments, electrodes 503 and 504 may include, for example, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. Exemplary materials for electrodes 503 and 504 may include metals having low work functions. The metal having a low work function may include, for example, but is not limited to, ti, al, ta, or combinations thereof. Each of the electrodes 503 and 504 may be a single layer or a plurality of layers having the same or different compositions. The electrodes 503 and 504 form ohmic contacts with the nitride-based semiconductor layer 502.
In the present embodiment, the distance between the electrode 503 and the gate structure GS2 may be substantially the same as the distance between the electrode 504 and the gate structure GS 2. In some embodiments, the distance between the electrode 503 and the gate structure GS2 may be smaller than the distance between the electrode 504 and the gate structure GS 2. The distance relationship described above is also determined by the device design.
The gate structure GS2 is disposed/located between the electrodes 503, 504. The gate structure GS2 further includes a doped nitride-based semiconductor layer 505 and a gate electrode 506. The doped nitride-based semiconductor layer 505 is in contact with the upper surface of the nitride-based semiconductor layer 502. The gate electrode 506 is disposed on/over/on the doped nitride-based semiconductor layer 505. The gate electrode 506 is in contact with the doped nitride-based semiconductor layer 505.
In the exemplary illustration of fig. 1, nitride-based transistor 50 is an enhancement mode device. The nitride-based transistor 50 is in a normally-off state when the gate electrode 506 is at about zero bias. Specifically, the doped nitride-based semiconductor layer 505 may form at least one pn-junction with the nitride-based semiconductor layer 502 to deplete the 2DEG region G2 such that at least one region of the 2DEG region G2 corresponding to a location below the corresponding gate electrode 506 has a different characteristic (e.g., a different electron concentration) than the remainder of the 2DEG region G2, and is thus blocked.
Due to such a mechanism, the nitride-based transistor 50 has normally-off characteristics. In other words, when no voltage is applied to the gate electrode 506 or the voltage applied to the gate electrode 506 is less than the threshold voltage (i.e., the minimum voltage required to form an inversion layer under the gate electrode 506), the portion of the 2DEG region G2 under the gate electrode 506 remains blocked, and thus no current flows.
In some embodiments, the doped nitride-based semiconductor layer 505 may be omitted such that the nitride-based transistor 50 is a depletion-mode device, meaning that the nitride-based transistor 50 is in a normally-on state at zero gate-to-source voltage.
The doped nitride-based semiconductor layer 505 may be a p-type doped III-V semiconductor layer. Exemplary materials for the doped nitride-based semiconductor layer 505 may include, for example, but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped material is obtained by using p-type impurities such as Be, zn, cd, and Mg. In some embodiments, nitride-based semiconductor layer 501 comprises undoped GaN, nitride-based semiconductor layer 502 comprises AlGaN, and doped nitride-based semiconductor layer 505 is a p-type GaN layer capable of bending the underlying band structure upward and depleting the corresponding region of 2DEG region G2, thereby placing nitride-based transistor 50 in an off state.
Exemplary materials for the gate electrode 506 may include metals or metal compounds. The gate electrode 506 may be formed as a single layer or multiple layers of the same or different compositions. Exemplary materials for the metal or metal compound may include, for example, but are not limited to W, au, pd, ti, ta, co, ni, pt, mo, tiN, taN, metal alloys or compounds thereof, or other metal compounds.
The connection 206 between the diamond-based transistor 30 and the nitride-based transistor 50 may provide good insulation due to its high resistivity. In some embodiments, at least one Shallow Trench Isolation (STI) may be formed in the connection 206 to separate and define the diamond transistor 30 and the nitride-based transistor 50.
Based on the above description, in the semiconductor device 1A, the diamond transistor 30 serving as a p-channel transistor and the nitride-based transistor 50 serving as an n-channel transistor may be integrated on the same diamond substrate 10A, thereby constituting a CMOS device. Due to the high thermal conductivity of the diamond substrate 10A, heat generated during operation of the semiconductor device 1A can be rapidly dissipated through the diamond substrate 10A. Therefore, the semiconductor device 1A can be applied to a high-temperature environment. In addition, the diamond transistor 30 has high hole mobility and high current density comparable to the nitride-based transistor 50. Thus, a more balanced CMOS device can be realized in the semiconductor device 1A.
Different stages of a method for manufacturing the semiconductor device 1A are shown in fig. 2A, 2B, 2C, 2D, 2E and 2F. Hereinafter, deposition techniques may include, for example, but are not limited to, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), metal Organic CVD (MOCVD), plasma Enhanced CVD (PECVD)), low Pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
Referring to fig. 2A, a semi-insulating drift layer 60 is formed on/over the diamond substrate 10A.
Referring to fig. 2B, a mask layer ML is provided on the semi-insulating drift layer 10A. The mask layer ML has an opening OG (aperture) to define the position of the portion 202 of the semi-insulating drift layer 10A. Then, a hydrogen capping process is performed using a hydrogen element such that the upper surface TS1 of the portion 202 of the semi-insulating drift layer 10A is hydrogen capped, thereby forming a two-dimensional hole gas (2 DHG) region G1 adjacent to the upper surface TS1 of the portion 202. The remaining portion of the semi-insulating drift layer 10A is free of hydrogen element due to the blocking of the mask layer ML.
Referring to fig. 2C, a diamond based transistor 30 is formed on/over/on the upper surface TS1 of the portion 202 of the semi-insulating drift layer 20A. More specifically, the electrodes 303, 304 of the diamond-based transistor 30 are formed on/above the upper surface TS1 of the portion 202 of the semi-insulating drift layer 20A. The gate structure GS1 of the diamond-based transistor 30 is formed on/over/on the portion 202 of the semi-insulating drift layer 20A and between the electrodes 303, 304. A doped diamond layer 305 of the gate structure GS1 is formed on/over/on the upper surface TS1 of the portion 202 of the semi-insulating drift layer 20A and between the electrodes 303, 304. The doped diamond layer 305 may deplete the region of the 2DHG region G1 therebelow. A gate electrode 306 of the gate structure GS1 is formed on/over the doped diamond layer 305.
Referring to fig. 2D, the buffer layer 40 is formed to be in contact with the upper surface TS2 of the portion 204 of the semi-insulating drift layer 20A.
Referring to fig. 2E, the nitride-based transistor 50 is formed over the upper surface TS2 of the portion 204 of the semi-insulating drift layer 20A, wherein the portion 204 of the semi-insulating drift layer 20A is separated from the portion 202.
Specifically, the nitride-based semiconductor layer 501 of the nitride-based transistor 50 is formed in contact with the upper surface TSB of the buffer layer 40. A nitride-based semiconductor layer 502 of the nitride-based transistor 50 is formed on/over/on the nitride-based semiconductor layer 501, wherein the band gap of the nitride-based semiconductor layer 502 is larger than that of the nitride-based semiconductor layer 501, thereby forming a heterojunction and a 2DEG region G2 adjacent to the heterojunction.
Referring to fig. 2F, electrodes 503, 504 of the nitride-based transistor 50 are formed on/over/above the nitride-based semiconductor layer 502. A gate structure GS2 of the nitride-based transistor 50 is formed over the nitride-based semiconductor layer 502 such that the gate structure GS2 is formed between the electrodes 503 and 504. More specifically, the doped nitride-based semiconductor layer 505 of the gate structure GS2 is formed on/over/above the nitride-based semiconductor layer 502. The doped nitride-based semiconductor layer 505 may deplete the region of the 2DEG region G2 therebelow. The gate electrode 506 of the gate structure GS2 is formed on/over/on the doped nitride-based semiconductor layer 505. Thus, the semiconductor device 1A shown in fig. 1 is formed.
Fig. 3 is a vertical cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure. The semiconductor device 1B is similar to the semiconductor device 1A described and illustrated with reference to fig. 1, but the diamond substrate 10B may have portions 102, 104 of different thickness, wherein the thickness T1 of the portion 102 of the diamond substrate 10B is greater than the thickness T2 of the portion 104 (i.e., recessed portion) of the diamond substrate 10B. That is, the height of the upper surface of the portion 102 of the diamond substrate 10B is higher than the height of the upper surface of the portion 104 of the diamond substrate 10B.
The semi-insulating drift layer 20B is disposed conformally with the diamond substrate 10 such that the semi-insulating drift layer 20B may have portions 202, 204 at different heights. In the present embodiment, the height of the upper surface TS1 of the portion 202 of the semi-insulating drift layer 20B is higher than the height of the upper surface TS2 of the portion 104 of the semi-insulating drift layer 20B. The connection 206 of the semi-insulating drift layer 20 may extend vertically from the portion 202 to the portion 204.
The buffer layer 40 is disposed over the upper surface TS2 of the portion 204 of the semi-insulating drift layer 20B. The buffer layer 40 is in contact with the upper surface TS2 of the portion 204 of the semi-insulating drift layer 20B. The upper surface TSB of buffer layer 40 is lower than upper surface TS1 of portion 202. Buffer layer 40 is within a thickness T1 of portion 202 of diamond substrate 10B.
Because of the height relationship between the upper surface TS1 of the portion 202 and the upper surface TSB of the buffer layer 40, the nitride-based transistor 50 may be formed lower than the diamond-based transistor 30, and the nitride-based transistor 50 may be formed within the thickness T1 of the portion 202 of the diamond substrate 10B. Accordingly, the semiconductor device 1B may have a reduced thickness as compared to the semiconductor device 1A in fig. 1. As shown in fig. 1, it is advantageous to cater to the trend of miniaturization of electronic devices.
Fig. 4 is a vertical cross-sectional view of a semiconductor device 1C according to some embodiments of the present disclosure. The semiconductor device 1C is similar to the semiconductor device 1A described and illustrated with reference to fig. 1, except that the thickness T3 of the portion 202 of the semi-insulating drift layer 20C is greater than the thickness T4 of the portion 204 (i.e., recessed portion) of the semi-insulating drift layer 20C. The upper surface TS1 of portion 202 is within the thickness of buffer layer 40.
Since the nitride-based transistor 50 is formed in the concave portion 204 of the semi-insulating drift layer 20C, the semiconductor device 1C can have a reduced thickness as compared with the semiconductor device 1A in fig. 1, which is advantageous in catering to the trend of miniaturization of electronic devices.
Based on the above description, in the present disclosure, a semi-insulating drift layer is formed over a diamond substrate. A 2DHG region is formed adjacent to an upper surface of the hydrogen-terminated portion of the semi-insulating drift layer by performing a hydrogen-terminated process using a hydrogen element on a portion of the semi-insulating drift layer. Then, a diamond-based transistor is formed on the hydrogen-terminated portion of the semi-insulating drift layer to function as a p-channel transistor. On the other hand, before forming the nitride-based transistor, a buffer layer may be formed on another portion of the semi-insulating drift layer. Then, a nitride-based transistor is formed on the buffer layer to serve as an n-channel transistor. In this way, the diamond-based transistor and the nitride-based transistor can be integrated on the same diamond substrate having high thermal conductivity. Therefore, the heat dissipation efficiency of the semiconductor device can be improved. In addition, since the carrier mobility/current density value of the diamond-based transistor is comparable to that of the nitride-based transistor, the imbalance problem can be alleviated. Thus, a more balanced CMOS device can be realized.
The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, to thereby enable others skilled in the art to understand the disclosure for various embodiments and with various modifications as are suited to the particular use contemplated.
The terms "substantially," "about," and "approximately" as used herein and not otherwise defined are used to describe and explain small variations. When used in connection with an event or circumstance, the terms can encompass instances where the event or circumstance occurs precisely and instances where the event or circumstance occurs very closely. For example, when used in conjunction with a numerical value, these terms may encompass a variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces lying within a few microns along the same plane, for example within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm along the same plane.
As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, an element disposed "on" or "over" another element may encompass the situation in which the former element is directly on (e.g., in physical contact with) the latter element, as well as the situation in which one or more intervening elements are located between the former element and the latter element.
While the present disclosure has been depicted and described with reference to particular embodiments thereof, such depicted and described are not meant to be limiting. It will be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations are not necessarily drawn to scale. There may be differences between artistic manifestations in the present disclosure and actual devices due to manufacturing processes and tolerances. Furthermore, it should be appreciated that the actual devices and layers may deviate from the rectangular layer depiction in the figures and may include angled surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. Other embodiments not specifically shown may exist in the present disclosure. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present invention. Accordingly, unless specifically indicated herein, the order and grouping of operations is not limited.

Claims (25)

1. A semiconductor device, comprising:
A semi-insulating drift layer disposed over the diamond substrate;
a diamond-based transistor comprising a drain and a source over an upper surface of a first portion of the semi-insulating drift layer, wherein the upper surface of the first portion is hydrogen terminated such that a two-dimensional hole gas 2DHG region is formed adjacent the upper surface of the first portion; and
A nitride-based transistor comprising a first nitride-based semiconductor layer and a second nitride-based semiconductor layer stacked over an upper surface of a second portion of the semi-insulating drift layer, wherein a band gap of the second nitride-based semiconductor layer is greater than a band gap of the first nitride-based semiconductor layer to form a heterojunction and a two-dimensional electron gas 2DEG region adjacent to the heterojunction.
2. A semiconductor device according to any preceding claim, wherein the semi-insulating drift layer is p-doped.
3. A semiconductor device according to any preceding claim, wherein the p-type semi-insulating drift layer is doped with boron (B).
4. A semiconductor device according to any preceding claim, wherein the diamond-based transistor further comprises a gate structure disposed between the drain and the source of the diamond-based transistor.
5. The semiconductor device of any of the preceding claims, wherein the gate structure further comprises a doped diamond layer in contact with the semi-insulating drift layer and a gate electrode disposed over the doped diamond layer.
6. A semiconductor device according to any preceding claim, wherein the doped diamond layer is n-doped.
7. A semiconductor device according to any of the preceding claims, wherein the N-doped diamond layer is doped with nitrogen (N), phosphorus (P), lithium (Li), sodium (Na), antimony (Sb), oxygen (O), sulfur (S), or a combination of nitrogen, phosphorus, lithium, sodium, antimony, oxygen, sulfur.
8. The semiconductor device of any of the preceding claims, wherein the nitride-based transistor further comprises a source, a drain, and a gate structure disposed over the second nitride-based semiconductor layer, wherein the gate structure of the nitride-based transistor is located between the source and the drain.
9. The semiconductor device of any of the preceding claims, wherein the gate structure further comprises a doped nitride-based semiconductor layer in contact with the second nitride-based semiconductor layer and a gate electrode disposed over the doped nitride-based semiconductor layer.
10. The semiconductor device of any of the preceding claims, further comprising a buffer layer in contact with the upper surface of the second portion of the semi-insulating drift layer and located between the semi-insulating drift layer and the first nitride-based semiconductor layer of the nitride-based transistor.
11. The semiconductor device of any of the preceding claims, wherein the hydrogen-terminated upper surface of the first portion comprises carbon-hydrogen bonds.
12. The semiconductor device of any of the preceding claims, wherein the upper surface of the second portion of the semi-insulating drift layer is free of hydrogen elements.
13. A semiconductor device according to any preceding claim, wherein the diamond substrate is a semi-insulating diamond substrate.
14. The semiconductor device of any of the preceding claims, wherein the semi-insulating drift layer further comprises a connection connecting the first portion to the second portion.
15. The semiconductor device of any of the preceding claims, wherein a thickness of the first portion of the semi-insulating drift layer is thinner than an entire thickness of the semi-insulating drift layer.
16. A method of manufacturing a semiconductor device, comprising:
forming a semi-insulating drift layer over the diamond substrate;
performing a hydrogen capping process using a hydrogen element such that an upper surface of a first portion of the semi-insulating drift layer is hydrogen capped, thereby forming a two-dimensional hole gas 2DHG region adjacent to the upper surface of the first portion;
Forming a diamond-based transistor over the upper surface of the first portion of the semi-insulating drift layer; and
A nitride-based transistor is formed over an upper surface of a second portion of the semi-insulating drift layer, wherein the second portion of the edge drift layer is separated from the first portion.
17. The manufacturing method according to any one of the preceding claims, further comprising:
A mask layer is provided over the semi-insulating drift layer prior to performing the hydrogen termination process, wherein the mask layer has an opening to define the first portion of the semi-insulating drift layer.
18. The method of manufacturing according to any one of the preceding claims, wherein forming the diamond-based transistor further comprises:
forming a source and a drain on the upper surface of the first portion of the semi-insulating drift layer; and
A gate structure is formed on the upper surface of the first portion and between the source and the drain of the diamond-based transistor.
19. The manufacturing method according to any one of the preceding claims, further comprising:
A buffer layer is formed in contact with the upper surface of the second portion of the semi-insulating drift layer prior to forming the nitride-based transistor.
20. The method of manufacturing according to any one of the preceding claims, wherein forming the nitride-based transistor further comprises:
forming a first nitride-based semiconductor layer in contact with the upper surface of the buffer layer;
forming a second nitride-based semiconductor layer over the first nitride-based semiconductor layer, wherein a band gap of the second nitride-based semiconductor layer is greater than a band gap of the first nitride-based semiconductor layer;
forming a source electrode and a drain electrode over the second nitride-based semiconductor layer; and
A gate structure is formed over the second nitride-based semiconductor layer such that the gate structure is formed between the source and the drain of the nitride-based transistor.
21. A semiconductor device, comprising:
A semi-insulating drift layer disposed over the diamond substrate;
A diamond-based transistor disposed over an upper surface of a first portion of the semi-insulating drift layer and comprising a drain and a source over the upper surface of the first portion, wherein the upper surface of the first portion is hydrogen-terminated such that a two-dimensional hole gas 2DHG is formed adjacent the upper surface of the first portion;
a buffer layer disposed over an upper surface of the second portion of the semi-insulating drift layer; and
A nitride-based transistor disposed over an upper surface of the buffer layer and comprising:
A first nitride-based semiconductor layer in contact with the upper surface of the buffer layer; and
A second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer and having a band gap greater than that of the first nitride-based semiconductor layer to form a heterojunction and a two-dimensional electron gas 2DEG region adjacent to the heterojunction;
Wherein a height of the upper surface of the buffer layer is different from a height of the upper surface of the first portion of the semi-insulating drift layer such that the diamond-based transistor and the nitride-based transistor are at different heights.
22. The semiconductor device of any of the preceding claims, wherein a height of the upper surface of the first portion is substantially the same as a height of the upper surface of the second portion such that the upper surface layer of the buffer layer is higher than the upper surface of the first portion.
23. A semiconductor device according to any preceding claim, wherein the nitride-based transistor is higher than the diamond-based transistor.
24. The semiconductor device of any of the preceding claims, wherein a height of the upper surface of the first portion is higher than a height of the upper surface of the second portion such that a height of the upper surface of the buffer layer is lower than a height of the upper surface of the first portion.
25. A semiconductor device according to any preceding claim, wherein the nitride-based transistor is lower than the diamond-based transistor.
CN202280060418.4A 2022-05-05 2022-05-05 Semiconductor device and method for manufacturing the same Pending CN117941056A (en)

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