WO2024113097A1

WO2024113097A1 - Semiconductor device and method for manufacturing the same

Info

Publication number: WO2024113097A1
Application number: PCT/CN2022/134705
Authority: WO
Inventors: Chi Sun; Ronghui Hao; King Yuen Wong
Original assignee: Innoscience (suzhou) Semiconductor Co., Ltd.
Priority date: 2022-11-28
Filing date: 2022-11-28
Publication date: 2024-06-06
Also published as: CN118613917A

Abstract

The semiconductor device includes a silicon-based substrate, at least one III-V buffer layer, at least one high-electron-mobility transistor (HEMT), and a first conductive pad. The silicon-based substrate includes at least one p-doped region and at least one n-doped region which abut against each other. The at least one III-V buffer layer is disposed on the p-doped region of the silicon-based substrate. The at least one HEMT is disposed on the III-V buffer layer. The first conductive pad is disposed over the n-doped region and makes contact with the n-doped region.

Description

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Chi SUN; Ronghui HAO; King Yuen WONG

Field of the Disclosure:

The present disclosure generally relates to a semiconductor device. More specifically, the present disclosure relates to a semiconductor device integrated with electrostatic discharge (ESD) protection components and high-electron-mobility transistors (HEMTs) .

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a silicon-based substrate, at least one III-V buffer layer, at least one high-electron-mobility transistor (HEMT) , and a first conductive pad. The silicon-based substrate includes at least one p-doped region and at least one n-doped region which abut against each other. The at least one III-V buffer layer is disposed on the p-doped region of the silicon-based substrate. The at least one HEMT is disposed on the III-V buffer layer. The first conductive pad is disposed over the n-doped region and makes contact with the n-doped region.

In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed on a silicon-based substrate including at least one p-doped region.

A second nitride-based semiconductor layer is formed on the first nitride-based semiconductor layer. At least one high-electron-mobility transistor (HEMT) is formed over the second nitride-based semiconductor layer. At least one n-doped region is formed in the silicon-based substrate. A first conductive pad is formed to make contact with the n-doped region.

In accordance with one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a silicon-based substrate, a plurality of III-V buffer layers, a plurality of high-electron-mobility transistors (HEMTs) , and a plurality of electrostatic discharge (ESD) protection components. The silicon-based substrate includes at least one p-doped region and a plurality of n-doped regions. The III-V buffer layers are disposed on the p-doped region of the silicon-based substrate and are separated from each other. The high-electron-mobility transistors (HEMTs) are disposed on the III-V buffer layers. The electrostatic discharge (ESD) protection components are disposed on the silicon-based substrate and at least apply the n-doped regions.

Based on the above, in the present disclosure, the HEMT and the ESD protection component are formed from the same silicon-based substrate, and the HEMT is electrically coupled to the ESD protection component. Since the manufacturing method applied to the silicon-based substrate has a high manufacturing precision, the HEMT and the ESD protection component can be manufactured in a small volume. Furthermore, as an ESD event occurs, the electrostatic accumulate in the HEMT can discharge through the ESD protection component during the operation of the semiconductor device. Hence, the semiconductor device can have a good reliability.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1A is a top view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 1B is a vertical cross-sectional view of the semiconductor device in the FIG. 1A taken along a line A-A’ according to some embodiments of the present disclosure;

FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show different stages of a method for manufacturing a semiconductor device in the FIGS. 1A and 1B according to some embodiments of the present disclosure;

FIG. 3A and FIG. 3B show different stages of another method for manufacturing a semiconductor device in the FIGS. 1A and 1B according to some embodiments of the present disclosure;

FIG. 4 shows a top view of a resulted structure in the FIG. 3A;

FIG. 5 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 6 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 7 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 8 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

FIG. 9A and FIG. 9B show different stages of a method for manufacturing a semiconductor device in the FIG. 7 according to some embodiments of the present disclosure; and

FIG. 10 is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

In order to conform to the trend of continued miniaturization of electronic devices, semiconductor devices are manufactured to become smaller. However, the advanced semiconductor devices also become more susceptible to ESD damage. ESD phenomenon occurs when excess charges are transmitted from the I/O pin to the integrated circuit too quickly, which damages the internal circuit. As a result, there is a need to build the ESD protection circuits onto the chip to protect the devices and circuits of the IC against ESD damage. Nevertheless, the volume of existing semiconductor devices integrating with ESD protection circuits is still too large, which is unfavorable to meet the trend of device miniaturization.

At least to overcome the aforesaid issue, the present disclosure provides a novel structure.

FIG. 1A is a top view of a semiconductor device 1A according to some embodiments of the present disclosure. FIG. 1B is a vertical cross-sectional view of the semiconductor device 1A in the FIG. 1A taken along a line A-A’ according to some embodiments of the present disclosure.

Referring FIGS. 1A and 1B, the semiconductor device 1A includes a substrate 10, a buffer layer 20, a plurality of high-electron-mobility transistors (HEMT) 100, and a plurality of electrostatic discharge (ESD) protection components 200. Each of the HEMT 100 includes nitride-based semiconductor layers 22, 24,

electrodes

30, 32, a doped nitride-based semiconductor layer 40, and a gate electrode 42. Each of the ESD protection components 200 includes a PN junction 210 and a pair of

conductive pads

50, 52.

Since the semiconductor manufacturing process applying on a silicon-based substrate can achieve a favorable manufacturing precision, in the present disclosure, the substrate 10 is selected as a silicon-based substrate to form the HEMTs 100 mainly realizing electrical functions and the ESD protection components 200 with electrostatic protection functions

Firstly, a p-type doped intermediate silicon-based substrate is provided. Then, an implanting process is performed on the p-type doped intermediate silicon-based substrate to form at least one n-doped regions 104. The formed silicon-based substrate 10 includes a p-doped region 102 and a n-doped region 104, in which the p-doped region 102 includes p-type dopants and the n-doped region 104 includes n-type dopants. For example, the p-type dopants can include boron (B) or gallium (Ga) . The n-type dopants can include arsenic (As) or phosphorus (P) . The n-doped region 104 abuts against the p-doped region 102, and thus a PN diode/junction 210 is formed therebetween. Each of the n-doped regions 104 is surrounded by the p-doped region. Each of the n-doped regions 104 is adjacent to the corresponding HMET 100.

Then, the buffer layer 20 can be formed on/over/above the p-doped region 102, in which the buffer layer 20 includes a plurality of segments arranged on the p-doped region of the silicon-based substrate 10 so as to serve as a buffer array. The segments of the buffer layer 20 are separated from each other. The formed buffer layer 20 is disposed on/over/above the p-doped region 102. The buffer layer 20 is spaced apart from the n-doped region 104 by a portion of the p-doped region 102. The formed buffer layer 20 makes contact with the p-doped region 102. The buffer layer 20 can be configured to reduce lattice and thermal mismatches between the silicon-based substrate 10 and the nitride-based semiconductor layer 22, thereby curing defects due to the mismatches/difference. Thus, each of the segments of the buffer layer 20 can serve as a device region to form the HEMT 100. The buffer layer 20 may include a III-V compound, which means that the buffer layer 20 can be a III-V buffer layer. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer 20 can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown) . The nucleation layer may be formed between the silicon-based substrate 10 and the buffer layer 20. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the silicon-based substrate 10 and a III-nitride layer of the buffer layer 20. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The HEMTs 100 are formed on/over/above the different segments of the buffer layer 20. The HEMTs 100 are disposed on/over/above the different segments of the buffer layer 20, respectively. In the embodiment, all of the HEMTs 100 are designed to have the substantially same electrical properties. In some embodiments, the HEMTs 100 include at least one high voltage HEMT 100 and at least one low voltage HEMT 100 disposed on the different segments of the buffer layer 20, and the present disclosure is not limited thereto.

Specifically, the nitride-based semiconductor layer 22 of the HEMT 100 can be disposed on/over/above the segment of the buffer layer 20. The nitride-based semiconductor layer 22 of the HEMT 100 makes contact with the segment of the buffer layer 20. The nitride-based semiconductor layer 24 of the HEMT 100 can be disposed on/over/above the nitride-based semiconductor layer 22. The nitride-based semiconductor layer 24 of the HEMT 100 makes contact with the nitride-based semiconductor layer 22.

The exemplary materials of the nitride-based semiconductor layer 20 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y)N where x+y ≤ 1, Al _xGa _(1–x)N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 24 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y)N where x+y ≤ 1, Al _yGa _(1–y)N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layer 22 and the nitride-based semiconductor layer 24 are selected such that the nitride-based semiconductor layer 24 has a bandgap (i.e., forbidden band width) greater/higher than a bandgap of the nitride-based semiconductor layer 22, which causes electron affinities thereof different from each other and forms a heterojunction therebetween.

For example, when the nitride-based semiconductor layer 22 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 24 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layer 22 and the nitride-based semiconductor layer 24 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The

electrodes

30 and 32 of the HEMT 100 can be disposed on/over/above the nitride-based semiconductor layer 24. The

electrodes

30 and 32 of the HEMT 100 make contact with the nitride-based semiconductor layer 24. In some embodiments, the electrode 30 can serve as a source electrode. In some embodiments, the electrode 32 can serve as a drain electrode. In some embodiments, the electrode 30 can serve as a source electrode. In some embodiments, the electrode 32 can serve as a drain electrode. The role of the

electrodes

30 and 32 depends on the device design.

In some embodiments, the

electrodes

30 and 32 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

30 and 32 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. Each of the

electrodes

30 and 32 may be a single layer, or plural layers of the same or different composition. The

electrodes

30 and 32 form ohmic contacts with the nitride-based semiconductor layer 24. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

30 and 32. In some embodiments, each of the

electrodes

30 and 32 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer can include, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The doped nitride-based semiconductor layer 40 of the HEMT 100 is disposed on/over/above the nitride-based semiconductor layer 24. The doped nitride-based semiconductor layer 40 makes contact with the nitride-based semiconductor layer 24. The doped nitride-based semiconductor layer 40 is disposed between the nitride-based semiconductor layer 24 and the gate electrode 42. The gate electrode 42 of the HEMT 100 is disposed on/over/above the doped nitride-based semiconductor layer 40. The doped nitride-based semiconductor layer 40 and the gate electrode 42 are disposed/located between the

electrodes

30, 32. The doped nitride-based semiconductor layer 40 and the gate electrode 42 can act as a gate structure.

A width of the doped nitride-based semiconductor layer 40 is greater than that of the gate electrode 42. In some embodiments, a width of the doped nitride-based semiconductor layer 40 is substantially the same as a width of the gate electrode 42. The profiles of the doped nitride-based semiconductor layer 40 and the gate electrode 42 are the same, for example, both of them are rectangular profiles. In other embodiments, the profiles of the doped nitride-based semiconductor layer 40 and the gate electrode 42 can be different from each other, for example, the profile of the doped nitride-based semiconductor layer 40 can be a trapezoid profile, while the profile of the gate electrode 42 can be a rectangular profile.

In the exemplary illustration of FIG. 1B, the HEMT 100 is an enhancement mode HEMT, which is in a normally-off state when the gate electrode 42 is at approximately zero bias. Specifically, the doped nitride-based semiconductor layer 40 may create at least one p-n junction with the nitride-based semiconductor layer 24 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the gate electrode 42 has different characteristics (e.g., different electron concentrations) than the remaining of the 2DEG region and thus is blocked.

Due to such mechanism, the HEMT 100 has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 42 or a voltage applied to the gate electrode 42 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 42) , the zone of the 2DEG region below the gate electrode 42 is kept blocked, and thus no current flows therethrough.

In some embodiments, the doped nitride-based semiconductor layer 40 can be omitted, such that the HEMT 100 is a depletion-mode device, which means the HEMT 100 in a normally-on state at zero gate-source voltage.

The doped nitride-based semiconductor layer 40 can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped nitride-based semiconductor layer 40 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer 22 includes undoped GaN and the nitride-based semiconductor layer 24 includes AlGaN, and the doped nitride-based semiconductor layer 40 is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the HEMT 100 into an off-state condition.

The exemplary materials of the gate electrode 42 may include metals or metal compounds. The gate electrode 42 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.

The conductive pad 50 of the ESD protection component 200 is disposed on/over/above the n-doped region 104 of the silicon-based substrate 10. The conductive pad 50 makes contact with the n-doped region 104 of the silicon-based substrate 10. The conductive pad 52 of the ESD protection component 200 is disposed on/over/above the p-doped region 102 of the silicon-based substrate 10. The conductive pad 52 makes contact with the p-doped region 102 of the silicon-based substrate 10. The conductive pad 52 is located between the conductive pad 50 and the buffer layer 20.

The exemplary materials of the

conductive pads

50, 52 can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.

In addition, since the HEMTs 100 are formed/disposed on the segments of the buffer layer 20 and the ESD protection components 200 are formed directly on a top surface of the silicon-based substrate 10, the HEMTs 100 are at a position higher than the ESD protection components 200. Furthermore, in the embodiment, the number of the HEMTs 100 can be the same as that of the ESD protection components 200. In some embodiments, the number of the HEMTs 100 can be different from than that of the ESD protection components 200 according to the device requirement, and the present disclosure is not limited thereto.

The following paragraphs will fully be described the operation of the ESD protection component 200.

In the embodiment, each of the ESD protection components 200 is electrically coupled to the corresponding HEMT 100. Specifically, the conductive pad 50 of the ESD protection component 200 is electrically coupled to the gate electrode 42 of the corresponding HEMT 100. The conductive pad 52 of the ESD protection component 200 is electrically coupled to the electrode 30 of the HEMT 100, in which the electrode 30 serves as a source electrode of the HEMT 100 and the electrode 32 serves as a drain electrode of the HEMT 100.

The ESD protection component 200 can apply the PN diode/junction 210. In detail, as an ESD event occurs, a gate voltage applied to the gate electrode 42 exceeds a safe working voltage of the gate electrode 42 and exceeds a reverse voltage of the PN junction 210, resulting in occurring an avalanche effect in the PN junction 210. Thus, the PN junction 210 can be reverse conduction. Then, the current C generated by the ESD event can be discharged through the PN junction 210, so as to protect the HEMT 100 from damage caused by the ESD event. Thus, the reliability of the HEMT 100 can be ensured.

In some embodiments, the characteristics of the PN junction 210, for example the reverse voltage, can be changed by adjusting concentration of the n-type dopants in the n-doped region 104 and concentration of the p-type dopants in the p-doped dopants in the p-doped region 102, so as to meet different device requirements.

FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D show different stages of a method for manufacturing a semiconductor device 1A in the FIGs. 1A and 1B according to some embodiments of the present disclosure. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, an intermediate silicon-based substrate 10’ is provided, in which the intermediate silicon-based substrate 10’ is a p-doped intermediate silicon-based substrate 10’. An intermediate buffer layer 20’ is formed on/over/above the p-doped intermediate silicon-based substrate 10’ by using deposition techniques. An intermediate nitride-based semiconductor layer 22’is formed on/over/above the intermediate buffer layer 20’ by using deposition techniques. An intermediate nitride-based semiconductor layer 24’ is formed on/over/above the intermediate nitride-based semiconductor layer 22’ by using deposition techniques. An intermediate doped nitride-based semiconductor layer 40’ is formed on/over/above the intermediate nitride-based semiconductor layer 24’ by using deposition techniques. An intermediate gate electrode layer 42’ is formed on/over/above the intermediate doped nitride-based semiconductor layer 40’ by using deposition techniques.

Referring to FIG. 2B, portions of the intermediate doped nitride-based semiconductor layer 40’ and the intermediate gate electrode layer 42’ are removed, such that a doped nitride-based semiconductor layer 40 and a gate electrode 42 are formed. Then,

electrodes

30, 32 are formed on/over/above the intermediate nitride-based semiconductor layer 24’.

Referring to FIG. 2C, portions of the intermediate buffer layer 20’ and the intermediate nitride-based semiconductor layers 22’, 24’ are removed by applying an etching process, so as to exposed a portion of the intermediate silicon-based substrate 10’. Thus, a HEMT 100 can be obtained. Then, an implanting process is performed on the exposed portion of the intermediate silicon-based substrate 10’, such that a n-doped region 104 is formed in the exposed portion of the intermediate silicon-based substrate 10’. As such, a silicon-based substrate 10 including a p-doped region 102 and a n-doped region 104 can be obtained. A PN junction 210 is formed between the p-doped region 102 and the n-doped region 104.

Referring to FIG 2D, a conductive pad 50 is formed to make contact with the n-doped region 104. A conductive pad 52 is formed on the exposed portion of the silicon-based substrate 10, in which the conductive pad 52 is formed to be located between the conductive pad 50 and the nitride-based semiconductor layer 22. Thus, the ESD protection component 200 can be obtained. Therefore, the semiconductor device 1A in the FIGs. 1A and 1B can be obtained.

FIG. 3A and FIG. 3B show different stages of another method for manufacturing a semiconductor device in the FIGs. 1A and 1B according to some embodiments of the present disclosure. FIG. 4 shows a top view of a resulted structure in the FIG. 3A.

Referring to FIGs. 3A and FIG. 4, a passivation layer 60 with a plurality of through holes TH is formed to cover the intermediate silicon-based substrate 10’, in which the through hole TH is defined as a device region. Then, a buffer layer 20, nitride-based semiconductor layers 22, 24, an intermediate doped nitride-based semiconductor layer 40’, and intermediate gate electrode layer 42’ are formed on/over/above the intermediate silicon-based substrate 10’ and in the through hole TH in sequence.

The exemplary material of the passivation layer 60 can include, for example but are not limited to, dielectric materials. For example, the passivation layer 60 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof.

Referring to FIG. 3B, portions of the intermediate doped nitride-based semiconductor layer 40’, and the intermediate gate electrode layer 42’ are removed, such that the doped nitride-based semiconductor layer 40 and the gate electrode 42 can be formed. Then,

electrodes

30, 32 are formed on the nitride-based semiconductor layer 24. The HEMT 100 can be obtained.

After that, the passivation layer 60 is removed. Then, an implanting process is performed on the intermediate silicon-based substrate 10’, such that a n-doped region 104 is formed in the exposed portion of the intermediate silicon-based substrate 10’. As such, a silicon-based substrate 10 including a p-doped region 102 and a n-doped region 104 can be obtained. Thus, the semiconductor device 1A in the FIGs. 1A and 1B can be obtained.

With respect to the manufacturing method in the FIGs. 3A, 3B and 4, a passivation layer 60 with a plurality of through holes TH is formed firstly, and the through hole TH thereof is used to define the device region. As such, the size of electrical property layers (e.g., the nitride-based semiconductor layers 20, 24) of the semiconductor device 1A can be defined by size of the through holes TH, instead of using a destructive manufacturing process (e.g., etching process) . Such a manufacturing method can improve the quality of the formed electrical property layers in the semiconductor device 1A.

FIG. 5 is a vertical view of a semiconductor device 1B according to some embodiments of the present disclosure. The semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIGs. 1A and 1B, except that the silicon-based substrate 10B has a plurality of n-doped regions 104 separated from each other in a vertical direction, in which the number of the n-doped regions 104 can be two for example. Thus, two PN junctions 210 are arranged/formed in the silicon-based substrate 10B, and they are electrically coupled in series.

FIG. 6 is a vertical view of a semiconductor device 1C according to some embodiments of the present disclosure. The semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIGs. 1A and 1B except that the silicon-based substrate 10C has a plurality of n-doped regions 104 separated from each other in a horizontal direction, in which the number of the n-doped regions 104 can be two for example. A plurality of the conductive pads 50 are fo to make contact with the n-doped regions 104C, respectively. Thus, two PN junctions 210 are arranged/formed in the silicon-based substrate 10B, and they are electrically coupled in parallel.

With respect to the semiconductor devices 1B and 1C, by altering the numbers of the n-doped regions 104, the location of the n-doped regions 104 in the silicon-based substrate 10B, and the configuration of the circuit design in the devices, the overall impedance of the plurality of the PN junctions 210 can be altered by different ways, so as to meet different device requirements.

FIG. 7 is a vertical view of a semiconductor device 1D according to some embodiments of the present disclosure. The semiconductor device 1D is similar to the semiconductor device 1A as described and illustrated with reference to FIGs. 1A and 1B except that semiconductor device 1D further includes a passivation layer 70, a plurality of contact vias 80, and a patterned circuit layer 90.

The passivation layer 70 covers the silicon-based substrate 10, the

electrodes

30, 32, and the gate electrode 42 of the HEMT 100, and the

conductive pads

50, 52 of the ESD protection component 200, so as to protect the HEMT 100 and the ESD protection component 200. The exemplary material of the passivation layer 70 can include, for example but are not limited to, dielectric materials. For example, the passivation layer 70 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the passivation layer 70 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

Moreover, the passivation layer 70 can serve as a planarization layer which has a level top surface to support other layers/elements. In some embodiments, the passivation layer 70 can be formed as a thicker layer, and a planarization process, such as chemical mechanical polish (CMP) process, is performed on the passivation layer 70 to remove the excess portions, thereby forming a level top surface.

The contact vias 80 (e.g., conductive vias) are disposed within the passivation layer 70. The contact vias 80 can penetrate the passivation layer 70. The contact vias 80 can extend longitudinally to electrically connect to the

conductive pads

50, 52 of the ESD protection component 200, the

electrodes

30, 32 and the gate electrode 42 of the HEMT 100, respectively. Thus, some of the contact vias 80 are electrically connected to the HEMT 100, and some of the contact vias 80 are electrically connected to the ESD protection component 200. The upper surfaces of the contact vias 80 are free from coverage of the passivation layer 70. The exemplary materials of the contact vias 80 can include, for example but are not limited to, conductive materials, such as metals or alloys.

The patterned circuit layer 90 is disposed on/over/above the passivation layer 70. The patterned circuit layer 90 may have metal lines, pads, traces, or combinations thereof, such that the patterned circuit layer 90 can form at least one circuit. The patterned circuit layer 90 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

With respect to the semiconductor device 1D, the

electrodes

30, 32, and the gate electrode 42 of the HEMT 100 and the

conductive pads

50, 52 of the ESD protection component 200 can be electrically coupled to different portions of the patterned circuit layer 90 at the same height level through the contact vias 80, such a configuration can reduce the complexity of circuit design.

FIG. 8 is a vertical view of a semiconductor device 1E according to some embodiments of the present disclosure. The semiconductor device 1E is similar to the semiconductor device 1A as described and illustrated with reference to FIGs. 1A and 1B except that the ESD protection component 200E include a n-type metal oxide semiconductor (NMOS) . Specifically, the ESD protection component 200E includes two n-doped regions 104 separated from each other by a portion P of the p-doped region 102, and

conductive pads

50, 52, 54. The

conductive pads

50, 52 are located on/over/above the different n-doped regions 104. Each of the

conductive pads

50, 52 makes contact with the correspondingly n-doped region 104. The conductive pad 54 is disposed/located between the

conductive pads

50, 52. The conductive pad 54 makes contact with the portion P of the p-doped region 102.

In some embodiments, the conductive pad 50 can serve as a source electrode of the NMOS, the conductive pad 52 can serve as a drain electrode of the NMOS, and the conductive pad 54 can serve as a gate electrode of the NMOS.

In the embodiment, the ESD protection component 200E is electrically coupled to the corresponding HEMT 100. Specifically, the conductive pad 50 of the ESD protection component 200E is electrically coupled to the electrode 30 of the HEMT 100, the conductive pad 52 of the ESD protection component 200E is electrically coupled to the gate electrode 42 of the HEMT 100, and the conductive pad 54 of the ESD protection component 200E is electrically coupled to the ground. By such a configuration, the NMOS of the ESD protection component 200E can serve as a gate-grounded NMOS (ggNMOS) , and the ggNMOS of the ESD protection component 200E can protect the HEMT 100 from damage caused by an ESD event.

FIG. 9A, and FIG. 9B show different stages of a method for manufacturing a semiconductor device 1E in the FIGs. 9A and 9B according to some embodiments of the present disclosure. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to the FIG. 9A, after formation of the HEMT 100, an implantation process is performed on the intermediate silicon-based substrate, such that two n-doped regions 104 can be formed in the silicon-based substrate, in which the n-doped regions 10 are separated by a portion of the silicon-based substrate.

Referring to the FIG. 9B, a plurality of

conductive pads

50, 52 are formed on/over/above the n-doped regions 104, respectively. Then, a conductive pad 54 is formed between the

conductive pads

50, 52. The conductive pad 54 is formed to make contact with the portion P of the p-doped region 102 between the two n-doped regions 104. Therefore, the semiconductor device 1E in the FIG. 8 can be obtained.

FIG. 10 is a vertical view of a semiconductor device 1F according to some embodiments of the present disclosure. The semiconductor device 1F is similar to the semiconductor device 1A as described and illustrated with reference to FIG. 8, except that the semiconductor device 1F further includes a passivation layer 70, a plurality of contact vias 80, and a patterned circuit layer 90.

The passivation layer 70 covers the silicon-based substrate 10E, the

electrodes

30, 32, and the gate electrode 42 of the HEMT 100, and the

conductive pads

50, 52, 54 of the ESD protection component 200E, so as to protect the HEMT 100 and the ESD protection component 200E. The exemplary material of the passivation layer 70 can include, for example but are not limited to, dielectric materials. For example, the passivation layer 70 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the passivation layer 70 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

The contact vias 80 (e.g., conductive vias) are disposed within the passivation layer 70. The contact vias 80 can penetrate the passivation layer 70. The contact vias 80 can extend longitudinally to connect to the

conductive pads

50, 52, 54 of the ESD protection component 200, the

electrodes

30, 32 and the gate electrode 42 of the HEMT 100, respectively. The upper surfaces of the contact vias 80 are free from coverage of the passivation layer 70. The exemplary materials of the contact vias 80 can include, for example but are not limited to, conductive materials, such as metals or alloys.

With respect to the semiconductor device 1F, the

electrodes

30, 32, and the gate electrode 42 of the HEMT 100 and the

conductive pads

50, 52, 54 of the ESD protection component 200E can be electrically coupled to different portions of the patterned circuit layer 90 at the same height level through the contact vias 80, such a configuration can reduce the complexity of circuit design.

In the present disclosure, the provided is a solution which can make the device specifical and realizable. Moreover, since the switch device is built in HEMT, the substrate can be designed in view of the ESD protection component. More specifically, the doping in the substrate is made for the consideration of the ESD protection component, so the design for the ESD protection component can get more flexible.

Based on above, in the present disclosure, a region of the p-doped silicon-based substrate is formed with a III-V buffer layer, so as to serve a device region, thereby forming a nitride-based HMET thereon. Another region of the p-doped silicon-based substrate is implanted to form n-doped region, so as to form a PN junction therebetween. The ESD protection component can apply the silicon-based PN junction, so as to prevent the damage caused by an ESD event to the HEMT. In some cases, the ESD protection component can include a PN junction. In some cases, the ESD protection component can include a NMOS. Since the manufacturing method applied to the silicon-based substrate has a high manufacturing precision, the HEMT and the ESD protection component can be manufactured in a small volume. Hence, the semiconductor device can have a good reliability and can maintain a small volume.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A semiconductor device, comprising:

a silicon-based substrate comprising at least one p-doped region and at least one n-doped region which abut against each other;

at least one III-V buffer layer disposed on the p-doped region of the silicon-based substrate;

at least one high-electron-mobility transistor (HEMT) disposed on the III-V buffer layer; and

a first conductive pad disposed over the n-doped region and making contact with the n-doped region.
The semiconductor device of any one of the preceding claims, wherein the buffer layer is spaced apart from the n-doped region.
The semiconductor device of any one of the preceding claims, further comprising a second conductive pad disposed over the p-doped region and making contact with the p-doped region.
The semiconductor device of any one of the preceding claims, wherein the second conductive pad is located between the first conductive pad and the III-V buffer layer.
The semiconductor device of any one of the preceding claims, wherein the silicon-based substrate comprises the two n-doped regions which are separated from each other by a portion of the p-doped region.
The semiconductor device of any one of the preceding claims, further comprising a second conductive pad disposed over the silicon-based substrate, wherein the first conductive pad and the second conductive pad are located on the different n-doped regions.
The semiconductor device of any one of the preceding claims, further comprising a third conductive pad disposed over the silicon-based substrate and located between the first conductive pad and the second conductive pad.
The semiconductor device of any one of the preceding claims, wherein the third conductive pad makes contact with the portion of the p-doped region.
The semiconductor device of any one of the preceding claims, wherein the III-V buffer layer has a plurality of segments arranged on the p-doped region of the silicon-based substrate so as to serve as a buffer array.
The semiconductor device of any one of the preceding claims, further comprising at least one high voltage HEMT and at least one low voltage HEMT disposed on the different segments of the III-V buffer layer.
The semiconductor device of any one of the preceding claims, wherein the HEMT comprises:

a first nitride-based semiconductor layer; and

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer.
The semiconductor device of any one of the preceding claims, wherein the HEMT comprises:

a doped nitride-based semiconductor layer disposed on the second nitride-based semiconductor layer; and

a gate electrode disposed on the doped nitride-based semiconductor layer.
The semiconductor device of any one of the preceding claims, wherein the HEMT comprises a source electrode and a drain electrode disposed on the second nitride-based semiconductor layer.
The semiconductor device of any one of the preceding claims, further comprising a passivation layer covering the HEMT and the first conductive pad.
The semiconductor device of any one of the preceding claims, further comprising:

a first contact via within the passivation layer and electrically connected to the HEMT; and

a second contact via within the passivation layer and electrically connected to the first conductive pad.
A method for manufacturing a semiconductor device, comprising:

forming a first nitride-based semiconductor layer on a silicon-based substrate comprising at least one p-doped region;

forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;

forming at least one high-electron-mobility transistor (HEMT) over the second nitride-based semiconductor layer

forming at least one n-doped region in the silicon-based substrate; and

forming a first conductive pad making contact with the n-doped region.
The method of any one of the preceding claims, further comprising:

removing a portion of the second nitride-based semiconductor layer; and

removing a portion of the first nitride-based semiconductor layer, so as to exposed a portion of the silicon-based substrate.
The method of any one of the preceding claims, wherein the n-doped region is formed in the exposed portion of the silicon-based substrate.
The method of any one of the preceding claims, further forming a second conductive pad on the exposed portion of the silicon-based substrate.
The method of any one of the preceding claims, wherein the second conductive pad is located between the first conductive pad and the first nitride-based semiconductor layer.
A semiconductor device, comprising:

a silicon-based substrate comprising at least one p-doped region and a plurality of n-doped regions;

a plurality of III-V buffer layers disposed on the p-doped region of the silicon-based substrate and are separated from each other;

a plurality of high-electron-mobility transistors (HEMTs) disposed on the III-V buffer layers; and

a plurality of electrostatic discharge (ESD) protection components disposed on the silicon-based substrate and at least applying the n-doped regions.
The semiconductor device of any one of the preceding claims, wherein the HEMTs are at a position higher than the ESD protection components.
The semiconductor device of any one of the preceding claims, wherein the number of the HEMTs is different from the number of the ESD protection components.
The semiconductor device of any one of the preceding claims, wherein the HEMTs are electrically coupled with the ESD protection components.
The semiconductor device of any one of the preceding claims, wherein the ESD protection components comprise PN junction.