CN106298887B - Preparation method of groove gate MOSFET with high threshold voltage and high mobility - Google Patents
Preparation method of groove gate MOSFET with high threshold voltage and high mobility Download PDFInfo
- Publication number
- CN106298887B CN106298887B CN201610868777.9A CN201610868777A CN106298887B CN 106298887 B CN106298887 B CN 106298887B CN 201610868777 A CN201610868777 A CN 201610868777A CN 106298887 B CN106298887 B CN 106298887B
- Authority
- CN
- China
- Prior art keywords
- layer
- aluminum component
- gan
- algan
- threshold voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 52
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 43
- 230000004888 barrier function Effects 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 238000001039 wet etching Methods 0.000 claims abstract description 7
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 230000001105 regulatory effect Effects 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 16
- 229910001020 Au alloy Inorganic materials 0.000 claims description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 4
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 230000008719 thickening Effects 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 2
- 229910001252 Pd alloy Inorganic materials 0.000 claims description 2
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims description 2
- 229910052742 iron Inorganic materials 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 238000010025 steaming Methods 0.000 claims description 2
- 230000001276 controlling effect Effects 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 7
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 4
- 238000011161 development Methods 0.000 abstract description 3
- 230000005012 migration Effects 0.000 abstract description 3
- 238000013508 migration Methods 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 28
- 229910002601 GaN Inorganic materials 0.000 description 27
- 230000005669 field effect Effects 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical group F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
Abstract
The present invention relates to the technical field of semiconductor epitaxial processes and, more particularly, relates to a preparation method of a groove gate MOSFET with high threshold voltage and high mobility. Comprising the following steps: firstly, providing a heterojunction material with a low-aluminum component AlGaN/GaN/high-aluminum component AlGaN laminated barrier layer, depositing a dielectric layer on the surface of the material to serve as a mask layer, removing the dielectric layer in a grid region by adopting a photoetching development technology and wet etching to realize the patterning of the mask layer, removing the high-aluminum component AlGaN on the top layer of the grid region by utilizing dry-wet combination to obtain a groove, removing the surface damage of the groove by taking a GaN thin layer as a wet etching stop layer, and enabling the reserved low-aluminum component AlGaN barrier layer to realize high channel mobility and high threshold voltage. The threshold voltage is further regulated by depositing p-type oxide as a gate. And finally forming source electrode and drain electrode regions at two ends and covering metal to form the source electrode and the drain electrode. The method has simple process, can well solve the damage to the grid electrode region during the conventional dry etching of the groove, and can form a channel with low two-dimensional electron gas concentration, thereby improving the channel migration and simultaneously obtaining high threshold voltage.
Description
Technical Field
The invention relates to the technical field of semiconductor epitaxial processes, in particular to a preparation method of a groove gate MOSFET with high threshold voltage and high mobility.
Background
The gallium nitride (GaN) material has the advantages of large forbidden bandwidth, high breakdown electric field strength, high electron saturation drift speed, high heat conductivity and the like, and is very suitable for manufacturing high-power, high-frequency and high-temperature power electronic devices. In the field of power electronics applications, in order to meet fail-safe, field Effect Transistor (FET) devices must implement normally-off (also known as enhancement) operation, and in some cases the threshold voltage needs to be at least 4-5V. Whereas for conventional AlGaN/GaN Heterojunction Field Effect Transistors (HFETs), the device is in an on state (normally on device) due to the presence of the two-dimensional electron gas (2 DEG) with high concentration and high mobility at the interface, even when the applied gate voltage is zero. To solve these problems, an insulated gate field effect transistor (MOSFET) employing a MOS structure is an effective technical route.
On the premise of keeping the concentration of the 2DEG of the access region (without sacrificing the on-characteristic of the device), the GaN-based groove gate MOSFET device achieves the purpose of reducing or even completely removing the 2DEG below the grid when the zero bias voltage is removed by partially or completely etching the AlGaN barrier layer of the grid region, and can adopt the grid with the MOS structure to achieve normally-off type, low leakage current and high grid voltage swing. The partial etching of the barrier layer is effective to preserve the electron channel and achieve high field effect mobility, but the remaining barrier layer forms a MOSHFET with the gate metal and gate dielectric layer to lower the threshold voltage. Conversely, fully etching the barrier layer can achieve a high threshold voltage, but an electron channel is generated between the gate dielectric layer and GaN, and strong interface scattering leads to low field effect mobility. In addition, in the groove etching process, the conventional plasma dry etching can damage the crystal lattice of the channel region, and the wet etching can effectively remove the plasma damage, but a large number of etching holes can be observed on the surface of the GaN channel layer after long-time treatment, so that the reliability and stability of the MOS interface are affected. There is therefore a need for a method of fabricating a high threshold voltage high mobility trench gate MOSFET, to overcome the disadvantages of the conventional processes and to obtain higher mobility and threshold voltage.
Disclosure of Invention
The invention provides a preparation method of a groove gate MOSFET with high threshold voltage and high mobility, which can effectively improve channel mobility and threshold voltage. The technical scheme adopted by the invention is as follows: the stacked barrier layer structure is utilized, the GaN insertion layer is used as a wet etching stop layer, plasma damage can be removed, low-aluminum component AlGaN can be reserved to form a channel with low two-dimensional electron gas concentration, and the channel carrier concentration is regulated and controlled by combining a p-type oxide grid electrode, so that the channel migration is improved, and meanwhile, the high threshold voltage is obtained.
The method specifically comprises the following steps:
s1 growing a stress buffer layer on the substrate;
s2, growing a GaN epitaxial layer on the stress buffer layer;
s3, growing a low-aluminum component AlGaN barrier layer on the GaN epitaxial layer;
s4, depositing a GaN etching stop layer on the AlGaN barrier layer with the low aluminum component;
s5, growing a high aluminum component AlGaN barrier layer on the GaN etching stop layer;
s6, depositing a layer of SiO on the AlGaN barrier layer 2 As a mask layer;
s7, removing the mask layer of the grid region by a photoetching and wet etching method;
s8, removing the high aluminum component AlGaN barrier layer of the gate region by utilizing the combination of a dry method and a wet method;
s9, performing dry etching to complete device isolation, cleaning the surface and depositing a p-type oxide grid;
s10, evaporating source electrode and drain electrode ohmic contact metal on the source electrode and drain electrode regions;
s11 and (3) steaming metal in the groove grid region to form ohmic contact with the p-type oxide.
Specifically, the heterojunction material of the low-aluminum component AlGaN/GaN/high-aluminum component AlGaN laminated barrier layer grows in the steps S3-S5; in the step S9, a p-type oxide grid is deposited to modulate the electron concentration of a channel, so that the threshold voltage is regulated and controlled.
The substrate is any one of a Si substrate, a sapphire substrate, a silicon carbide substrate and a GaN self-supporting substrate.
The stress buffer layer is any one or combination of AlN, alGaN, gaN; the thickness of the stress buffer layer is 10 nm-5 μm.
The GaN epitaxial layer is an unintentionally doped GaN epitaxial layer or a doped high-resistance GaN epitaxial layer, and the doping element of the doped high-resistance GaN epitaxial layer is carbon or iron; gaN epitaxial layer thickness of 100nm to 20 mu m.
The low-aluminum component AlGaN barrier layer is low-aluminum component AlGaN, the thickness of the AlGaN layer is 0-20nm, and the concentration of the aluminum component can be changed between 0% and 15%.
The GaN etching stop layer is a high-quality GaN etching stop layer with low dislocation density; the thickness of the termination layer is 0 nm-20 nm.
The high-aluminum component AlGaN barrier layer is high-aluminum component AlGaN, the AlGaN layer has a thickness of 0-50nm, and the concentration of the aluminum component can vary from 15-40%.
The AlGaN potential barrier the layer material can also be AlInN, inGaN, alInGaN, alN, or a combination of any of the foregoing.
In the AlGaN barrier layer with high aluminum composition, an AlN thin layer with the thickness of 1-10nm can be inserted between the GaN layer and the GaN layer;
the p-type oxide grid electrode is high-quality NiO Cu (Cu) 2 O, znO or the like or a combination thereof, and the thickness is 1-500nm;
the source electrode and the drain electrode are made of Ti/Al/Ni/Au alloy, ti/Al/Ti/Au alloy, ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy; the gate electrode thickening metal material is Ni/Au alloy, in/Au alloy or Pd/Au alloy;
the growth methods of the stress buffer layer in the step S1, the GaN epitaxial layer in the step S2, the low-aluminum component AlGaN barrier layer in the step S3, the GaN etching stop layer in the step S4 and the high-aluminum component AlGaN barrier layer in the step S5 are high-quality film forming methods such as a metal organic chemical vapor deposition method, a molecular beam epitaxy method and the like; the mask layer growth method in the step S6 is a plasma enhanced chemical vapor deposition method atomic layer deposition, physical vapor deposition, or magnetron sputtering.
In addition, the following steps can be summarized:
1. providing AlGaN/GaN/AlGaN heterojunction materials needing to be subjected to groove gate etching;
2. depositing a dielectric layer on the material to form a mask layer;
3. exposing a grid region on the mask layer by utilizing a photoetching development technology;
4. the masking material of the gate region is removed using a chemical solution, reserving mask materials in other areas to realize mask layer patterning;
5. and realizing groove etching with the aid of the mask pattern.
6. The gate region is exposed and a thin layer of p-type oxide is grown using photolithographic development techniques.
Further, in the step 1, the substrate is a multi-layer epitaxial layer substrate having different components.
In the step 2, the dielectric layer is formed by plasma enhanced chemical vapor deposition or atomic layer deposition or physical vapor deposition or magnetron sputtering. The dielectric layer is SiO 2 Or SiN.
In the step 3, the step of the method is carried out, the photoresist is a positive or negative photoresist.
In the step 4, the chemical solution used for removing the dielectric layer is hydrofluoric acid aqueous solution or mixed solution of hydrofluoric acid and ammonium fluoride.
In the step 5, the recess etching is Inductively Coupled Plasma (ICP) or Reactive Ion Etching (RIE). The reaction gas being Cl 2 、BCl 3 、SiCl 4 Or a mixture thereof.
In the step 6, the growth of the p-type oxide thin layer is a metal organic chemical vapor deposition method, a sputtering method, a thermal oxidation method or a molecular beam epitaxy method.
Compared with the prior art, the beneficial effects are that: the invention provides a preparation method of a groove gate MOSFET with high threshold voltage and high mobility, which utilizes a laminated barrier layer structure, a GaN insertion layer is used as a wet etching stop layer to remove plasma damage, the low-aluminum component AlGaN can be reserved to form a channel with low two-dimensional electron gas concentration, and the channel carrier concentration is regulated and controlled by combining the p-type oxide grid electrode, so that the channel migration is improved, and meanwhile, the high threshold voltage is obtained.
Drawings
Fig. 1-11 are process diagrams illustrating a device manufacturing method according to embodiment 1 of the present invention.
Fig. 12 is a schematic view of the device structure of embodiment 2 of the present invention.
FIG. 13 is a diagram of an embodiment of the present invention 3, a device structure schematic diagram.
Detailed Description
The drawings are to be regarded as illustrative in nature, and are not to be construed as limiting the present patent; for the purpose of better illustrating the embodiments, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the actual product dimensions; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationship depicted in the drawings is for illustrative purposes only and is not to be construed as limiting the present patent.
Implementation of the embodiments example 1
Fig. 11 is a schematic view of the device structure of this embodiment, where the structure sequentially includes, from bottom to top, a substrate 1, a stress buffer layer 2, a gan epitaxial layer 3, a low-aluminum AlGaN barrier layer 4, a gan etching stop layer 5, a high-aluminum AlGaN barrier layer 6, a p-type oxide gate 7, source and drain electrodes formed at both ends, and thickened metal deposited on the oxide gate.
The manufacturing method of the device field effect transistor of the high threshold voltage high mobility recessed gate MOSFET is shown in fig. 1-11, and comprises the following steps:
s1, growing a stress buffer layer 2 on a Si substrate 1 by using a metal organic chemical vapor deposition method, as shown in FIG. 1;
s2, growing a GaN epitaxial layer 3 on the stress buffer layer 2 by using a metal organic chemical vapor deposition method, as shown in FIG. 2;
s3, growing a low-aluminum component AlGaN barrier layer 4 on the GaN epitaxial layer 3 by using a metal organic chemical vapor deposition method, as shown in FIG. 3;
s4, growing a GaN etching stop layer 5 on the AlGaN barrier layer 4 with low aluminum composition by using a metal organic chemical vapor deposition method, as shown in FIG. 4;
s5, utilizing a metal organic chemical vapor deposition method, growing a high-aluminum component AlGaN barrier layer 6 on the GaN etching stop layer 5, as shown in FIG. 5;
s6, depositing a layer of SiO through plasma enhanced chemical vapor deposition 2 As a mask layer 10, as shown in fig. 6;
s7, selecting area etching by a photoetching method, removing the mask layer 10 of the gate region as shown in fig. 7;
s8, removing the AlGaN barrier layer 6 with the high aluminum component in the gate region by utilizing Inductively Coupled Plasma (ICP) or Reactive Ion Etching (RIE) to form a groove, as shown in FIG. 8;
s9, removing the mask layer 10 to finish device isolation, and growing a high-quality p-type oxide thin layer by using a sputtering method, as shown in FIG. 9;
s10, photoetching and developing source electrode and drain electrode ohmic contact areas, and evaporating Ti/Al/Ni/Au alloy serving as source electrode and drain electrode ohmic contact metal 8, as shown in FIG. 10;
s11, a Ni/Au alloy is vapor deposited as a gate thickening metal on the p-type oxide gate electrode 7, as shown in fig. 11.
So far as the process is concerned, the whole device preparation process is completed. Fig. 11 is a schematic diagram of the device structure of embodiment 1.
Implementation of the embodiments example(s) 2
As shown in fig. 12, the device structure of this embodiment is different from that of embodiment 1 only in that: the gate electrode in embodiment 1 is a single oxide, and the stacked gate electrode structure is formed using two or more oxides in embodiment 2.
Example 3
As shown in fig. 13, the device structure of this embodiment is different from that of embodiment 1 only in that: in example 1, the gate electrode is a p-type oxide, and in example 3, an insulating dielectric layer 11 is introduced under the p-type oxide gate electrode 7, the dielectric layer is Al 2 O 3 Or HfO 2 The thickness is 1-100nm; a dielectric layer/oxide stack structure is formed.
Further, it is noted that the drawings of the above embodiments are for illustrative purposes only and are not necessarily drawn to scale.
It is to be understood that the above examples of the present invention are provided by way of illustration only and not by way of limitation of the embodiments of the present invention. As will be apparent to one of ordinary skill in the art, other variations or modifications may be made in the various forms based on the above description. It is not necessary here nor is it exhaustive of all embodiments. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are desired to be protected by the following claims.
Claims (3)
1. A preparation method of a groove gate MOSFET with high threshold voltage and high mobility utilizes heterojunction materials of low-aluminum component AlGaN/GaN/high-aluminum component AlGaN laminated barrier layers, and specifically comprises the following steps:
s1, growing a stress buffer layer (2) on a substrate (1);
s2, growing a GaN epitaxial layer (3) on the stress buffer layer;
s3, growing a low-aluminum component AlGaN barrier layer (4) on the GaN epitaxial layer (3);
s4, depositing a GaN etching stop layer (5) on the AlGaN barrier layer (4) with the low aluminum component;
s5, growing a layer of AlGaN barrier layer (6) with high aluminum composition on the GaN etching stop layer (5);
s6, depositing a layer of SiO on the AlGaN barrier layer 2 As a mask layer (10);
s7, removing the mask layer (10) of the grid region by a photoetching and wet etching method;
s8, removing the high aluminum component AlGaN barrier layer (6) of the grid region by utilizing the combination of a dry method and a wet method;
s9, performing dry etching to complete device isolation, cleaning the surface and depositing a p-type oxide grid (7);
s10, evaporating source electrode and drain electrode ohmic contact metal (8) on the source electrode and drain electrode regions;
s11, steaming metal in a groove grid region to form ohmic contact with the p-type oxide;
growing heterojunction materials of low-aluminum component AlGaN/GaN/high-aluminum component AlGaN laminated barrier layers in the steps S3-S5; the deposition of the p-type oxide gate in step S9 modulates the channel electron concentration, thereby regulating and controlling the threshold voltage;
wherein the substrate (1) is any one of a Si substrate, a sapphire substrate, a silicon carbide substrate and a GaN self-supporting substrate; the stress buffer layer (2) is any one or combination of AlN, alGaN, gaN; the thickness of the stress buffer layer is 10 nm-5 mu m; the GaN epitaxial layer (3) is an unintentionally doped GaN epitaxial layer or a doped high-resistance GaN epitaxial layer, and the doping element of the doped high-resistance GaN epitaxial layer is carbon or iron; the thickness of the GaN epitaxial layer is 100 nm-20 mu m; the low-aluminum component AlGaN barrier layer (4) is low-aluminum component AlGaN, the thickness of the AlGaN layer is 0-20nm, and the concentration of the aluminum component can be changed between 0% and 15%; the GaN etching stop layer (5) is a high-quality GaN etching stop layer with low dislocation density; the thickness of the termination layer is 0 nm-20 nm; the high-aluminum component AlGaN barrier layer (6) is high-aluminum component AlGaN, the thickness of the AlGaN layer is 0-50-nm, and the concentration of the aluminum component can be changed between 15% and 40%.
2. The method for manufacturing the high threshold voltage high mobility trench gate MOSFET according to claim 1, wherein: the AlGaN barrier layer material can also be one or a combination of any of AlInN, inGaN, alInGaN, alN.
3. The method for manufacturing the high threshold voltage high mobility trench gate MOSFET according to claim 1, wherein: an AlN thin layer with the thickness of 1-10nm can be inserted between the AlGaN barrier layer (6) with the high aluminum component and the GaN layer;
the p-type oxide grid electrode (7) is high-quality NiO and Cu 2 O, znO or the like or a combination thereof, and the thickness is 1-500nm;
the source electrode and the drain electrode are made of Ti/Al/Ni/Au alloy, ti/Al/Ti/Au alloy, ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy; the gate electrode thickening metal material is Ni/Au alloy, in/Au alloy or Pd/Au alloy;
the growth methods of the stress buffer layer (2) in the step S1, the GaN epitaxial layer (3) in the step S2, the low-aluminum component AlGaN barrier layer (4) in the step S3, the GaN etching stop layer (5) in the step S4 and the high-aluminum component AlGaN barrier layer (6) in the step S5 are high-quality film forming methods such as a metal organic chemical vapor deposition method, a molecular beam epitaxy method and the like; the growth method of the mask layer (10) in the step S6 is a plasma enhanced chemical vapor deposition method, an atomic layer deposition method, a physical vapor deposition method or a magnetron sputtering method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610868777.9A CN106298887B (en) | 2016-09-30 | 2016-09-30 | Preparation method of groove gate MOSFET with high threshold voltage and high mobility |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610868777.9A CN106298887B (en) | 2016-09-30 | 2016-09-30 | Preparation method of groove gate MOSFET with high threshold voltage and high mobility |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106298887A CN106298887A (en) | 2017-01-04 |
| CN106298887B true CN106298887B (en) | 2023-10-10 |
Family
ID=57715928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610868777.9A Active CN106298887B (en) | 2016-09-30 | 2016-09-30 | Preparation method of groove gate MOSFET with high threshold voltage and high mobility |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106298887B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108666359A (en) * | 2017-03-29 | 2018-10-16 | 北京大学 | A kind of device architecture and implementation method improving GaN enhancement type channel mobilities using novel barrier layer |
| CN107316806A (en) * | 2017-07-07 | 2017-11-03 | 西安电子科技大学 | The preparation method of injection integral high frequency high threshold GaN base enhancement device is etched based on ICP F ions |
| CN108321256A (en) * | 2018-03-29 | 2018-07-24 | 中山大学 | A kind of preparation method based on p-type transparent grid electrode GaN base ultraviolet detector |
| WO2019241905A1 (en) * | 2018-06-19 | 2019-12-26 | 深圳大学 | Heterojunction field effect transistor and preparation method therefor |
| CN108807530B (en) * | 2018-06-19 | 2021-02-09 | 深圳大学 | Heterojunction field effect transistor and preparation method thereof |
| CN108950504B (en) * | 2018-08-03 | 2020-08-14 | 江苏环奥金属材料科技有限公司 | Preparation method of alloy target material for forming ohmic contact on surface of N-type gallium arsenide |
| CN109540988B (en) * | 2018-11-09 | 2020-12-29 | 中山大学 | No reference electrode GaN base pH sensor based on interdigital electrode and groove structure |
| CN109540987B (en) * | 2018-11-09 | 2020-12-04 | 中山大学 | Reference electrode-free GaN-based pH sensor based on groove structure and preparation method thereof |
| CN109887818B (en) * | 2019-03-13 | 2024-03-12 | 西安众力为半导体科技有限公司 | Electron beam device and manufacturing method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2136406A1 (en) * | 2008-06-18 | 2009-12-23 | Samsung Mobile Display Co., Ltd. | Thin film transistor, method of manufacturing the same, and flat panel display device having the same |
| CN102082176A (en) * | 2010-12-03 | 2011-06-01 | 中山大学 | Gallium nitride (GaN) enhancement type metal insulator semiconductor field effect transistor (MISFET) device and manufacturing method thereof |
| CN102332469A (en) * | 2011-09-22 | 2012-01-25 | 中山大学 | Longitudinally-conductive GaN (gallium nitride) normally-closed MISFET (metal integrated semiconductor field effect transistor) device and manufacturing method thereof |
| CN102386223A (en) * | 2011-11-01 | 2012-03-21 | 中山大学 | High-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and manufacturing method |
| CN104183651A (en) * | 2014-08-17 | 2014-12-03 | 复旦大学 | Gallium nitride semi-floating-gate power component and manufacturing method thereof |
| CN105679679A (en) * | 2016-03-23 | 2016-06-15 | 中山大学 | Preparation method of novel GaN-based grooved gate MISFET |
-
2016
- 2016-09-30 CN CN201610868777.9A patent/CN106298887B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2136406A1 (en) * | 2008-06-18 | 2009-12-23 | Samsung Mobile Display Co., Ltd. | Thin film transistor, method of manufacturing the same, and flat panel display device having the same |
| CN102082176A (en) * | 2010-12-03 | 2011-06-01 | 中山大学 | Gallium nitride (GaN) enhancement type metal insulator semiconductor field effect transistor (MISFET) device and manufacturing method thereof |
| CN102332469A (en) * | 2011-09-22 | 2012-01-25 | 中山大学 | Longitudinally-conductive GaN (gallium nitride) normally-closed MISFET (metal integrated semiconductor field effect transistor) device and manufacturing method thereof |
| CN102386223A (en) * | 2011-11-01 | 2012-03-21 | 中山大学 | High-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and manufacturing method |
| CN104183651A (en) * | 2014-08-17 | 2014-12-03 | 复旦大学 | Gallium nitride semi-floating-gate power component and manufacturing method thereof |
| CN105679679A (en) * | 2016-03-23 | 2016-06-15 | 中山大学 | Preparation method of novel GaN-based grooved gate MISFET |
Non-Patent Citations (2)
| Title |
|---|
| 杨帆 ; 何亮 ; 郑越 ; 沈震 ; 刘扬 ; .选择区域外延槽栅结构GaN常关型MOSFET的研究.电源学报.2016,(04),全文. * |
| 王冲 ; 全思 ; 马晓华 ; 郝跃 ; 张进城 ; 毛维 ; .增强型AlGaN/GaN高电子迁移率晶体管高温退火研究.物理学报.2010,(第10期),全文. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106298887A (en) | 2017-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106298887B (en) | Preparation method of groove gate MOSFET with high threshold voltage and high mobility | |
| JP5487615B2 (en) | Field effect semiconductor device and manufacturing method thereof | |
| JP5919626B2 (en) | Compound semiconductor device and manufacturing method thereof | |
| CN102810564B (en) | A kind of radio-frequency devices and preparation method thereof | |
| JP2011082216A (en) | Compound semiconductor device and method for manufacturing the same | |
| KR102080745B1 (en) | Nitride semiconductor and method thereof | |
| CN105336789A (en) | GaN-based field effect transistor with high quality MIS structure and preparation method of GaN-based field effect transistor | |
| JP2009231458A (en) | Field-effect transistor | |
| JP6199147B2 (en) | Field effect type compound semiconductor device and manufacturing method thereof | |
| JP6343807B2 (en) | Field effect transistor and manufacturing method thereof | |
| CN107785435A (en) | A kind of low on-resistance MIS notched gates GaN base transistors and preparation method | |
| TW201947766A (en) | High electron mobility transistor | |
| CN206441733U (en) | A kind of high threshold voltage high mobility notched gates MOSFET structure | |
| JP6236919B2 (en) | Compound semiconductor device and manufacturing method thereof | |
| JP2006114795A (en) | Semiconductor device | |
| US10373833B2 (en) | Semiconductor device and method for manufacturing the same | |
| CN114883407B (en) | HEMT based on Fin-FET gate structure and manufacturing method thereof | |
| JP2010287594A (en) | Field effect transistor | |
| CN105679679A (en) | Preparation method of novel GaN-based grooved gate MISFET | |
| JP5666992B2 (en) | Field effect transistor and manufacturing method thereof | |
| CN113571516B (en) | III-nitride semiconductor integrated circuit structure, manufacturing method and application thereof | |
| CN114496788A (en) | P-type channel gallium nitride transistor and preparation method thereof | |
| CN113628962A (en) | III-nitride enhanced HEMT device and manufacturing method thereof | |
| CN106449406A (en) | Vertical-structure GaN-based enhancement mode field effect transistor and manufacturing method therefor | |
| CN114883396B (en) | Concave Fin-JFET gate structure HEMT and manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |