CN102332469A - Longitudinally-conductive GaN (gallium nitride) normally-closed MISFET (metal integrated semiconductor field effect transistor) device and manufacturing method thereof - Google Patents
Longitudinally-conductive GaN (gallium nitride) normally-closed MISFET (metal integrated semiconductor field effect transistor) device and manufacturing method thereof Download PDFInfo
- Publication number
- CN102332469A CN102332469A CN201110282654A CN201110282654A CN102332469A CN 102332469 A CN102332469 A CN 102332469A CN 201110282654 A CN201110282654 A CN 201110282654A CN 201110282654 A CN201110282654 A CN 201110282654A CN 102332469 A CN102332469 A CN 102332469A
- Authority
- CN
- China
- Prior art keywords
- layer
- gan
- heterostructure
- barrier layer
- gan layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a longitudinally-conductive GaN (gallium nitride) normally-closed MISFET (metal integrated semiconductor field effect transistor) device and a manufacturing method thereof. The device successively comprises a substrate (1), an n-type GaN layer (2), an electronic barrier layer (3), a non-doped GaN layer (4) and a heterostructure potential barrier layer (5) from bottom to top, wherein a groove is etched in the n-type GaN layer from the surface of the heterostructure potential barrier layer; a p-type GaN layer is formed on the groove by secondary growth so as to realize a grid conducting channel (7); two ends of the heterostructure potential barrier layer form source electrodes (9); an insulating layer (8) is covered on the grid conducting channel and the exposed surface of the heterostructure potential barrier layer; a grid electrode (11) is covered at a channel position on the insulating layer; and drain electrodes (10) are covered on the underside of the substrate. In the invention, a two-dimensional electron gas heterostructure with high concentration is taken as an access area, thus effectively reducing the on resistance; and the thin p-type GaN layer is formed in the etching groove by secondary growth, thus being easy to improve the threshold voltage and channel mobility of the longitudinally-conductive normally-closed MISFET.
Description
Technical field
The present invention relates to field of semiconductor devices, the GaN that is specifically related to a kind of vertical conducting is pass type MISFET device and preparation method thereof often.
Background technology
The GaN semi-conducting material is because its broad stopband width, high breakdown electric field (up to 3MV/cm), high saturated electron drift velocity and good superior performances such as thermal conductivity; Compare with the Si material; Be fit to make the device for power switching of high-power high-capacity, high switching speed more, become the ideal substitute of device for power switching of future generation.
The GaN material has stronger polarity effect, and the interface of the AlGaN/GaN heterojunction of growing on the polarised direction is because polarity effect forms 10
13Cm
-2The two-dimensional electron gas of left and right sides high concentration and high electron mobility (2DEG) makes AlGaN/GaN HFET (HFETs) have extremely low conducting resistance, is fit to very much make device for power switching.Therefore utilizing the GaN heterostructure with 2DEG to prepare high performance normal pass type device for power switching, is the important topic that realizes GaN device for power switching practicability target.
The GaN device for power switching is divided into side direction conduction device and vertical conduction device from device architecture.The side direction conducting is a present GaN base HFET device device architecture commonly used; Directly utilize AlGaN/GaN heterostructure 2DEG raceway groove as the break-over of device raceway groove; The active area of device concentrates on the device epitaxial layers surface like this, and device source electrode, grid and drain electrode all design on the same plane of device.Side direction conducting GaN electronic device owing to electric field between grid, the drain electrode is concentrated relatively, forms the electric field collection side effect at gate edge especially easily under high-tension operational environment, device is prone to puncture.Vertically conduction device is that source electrode is positioned on the potential barrier of heterogenous junction layer, and drain electrode is positioned at bottom electrode, utilizes the conductive channel of grid control vertical conducting.Vertically conducting GaN electronic device electric current vertically is distributed in the device, and Electric Field Distribution is more even, effectively improves device electric breakdown strength.Compare side direction conducting GaN switching device, vertically conducting GaN switching device is fit to be applied in high-power, the high-tension operational environment more.
In the power electronic equipment that with the Semiconductor Converting Technology is the basis, the power switch transistor of control unsteady flow process all is normal (claiming enhancement mode again) of pass type, and this point is the basis that guarantees power electronics loop " fail safe ".The preparation that realizes enhancement mode GaN device for power switching is the present International Technology circle scientific and technological difficult point generally acknowledged with industrial circle.
Realize at present vertical conducting often pass type GaN FET device the mainstream technology scheme be traditional metal dielectric layer semiconductor field effect transistor (MISFET).The source electrode of this device is positioned at through ion and injects the perhaps method formation n of alloy
+The access district, conducting channel is arranged in p type GaN layer, adds certain positive voltage at grid; Make the MIS arrangement works at anti-type state, form n type conducting channel, realize break-over of device at the p-GaN laminar surface; MISFET can effectively improve device threshold voltage, reduces leakage current.People such as the Hirotaka OTAKE of Japanese rom semiconductor R&D Headquarters in 2007 and the Japanese Yasushi NANISHI of Ritsumeikan University introduce vee-cut grid structure in MISFET, its gate insulator is Si
xN
y/ SiO
2, utilize the heavily doped n type of Si GaN layer to insert the district as source electrode, the threshold voltage of device is 5.1V, has realized normal pass type device, its channel mobility reaches 133cm
2/ (Vs).The people such as Hirotaka OTAKE of rom semiconductor R&D Headquarters in 2008 have realized the vertical conducting of notched gates pass type MOSFET often on the GaN substrate, its gate insulator adopts Si
xN
y/ SiO
2, source electrode inserts the district and is the heavily doped n type of Si GaN layer, and the threshold voltage of its device is 3.7V, and conducting resistance is 9.3m Ω cm
2, channel mobility reaches 131 cm in theory
2/ (Vs).
From above-mentioned report; The vertical conducting of GaN base notched gates often the conducting resistance of pass type device still than higher; Electron mobility in the raceway groove is also lower, and this mainly is to utilize ICP to be etched in the heterostructure in the process that forms groove, and the lattice of recess edge is caused damage.In device work engineering, recess edge is as conducting channel, because the influence of damage lattice, causes the conducting resistance of device to become big and channel electron mobility reduces.
Summary of the invention
The objective of the invention is to improve the break-over of device resistance height that prior art is made; The deficiency of etched recesses damage lattice, the GaN that a kind of vertical conducting that can realize high forward threshold voltage, high electron mobility, superior performance is provided is pass type MISFET device and preparation method thereof often.
The heterostructure that the present invention has combined to have the high concentration two-dimensional electron gas is distinguished the low characteristic of conducting resistance as inserting, and combines the diauxic growth technology, recovers the lattice of grooved area dry etching damage.
For realizing above-mentioned purpose; Technical scheme of the present invention is: a kind of GaN of vertical conducting is pass type MISFET device often, comprises conduction GaN substrate, n type GaN layer from lower to upper successively, electronic barrier layer, non-Doped GaN layer and heterostructure barrier layer; By heterostructure barrier layer surface etch one groove to n type GaN layer; Diauxic growth p type GaN layer is realized the grid conducting channel on groove, and the two ends of heterostructure barrier layer are formed with source electrode, surface coverage one insulating barrier that grid conducting channel and heterostructure barrier layer are exposed; Raceway groove position on the insulating barrier is coated with grid, and conduction GaN substrate bottom surface is coated with drain electrode.
This groove is U type, V-type or trapezoidal-structure.
Substrate is conduction GaN substrate, perhaps, is made up of low-resistance silicon substrate or low-resistance carborundum and conductive buffer layer.
The conduction GaN substrate Doped GaN substrate of attaching most importance to, n type GaN layer is a light dope GaN layer; Wherein, doping content is 10
18More than being heavy doping, is light dope under this numerical value.
Groove is selected the P type GaN layer of growth, and thickness is 1-20nm; The thickness of said n type GaN layer is 1-50 μ m.The AlN layer of between electronic barrier layer and non-Doped GaN layer, also growing.
The GaN layer or the high resistant GaN layer that mixes that said electronic barrier layer material mixes for the p type, the doped chemical of said doping high resistant GaN layer is carbon or iron; Said electronic barrier layer thickness is 50-500nm; The thickness of said non-Doped GaN layer is 10-500nm; Said heterostructure barrier layer material is a kind of or any several kinds combination among AlGaN, AlInN, AlInGaN, the AlN, and said heterostructure barrier layer thickness is 1-50nm.
Said insulating layer material is SiO
2, SiN
x, Al
2O
3, AlN, HfO
2, MgO, Sc
2O
3, Ga
2O
3, AlHfO
xOr HfSiON, said thickness of insulating layer is 1-100nm; Source electrode and drain material are Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy or Ti/Al/Mo/Au alloy; Grid material is Ni/Au alloy, Pt/Al alloy or Pd/Au alloy.
Simultaneously, the GaN that the present invention also provides a kind of vertical conducting is the manufacture method of pass type MISFET device often, and it may further comprise the steps:
1. growing n-type GaN layer, electronic barrier layer, non-Doped GaN layer and heterostructure barrier layer successively on conduction GaN substrate;
2. at potential barrier of heterogenous junction layer growth one deck dielectric layer, as the mask layer of dry etching;
3. adopt photoetching technique, select the mask layer of regional etching area of grid;
4. utilization is dry-etched in area of grid and etches groove;
5. select growing p-type GaN layer to form the grid conducting channel at the groove position;
6. remove mask layer;
7. at the insulating barrier of potential barrier of heterogenous junction layer and p type GaN laminar surface deposition grid;
8. dry etching is accomplished device isolation, etches source electrode ohmic contact zone at insulating barrier and mask layer simultaneously.
9. source electrode metal ohmic contact on the vapor deposition of source region, metal ohmic contact drains on conduction GaN substrate back vapor deposition;
10. area of grid vapor deposition gate metal on insulating barrier.
Manufacture method of the present invention, direct growth source electrode heterojunction inserts the district as low on-resistance, because the heterostructure barrier layer has two electron gases of high areal density, effectively reduces conducting resistance.Improve the device grids threshold voltage through etched recesses diauxic growth p type GaN layer, improved the mobility of electronics in the raceway groove, improved device reliability.
The growing method of p type GaN layer is Metalorganic Chemical Vapor Deposition or molecular beam epitaxy in n type GaN layer, electronic barrier layer, non-Doped GaN layer, heterostructure barrier layer and the groove of said step in 1..
Said step 2. medium layer and step 7. in the growing method of insulating barrier be plasma enhanced chemical vapor deposition method, atomic layer deposition method, physical vaporous deposition or magnetron sputtering method.
Compared with prior art, beneficial effect of the present invention is,
The present invention utilizes the AlGaN/GaN heterostructure to insert the district as device, simultaneously the method for diauxic growth thin layer p type GaN on the heterostructure etched recesses.High two-dimensional electron gas can reduce the conducting resistance of device in the heterostructure, utilizes diauxic growth to make the lattice of groove edge damage in high growth temperature, recover lattice again.Utilize diauxic growth thin layer p type GaN layer to replace having reduced interface roughness scattering and the influence of dislocation scattering, raising channel mobility as conducting channel to channel electron mobility through the recess edge layer of etching injury.P type GaN layer needs grid to provide enough big positive voltage could form the electron inversion layer as conducting channel simultaneously, has improved threshold voltage, realizes satisfying the normal pass type device of practical needs.
Description of drawings
Fig. 1-10 is the device manufacture method process schematic representation of the embodiment of the invention 1;
Figure 11 is the device architecture sketch map of the embodiment of the invention 2;
Figure 12 is the device architecture sketch map of the embodiment of the invention 3;
Figure 13 is the device architecture sketch map of the embodiment of the invention 4;
Figure 14 is the device architecture sketch map of the embodiment of the invention 5;
Figure 15 is the device architecture sketch map of the embodiment of the invention 6.
Embodiment
Below in conjunction with embodiment and accompanying drawing the present invention is carried out detailed description.
Shown in figure 10 is the device architecture sketch map of present embodiment; Comprise grid 11, source electrode 9, drain electrode 10, insulating barrier 8, conduction GaN substrate 1, n type GaN layer 2, electronic barrier layer 3, non-Doped GaN layer 4 and heterostructure barrier layer 5; Dry etching forms groove, and diauxic growth p type GaN layer is realized grid conducting channel 7, the surface coverage insulating barrier 8 of raceway groove 7 and heterostructure barrier layer 5; Grid 11 is covered in raceway groove 7 places on the insulating barrier, etching insulating barrier 8 and SiO
2The mask two ends form the source region, and place, source region vapor deposition ohmic metal forms the source electrode 5 that contacts with heterostructure barrier layer 5, and drain electrode 10 places conduction GaN substrate back.In the present embodiment, the conduction GaN substrate 1 Doped GaN substrate of attaching most importance to, n type GaN layer 2 is a light dope GaN layer.
The GaN of above-mentioned vertical conducting is manufacture method such as Fig. 1 of pass type MISFET device-shown in Figure 10 often, may further comprise the steps:
1. utilize metal organic chemical vapor deposition growth one deck n type light dope GaN layer 2 on conduction GaN substrate 1; The GaN layer that the P type mixes is as electronic barrier layer 3, non-Doped GaN layer 4, AlGaN heterostructure barrier layer 5; N type light dope GaN layer 2, electronic barrier layer 3, non-Doped GaN layer 4, AlGaN heterostructure barrier layer 5 thickness are respectively 1-50 μ m, 250-500nm, 10-500nm, 1-50nm, and are as shown in Figure 1;
2. on AlGaN heterostructure barrier layer 5, as the mask layer 6 of selecting growth, as shown in Figure 2 through plasma enhanced chemical vapor deposition method growth one deck dielectric layer;
3. adopt photoetching technique, select the mask layer 6 of regional etching area of grid,, as shown in Figure 3;
4. utilize ICP to etch groove in the zone of removing mask, groove is etched in the n type light dope GaN layer deeply, and is as shown in Figure 4.
5. utilize metal organic chemical vapor deposition to select growing p-type GaN layer 7 at the position of groove, as conducting channel, thickness is 1-20nm.As shown in Figure 5;
6. remove mask layer 6, as shown in Figure 6;
7. use the plasma enhanced chemical vapor deposition method, at potential barrier of heterogenous junction layer and p type GaN surface deposition one floor height K dielectric insulation layer 8, thickness is 1-100nm, and is as shown in Figure 7;
8. utilize ICP to accomplish device isolation, etch source electrode ohmic contact zone at insulating barrier 8 simultaneously, as shown in Figure 8;
9. on the vapor deposition of source region the Ti/Al/Ni/Au alloy as the ohmic contact of source electrode 9, on conduction GaN substrate 1 bottom surface also vapor deposition the Ti/Al/Ni/Au alloy as the ohmic contact of drain electrode 10, as shown in Figure 9.
10. adopt evaporation process, on insulating barrier 8 vapor deposition Ni/Au alloy as the ohmic contact of grid 11, shown in figure 10.So far, promptly accomplished the preparation process of entire device.Figure 10 is the device architecture sketch map of embodiment 1.
Shown in figure 11 is the device architecture sketch map of present embodiment, itself and embodiment 1 similar, and the difference thickness that only is on electronic barrier layer 3, to grow earlier before the non-Doped GaN layer 4 of growth is the AlN layer 12 of 5-50nm.Because in the growth of electronic barrier layer 3, for making the high resistance barrier of this layer formation electronics, carried out the p type and mixed, impurity possibly diffuse in the non-Doped GaN layer 4 on its upper strata in the process of growth, influences device performance.Therefore the AlN layer 12 of introducing skim will stop effectively that these diffusion of impurities go into non-Doped GaN layer 4.
Shown in figure 12 is the device architecture sketch map of present embodiment, itself and embodiment 1 similar, difference only with after the area of grid etched recesses, do not remove mask layer 6, directly carry out subsequent process steps.The purpose of doing like this is to reduce removes mask layer 6 steps, simplifies technological process, and mask layer 6 can be used as passivation layer simultaneously.
Shown in figure 13 is the device architecture sketch map of present embodiment, and itself and embodiment 1 similar after difference only is to remove the epitaxial loayer reticule, utilize dry etching to form V-shaped groove removing masked areas.The vertical conducting MISFET of trapezoidal grid can obtain than higher electron mobility in raceway groove when realizing normal pass type device.
Shown in figure 14 is the device architecture sketch map of present embodiment; Itself and embodiment 4 similar; Difference only is to utilize dry etching to form dovetail groove removing masked areas, obtains than higher channel electron mobility when often can realize pass type device equally.
Shown in figure 15 is the device architecture sketch map of ability instance; Itself and embodiment 1 are similar; Difference is to utilize low-resistance silicon substrate or low-resistance carborundum 14 to replace conduction GaN substrate 1 with conductive buffer layer 13; Use cheap silicon substrate can reduce device cost, above-mentioned low-resistance is meant electricalresistivity < the 20 Ω cm of silicon substrate.
Claims (10)
1. the normal pass type MISFET device of the GaN of a vertical conducting; It is characterized in that; Comprise substrate (1), n type GaN layer (2) from lower to upper successively; Electronic barrier layer (3), non-Doped GaN layer (4) and heterostructure barrier layer (5), to n type GaN layer (2), diauxic growth p type GaN layer is realized grid conducting channel (7) on groove by heterostructure barrier layer (5) surface etch one groove; The two ends of heterostructure barrier layer (5) are formed with source electrode (9); Surface coverage one insulating barrier (8) that grid conducting channel (7) and heterostructure barrier layer (5) are exposed, raceway groove (7) position on the insulating barrier (8) is coated with grid (11), and substrate (1) bottom surface is coated with drain electrode (10).
2. the normal pass type MISFET device of the GaN of vertical conducting according to claim 1 is characterized in that this groove is U type, V-type or trapezoidal-structure.
3. the normal pass type MISFET device of the GaN of vertical conducting according to claim 1 is characterized in that, substrate (1) is conduction GaN substrate, perhaps, is made up of low-resistance silicon substrate or low-resistance carborundum (14) and conductive buffer layer (13).
4. the normal pass type MISFET device of the GaN of vertical conducting according to claim 3 is characterized in that, conduction GaN substrate (1) the Doped GaN substrate of attaching most importance to, and n type GaN layer (2) is a light dope GaN layer; Groove is selected the P type GaN layer of growth, and thickness is 1-20nm; The thickness of said n type GaN layer is 1-50 μ m.
5. the normal pass type MISFET device of the GaN of vertical conducting according to claim 1 is characterized in that the AlN layer (12) of between electronic barrier layer (3) and non-Doped GaN layer (4), also growing.
6. the normal pass type MISFET device of the GaN of vertical conducting according to claim 1 is characterized in that, said electronic barrier layer (3) material is the GaN layer or the high resistant GaN layer that mixes that the p type mixes, and the doped chemical of said doping high resistant GaN layer is carbon or iron;
Said electronic barrier layer (3) thickness is 50-500nm;
The thickness of said non-Doped GaN layer (4) is 10-500nm;
Said heterostructure barrier layer (5) material is a kind of or any several kinds combination among AlGaN, AlInN, AlInGaN, the AlN, and said heterostructure barrier layer thickness is 1-50nm.
7. the normal pass type MISFET device of the GaN of vertical conducting according to claim 1 is characterized in that said insulating barrier (8) material is SiO
2, SiN
x, Al
2O
3, AlN, HfO
2, MgO, Sc
2O
3, Ga
2O
3, AlHfO
xOr HfSiON, said insulating barrier (8) thickness is 1-100nm; Source electrode (9) and drain electrode (10) material are Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy or Ti/Al/Mo/Au alloy; Grid (11) material is Ni/Au alloy, Pt/Al alloy or Pd/Au alloy.
8. the normal manufacture method of pass type MISFET device of the GaN of the described vertical conducting of claim 1 is characterized in that, may further comprise the steps:
1. growing n-type GaN layer, electronic barrier layer, non-Doped GaN layer and heterostructure barrier layer successively on conduction GaN substrate;
2. at potential barrier of heterogenous junction layer growth one deck dielectric layer, as the mask layer of dry etching;
3. adopt photoetching technique, select the mask layer of regional etching area of grid;
4. utilization is dry-etched in area of grid and etches groove;
5. select growing p-type GaN layer to form the grid conducting channel at the groove position;
6. remove mask layer;
7. at the insulating barrier of potential barrier of heterogenous junction layer and p type GaN laminar surface deposition grid;
8. dry etching is accomplished device isolation, etches source electrode ohmic contact zone at insulating barrier and mask layer simultaneously;
9. source electrode metal ohmic contact on the vapor deposition of source region, metal ohmic contact drains on conduction GaN substrate back vapor deposition;
10. area of grid vapor deposition gate metal on insulating barrier.
9. the normal pass type MISFET device manufacture method of the GaN of vertical conducting according to claim 8; It is characterized in that the growing method of p type GaN layer is Metalorganic Chemical Vapor Deposition or molecular beam epitaxy in n type GaN layer, electronic barrier layer, non-Doped GaN layer, heterostructure barrier layer and the groove of said step in 1..
10. the normal pass type MISFET device manufacture method of the GaN of vertical conducting according to claim 8; It is characterized in that, said step 2. medium layer and step 7. in the growing method of insulating barrier be plasma enhanced chemical vapor deposition method, atomic layer deposition method, physical vaporous deposition or magnetron sputtering method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110282654.4A CN102332469B (en) | 2011-09-22 | 2011-09-22 | Longitudinally-conductive GaN (gallium nitride) normally-closed MISFET (metal integrated semiconductor field effect transistor) device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110282654.4A CN102332469B (en) | 2011-09-22 | 2011-09-22 | Longitudinally-conductive GaN (gallium nitride) normally-closed MISFET (metal integrated semiconductor field effect transistor) device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102332469A true CN102332469A (en) | 2012-01-25 |
| CN102332469B CN102332469B (en) | 2014-02-12 |
Family
ID=45484185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110282654.4A Active CN102332469B (en) | 2011-09-22 | 2011-09-22 | Longitudinally-conductive GaN (gallium nitride) normally-closed MISFET (metal integrated semiconductor field effect transistor) device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102332469B (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709320A (en) * | 2012-02-15 | 2012-10-03 | 中山大学 | Longitudinally-conductive GaN (gallium nitride)-substrate MISFET (metal insulated semiconductor field-effect transistor) device and manufacturing method thereof |
| CN102856366A (en) * | 2012-09-04 | 2013-01-02 | 程凯 | Enhancement type device |
| CN104681620A (en) * | 2015-01-21 | 2015-06-03 | 中山大学 | Longitudinal conduction GaN (gallium nitride) normally-off MISFET (metal-insulator-semiconductor field effect transistor) device and manufacturing method thereof |
| CN105428420A (en) * | 2015-12-28 | 2016-03-23 | 武汉华星光电技术有限公司 | Semiconductor layer structure and preparation method thereof and thin-film transistor |
| CN105655395A (en) * | 2015-01-27 | 2016-06-08 | 苏州捷芯威半导体有限公司 | Enhanced high electronic mobility transistor and manufacturing method thereof |
| CN105957890A (en) * | 2016-06-15 | 2016-09-21 | 浙江大学 | Novel enhanced AlGaN/GaN semiconductor device and preparation method thereof |
| CN106298887A (en) * | 2016-09-30 | 2017-01-04 | 中山大学 | A kind of preparation method of high threshold voltage high mobility notched gates MOSFET |
| CN107230628A (en) * | 2016-03-25 | 2017-10-03 | 北京大学 | Gallium nitride field effect transistor and its manufacture method |
| CN107393890A (en) * | 2017-08-24 | 2017-11-24 | 北京华进创威电子有限公司 | A kind of graphene buries heat dissipating layer and longitudinal channel GaN MISFET structure cells and preparation method |
| CN107431085A (en) * | 2015-04-14 | 2017-12-01 | Hrl实验室有限责任公司 | Iii-nitride transistor with trench gate |
| CN108962981A (en) * | 2018-07-13 | 2018-12-07 | 北京大学 | It is a kind of to reduce the structure and preparation method thereof leaked electricity in gallium nitride-based epitaxial layer |
| CN110875381A (en) * | 2018-08-29 | 2020-03-10 | 苏州能讯高能半导体有限公司 | Semiconductor device and manufacturing method thereof |
| WO2020216250A1 (en) * | 2019-04-26 | 2020-10-29 | 苏州晶湛半导体有限公司 | Enhanced device and preparation method therefor |
| CN113611731A (en) * | 2021-06-17 | 2021-11-05 | 西安电子科技大学广州研究院 | GaN-based enhanced vertical HEMT device and preparation method thereof |
| WO2023279524A1 (en) * | 2021-07-09 | 2023-01-12 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing semiconductor structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130160A (en) * | 2011-01-06 | 2011-07-20 | 西安电子科技大学 | Groove-shaped channel AlGaN/GaN-reinforced high electron mobility transistor (HEMT) component and manufacturing method thereof |
| CN102184956A (en) * | 2011-04-15 | 2011-09-14 | 中山大学 | Longitudinal conduction GaN enhancement type MISFET (Metal Integrated Semiconductor Field Effect Transistor) device and manufacturing method thereof |
-
2011
- 2011-09-22 CN CN201110282654.4A patent/CN102332469B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130160A (en) * | 2011-01-06 | 2011-07-20 | 西安电子科技大学 | Groove-shaped channel AlGaN/GaN-reinforced high electron mobility transistor (HEMT) component and manufacturing method thereof |
| CN102184956A (en) * | 2011-04-15 | 2011-09-14 | 中山大学 | Longitudinal conduction GaN enhancement type MISFET (Metal Integrated Semiconductor Field Effect Transistor) device and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| X.HU等: "Enhancement mode AlGaN/GaN HFET with selectively grown pn junction gate", 《ELECTRONICS LETTERS》, vol. 36, no. 8, 13 April 2000 (2000-04-13) * |
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102709320A (en) * | 2012-02-15 | 2012-10-03 | 中山大学 | Longitudinally-conductive GaN (gallium nitride)-substrate MISFET (metal insulated semiconductor field-effect transistor) device and manufacturing method thereof |
| CN102709320B (en) * | 2012-02-15 | 2014-09-24 | 中山大学 | Longitudinally-conductive GaN (gallium nitride)-substrate MISFET (metal insulated semiconductor field-effect transistor) device and manufacturing method thereof |
| CN102856366A (en) * | 2012-09-04 | 2013-01-02 | 程凯 | Enhancement type device |
| CN104681620A (en) * | 2015-01-21 | 2015-06-03 | 中山大学 | Longitudinal conduction GaN (gallium nitride) normally-off MISFET (metal-insulator-semiconductor field effect transistor) device and manufacturing method thereof |
| CN104681620B (en) * | 2015-01-21 | 2018-02-09 | 中山大学 | A kind of GaN normally-off MISFET devices longitudinally turned on and preparation method thereof |
| CN105655395A (en) * | 2015-01-27 | 2016-06-08 | 苏州捷芯威半导体有限公司 | Enhanced high electronic mobility transistor and manufacturing method thereof |
| CN107431085B (en) * | 2015-04-14 | 2019-11-12 | Hrl实验室有限责任公司 | III-nitride transistor with trench gate |
| CN107431085A (en) * | 2015-04-14 | 2017-12-01 | Hrl实验室有限责任公司 | Iii-nitride transistor with trench gate |
| CN105428420A (en) * | 2015-12-28 | 2016-03-23 | 武汉华星光电技术有限公司 | Semiconductor layer structure and preparation method thereof and thin-film transistor |
| US10109648B2 (en) | 2015-12-28 | 2018-10-23 | Wuhan China Star Optoelectonics Technology Co., Ltd | Semiconductor layer structure |
| WO2017113451A1 (en) * | 2015-12-28 | 2017-07-06 | 武汉华星光电技术有限公司 | Semiconductor layer structure and preparation method thereof |
| CN105428420B (en) * | 2015-12-28 | 2018-12-04 | 武汉华星光电技术有限公司 | Semiconductor layer structure and preparation method and thin film transistor (TFT) |
| CN107230628A (en) * | 2016-03-25 | 2017-10-03 | 北京大学 | Gallium nitride field effect transistor and its manufacture method |
| CN105957890A (en) * | 2016-06-15 | 2016-09-21 | 浙江大学 | Novel enhanced AlGaN/GaN semiconductor device and preparation method thereof |
| CN106298887A (en) * | 2016-09-30 | 2017-01-04 | 中山大学 | A kind of preparation method of high threshold voltage high mobility notched gates MOSFET |
| CN106298887B (en) * | 2016-09-30 | 2023-10-10 | 中山大学 | Preparation method of groove gate MOSFET with high threshold voltage and high mobility |
| CN107393890A (en) * | 2017-08-24 | 2017-11-24 | 北京华进创威电子有限公司 | A kind of graphene buries heat dissipating layer and longitudinal channel GaN MISFET structure cells and preparation method |
| CN107393890B (en) * | 2017-08-24 | 2023-10-20 | 北京华进创威电子有限公司 | Graphene buried heat dissipation layer and longitudinal channel GaN MISFET cell structure and preparation method |
| CN108962981A (en) * | 2018-07-13 | 2018-12-07 | 北京大学 | It is a kind of to reduce the structure and preparation method thereof leaked electricity in gallium nitride-based epitaxial layer |
| CN110875381A (en) * | 2018-08-29 | 2020-03-10 | 苏州能讯高能半导体有限公司 | Semiconductor device and manufacturing method thereof |
| CN110875381B (en) * | 2018-08-29 | 2022-09-06 | 苏州能讯高能半导体有限公司 | Semiconductor device and manufacturing method thereof |
| WO2020216250A1 (en) * | 2019-04-26 | 2020-10-29 | 苏州晶湛半导体有限公司 | Enhanced device and preparation method therefor |
| CN113611731A (en) * | 2021-06-17 | 2021-11-05 | 西安电子科技大学广州研究院 | GaN-based enhanced vertical HEMT device and preparation method thereof |
| WO2023279524A1 (en) * | 2021-07-09 | 2023-01-12 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102332469B (en) | 2014-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102332469B (en) | Longitudinally-conductive GaN (gallium nitride) normally-closed MISFET (metal integrated semiconductor field effect transistor) device and manufacturing method thereof | |
| CN102386223B (en) | High-threshold voltage gallium nitride (GaN) enhancement metal oxide semiconductor heterostructure field effect transistor (MOSHFET) device and manufacturing method | |
| TWI520337B (en) | Step trench metal-oxide-semiconductor field-effect transistor and method of fabrication the same | |
| CN105164811B (en) | Electrode of semiconductor devices and forming method thereof | |
| CN102184956B (en) | Longitudinal conduction GaN enhancement type MISFET (Metal Integrated Semiconductor Field Effect Transistor) device and manufacturing method thereof | |
| US8860089B2 (en) | High electron mobility transistor and method of manufacturing the same | |
| CN104067384A (en) | Method and system for a gallium nitride vertical JFET with self-aligned source and gate | |
| CN102709320B (en) | Longitudinally-conductive GaN (gallium nitride)-substrate MISFET (metal insulated semiconductor field-effect transistor) device and manufacturing method thereof | |
| JPWO2014038110A1 (en) | Semiconductor device | |
| CN104638010B (en) | A kind of GaN normally-off MISFET devices laterally turned on and preparation method thereof | |
| CN109560120B (en) | GaN normally-off MISFET device with vertical grooves grown in selective area and manufacturing method thereof | |
| CN102082176A (en) | Gallium nitride (GaN) enhancement type metal insulator semiconductor field effect transistor (MISFET) device and manufacturing method thereof | |
| CN103210496A (en) | Semiconductor device and manufacturing method therefor | |
| WO2012060206A1 (en) | Semiconductor device and manufacturing method therefor | |
| WO2020107754A1 (en) | Epitaxial layer structure for increasing threshold voltage of gan-enhanced mosfet and device fabrication method | |
| CN102856374A (en) | GaN enhanced MIS-HFET device and preparation method of same | |
| CN108376707A (en) | A kind of enhanced HEMT device of GaN base and preparation method thereof | |
| CN104681620B (en) | A kind of GaN normally-off MISFET devices longitudinally turned on and preparation method thereof | |
| CN108231880B (en) | Enhanced GaN-based HEMT device and preparation method thereof | |
| CN111081763B (en) | Normally-off HEMT device with honeycomb groove barrier layer structure below field plate and preparation method thereof | |
| CN210897283U (en) | Semiconductor device with a plurality of transistors | |
| CN117253917A (en) | GaN MIS HEMT shielded by surface trap and preparation method thereof | |
| US9362381B2 (en) | Insulated gate bipolar transistor with a lateral gate structure and gallium nitride substrate and manufacturing method thereof | |
| CN110970499B (en) | GaN-based transverse super-junction device and manufacturing method thereof | |
| CN114551586B (en) | Silicon carbide split gate MOSFET cell integrated with grid-controlled diode and preparation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20211117 Address after: Room 507-2, building 3, 111 Xiangke Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai 201210 Patentee after: CHIP FOUNDATION TECHNOLOGY Ltd. Address before: 510275 No. 135 West Xingang Road, Guangdong, Guangzhou Patentee before: SUN YAT-SEN University |
|
| TR01 | Transfer of patent right |