JP2010287594A - Field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor which has small parasitic resistance while actualizing normally off operation. <P>SOLUTION: The field effect transistor includes a buffer layer 2 formed on a substrate 1 and made of GaN, an electron supply layer 3 formed on the buffer layer 2 and made of In<SB>x</SB>Al<SB>y</SB>Ag<SB>1-x-y</SB>N (where 0≤x≤1, 0≤y≤1, and 0<x+y≤1), and a cap layer 4 which is formed on the electron supply layer 3 and has a different composition from the electron supply layer 3, to which an n-type impurity of high concentration is added, and which is made of In<SB>s</SB>Al<SB>t</SB>Ag<SB>1-s-t</SB>N (where 0≤s≤1, 0≤t≤1, and 0<s+t≤1). A recess 4a is formed in the cap layer 4, a source electrode 5 and a drain electrode 7 are formed in both regions by the recess 4a in the cap layer 4, and a gate electrode 6 is formed at the recess 4a in the cap layer 4 with the insulating film 8 interposed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a field effect transistor, and more particularly to a field effect transistor made of a group III nitride semiconductor and applicable to a power transistor.

  A group III nitride semiconductor typified by gallium nitride (GaN) has excellent physical properties exceeding silicon (Si) or gallium arsenide (GaAs) such as a high breakdown electric field and a high saturation electron velocity. For this reason, field effect transistors (hereinafter referred to as FETs) using group III nitride semiconductors are considered promising as next-generation high-frequency devices or high-power switching devices, and are actively developed. ing. Group III nitride semiconductors are characterized by having extremely large polarization, and high-concentration carriers are not added at the heterojunction interface made of GaN, indium nitride (InN), or aluminum nitride (AlN) without adding impurities. appear. This is preferable from the viewpoint of increasing the power consumption and output of the device, but it means that it is difficult to realize a normally-off operation at the same time. At present, most of the devices used in the power electronics market are normally-off type, and therefore normally-off operation is strongly demanded also in group III nitride semiconductor devices.

  For this reason, in Patent Document 1, a normally-off operation is realized by controlling the polarization generated by using InAlGaN, which is a mixed crystal of InN, AlN and GaN, in the electron supply layer, and suppressing the generation of carriers. Yes.

Japanese Patent No. 3209270 JP 2003-188190 A

Joural Of Appleid Physics Vol.87 P334-P336, 2005

  However, under the conditions described in Patent Document 1, only piezo polarization is taken into consideration, and therefore a normally-off operation cannot always be realized. Further, when a normally-off type is realized by using the structure described in Patent Document 1, carriers are not generated between the source electrode and the gate electrode and between the gate electrode and the drain electrode, so that the parasitic resistance A significant increase is inevitable. In order to alleviate this problem, a method using the structure described in Patent Document 2 can be considered.

  FIG. 9 shows a cross-sectional configuration of a conventional field effect transistor described in Patent Document 2 having a cap layer made of n-type GaN. As shown in FIG. 9, on the sapphire substrate 11, a buffer layer 12 made of undoped GaN, an electron supply layer 13 made of undoped InAlGaN, and a cap layer 14 made of n-type GaN doped with a high concentration of impurities are sequentially formed. It is formed by epitaxial growth. An opening that exposes the electron supply layer 13 therebelow is formed in the cap layer 14, and a gate electrode 16 made of nickel (Ni) / gold (Au) is formed on the exposed electron supply layer 13. ing. Further, a source electrode 15 and a drain electrode 17 made of titanium (Ti) / aluminum (Al) are respectively formed in regions on both sides of the opening on the cap layer 14. A two-dimensional electron gas layer 18 is formed in the vicinity of the interface between the buffer layer 12 and the electron supply layer 13.

  With this configuration, carriers can move through the cap layer 14, and thus the resistance of the device can be reduced. In particular, since the field effect transistor described in Patent Document 2 is a normally-on type, a certain degree of effect is expected. However, when the above configuration is applied to a normally-off type device, since the gate electrode 16 is formed away from the cap layer 14, the gap between the cap layer 14 on the source electrode 15 side and the gate electrode 16, and the drain A region where no carrier exists between the cap layer 14 on the electrode 17 side and the gate electrode 16 is generated, resulting in a problem that parasitic resistance increases.

  In view of the above-described conventional problems, an object of the present invention is to obtain a field effect transistor having a low parasitic resistance while realizing a normally-off operation.

  In order to achieve the above object, the present invention provides a field effect transistor in which an opening is formed in a cap layer formed on an electron supply layer, and a gate electrode is formed with an insulating film interposed in the opening. The configuration is as follows.

Specifically, the field-effect transistor according to the present invention is formed on the substrate, a first semiconductor layer made of GaN, formed on the first semiconductor layer, In _x Al _y Ga _{1- a} second semiconductor layer formed of _xy N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 <x + y ≦ 1), and the second semiconductor layer. and high-concentration n-type impurity has a different composition than the is _{added, in s Al t Ga 1-} s-t n ( where, 0 ≦ s ≦ 1,0 ≦ t ≦ 1,0 ≦ s + t ≦ 1 ), And an opening is formed in the third semiconductor layer, and a source electrode and a drain electrode are formed in regions on both sides of the opening in the third semiconductor layer. The gate electrode is formed in the opening of the third semiconductor layer with an insulating film interposed therebetween.

  According to the field effect transistor of the present invention, since the gate electrode is formed in the opening of the third semiconductor layer with the insulating film interposed therebetween, the polarization of the second semiconductor layer that is the electron supply layer has an appropriate size. Can be controlled. For this reason, a normally-off type operation can be realized, and the low-resistance third semiconductor layer can be brought close to the gate electrode, so that parasitic resistance can be reduced.

  In the field effect transistor of the present invention, the gate electrode is preferably formed so as to be in contact with the wall surface of the opening with an insulating film interposed therebetween.

In the field effect transistor of the present invention, the composition of In _x Al _y Ga _1-xy N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 <x + y ≦ 1) constituting the second semiconductor layer. Preferably satisfies y <1.2x ² + 1.8x + 0.15.

  In this way, the polarization of the second semiconductor layer, which is an electron supply layer, can be controlled to an appropriate magnitude, so that normally-off operation can be reliably realized.

In the field effect transistor of the present invention, the energy difference at the conduction band edge between the third semiconductor layer and the second semiconductor layer is In _x Al _y Ga _1-xy N (provided that the second semiconductor layer is formed) , 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 <x + y ≦ 1) and Al _u Ga _1-u N (where 0 <u ≦ 1) having a composition capable of generating carriers of the same concentration; Than the energy difference at the conduction band edge with In _s Al _t Ga _1-st N (where 0 ≦ s ≦ 1, 0 ≦ t ≦ 1, 0 ≦ s + t <1) constituting the third semiconductor layer Small is preferable.

  In this way, the polarization of the second semiconductor layer, which is an electron supply layer, can be controlled to an appropriate magnitude, so that a normally-off type operation can be realized, and carriers are transferred from the third semiconductor layer to the channel. Since the height of the energy barrier that hinders the reduction can be reduced, the parasitic resistance can be surely reduced.

  According to the field effect transistor of the present invention, the polarization of the electron supply layer (second semiconductor layer) can be controlled to an appropriate size, so that normally-off operation can be realized and parasitic resistance can be reduced. Become.

It is sectional drawing which shows the field effect transistor which concerns on one Embodiment of this invention. It is a graph which shows the relationship between the threshold voltage of a field effect transistor, and carrier concentration. It is a graph which shows the relationship between In composition of an InAlGaN layer, Al composition, and carrier concentration. It is a graph which shows the relationship between a threshold voltage, In composition, and Al composition. It is a graph which shows the relationship of In composition and Al composition which can implement | achieve normally-off operation. It is a graph which shows the energy band of the conduction band edge in the cross-sectional direction of the field effect transistor which concerns on the 1st Embodiment of this invention. (A)-(e) is sectional drawing of the order of a process which shows the manufacturing method of the field effect transistor which concerns on one Embodiment of this invention. It is a graph which shows the drain current-voltage characteristic of the field effect transistor which concerns on one Embodiment of this invention. It is sectional drawing which shows the field effect transistor which concerns on a prior art example.

(One embodiment)
An embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 1, on the main surface of a substrate 1 made of sapphire, a buffer layer 2 made of undoped GaN, undoped In _x Al _y Ga _1-xy N (however, 0 ≦ x ≦ 1, 0 ≦ An electron supply layer 3 composed of y ≦ 1, 0 <x + y ≦ 1) and a cap layer 4 composed of n-type GaN doped with a high concentration of impurities are sequentially formed by epitaxial growth.

Here, the compositions x and y of the electron supply layer 3 satisfy the relationship y <1.2x ² + 1.8x + 0.15. The n-type cap layer 4 is not limited to GaN, and is a semiconductor layer having a composition different from that of the electron supply layer 3, that is, In _s Al _t Ga _1-st N (where 0 ≦ s ≦ 1, 0 ≦ t ≦ 1, 0 ≦ s + t ≦ 1) can be used.

  The cap layer 4 is formed with a recess that exposes the electron supply layer 3 thereunder, and a gate electrode 6 made of, for example, nickel (Ni) / gold (Au) is nitrided on the exposed electron supply layer 3. It is formed with an insulating film 8 made of silicon (SiN) interposed. Although silicon nitride is used for the insulating film 8 here, silicon oxide, aluminum nitride, aluminum oxide, hafnium oxide, niobium oxide, gallium oxide, magnesium oxide, scandium oxide, tantalum oxide, or the like is used instead of silicon nitride. be able to. In addition, a source electrode 5 and a drain electrode 7 made of titanium (Ti) / aluminum (Al) are respectively formed in regions on both sides of the recess on the cap layer 4.

  By applying a voltage having an appropriate value to the gate electrode 6, two-dimensional electron gas is generated above the buffer layer 2, so that the upper portion of the buffer layer 2 functions as a channel layer of the field effect transistor.

  By the way, if the cap layer 4 doped with a high concentration of n-type impurities and the gate electrode 6 are in contact with each other, a good Schottky characteristic cannot be obtained, and a leakage current increases, thereby deteriorating device characteristics. Occurs. For this reason, conventionally, it has been difficult to form the cap layer 4 and the gate electrode 6 close to each other. However, in this embodiment, since the gate electrode 6 is formed so as to be in contact with the cap layer 4 with the insulating film 8 interposed therebetween, leakage current from the gate electrode 6 to the cap layer 4 is suppressed. . Thus, in this embodiment, since the cap layer 4 can be formed close to the gate electrode 6, it is possible to greatly reduce the parasitic resistance.

_{Here, In x Al y Ga 1-} x-y N ( where, 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 <x + y ≦ 1) In the composition in, Al composition and Ga constituting the electron supply layer 3 A method for achieving the normally-off of the field effect transistor according to the present embodiment by controlling each composition of the composition will be described.

Threshold voltage (V _th ) and carrier concentration of a field effect transistor having a so-called MIS (Metal-Insulator-Semiconductor) structure in which an insulating film 8 is interposed between the gate electrode 6 and the semiconductor layer (electron supply layer 3). The relationship with ( _ns ) is represented by the following formula (1).

_{V th = φ-ΔE c -} {q (e s d i + e i d s) / e s e i e 0} n s ...... (1)
In Equation (1), φ is the height of the Schottky barrier, ΔE _c is the energy difference at the conduction band edge between the semiconductor constituting the electron supply layer 3 and the semiconductor constituting the channel layer, q is an elementary charge, d _s and the film thickness of each d _i is the electron supply layer 3 and the insulating film 8, e _s and e _i is the relative dielectric constant of the semiconductor and the insulating film 8 that constitutes the electron supply layer 3, e ₀ represents the dielectric constant in vacuum, respectively ing.

FIG. 2 shows the relationship between the threshold voltage (V _th ) and the carrier concentration (n _s ). In FIG. 2, the normally-off operation of the MIS field effect transistor can be realized by controlling the carrier concentration ( _ns ) so that V _th > 0.

Next, determine the relation between the carrier concentration _{(n s)} and the In composition and the Al composition. Carriers (electrons) are generated by the difference in the magnitude of each polarization at the interface between the InAlGaN layer and the GaN layer. The relationship between the carrier concentration ( _ns ) and the polarization ( _Ptotal ) is expressed by the following formula (2) (for example, see Non-Patent Document 1).

_{n s = P total / q- (} e s e 0 / qd s) (φ-ΔE c + E f) ...... (2)
In the formula (2), E _f represents Fermi energy. The polarization (P _total ) is given by the sum of the spontaneous polarization P _sp peculiar to the material and the piezo polarization P _pe generated when the lattice is distorted due to an external force or the like. ) To (5).

_{P total = P sp + P pe} ...... (3)
P _sp = In composition × P _{sp InN} + Al composition × P _{sp AlN} + Ga composition × P _{sp GaN} (4)
P _pe = e ₃₃ d _z + e ₃₁ (d _x + d _y ) (5)
Here, P _{sp InN} , P _{sp AlN,} and P _{sp GaN} are spontaneous polarizations of InN, AlN, and GaN, respectively, e ₃₁ and e ₃₃ are piezo coefficients, and d _x and _dy are (0001) planes of the crystal lattice. The amount of displacement in the inward direction, d _z , represents the amount of displacement in the direction perpendicular to the (0001) plane of the crystal lattice. Further, the lattice constant of InAlGaN is expressed by the following formula (6).

a _InAlGaN = In composition × a _InN + Al composition × a _AlN + Ga composition × a _GaN (6)
Thus, represented by (0001) is the displacement amount in the plane direction of the plane _d x, _{d y} the following equation (7).

_{d x = d y = (a} InAlGaN -a GaN) / a GaN ...... (7)
Further, since the displacement amount in the direction perpendicular to the (0001) plane changes according to the displacement amount in the in-plane direction of the (0001) plane, it is expressed by the following equation (8).

d _z = −2 (C ₁₃ / C ₃₃ ) d _x (8)
Here, C ₁₃ and C ₃₃ represent the elastic constants of InAlGaN.

By substituting Equations (7) and (8) into Equations (3) to (5), the relationship between polarization, In composition, and Al composition is derived. Here, using Equation (6), if a _InAlGaN and a _GaN are equal to each other (a _InAlGaN = a _GaN ), the lattice constants of InAlGaN and GaN are equal, that is, a lattice matching condition is obtained. Al composition = 4.66 × In composition.

FIG. 3 shows the relationship between the carrier concentration ( _ns ) obtained using the above equations (2) to (8), the In composition, and the Al composition. Further, FIG. 4 shows the relationship between the threshold voltage (V _th ), the In composition, and the Al composition obtained by substituting the carrier concentration (n _s ) obtained by the expression (2) into the expression (1). In FIG. 4, a normally-off operation can be realized by setting the In composition and the Al composition so that the threshold voltage value is positive (V _th > 0).

Next, in order to use InAlGaN as the electron supply layer 3, the band gap is required to be larger than that of GaN used for the buffer layer 2. The band gap E _{g InAlGaN} of _InAlGaN is represented by the following formula (9).

E _{g InAlGaN} = In composition × E _{g InN} + Al composition × E _{g AlN} + Ga composition × E _{g GaN} −c × (In composition + Al composition) × (1-In composition−Al composition) (9)
Here, E _{g InN} , E _{g AlN,} and E _{g GaN} indicate band gaps of InN, AlN, and GaN, respectively. Further, c is a bowing parameter, which is about 2.5 in InAlGaN. Here, the following formula (10) is obtained from the condition of E _{g InAlGaN} > E _{g GaN} .

Al composition> {√ (5410 × In composition + 9) −50 × In composition−3} / 50 (10)
FIG. 5 shows the relationship between the In composition and the Al composition that can realize a normally-off operation that satisfies the above conditions. From FIG. 5, the lattice matching condition (Al composition = 4.66 × In composition) disclosed in Patent Document 1 does not necessarily become a boundary between normally-off and normally-on, and is expressed by the following formula (11).
Al composition <1.2 × (In composition) ² + 1.8 × In composition + 0.15 (11)
It can be seen that the normally-off operation can be surely realized for the first time by setting the Al composition to satisfy the above condition.

  The inventors of the present application have found that InAlGaN has a higher electron affinity than AlGaN generally used for the electron supply layer, based on various studies conducted so far. As shown in FIG. 6, this means that the potential barrier that hinders carrier movement at the interface with GaN is lowered. For this reason, by using InAlGaN for the electron supply layer 3, carriers can easily move from the cap layer 4 to the channel existing above the buffer layer 2, so that the parasitic resistance can be reduced.

  Hereinafter, a method of manufacturing the field effect transistor according to the present embodiment configured as described above will be described with reference to FIGS. 7A to 7E.

First, as shown in FIG. 7A, a substrate 1 made of sapphire whose principal surface has a (0001) plane by, for example, a metal organic chemical vapor deposition (MOCVD) method. A buffer layer 2 made of undoped GaN with a thickness of about 2 μm, an electron supply layer 3 made of undoped InAlGaN with a thickness of about 15 nm, and a cap layer 4 made of n-type GaN with a thickness of about 50 nm on the main surface of Epitaxially grows sequentially. The cap layer 4 is doped with silicon (Si) using silane (SiH ₄ ) gas, and the impurity concentration is about 1 × 10 ¹⁹ cm ⁻³ . The In composition and Al composition in the electron supply layer 3 are 0.04 and 0.20, respectively. These In composition and Al composition of the electron supply layer 3 are set so as to satisfy the above formula (11).

Next, a first resist pattern (not shown) having a stripe-shaped opening for forming a gate electrode is formed on the cap layer 4 by lithography. Here, the stripe-shaped opening width is about 1 μm. Subsequently, by using the formed first resist pattern as a mask, the cap layer 4 is etched by, for example, an inductively coupled plasma (ICP) etching method using chlorine (Cl ₂ ) gas. 4 is formed with a recess (opening) 4a exposing the electron supply layer 3 therebelow. Subsequently, by removing the first resist pattern, the configuration of FIG. 7B is obtained.

Next, a resist film is formed on the cap layer 4 including the recess 4a by lithography and etching, and then the resist film thus formed is spaced on both sides of the recess 4a and from the recess 4a. An opening is formed in the ohmic electrode formation region, which is a region, and a second resist pattern (not shown) is formed. Subsequently, a Ti film and an Al film are sequentially stacked on the second resist pattern having the opening by, for example, an electron beam evaporation method. Subsequently, as shown in FIG. 7C, a source electrode 5 and a drain electrode 7 made of Ti / Al are formed by a so-called lift-off method by removing the second resist pattern. Thereafter, in order to reduce the contact resistance, the source electrode 5 and the drain electrode 7 are heat-treated in a nitrogen (N ₂ ) atmosphere at 600 ° C., for example.

  Next, as shown in FIG. 7D, after the source electrode 5 and the drain electrode 7 are masked with a resist film, for example, by a plasma-assisted chemical vapor deposition (PCVD) method, An insulating film 8 made of silicon nitride (SiN) having a thickness of about 2 nm is deposited so as to cover the upper surface of the cap layer 4 including the bottom surface and wall surface of the recess 4a.

  Next, as shown in FIG. 7E, the Ni / Au laminated film, which is a Schottky electrode, is filled so as to fill the recess 4a with the insulating film 8 interposed, for example, by an electron beam evaporation method and a lift-off method. A gate electrode 6 is formed.

  Through the above steps, the field effect transistor according to the present embodiment shown in FIG. 1 can be manufactured.

FIG. 8 shows the drain current (I _DS ) -voltage (V _DS ) characteristics of the field effect transistor according to this embodiment. It can be seen that when the gate voltage (V _G ) is 0 V, no drain current flows and a normally-off operation can be realized.

  As described above, the field effect transistor manufacturing method according to the present embodiment makes it possible to realize a field effect transistor having a normally-off operation and a low parasitic resistance.

  The field effect transistor according to the present invention can realize a normally-off type operation and reduce parasitic resistance, and is useful for a field effect transistor applicable to a power transistor made of a group III nitride semiconductor.

1 Substrate 2 Buffer layer 3 Electron supply layer 4 Cap layer 4a Recess (opening)
5 Source electrode 6 Gate electrode 7 Drain electrode 8 Insulating film

Claims (5)

A first semiconductor layer made of GaN formed on a substrate;
Formed on the first semiconductor _{layer, In x Al y Ga 1-} x-y N ( where, 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 <x + y ≦ 1) consisting essentially of a second A semiconductor layer;
Formed on the second semiconductor layer, the second, high concentration n-type impurity having a composition different from the semiconductor layer is _{added, In s Al t Ga 1-} s-t N ( where , 0 ≦ s ≦ 1, 0 ≦ t ≦ 1, 0 ≦ s + t ≦ 1)
An opening is formed in the third semiconductor layer,
A source electrode and a drain electrode are formed in regions on both sides of the opening in the third semiconductor layer,
A field effect transistor, wherein a gate electrode is formed in the opening of the third semiconductor layer with an insulating film interposed.   2. The field effect transistor according to claim 1, wherein the gate electrode is formed so as to be in contact with a wall surface of the opening with the insulating film interposed therebetween. The composition of In _x Al _y Ga _1-xy N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 <x + y ≦ 1) constituting the second semiconductor layer is
y <1.2x ² + 1.8x + 0.15
The field effect transistor according to claim 1, wherein: The energy difference at the conduction band edge between the third semiconductor layer and the second semiconductor layer is the In _x Al _y Ga _1-xy N (where 0 ≦ x ≦ Al _u Ga _1-u N (where 0 <u ≦ 1) having a composition capable of generating carriers with the same concentration as 1, 0 ≦ y ≦ 1, 0 <x + y ≦ 1), and the third semiconductor It is smaller than the energy difference of the conduction band edge with In _s Al _t Ga _1-st N (where 0 ≦ s ≦ 1, 0 ≦ t ≦ 1, 0 ≦ s + t <1) constituting the layer. The field effect transistor according to any one of claims 1 to 3.   The field effect transistor according to claim 1, wherein the field effect transistor acts as an enhancement type.

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