CN106449406A - Vertical-structure GaN-based enhancement mode field effect transistor and manufacturing method therefor - Google Patents

Vertical-structure GaN-based enhancement mode field effect transistor and manufacturing method therefor Download PDF

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CN106449406A
CN106449406A CN201610366645.6A CN201610366645A CN106449406A CN 106449406 A CN106449406 A CN 106449406A CN 201610366645 A CN201610366645 A CN 201610366645A CN 106449406 A CN106449406 A CN 106449406A
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layer
gan
algan
enhancement mode
effect transistor
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CN106449406B (en
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文于华
刘阳
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Hunan Institute of Science and Technology
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate

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Abstract

The invention discloses a vertical-structure GaN-based enhancement mode field effect transistor and a manufacturing method therefor. The device comprises a substrate layer (1), a buffer layer (2), a non-intentionally-doped GaN (i-GaN) epitaxial layer (3), an n type AlGaN epitaxial layer (4), an n type AlN conductive layer (5), an n type AlN oxide isolation layer (6), an i-GaN regrowth layer (7), an AlGaN regrowth layer (8), a gate electrode oxide layer (9), a source electrode (10) arranged on the (8), a drain electrode (11) arranged on the (4), and a gate electrode (12) arranged on the (9). When the device is in use, the drain electrode current, by passing through the non-oxidized n type AlN conductive layer, flows to the source electrode to form the vertically and conductively structured enhancement mode device. The enhancement mode field effect transistor has the advantages of high breakdown voltage, high output current density, low leakage current and the like, and is suitable for the application in the field of the high-power electric power and electronics.

Description

A kind of vertical stratification GaN base enhancement mode field effect transistor and its manufacture method
Technical field
The present invention relates to field of semiconductor devices, more particularly, to a kind of vertical stratification GaN base enhancement mode field effect transistor And its manufacture method.
Background technology
GaN material as the representative of third generation semiconductor material with wide forbidden band, with first generation Ge, Si semi-conducting material, second Compare for GaAs, InP semi-conducting material, have energy gap (E g ) big, electronics saturation drift velocity (v sat ) high, mobility (μ) High, thermal conductivity (k) big, critical electric field (E c ) high, dielectric constant (ε) less the features such as, be therefore very suitable for making high temperature resistant, High pressure resistant, high-power, low-loss, superintegrated power electronic devices.
For electric power field-effect transistor, the threshold voltage of device is typically required to be more than 3V, as enhancement device, to protect " fail safe " of card circuit.Additionally, the use of enhancement device effectively can simplify circuit structure, thus reduce energy damaging Consumption and reduction noise." threshold voltage " of how realizing " enhancement mode " and improving device is always the focus of people's research, and And have been achieved for larger progress in recent years.
Chen Jing of Hong Kong University of Science and Thchnology et al. is in F-On the basis of ion injection method, equally adopt the deposit of ALD method Al2O3As gate dielectric layer, the threshold voltage of enhancement mode MISHFET produced is 5.1V, and maximum current density reaches 500mA/mm, maximum transconductance is 100mS/mm（Bibliography：Chang C T, Hsu T H, Chang E Y, Chen Y C. Trinh H D and Chen K J. Normally-off operation AlGaN/GaN MOS-HEMT with high threshold voltage. Electron. Lett., 2010, 46(18):1280-1282）.
Sugiyama of Japanese well-known city university et al., on the basis of P-GaN/AlGaN/GaN heterojunction structure, using nitrogen SiClx, as MIS gate dielectric material, forms compound grid structure, finds that the threshold voltage of normally-off device is big from+1V to+8V Amplitude can adjust (bibliography：T. Sugiyama*, D. Iida, M. Iwaya, S. Kamiyama, H. Amano, and I. Akasaki. Threshold voltage control using SiNxin normally off AlGaN/ GaN HFET with p-GaN gate.Phys. Status Solidi C 7, No. 7–8,1980–1982 (2010) ).
The above-mentioned AlGaN/GaN field-effect transistor being transverse conductance structure, compares in the potential near gate edge Concentrate, electric field occurs peak value, and therefore device is susceptible to herein puncture.Increase gate-source distance permissible within the specific limits Improve breakdown voltage, but there is saturated phenomenon, also increase conducting resistance simultaneously.Using metal and grid or source, drain electrode phase Even, grid field plate or source, leakage field plate can be formed.Electric Field Distribution near electrode can be changed by field plate, thus improving device The voltage endurance capability of part.
During using longitudinal conductive structure, the probability that device surface punctures substantially reduces, and breakdown voltage can be greatly improved, But the research of correlation report is less.2009, MAT was on the basis of source, the double field plate of grid, real using through hole technology Existing vertical conduction, have developed the device that breakdown voltage has reached 10400V.（Bibliography：Manabu Y, Yasuhiro U , Tetsuzo U , et al. Recent advances in GaN transistors for future emerging applications. Phys Stat Sol(a) , 2009 , 206(6) : 1221-1227）.
Content of the invention
It is an object of the invention to provide a kind of device architecture and process is simple, breakdown voltage are high, output current density is big, Little vertical stratification GaN base enhancement mode field effect transistor of leakage current and preparation method thereof.
For achieving the above object, the technical scheme is that：A kind of vertical stratification GaN base enhancement mode field effect transistor And preparation method thereof, comprise the following steps：
A）Successively in Grown cushion, i-GaN epitaxial layer, n-AlGaN layer, n-AlN layer；
B）One layer of medium is deposited on n-AlN layer and shelters film, photoetching simultaneously shelters film, then to not by caustic solution removal part Masking regional is selectively oxidized, and forms n-AlN oxide layer, then removes remaining media and shelters film；
C）On n-AlN layer and its oxide layer, secondary epitaxy growth i-GaN layer and AlGaN layer, form AlGaN/GaN hetero-junctions；
D）AlGaN/GaN hetero-junctions above N-shaped AlN conductive layer is carried out with plasma etching, etching depth enters i-GaN regeneration Long layer（I.e. i-GaN secondary epitaxy grown layer）, form groove structure；
E）In AlGaN re-growth layer（I.e. AlGaN secondary epitaxy grown layer）Make oxide layer with groove structure region；
F）Photoetching drain region figure, then selective dry etching semiconductor is to n-AlGaN layer;
G）Photoetching source electrode and drain region figure, and source region oxide layer is removed by wet etching, then pass through electron beam Evaporated metal makes source electrode and drain electrode, and alloy forms Ohmic contact；
H）After photoetched grid regional graphics, evaporation metal forms grid again.
In step C, on n-AlN layer and its oxide layer, the material of secondary epitaxy growth can be the GaN base list containing i-GaN layer Knot or many junction-type heterojunction or the homojunction that to be layer containing i-GaN constituted with N-shaped heavy doping GaN layer.
In step G, source electrode and drain electrode are formed by evaporation, their materials be Ti/Al/Ni/Au, Ti/Al/Pt/Au or Ti/Al/Mo/Au.
In step H, described gate metal is Ni/Au, Pt/Au or Pd/Au.
Source electrode due to device is located on the AlGaN/GaN heterojunction structure of secondary epitaxy growth, and drains positioned at the most nascent On long n-AlGaN/GaN heterojunction structure, when applying forward bias voltage in grid, below grid, n-AlN layer carries for communication For conducting charge, drain current must flow to source electrode through unoxidized N-shaped AlN conductive layer, thus forming the enhancing of vertical conduction Type device.
This device has following characteristic and innovation：
1）The formation of n-AlN oxide, can play modulating action to gate electric field, and makes conducting channel further from device surface, Electric current vertical conducting is it is contemplated that the voltage endurance capability of device may be increased substantially.Meanwhile, the presence of n-AlN oxide is likely to carry 2DEG concentration in high heterojunction structure below, thus the high-rate performance of boost device.
2）2DEG below area of grid is completely eliminated by dry etching, so device has higher threshold in theory Threshold voltage.Meanwhile, threshold voltage is controlled by adjusting etching depth.
3）Grid can adopt circular configuration, source electrode and drain electrode can adopt loop configuration, so large area interconnection can be formed Source, drain electrode, thus the output current of unit component is greatly improved, and the encapsulation of convenient device.
4）The use of no mask secondary epitaxy growing technology, than the selection region epitaxial growth having medium mask, in material In the raising of material quality, there is obvious advantage.
Brief description
Fig. 1（a）-（h）Device process flow figure for the embodiment of the present invention 1；
Fig. 2 is the device architecture schematic diagram of the embodiment of the present invention 2.
Specific embodiment
Below in conjunction with accompanying drawing, the present invention is described in detail.
Embodiment 1
Fig. 1（h）Device architecture schematic diagram for embodiment 1.Its structure includes substrate layer（1）, cushion（2）, unintentional doping GaN（i-GaN）Epitaxial layer（3）, N-shaped AlGaN epitaxial layer（4）, N-shaped AlN conductive layer（5）With N-shaped AlN oxidization isolation layer（6）、i- GaN re-growth layer（7）, AlGaN re-growth layer（8）, grid oxic horizon（9）, be arranged at（8）On source electrode（10）, be arranged at（4） On drain electrode（11）, be arranged at（9）On grid（12）.
The manufacturing process flow of above-mentioned vertical stratification GaN base enhancement mode field effect transistor is as follows：
A）As Fig. 1（a）Shown, using metal-organic chemical vapor deposition equipment（MOCVD）Method, successively in substrate（1）Upper growth Cushion（2）, i-GaN epitaxial layer（3）, n-AlGaN layer（4）, n-AlN layer（5）, epitaxial growth temperature is at 1050 DEG C to 1100 DEG C Between, substrate（1）For one of sapphire, silicon, carborundum or gallium nitride, cushion（2）For AlN or low-temperature gan layer；
B）As Fig. 1（b）Shown, in n-AlN layer（5）One layer of medium of upper deposit shelters film, shelters film and can be selected for SiN or SiO2, light Carve and film is sheltered by wet etching method removal part, then unmasked region is selectively oxidized, form oxide layer （6）, more completely remove remaining media shelter film；
C）As Fig. 1（c）Shown, in n-AlN layer（5）And its oxide layer（6）Upper secondary epitaxy grows i-GaN layer（7）With AlGaN layer （8）, form AlGaN/GaN hetero-junctions；
D）As Fig. 1（d）Shown, to N-shaped AlN conductive layer（5）The AlGaN/GaN hetero-junctions of top carries out ICP plasma etching, carves Erosion depth enters i-GaN re-growth layer（7）, form groove structure；
E）As Fig. 1（e）Shown, in AlGaN re-growth layer（7）Pass through P ECVD or ald side with groove structure region Legal system makees oxide layer（8）；
F）As Fig. 1（f）Shown, photoetching drain area electrode figure, then selective plasma dry etching semiconductor is to n- AlGaN layer（4）;
G）As Fig. 1（g）Shown, photoetching source electrode and drain area electrode figure, and source region is removed by wet etching aoxidize Layer, then makes source electrode by electron beam evaporation metal（10）With drain electrode（11）, and alloy forms Ohmic contact；
H）As Fig. 1（h）Shown, after photoetched grid regional graphics, evaporation metal forms grid again（12）, complete embodiment 1 Element manufacturing.
Embodiment 2
If Fig. 2 is the device architecture schematic diagram of embodiment 2.It is similar with the device architecture of embodiment 1, differs only in manufacture work In skill process step C, in n-AlN layer（5）And its oxide layer（6）Upper secondary epitaxy grown containing i-GaN layer（7）With n+-GaN Layer（8）The homojunction constituting.
Above vertical stratification GaN base enhancement mode field effect transistor provided by the present invention and its manufacture method are carried out It is discussed in detail, for one of ordinary skill in the art, according to the thought of the embodiment of the present invention, in specific embodiment and application All will change in scope, in sum, this specification content should not be construed as limitation of the present invention.

Claims (4)

1. a kind of manufacture method of vertical stratification GaN base enhancement mode field effect transistor, comprises the following steps：
A）Successively in substrate（1）Upper grown buffer layer（2）, i-GaN epitaxial layer（3）, n-AlGaN layer（4）, n-AlN layer（5）；
B）In n-AlN layer（5）One layer of medium of upper deposit shelters film, and photoetching simultaneously shelters film, then by caustic solution removal part Unmasked region is selectively oxidized, forms oxide layer（6）, then remove remaining media and shelter film；
C）In n-AlN layer（5）And its oxide layer（6）Upper secondary epitaxy grows i-GaN layer（7）With AlGaN layer（8）, formed AlGaN/GaN hetero-junctions；
D）To N-shaped AlN conductive layer（5）The AlGaN/GaN hetero-junctions of top carries out plasma etching, and etching depth enters i-GaN Re-growth layer（7）, form groove structure；
E）In AlGaN re-growth layer（7）Make oxide layer with groove structure region（8）；
F）Photoetching drain region figure, then selective etch semiconductor is to n-AlGaN layer（4）;
G）Photoetching source electrode and drain region figure, and source region oxide layer is removed by wet etching, then pass through electron beam Evaporated metal makes source electrode（10）With drain electrode（11）, and alloy forms Ohmic contact；
H）After photoetched grid regional graphics, evaporation metal forms grid again（12）.
2. the preparation method of vertical stratification GaN base enhancement mode field effect transistor according to claim 1, its feature exists In：In step C, on n-AlN layer and its oxide layer, the material of secondary epitaxy growth is the GaN base unijunction or many containing i-GaN layer Junction-type heterojunction or the homojunction that to be layer containing i-GaN constituted with N-shaped heavy doping GaN layer.
3. the preparation method of vertical stratification GaN base enhancement mode field effect transistor according to claim 1, its feature exists In：In step G, source electrode is formed by evaporation（10）With drain electrode（11）, their materials are Ti/Al/Ni/Au, Ti/Al/Pt/Au Or Ti/Al/Mo/Au.
4. the preparation method of vertical stratification GaN base enhancement mode field effect transistor according to claim 1, its feature exists In：In step H, described grid（12）Metal is Ni/Au, Pt/Au or Pd/Au.
CN201610366645.6A 2016-05-30 2016-05-30 GaN-based enhanced field effect transistor with vertical structure and manufacturing method thereof Expired - Fee Related CN106449406B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111081764A (en) * 2019-12-30 2020-04-28 深圳第三代半导体研究院 Transistor with embedded source and drain and preparation method thereof
CN111697964A (en) * 2020-06-28 2020-09-22 南京大学 Unit circuit and multifunctional logic circuit based on adjustable homojunction field effect device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100012977A1 (en) * 2008-07-15 2010-01-21 Interuniversitair Microelektronica Centrum Vzw (Imec) Semiconductor device
CN102197468A (en) * 2008-10-29 2011-09-21 富士通株式会社 Compound semiconductor device and method for manufacturing the same
CN102386213A (en) * 2010-09-02 2012-03-21 富士通株式会社 Semiconductor device, method of manufacturing the same, and power supply apparatus
CN102810564A (en) * 2012-06-12 2012-12-05 程凯 Radio frequency device and manufacturing method thereof
US20130077352A1 (en) * 2010-04-22 2013-03-28 Fujitsu Limited Semiconductor device and method of manufacturing the same, and power supply apparatus
CN103367419A (en) * 2012-03-28 2013-10-23 富士通株式会社 Compound semiconductor device and method of manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100012977A1 (en) * 2008-07-15 2010-01-21 Interuniversitair Microelektronica Centrum Vzw (Imec) Semiconductor device
CN102197468A (en) * 2008-10-29 2011-09-21 富士通株式会社 Compound semiconductor device and method for manufacturing the same
US20130077352A1 (en) * 2010-04-22 2013-03-28 Fujitsu Limited Semiconductor device and method of manufacturing the same, and power supply apparatus
CN102386213A (en) * 2010-09-02 2012-03-21 富士通株式会社 Semiconductor device, method of manufacturing the same, and power supply apparatus
CN103367419A (en) * 2012-03-28 2013-10-23 富士通株式会社 Compound semiconductor device and method of manufacturing the same
CN102810564A (en) * 2012-06-12 2012-12-05 程凯 Radio frequency device and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111081764A (en) * 2019-12-30 2020-04-28 深圳第三代半导体研究院 Transistor with embedded source and drain and preparation method thereof
CN111697964A (en) * 2020-06-28 2020-09-22 南京大学 Unit circuit and multifunctional logic circuit based on adjustable homojunction field effect device
CN111697964B (en) * 2020-06-28 2021-07-09 南京大学 Unit circuit and multifunctional logic circuit based on adjustable homojunction field effect device

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