KR101334164B1 - High electron mobility transistors device and method of manufacturing the same - Google Patents

Abstract

The present invention relates to a high electron mobility transistor device of a normally-off property and a manufacturing method thereof, capable of depleting a 2DEG layer by inserting a capping layer with a self-aligned shape on the lower side of a gate electrode without etching damage when an AlGaN/GaN heterogeneous junction high electron mobility transistor (HEMT) device is manufactured.

Description

High Electron Mobility Transistors device and method of manufacturing the same

The present invention relates to a high-electron mobility transistor device and a method of manufacturing the same, and more particularly, to a high-electron mobility transistor device capable of realizing a normally off characteristic by depleting a 2DEG layer locally at a lower end of a gate electrode, and a method of manufacturing the same. It relates to a manufacturing method.

Recently, the remarkable development of the electronics industry and the development of wireless information communication technology are increasing in demand from personal handheld terminals to commercial and military millimeter wave integrated devices. There is an urgent need for possible high power / high frequency devices.

In general, gallium nitride (GaN) -based materials have high band gap energy, high electron saturation rate, and excellent thermal conductivity compared to other semiconductor materials. The application range is expanding to the field which has limitation with existing semiconductor materials, such as an engine control system which requires heat resistance.

Examples of power devices using gallium nitride-based materials include MESFETs, HFETs, HEMTs, MOS-HFETs, and BJTs, among which high-electron mobility transistors (HEMTs) using GaN / AlGaN materials. Is characterized by high electron density, high breakdown voltage, wide bandgap, large conduction band offset, and high electron mobility.

The HEMT device uses a 2D Dimensional Electron Gas (2DEG) layer formed by a piezoelectric effect due to heterogeneous bonding of AlGaN and GaN materials having different lattice sizes and band gap energies. The 2DEG layer is used as a current path between the drain electrode and the source electrode, and the current flowing through the current path is controlled by a bias voltage applied to the gate electrode.

However, a typical HEMT device has a normally on characteristic. In order to turn off the normally-on HEMT element, a negative power source for bringing the gate electrode to a negative potential is required, and the electric circuit becomes expensive. In addition, since the HEMT of the normally on characteristic has a 2DEG layer, the device always maintains the normally on state where the device is always on. Therefore, voltage must be applied to the device so that the power consumption in the standby state is large. It is difficult to use.

Therefore, in the prior art, techniques for HEMT devices having a normally off characteristic have been proposed, and among them, as shown in Korean Patent Publication No. 10-2009-0029897, to secure the normally off characteristics of an HEMT device. In order to minimize the density of the 2DEG layer by the method of the HEMT device of the recess structure to remove the AlGaN layer formed on the lower surface of the gate or the fluorine plasma treatment process, such as Korea Patent Publication No. 10-2005-0087871 Ways to achieve off characteristics have been proposed.

However, as in the above-mentioned Korean Patent Publication No. 10-2009-0029897, the gate recess process technology of removing the 2DEG layer by etching the AlGaN layer at the lower end of the gate in order to obtain the normally off characteristic of the HEMT device is performed using a fine AlGaN layer. Since etching is required, there is a difficulty in etching, and there is also a problem that the surface state density is enhanced by etching damage accompanying the surface of the etched AlGaN layer.

In addition, as described in Korean Patent Laid-Open No. 10-2005-0087871, the technique of reducing the concentration of the 2DEG layer by the fluorine plasma treatment process has difficulty in controlling the concentration of the 2DEG layer due to the diffusion of ion implanted fluorine ions. As a result, problems arise in the reliability and reproducibility of the device.

Therefore, there is a need in the art for a new way to secure the normally off characteristics of HEMT devices without the above problems.

The present invention uses a gate electrode as an etch mask to form a self-aligned capping layer in a lower region of the gate electrode, thereby allowing a high-electron mobility transistor having a normally off characteristic to deplete a 2DEG layer locally. An object thereof is to provide a device and a method of manufacturing the same.

In addition, the present invention provides a high-electron mobility transistor device having a normally-off characteristic that can alleviate surface etching damage occurring on the surface of an AlGaN layer when forming a capping layer for implementing a normally-off characteristic of an HEMT device. The purpose is to provide.

The present invention relates to a substrate; A lower semiconductor layer and an upper semiconductor layer sequentially stacked on the substrate; A capping layer formed on the upper semiconductor layer; A gate electrode formed on the capping layer; And a source electrode and a drain electrode formed at both sides of the gate electrode, wherein the capping layer provides a high-electron mobility transistor device formed in a self-aligned form using the gate electrode as an etching mask.

A buffer layer is further included between the substrate and the lower semiconductor layer.

The lower semiconductor layer is formed of an i-type gallium nitride-based semiconductor layer, the upper semiconductor layer is formed of an i-type gallium nitride-based semiconductor layer containing aluminum,

Surface damage recovery region is provided on the surface of the upper semiconductor layer,

The surface damage recovery region is made of an electron beam irradiation method,

The capping layer is formed only in the lower region of the gate electrode,

The capping layer is formed of a p-type semiconductor layer,

The p-type semiconductor layer is formed of a p-type gallium nitride-based semiconductor layer,

The gate electrode is made of at least one material selected from Ni, Pt, W, Pd, Cr, Cu, Au, or a mixture containing the same.

In addition, the present invention comprises the steps of sequentially forming a lower semiconductor layer and an upper semiconductor layer on a substrate; Depositing a capping layer forming material on the upper semiconductor layer; Forming a gate electrode on the capping layer forming material; Etching the capping layer forming material using the gate electrode as an etch mask to form a self-aligned capping layer on the upper semiconductor layer; And forming a source electrode and a drain electrode in an upper view of the upper semiconductor layer on both sides of the self-aligned capping layer.

A buffer layer is further formed between the substrate and the lower semiconductor layer,

The lower semiconductor layer is formed of an i-type gallium nitride-based semiconductor layer, the upper semiconductor layer is formed of an i-type gallium nitride-based semiconductor layer containing aluminum,

The capping layer is formed only in the lower region of the gate electrode,

The capping layer is formed of a p-type semiconductor layer,

The p-type semiconductor layer is formed of a p-type gallium nitride-based semiconductor layer,

The gate electrode is formed of at least one material selected from Ni, Pt, W, Pd, Cr, Cu, Au, or a mixture containing the same,

And after the forming of the source electrode and the drain electrode, irradiating an electron beam to the entire structure in which the source electrode and the drain electrode are formed.

The electron beam irradiation is performed by applying RF power of 50 to 250 GHz and DC power of 50 to 1500 V.

The present invention inserts a self-aligned capping layer at the bottom of the gate electrode to locally deplete the 2DEG layer, so that the source-drain electrode is turned off without applying a bias voltage to the gate electrode. The electron mobility transistor has an effect that can be implemented in the normally off state.

In addition, the present invention is self-aligned using the gate electrode as an etch mask to be formed only in the lower region of the gate electrode in the process of forming a capping layer on the lower end of the gate electrode in order to obtain the normally off characteristics of the HEMT device Since the capping layer is formed, the capping layer can be simply formed without an additional complicated process, thereby simplifying the manufacturing process of the device and reducing the process cost.

In addition, according to the present invention, the surface damage recovery region is formed on the surface of the upper semiconductor layer on which the capping layer is formed by performing electron beam irradiation on the HEMT device on which the capping layer is formed, thereby forming the capping layer using the gate electrode as an etching mask. Since the surface etch damage that may occur during the etching process to minimize the effect through the surface damage recovery region, thereby avoiding problems that may be caused by the etching process for forming the capping layer The effect can be obtained.

1 shows a HEMT device in accordance with the present invention.
2A to 2E are views for explaining a method for manufacturing a HEMT device according to the present invention.

Hereinafter, exemplary embodiments of a high-electron mobility transistor (HEMT) device and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power electronic device. Preferably, the present invention relates to a HEMT device in which a GaN layer and an AlGaN layer are sequentially stacked to form a hetero-structure, and is self-aligned under a gate electrode. Provided is a normally-off HEMT device that inserts a capping layer in the form to deplete a portion of a 2DEG layer used as a channel of the device.

1 is a view showing an HEMT device according to the present invention.

Referring to FIG. 1, the HEMT device includes a buffer layer 110, a lower semiconductor layer 120, and an upper semiconductor layer 130 sequentially stacked on a substrate 100, and the gate electrode 150G as a schottky electrode. ), A source electrode 150S and a drain electrode 150D are formed as ohmic electrodes, and a capping layer having a self-aligned form using the gate electrode 150G as an etching mask in a lower region of the gate electrode 150G. (capping layer 140C) is formed.

In addition, a surface damage recovery region 160 may be further provided on the surface of the upper semiconductor layer 130, and the surface damage recovery region 160 uses RF power of 50 to 250 kW and DC power of 50 to 1500V. It is to be made by the electron beam irradiation (E-beam irradiation) method.

The lower semiconductor layer 120 may be formed of an intrinsic-type gallium nitride based semiconductor layer, and preferably, may be formed of a high resistance i-type GaN layer. The upper semiconductor layer 130 may be formed of an i-type gallium nitride-based semiconductor layer including aluminum having a different lattice constant from the lower semiconductor layer 120. Preferably, the upper semiconductor layer 130 may be formed of an i-type AlGaN layer. . If the lower semiconductor layer 120 and the upper semiconductor layer 130 have a lattice constant difference that is sufficient to generate a 2DEG layer between the lower semiconductor layer and the upper semiconductor layer, other compound semiconductors than the compound semiconductor layer illustrated above Layers or other material layers.

An interface of the upper semiconductor layer 140 in contact with the lower semiconductor layer 130 in the process of forming the lower semiconductor layer and the upper semiconductor layer according to the lattice constant difference between the lower semiconductor layer 120 and the upper semiconductor layer 130. Polarization is generated in the. The polarization field forms a 2DEG layer (not shown) having high electron mobility and high carrier concentration at the interface of the lower semiconductor layer 130. The 2DEG layer serves as a channel through which current can flow between the source electrode 150S and the drain electrode 150D.

However, since a typical HEMT device having a 2DEG layer is formed on a normally on characteristic, a voltage must always be applied in order to use the device, so that power consumption in a standby state is difficult to use as a switch. In the related art, techniques for obtaining a normally-off characteristic of a HEMT device have been proposed by removing a part of a 2DEG layer used as a channel layer.

Thus, the present invention is to form a self-aligned capping layer 140C under the gate electrode 150G to deplete the 2DEG layer to implement the normally off characteristics of the HEMT device.

Since the capping layer 140C formed in the self-aligned form is present under the gate electrode 150G and effectively increases the threshold voltage, the 2DEG layer formed on the lower region of the capping layer 140C may be completely removed or the 2DEG layer may be removed. By reducing the electron concentration of, the 2DEG layer can be locally depleted.

As such, the present invention makes the 2DEG layer, which is a channel passage through which electrons move through the capping layer 140C formed in the lower region of the gate electrode 150G, at least partially (2DEG layer region formed at the lower end of the gate electrode). It can be.

Therefore, the 2DEG layer, which serves as a channel through which the current flows between the source electrode 150S and the drain electrode 150D, is cut off under the gate electrode, so that a current cannot flow between the source electrode and the drain electrode. The source-drain electrodes are turned off in a state where no bias voltage is applied to the high-electron mobility transistor so that the high-electron mobility transistor is normally turned off.

In addition, the present invention can maintain a high concentration of 2DEG layer in the source electrode 150S and drain electrode 150D region, thereby minimizing the resistance, thereby forming a high output electronic device.

In addition, in the process of forming a capping layer on the lower end of the gate electrode in order to obtain the normally off characteristics of the HEMT device, the self-aligned by using the gate electrode as an etching mask to be formed only in the lower region of the gate electrode Since the capping layer is formed, the capping layer can be simply formed without additional complicated processes, thereby simplifying the manufacturing process of the device and shortening the process time.

In addition, the present invention is the energy transfer of the electron beam to the surface of the upper semiconductor layer 130 is formed on the surface of the upper semiconductor layer on which the capping layer of the self-aligned form is formed to enable the diffusion of the upper semiconductor layer components In addition, since the surface defect recovery region is formed by repairing or mitigating by compensating hydrogen defects existing on the surface of the upper semiconductor layer, the surface damage recovery region 160 may occur in the AlGaN layer, which is the upper semiconductor layer. It is possible to recover the surface etching damage phenomenon, thereby preventing the problem of surface state density enhancement due to the etching damage.

Typically, during the process of forming the capping layer at the lower end of the gate electrode in order to obtain a normally off characteristic of the HEMT device, dry etching is performed by an etching process on a capping layer made of a p-type GaN layer or a p-type AlGaN layer. In this case, the dry etching process may cause a problem of surface state density enhancement due to etching damage on the surface of the AlGaN layer.

However, in the present invention, the surface damage recovery region is formed on the surface of the upper semiconductor layer on which the capping layer is formed by performing electron beam irradiation on the HEMT device on which the capping layer is formed. Therefore, since the surface etching damage that may be generated in the AlGaN layer during the etching process for forming the capping layer may be minimized through the surface damage recovery region, the etching process for forming the capping layer is thereby performed. It is possible to prevent a problem that may be caused by, namely, a problem of strengthening the surface state density due to etching damage.

In addition, the capping layer 140C may be formed of a p-type semiconductor layer, preferably a p-type gallium nitride-based semiconductor layer, more preferably locally by increasing the threshold voltage of the device effectively. It may be formed of a p-type GaN layer or a p-type AlGaN layer capable of depleting the 2DEG layer.

In addition, the capping layer 140C may be formed only in the lower region of the gate electrode 150G so that the area thereof is the same or similar. If the capping layer 140C is formed to have an area larger than the area of the gate electrode, a depletion state is formed in the entire channel layer of the device, thereby causing an on-current downward phenomenon of the device. In the case where the capping layer is formed with an area that is too small than the area of the gate electrode, the depletion state of the 2DEG layer may not be obtained in a desired region, thereby making it difficult to implement the normally off characteristic of the HEMT device.

A method of manufacturing an HEMT device according to the present invention will be described in detail with reference to FIGS. 2A to 2E.

Referring to FIG. 2A, after forming a buffer layer 110 as a buffer layer for lowering interfacial stress on a substrate 100 such as Si, SiC, etc., a lower semiconductor layer 120 and an upper semiconductor layer are formed on the buffer layer 110. 130 is formed by lamination.

The lower semiconductor layer 120 and the upper semiconductor layer 130 may be formed as semiconductor layers having different polarization rates and different band gaps. Preferably, the lower semiconductor layer 120 is formed of a high resistance i-type GaN layer in the III-V compound material, and the upper semiconductor layer 130 is an i-type AlGaN, which is a gallium nitride based semiconductor material including aluminum. To form a layer. The upper semiconductor layer 130 is formed of a material having a different band gap from the lower semiconductor layer 120 to form a heterojunction. The lower semiconductor layer part is formed by heterojunction of two semiconductor materials having different band gaps. The 2DEG layer is formed on the substrate.

Subsequently, a capping layer forming material 140 is deposited on the upper semiconductor layer 130. The capping layer forming material 140 is deposited by using a p-type semiconductor material, preferably by using a p-type gallium nitride-based semiconductor material, and more preferably locally by increasing the threshold voltage of the device effectively. The p-type GaN material or p-type AlGaN material may be deposited to deplete the 2DEG layer.

Referring to FIG. 2B, after forming a photoresist mask exposing a gate formation region on the capping layer forming material 140, a gate electrode forming material is formed on the capping layer forming material including the PR mask. Deposit. As the gate electrode forming material, a material capable of Schottky contact with a semiconductor material, for example, at least one material selected from Ni, Pt, W, Pd, Cr, Cu, Au, or a mixture containing the same This can be used.

Subsequently, a gate electrode is formed on the gate forming region of the capping layer forming material by performing a lift-off process on the PR mask to remove the PR mask and the gate forming material formed on the PR mask. Form.

In the present invention, as the gate electrode is formed through the lift-off process, the gate electrode can be formed without performing a separate patterning process for the gate forming material, thereby simplifying the process. do.

On the other hand, the manufacturing process for forming the gate electrode is not limited to the lift-off process, it is also possible to perform a patterning process using a PR mask and a hard mask (Hard mask). That is, the gate electrode may be formed by forming a hard mask and a PR mask on the gate forming material and etching the gate electrode forming material using the masks.

Referring to FIG. 2C, the capping layer forming material may be etched in a self-aligned manner using the gate electrode 150G as an etching mask to form a self-aligned shape on the upper semiconductor layer 130 ( 140C).

Here, the present invention provides a self-aligned cap made of a p-type semiconductor layer capable of locally depleting the 2DEG layer by effectively increasing the threshold voltage of the device at the bottom of the gate electrode in order to obtain the normally off characteristic of the HEMT device. An ping layer was formed.

The formation of the capping layer 140C reduces the difference in lattice constant between the lower semiconductor layer 120 and the upper semiconductor layer 130, and the piezoelectric effect disappears, and the 2DEG layer is locally only in the lower region of the capping layer 140C. This depletion state causes the 2DEG layer to break due to the depletion of the local 2DEG layer, so that a current cannot flow between the source electrode and the drain electrode. As a result, the source-drain electrodes are turned off in a state in which a bias voltage is not applied to the gate electrode, thereby allowing the HEMT device to implement a normally off state.

In addition, in the process of forming the capping layer on the lower end of the gate electrode in order to obtain the normally off characteristics of the HEMT device, after forming the gate electrode on the capping layer forming material using the gate electrode as an etching mask The formation of an aligned capping layer eliminates the need for additional masking and patterning processes to etch the capping layer, thereby automatically forming and aligning the capping layer only in the lower region of the gate electrode without additional complicated processes. The capping layer can be formed simply.

By this process, the present invention can realize the off-characteristics of the HEMT device while having advantages such as simplifying the device manufacturing process and shortening the process time.

In addition, the capping layer 140C is formed only in the lower region of the gate electrode so that the area thereof is the same or similar. If the capping layer 140C is formed to have an area larger than the area of the gate electrode, a depletion state is formed in the entire channel layer of the device, thereby causing an on-current downward phenomenon of the device. If the capped layer is formed to have an area too small than that of the gate electrode, the depletion state of the 2DEG layer may not be obtained in a desired region, which may make it difficult to implement the normally off characteristic of the HEMT device.

Referring to FIG. 2D, a source electrode 150S and a drain electrode 150D, which are ohmic electrodes spaced at given intervals, are formed on the upper semiconductor layer 130 formed by stacking the capping layer 140C and the gate electrode 150G. To form a HEMT device according to the present invention. The source electrode 150S and the drain electrode 150D may be formed in a single layer or a stacked structure using any one or more metals selected from Ta / Ti / Al / Ni / Au.

Referring to FIG. 2E, E-beam irradiation is performed on the entire structure in which the source electrode 150S and the drain electrode 150D are formed. The electron beam irradiation is preferably performed by applying an RF power of 50 to 250 GHz and a DC power of 50 to 1500 V. The RF power adjusts the density of the electron beam, and the DC power performs a function of accelerating the electron beam. It is possible to use both the RF power and the DC power or to selectively use either of them. At this time, hydrogen defects existing on the surface of the AlGaN layer, which is the upper semiconductor layer, are reduced by the electron beam irradiation, thereby forming a surface damage recovery region 160 on the surface of the upper semiconductor layer 130.

That is, the surface damage of the upper semiconductor layer 130 generated in the etching process is irradiated with a low energy electron beam, the energy of the electron beam is delivered to the surface of the upper semiconductor layer 130, the diffusion of the components of the upper semiconductor layer It becomes possible and also repairs or mitigates by compensating for the electronic defects present on the surface of the upper semiconductor layer to create the surface damage recovery region 160.

According to an exemplary embodiment of the present invention, an electron beam irradiation using RF power and DC power is performed on an HEMT device on which the capping layer 140C is formed, and thus a surface damage recovery region may be formed on the surface of the upper semiconductor layer 130 on which the capping layer 140C is formed. By forming the 160, the surface etching damage that may occur on the surface of the AlGaN layer, which is the upper semiconductor layer 130, during the etching process for forming the capping layer 140C using the gate electrode 150G as an etching mask. Since it is recovered and removed through the surface damage recovery region 160, it is possible to prevent problems that may be caused by an etching process for forming the capping layer 140C, thereby optical and electrical characteristics of the HEMT device. By improving the stability and efficiency of the device can be increased.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but many variations and modifications may be made without departing from the spirit and scope of the invention. The scope of which is set forth in the appended claims.

100: substrate 110: buffer layer
120: lower semiconductor layer 130: upper semiconductor layer
140C: capping layer 140: capping layer forming material
150S: source electrode 150D: drain electrode
150G: gate electrode
160: surface damage recovery area

Claims (18)

Board;
A lower semiconductor layer and an upper semiconductor layer sequentially stacked on the substrate;
A capping layer formed on the upper semiconductor layer;
A gate electrode formed on the capping layer; And
And a source electrode and a drain electrode formed at both sides of the gate electrode.
The capping layer is formed in a self-aligned form using the gate electrode as an etching mask,
And a surface damage recovery region formed on the surface of the upper semiconductor layer by an electron beam irradiation method.
The method of claim 1,
The high electron mobility transistor device further comprises a buffer layer between the substrate and the lower semiconductor layer.
The method of claim 1,
And the lower semiconductor layer is formed of an i-type gallium nitride based semiconductor layer, and the upper semiconductor layer is formed of an i-type gallium nitride based semiconductor layer including aluminum.
delete delete The method of claim 1,
And the capping layer is formed only in a lower region of the gate electrode.
The method according to any one of claims 1 to 3 or 6,
The capping layer is a high-electron mobility transistor device formed of a p-type semiconductor layer.
The method of claim 7, wherein
The p-type semiconductor layer is a high-electron mobility transistor device formed of a p-type gallium nitride-based semiconductor layer.
The method of claim 1,
The gate electrode is a high-electron mobility transistor device consisting of at least one material selected from Ni, Pt, W, Pd, Cr, Cu, Au or a mixture containing the same.
Sequentially forming a lower semiconductor layer and an upper semiconductor layer on the substrate;
Depositing a capping layer forming material on the upper semiconductor layer;
Forming a gate electrode on the capping layer forming material;
Etching the capping layer forming material using the gate electrode as an etch mask to form a self-aligned capping layer on the upper semiconductor layer; And
Forming a source electrode and a drain electrode over the upper semiconductor layer on both sides of the self-aligned capping layer; And
And irradiating an electron beam to the entire structure in which the source electrode and the drain electrode are formed.
11. The method of claim 10,
And forming a buffer layer between the substrate and the lower semiconductor layer.
11. The method of claim 10,
The lower semiconductor layer is formed of an i-type gallium nitride-based semiconductor layer, and the upper semiconductor layer is formed of an i-type gallium nitride-based semiconductor layer containing aluminum.
11. The method of claim 10,
And the capping layer is formed only in a lower region of the gate electrode.
The method according to any one of claims 10 to 13,
And the capping layer is formed of a p-type semiconductor layer.
15. The method of claim 14,
And the p-type semiconductor layer is formed of a p-type gallium nitride-based semiconductor layer.
11. The method of claim 10,
The gate electrode is formed of at least one material selected from Ni, Pt, W, Pd, Cr, Cu, Au, or a mixture comprising the same.
delete 11. The method of claim 10,
The electron beam irradiation is a method of manufacturing a high-electron mobility transistor device is performed by applying a RF power of 50 to 250 GHz and a DC power of 50 to 1500V.

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