CN117894835A - Gallium nitride semiconductor device and preparation method thereof - Google Patents
Gallium nitride semiconductor device and preparation method thereof Download PDFInfo
- Publication number
- CN117894835A CN117894835A CN202410288763.4A CN202410288763A CN117894835A CN 117894835 A CN117894835 A CN 117894835A CN 202410288763 A CN202410288763 A CN 202410288763A CN 117894835 A CN117894835 A CN 117894835A
- Authority
- CN
- China
- Prior art keywords
- layer
- barrier layer
- away
- gate
- doped iii
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 175
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 59
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 55
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 230000004888 barrier function Effects 0.000 claims abstract description 152
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 125000004429 atom Chemical group 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 27
- 125000001153 fluoro group Chemical group F* 0.000 claims description 17
- 125000004434 sulfur atom Chemical group 0.000 claims description 17
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 9
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 8
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 8
- 238000004381 surface treatment Methods 0.000 claims description 5
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 25
- 239000010410 layer Substances 0.000 description 463
- 230000001681 protective effect Effects 0.000 description 8
- 238000002161 passivation Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 229910052731 fluorine Inorganic materials 0.000 description 5
- 229910052717 sulfur Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 230000008439 repair process Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000012779 reinforcing material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a gallium nitride semiconductor device and a preparation method thereof. The gallium nitride semiconductor device includes: a substrate; a channel layer located on one side of the substrate; a barrier layer located on a side of the channel layer away from the substrate; a gate structure comprising a doped III-V semiconductor layer and a gate; the first insulating medium layer covers the side face of the grid electrode, the surface of the grid electrode far away from the doped III-V semiconductor layer and the surface of the doped III-V semiconductor layer far away from the barrier layer; the stress layer covers the surface of the barrier layer far away from the channel layer and the surface side of the first insulating medium layer far away from the grid electrode; the surface of the barrier layer remote from the channel layer is doped with electronegative atoms. The technical scheme provided by the embodiment of the invention reduces the leakage current of the grid electrode, improves the surface state of the barrier layer at the channel region, and improves the concentration of the two-dimensional electron gas in the channel region.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gallium nitride semiconductor device and a preparation method thereof.
Background
In the conventional gallium nitride semiconductor device, the protective layer covering the channel region and the gate electrode is the same film layer. The protection layer cannot meet the requirements of high concentration of two-dimensional electron gas in the channel region and reduction of leakage current at the gate.
Disclosure of Invention
The invention provides a gallium nitride semiconductor device and a preparation method thereof, which are used for reducing the leakage current of a grid electrode, improving the surface state of a barrier layer at a channel region and increasing the concentration of two-dimensional electron gas in the channel region.
According to an aspect of the present invention, there is provided a gallium nitride semiconductor device including: a substrate; a channel layer located on one side of the substrate; a barrier layer located on a side of the channel layer remote from the substrate; a gate structure comprising a doped iii-v semiconductor layer and a gate, the doped iii-v semiconductor layer being located on a surface of the barrier layer remote from the channel layer, the gate being located on a surface of the doped iii-v semiconductor layer remote from the barrier layer, a front projection of the gate on the substrate covering a portion of a front projection of the doped iii-v semiconductor layer on the substrate; a first insulating dielectric layer covering a side of the gate, a surface of the gate away from the doped iii-v semiconductor layer, and a surface of the doped iii-v semiconductor layer away from the barrier layer; a source electrode located on a surface of the barrier layer away from the channel layer; a drain electrode located on a surface of the barrier layer remote from the channel layer; a stress layer covering a surface of the barrier layer away from the channel layer and a surface side of the first insulating dielectric layer away from the gate electrode; the surface of the barrier layer far away from the channel layer is doped with electronegative atoms, wherein the positive projection of the barrier layer doped with the electronegative atoms on the substrate and the positive projection of the grid electrode on the substrate are not overlapped, and the electronegativity of the electronegative atoms is greater than or equal to that of sulfur atoms and less than or equal to that of fluorine atoms.
Optionally, a surface of the barrier layer remote from the channel layer is doped with at least one of oxygen atoms, nitrogen atoms, fluorine atoms, and sulfur atoms.
Optionally, a second insulating dielectric layer is further included, the second insulating dielectric layer covering at least a side of the doped III-V semiconductor layer.
Optionally, the first insulating dielectric layer includes silicon oxide and/or silicon nitride.
Optionally, the stress layer comprises aluminum nitride and/or aluminum oxide.
According to another aspect of the present invention, there is provided a method of manufacturing a gallium nitride semiconductor device, comprising: providing a substrate; forming a channel layer on one side of the substrate; forming a barrier layer on one side of the channel layer away from the substrate; forming a doped III-V semiconductor layer on the surface of the barrier layer away from the channel layer; forming a grid electrode on the surface of the doped III-V semiconductor layer, which is far away from the barrier layer, wherein the grid electrode is positioned on the surface of the doped III-V semiconductor layer, which is far away from the barrier layer, and the orthographic projection of the grid electrode on the substrate covers the orthographic projection of part of the doped III-V semiconductor layer on the substrate, and the doped III-V semiconductor layer and the grid electrode form a grid electrode structure; forming a first insulating medium layer on the side surface of the grid electrode, the surface of the grid electrode far away from the doped III-V semiconductor layer and the surface of the doped III-V semiconductor layer far away from the barrier layer; patterning the doped III-V semiconductor layer by taking the first insulating medium layer as a mask plate so that the doped III-V semiconductor layer and the grid form a grid structure; doping electronegative atoms on the surface of the barrier layer far away from the channel layer, wherein the positive projection of the barrier layer doped with the electronegative atoms on the substrate and the positive projection of the grid electrode on the substrate are not overlapped, and the electronegativity of the electronegative atoms is greater than or equal to that of sulfur atoms and less than or equal to that of fluorine atoms; forming a source electrode and a drain electrode on the surface of the barrier layer away from the channel layer; and forming a stress layer on the surface of the barrier layer away from the channel layer and the surface side of the first insulating medium layer away from the grid electrode.
Optionally, doping electronegative atoms at a surface of the barrier layer remote from the channel layer includes:
At least one of oxygen atoms, nitrogen atoms, fluorine atoms and sulfur atoms is doped on the surface of the barrier layer away from the channel layer through a plasma surface treatment process.
Optionally, after forming a first insulating medium layer on the side surface of the gate, the surface of the gate away from the doped iii-v semiconductor layer, and the surface of the doped iii-v semiconductor layer away from the barrier layer, the method further comprises: and forming a second insulating medium layer at least on the side surface of the doped III-V semiconductor layer.
Optionally, forming a first insulating dielectric layer on a side of the gate, a surface of the gate away from the doped iii-v semiconductor layer, and a surface of the doped iii-v semiconductor layer away from the barrier layer includes: silicon oxide and/or silicon nitride is formed on the side of the gate electrode, the surface of the gate electrode remote from the doped iii-v semiconductor layer, and the surface of the doped iii-v semiconductor layer remote from the barrier layer.
Optionally, forming a stress layer on a surface of the barrier layer away from the channel layer and a surface side of the first insulating dielectric layer away from the gate electrode includes: aluminum nitride and/or aluminum oxide is formed on the surface of the barrier layer away from the channel layer and the surface side of the first insulating medium layer away from the grid electrode.
According to the technical scheme provided by the embodiment of the invention, the first insulating medium layer covers the side face of the grid, the surface of the grid far away from the doped III-V semiconductor layer and the surface of the doped III-V semiconductor layer far away from the barrier layer, the stress layer covers the surface of the barrier layer far away from the channel layer and the surface side of the first insulating medium layer far away from the grid, the film layers covering the side face of the grid and the surface of the grid far away from the doped III-V semiconductor layer are the first insulating medium layer and the stress layer, and the number of protective film layers covering the side face of the grid and the surface of the grid far away from the doped III-V semiconductor layer is increased, so that leakage current at the grid is reduced. The surface of the barrier layer corresponding to the channel region, which is far away from the channel layer, is doped with electronegativity atoms, wherein the electronegativity of the electronegativity atoms is larger than or equal to that of sulfur atoms and smaller than or equal to that of fluorine atoms, and the electronegativity is relatively strong, so that the surface state of the barrier layer at the channel region can be improved, the concentration of two-dimensional electron gas of the channel region can be improved, and the performance of the gallium nitride semiconductor device can be further improved. Meanwhile, the first insulating medium layer is positioned between the grid electrode and the stress layer, when the potential barrier layer corresponding to the channel region is far away from the surface of the channel layer and doped with electronegative atoms, the first insulating medium layer can isolate and protect the grid electrode, and when the potential barrier layer corresponding to the channel region is far away from the surface of the channel layer and doped with electronegative atoms, the leakage current at the grid electrode can be prevented from being reduced. In summary, the technical scheme provided by the embodiment of the invention reduces the leakage current of the grid electrode, improves the surface state of the barrier layer at the channel region, and improves the concentration of two-dimensional electron gas in the channel region, thereby improving the performance of the gallium nitride semiconductor device. In addition, the stress layer can be used for increasing the stress of the device, repairing the damaged interface, improving the two-dimensional electron gas concentration and improving the performance of the device.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a method for manufacturing a gallium nitride semiconductor device according to the prior art;
Fig. 2 to 7 are schematic structural views corresponding to steps of a method for fabricating the gallium nitride semiconductor device of fig. 1;
fig. 8 is a schematic structural view of a gallium nitride semiconductor device according to an embodiment of the present invention;
Fig. 9 is a schematic structural view of another gallium nitride semiconductor device according to an embodiment of the invention;
fig. 10 is a schematic structural view of yet another gallium nitride semiconductor device according to an embodiment of the invention;
fig. 11 is a flowchart of a method for manufacturing a gallium nitride semiconductor device according to an embodiment of the invention;
FIGS. 12-17 are schematic views of the structure corresponding to the steps in FIG. 11;
fig. 18 is a flowchart of another method for manufacturing a gallium nitride semiconductor device according to an embodiment of the invention;
FIGS. 19-21 are schematic views of a structure corresponding to the steps in FIG. 18;
fig. 22-24 are schematic views of another structure corresponding to each step in fig. 18.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or means is not necessarily limited to those steps or means that are expressly listed or inherent to such process, method, article, or apparatus.
As described in the foregoing background art, the existing gallium nitride semiconductor device cannot simultaneously satisfy the requirement that the channel region requires a high concentration of two-dimensional electron gas and the requirement that the leakage current be reduced at the gate electrode. As shown in fig. 1 and fig. 2 to 7, fig. 1 is a flowchart of a method for manufacturing a gallium nitride semiconductor device provided in the prior art, and fig. 2 to 7 are schematic structural diagrams corresponding to steps of the method for manufacturing a gallium nitride semiconductor device in fig. 1, and the inventor has found through careful study that the method for manufacturing a gallium nitride semiconductor device in the prior art includes: and S100, providing a substrate, and forming a channel layer, a barrier layer, a doped III-V semiconductor layer and a grid electrode on one side of the substrate. S110, forming a mask layer, wherein the mask layer covers the grid electrode, the doped III-V semiconductor layer and the barrier layer. S120, patterning the mask layer. And S130, patterning the doped III-V semiconductor layer by using a mask layer position mask plate so that the grid covers part of the doped III-V semiconductor layer. And S140, forming a source electrode and a drain electrode on the surface of the barrier layer away from the channel layer. And S150, forming a passivation layer, wherein the passivation layer covers the grid electrode, the doped III-V semiconductor layer, the barrier layer, the side surface of the grid electrode and the side surface of the doped III-V semiconductor layer. Wherein reference numerals in fig. 2-7 are illustrated as follows: 100-substrate, 101-channel layer, 102-barrier layer, 103-doped III-V semiconductor layer, 104-gate, 105-mask layer, 106-source, 107-drain, 108-passivation layer.
As shown in fig. 7, in the conventional gallium nitride semiconductor device, the protective layer covering the channel region (the region between the gate electrode 104 and the source electrode 106 and the region between the gate electrode 104 and the drain electrode 107) and the gate electrode 104 is the same film layer, i.e., the passivation layer 108. The thicker the passivation layer 108 needs to be set, the better if the leakage current at the gate needs to be reduced; if it is desired to increase the two-dimensional electron gas concentration of the channel region, the passivation layer 108 need not be provided to be very thick. Therefore, the passivation layer 108, which is used as a protection layer for covering the channel region and the gate 104, cannot meet the requirements of high concentration of two-dimensional electron gas in the channel region and reduced leakage current at the gate 104.
Aiming at the technical problems, the embodiment of the invention provides the following technical scheme:
As shown in fig. 8, fig. 8 is a schematic structural diagram of a gallium nitride semiconductor device according to an embodiment of the invention, the gallium nitride semiconductor device includes: a substrate 200; a channel layer 201, the channel layer 201 being located at one side of the substrate 200; a barrier layer 202, the barrier layer 202 being located on a side of the channel layer 201 remote from the substrate 200; a gate structure comprising a doped iii-v semiconductor layer 203 and a gate 204, the doped iii-v semiconductor layer 203 being located on a surface of the barrier layer 202 remote from the channel layer 201, the gate 204 being located on a surface of the doped iii-v semiconductor layer 203 remote from the barrier layer 202, an orthographic projection of the gate 204 on the substrate 200 covering an orthographic projection of a portion of the doped iii-v semiconductor layer 203 on the substrate 200; the first insulating dielectric layer 205, the first insulating dielectric layer 205 covers the side surface of the gate 204, the surface of the gate 204 away from the doped iii-v semiconductor layer 203, and the surface of the doped iii-v semiconductor layer 203 away from the barrier layer 202; a source electrode 206, the source electrode 206 being located on a surface of the barrier layer 202 remote from the channel layer 201; a drain electrode 207, the drain electrode 207 being located on a surface of the barrier layer 202 remote from the channel layer 201; a stress layer 208, the stress layer 208 covering a surface of the barrier layer 202 remote from the channel layer 201 and a surface side of the first insulating dielectric layer 205 remote from the gate 204; the surface of the barrier layer 202 remote from the channel layer 201 is doped with electronegative atoms, wherein the front projection of the barrier layer 202 doped with electronegative atoms on the substrate 200 does not overlap with the front projection of the gate 204 on the substrate 200. The electronegativity of the electronegative atom is greater than or equal to the electronegativity of the sulfur atom and less than or equal to the electronegativity of the fluorine atom.
In this embodiment, when the surface of the barrier layer 202 corresponding to the channel region, which is far from the channel layer 201, is doped with electronegative atoms, the first insulating dielectric layer 205 may perform isolation protection on the gate 204, and the first insulating dielectric layer 205 may be made of a material with a relatively large dielectric constant.
According to the technical scheme provided by the embodiment of the invention, the first insulating medium layer 205 covers the side surface of the gate 204, the surface of the gate 204 far away from the doped III-V semiconductor layer 203 and the surface of the doped III-V semiconductor layer 203 far away from the barrier layer 202, the stress layer 208 covers the surface of the barrier layer 202 far away from the channel layer 201 and the surface side of the first insulating medium layer 205 far away from the gate 204, and the film layers covering the side surface of the gate 204 and the surface of the gate 204 far away from the doped III-V semiconductor layer 203 are the first insulating medium layer 205 and the stress layer 208 in sequence, so that the number of protective film layers covering the side surface of the gate 204 and the surface of the gate 204 far away from the doped III-V semiconductor layer 203 is increased, and the leakage current at the gate 204 is reduced. And the surface of the barrier layer 202, which is far away from the channel layer 201, is doped with electronegativity atoms, wherein the electronegativity of the electronegativity atoms is greater than or equal to that of sulfur atoms and less than or equal to that of fluorine atoms, and the electronegativity is relatively strong, so that the surface state of the barrier layer 202 at the channel region can be improved, the concentration of two-dimensional electron gas of the channel region can be increased, and the performance of the gallium nitride semiconductor device can be further improved. Meanwhile, the first insulating dielectric layer 205 is located between the gate 204 and the stress layer 208, and when the barrier layer 202 corresponding to the channel region is far away from the surface of the channel layer 201 and doped with electronegative atoms, the first insulating dielectric layer 205 can perform isolation protection on the gate 204, so that when the barrier layer 202 corresponding to the channel region is far away from the surface of the channel layer 201 and doped with electronegative atoms, the leakage current at the gate 204 can be prevented from being reduced. In summary, the technical solution provided by the embodiment of the present invention reduces the leakage current of the gate 204, improves the surface state of the barrier layer 202 at the channel region, and increases the concentration of the two-dimensional electron gas in the channel region, thereby improving the performance of the gallium nitride semiconductor device. In addition, the stress layer 208 can be used to increase the stress of the device, repair damaged interfaces, increase the two-dimensional electron gas concentration, and improve the device performance.
Optionally, on the basis of the above technical solution, the surface of the barrier layer 202 far from the channel layer 201 is doped with at least one of an oxygen atom, a nitrogen atom, a fluorine atom and a sulfur atom, and at least one of the oxygen atom, the nitrogen atom, the fluorine atom and the sulfur atom can improve the surface state of the barrier layer 202 at the channel region, and increase the concentration of the two-dimensional electron gas in the channel region, thereby improving the performance of the gallium nitride semiconductor device. Here, the surface of the barrier layer 202 away from the channel layer 201 was doped with electronegative atoms by a plasma surface treatment process, and the surface of the barrier layer 202 away from the channel layer 201 was modified, so that the concentration of electronegative atoms in the barrier layer 202 was negligible.
Optionally, on the basis of the above technical solutions, as shown in fig. 9 and fig. 10, fig. 9 is a schematic structural diagram of another gallium nitride semiconductor device provided according to an embodiment of the present invention, and fig. 10 is a schematic structural diagram of another gallium nitride semiconductor device provided according to an embodiment of the present invention, where the gallium nitride semiconductor device further includes a second insulating dielectric layer 209, and the second insulating dielectric layer 209 covers at least a side surface of the doped iii-v semiconductor layer 203.
Specifically, the second insulating dielectric layer 209 at least covers the side surface of the doped iii-v semiconductor layer 203, and increases the number of protective film layers covering the side surface of the doped iii-v semiconductor layer 203, thereby further reducing the leakage current at the gate 204. Meanwhile, the second insulating dielectric layer 209 and the first insulating dielectric layer 205 are both located between the gate 204 and the stress layer 208, when the surface of the barrier layer 202 corresponding to the channel region is far away from the channel layer 201 and doped with electronegative atoms, the first insulating dielectric layer 205 and the second insulating dielectric layer 209 can perform isolation protection on the gate structure, and when the surface of the barrier layer 202 corresponding to the channel region is far away from the channel layer 201 and doped with electronegative atoms, the leakage current at the gate 204 can be further prevented from being reduced. As shown in fig. 9, a second insulating dielectric layer 209 covers the sides of the doped iii-v semiconductor layer 203. As shown in fig. 10, the second insulating dielectric layer 209 covers the side surface of the doped iii-v semiconductor layer 203 and the first insulating dielectric layer 205, and further increases the number of protective film layers covering the entire gate structure, thereby further reducing the leakage current at the gate 204.
Optionally, on the basis of the above technical solution, the first insulating dielectric layer 205 includes silicon oxide and/or silicon nitride.
Specifically, the silicon oxide and/or silicon nitride may be used as the first insulating dielectric layer 205 to isolate and protect the gate 204, which has a relatively large dielectric constant for reducing the leakage current of the gate 204.
Optionally, the second insulating dielectric layer 209 includes silicon oxide and/or silicon nitride, which has a relatively high dielectric constant, so as to further isolate and protect the gate structure, and reduce the leakage current of the gate 204.
Optionally, based on the above-described aspects, stress layer 208 includes aluminum nitride and/or aluminum oxide.
Specifically, aluminum nitride and/or aluminum oxide are good stress reinforcing materials and insulating materials, and meanwhile, damaged interfaces can be repaired, the two-dimensional electron gas concentration is improved, the grid leakage is reduced, and the device performance is improved. Specifically, aluminum nitride is used as a stress layer 208 to cooperate with the first insulating dielectric layer 205 to protect the gate structure to reduce leakage current; aluminum nitride as the stress layer 208 can be used to improve the surface state of the barrier layer 202 corresponding to the channel region, so as to increase the concentration of the two-dimensional electron gas in the channel region, thereby improving the performance of the gallium nitride semiconductor device. When the gallium nitride semiconductor device further includes the second insulating dielectric layer 209, aluminum nitride is used as the stress layer 208 and the first insulating dielectric layer 205 and the second insulating dielectric layer 209 cooperate to protect the gate structure to reduce leakage current. And aluminum nitride and/or aluminum oxide are good stress enhancement materials, which can improve the two-dimensional electron gas concentration.
The embodiment of the invention also provides a preparation method of the gallium nitride semiconductor device. As shown in fig. 11, fig. 11 is a flowchart of a method for manufacturing a gallium nitride semiconductor device according to an embodiment of the invention, the method for manufacturing a gallium nitride semiconductor device including:
s200, providing a substrate.
As shown in fig. 12, the substrate 200 may be a silicon substrate.
And S210, forming a channel layer on one side of the substrate.
As shown in fig. 12, a channel layer 201 is formed on one side of a substrate 200 through an epitaxial process. The channel layer 201 includes one or more of GaN, alGaN, and InGaN, preferably GaN.
And S220, forming a barrier layer on the side of the channel layer away from the substrate.
As shown in fig. 12, a barrier layer 202 is formed on a side of the channel layer 201 remote from the substrate 200 by an epitaxial process. The barrier layer 202 may be AlGaN. The interface of the heterojunction formed by the channel layer 201 and the barrier layer 202 can provide a high-concentration two-dimensional electron gas for improving the performance of the gallium nitride semiconductor device.
S230, forming a doped III-V semiconductor layer on the surface of the barrier layer away from the channel layer.
As shown in fig. 12, a doped group iii-v semiconductor layer 203 is formed on the surface of the barrier layer 202 remote from the channel layer 201. The doped iii-v semiconductor layer 203 is used to deplete the two-dimensional electron gas on the surface of the underlying barrier layer 202, and the gallium nitride semiconductor device can be turned off at low voltages. The doped III-V semiconductor layer 203 comprises p-type doped AlN or GaN, preferably p-type doped GaN.
And S240, forming a grid electrode on the surface of the doped III-V semiconductor layer far away from the barrier layer.
As shown in fig. 12, a gate 204 is formed on the surface of the doped iii-v semiconductor layer 203 remote from the barrier layer 202, wherein the gate 204 is located on the surface of the doped iii-v semiconductor layer 203 remote from the barrier layer 202, and the orthographic projection of the gate 204 on the substrate 200 covers the orthographic projection of the partially doped iii-v semiconductor layer 203 on the substrate 200.
And S250, forming a first insulating medium layer on the side surface of the grid electrode, the surface of the grid electrode far away from the doped III-V semiconductor layer and the surface of the doped III-V semiconductor layer far away from the barrier layer.
As shown in fig. 13, a first insulating dielectric layer 205 is formed. Then, as shown in fig. 14, a first insulating medium layer 205 is formed on the side surface of the gate 204, the surface of the gate 204 away from the doped iii-v semiconductor layer 203, and the surface of the doped iii-v semiconductor layer 203 away from the barrier layer 202 by a patterning process.
The first insulating dielectric layer 205 covers the sides of the gate 204, the surface of the gate 204 remote from the doped iii-v semiconductor layer 203, and the surface of the doped iii-v semiconductor layer 203 remote from the barrier layer 202, thereby reducing leakage current at the gate 204.
And S260, patterning the doped III-V semiconductor layer by taking the first insulating medium layer as a mask plate so that the doped III-V semiconductor layer and the grid electrode form a grid electrode structure.
As shown in fig. 15, the doped iii-v semiconductor layer 203 is patterned with the first insulating dielectric layer 205 as a mask, exposing the channel region, the source and the drain corresponding to the barrier layer 202, so that the doped iii-v semiconductor layer 203 and the gate 204 form a gate structure. In this process, the first insulating dielectric layer 205 can avoid damage to the gate 204 during the patterning process of the doped iii-v semiconductor layer 203, thereby further reducing the leakage current at the gate 204.
And S270, doping electronegative atoms on the surface of the barrier layer away from the channel layer.
As shown in fig. 16, electronegative atoms are doped on the surface of the barrier layer 202 remote from the channel layer 201, wherein the front projection of the barrier layer 202 doped with electronegative atoms on the substrate 200 does not overlap with the front projection of the gate 204 on the substrate 200. The electronegativity of the electronegative atom is greater than or equal to the electronegativity of the sulfur atom and less than or equal to the electronegativity of the fluorine atom. Specifically, the surface of the barrier layer 202, which is far away from the channel layer 201, corresponding to the channel region is doped with electronegative atoms, so that the surface state of the barrier layer 202 at the channel region can be improved, the concentration of two-dimensional electron gas in the channel region can be increased, and the performance of the gallium nitride semiconductor device can be further improved. Meanwhile, the first insulating dielectric layer 205 is located between the gate 204 and the stress layer 208, and when the barrier layer 202 corresponding to the channel region is far away from the surface of the channel layer 201 and doped with electronegative atoms, the first insulating dielectric layer 205 can perform isolation protection on the gate 204, so that when the barrier layer 202 corresponding to the channel region is far away from the surface of the channel layer 201 and doped with electronegative atoms, the leakage current at the gate 204 can be prevented from being reduced.
And S280, forming a source electrode and a drain electrode on the surface of the barrier layer away from the channel layer.
As shown in fig. 17, a source electrode 206 is formed on the surface of the barrier layer 202 away from the channel layer 201; a drain electrode 207 is formed on a surface of the barrier layer 202 remote from the channel layer 201.
And S290, forming a stress layer on the surface of the barrier layer away from the channel layer and the surface side of the first insulating medium layer away from the grid electrode.
As shown in fig. 8, a stress layer 208 is formed on the surface of the barrier layer 202 away from the channel layer 201 and the surface side of the first insulating dielectric layer away from the gate electrode. The stress layer 208 covers the surface of the barrier layer 202 away from the channel layer 201 and the surface side of the first insulating dielectric layer away from the gate 204, and the film layer covering the side of the gate 204 and the surface of the gate 204 away from the doped iii-v semiconductor layer 203 is the first insulating dielectric layer 205 and the stress layer 208 in sequence, increasing the number of protective film layers covering the side of the gate 204 and the surface of the gate 204 away from the doped iii-v semiconductor layer 203, thereby reducing the leakage current at the gate 204. In addition, the stress layer 208 can be used to increase the stress of the device, repair damaged interfaces, increase the two-dimensional electron gas concentration, and improve the device performance.
According to the technical scheme provided by the embodiment of the invention, the first insulating medium layer 205 covers the side surface of the gate 204, the surface of the gate 204 far away from the doped III-V semiconductor layer 203 and the surface of the doped III-V semiconductor layer 203 far away from the barrier layer 202, the stress layer 208 covers the surface of the barrier layer 202 far away from the channel layer 201 and the surface side of the first insulating medium layer far away from the gate 204, the film layers covering the side surface of the gate 204 and the surface of the gate 204 far away from the doped III-V semiconductor layer 203 are the first insulating medium layer 205 and the stress layer 208, and the number of protective film layers covering the side surface of the gate 204 and the surface of the gate 204 far away from the doped III-V semiconductor layer 203 is increased, so that the leakage current at the gate 204 is reduced. And the surface of the barrier layer 202, which is far away from the channel layer 201, is doped with electronegativity atoms, wherein the electronegativity of the electronegativity atoms is greater than or equal to that of sulfur atoms and less than or equal to that of fluorine atoms, and the electronegativity is relatively strong, so that the surface state of the barrier layer 202 at the channel region can be improved, the concentration of two-dimensional electron gas of the channel region can be increased, and the performance of the gallium nitride semiconductor device can be further improved. Meanwhile, the first insulating dielectric layer 205 is located between the gate 204 and the stress layer 208, and when the barrier layer 202 corresponding to the channel region is far away from the surface of the channel layer 201 and doped with electronegative atoms, the first insulating dielectric layer 205 can perform isolation protection on the gate 204, so that when the barrier layer 202 corresponding to the channel region is far away from the surface of the channel layer 201 and doped with electronegative atoms, the leakage current at the gate 204 can be prevented from being reduced. In summary, the technical solution provided by the embodiment of the present invention reduces the leakage current of the gate 204, improves the surface state of the barrier layer 202 at the channel region, and increases the concentration of the two-dimensional electron gas in the channel region, thereby improving the performance of the gallium nitride semiconductor device. In addition, the stress layer 208 can be used to increase the stress of the device, repair damaged interfaces, increase the two-dimensional electron gas concentration, and improve the device performance.
Optionally, based on the above technical solution, doping the electronegative atoms on a surface of the barrier layer away from the channel layer in S260 includes:
at least one of oxygen atoms, nitrogen atoms, fluorine atoms, and sulfur atoms is doped on the surface of the barrier layer remote from the channel layer by a plasma surface treatment process.
As shown in fig. 16, doping at least one of an oxygen atom, a nitrogen atom, a fluorine atom, and a sulfur atom on the surface of the barrier layer 202 remote from the channel layer 201 can improve the surface state of the barrier layer 202 at the channel region, increase the concentration of the two-dimensional electron gas in the channel region, and further improve the performance of the gallium nitride semiconductor device. Here, the surface of the barrier layer 202 away from the channel layer 201 was doped with electronegative atoms by a plasma surface treatment process, and the surface of the barrier layer 202 away from the channel layer 201 was modified, so that the concentration of electronegative atoms in the barrier layer 202 was negligible.
Optionally, on the basis of the above technical solution, as shown in fig. 18, fig. 18 is a flowchart of another method for manufacturing a gallium nitride semiconductor device according to an embodiment of the present invention, and S260 uses the first insulating medium layer as a mask to pattern the doped iii-v semiconductor layer, so that after the doped iii-v semiconductor layer and the gate form a gate structure, the method further includes:
s2601, forming a second insulating medium layer at least on the side surface of the doped III-V semiconductor layer.
As shown in fig. 19, the doped iii-v semiconductor layer 203 is patterned using the first insulating dielectric layer 205 as a mask, exposing the channel region, the source and the drain regions, and the corresponding barrier layer 202. A second insulating dielectric layer 209 is then formed on the sides of the doped iii-v semiconductor layer 203. As shown in fig. 20, the surface of the barrier layer 202 corresponding to the channel region, which is remote from the channel layer 201, is doped with electronegative atoms. As shown in fig. 21, a source electrode 206 and a drain electrode 207 are formed on the surface of the barrier layer 202 remote from the channel layer 201. As shown in fig. 9, corresponding to S2901 in fig. 18, a stress layer 208 is formed on the surface of the barrier layer 202 away from the channel layer 201 and the surface side of the first insulating dielectric layer 205 away from the gate electrode 204, and the stress layer 208 also covers the second insulating dielectric layer 209.
Alternatively, as shown in fig. 22, the doped iii-v semiconductor layer 203 is patterned using the first insulating dielectric layer 205 as a mask to expose the channel region, the source and the barrier layer 202 corresponding to the region where the drain is located. A second insulating dielectric layer 209 is then formed on the side of the doped iii-v semiconductor layer 203 and on the surface of the first insulating dielectric layer 205 remote from the gate 204. As shown in fig. 23, the surface of the barrier layer 202 corresponding to the channel region, which is remote from the channel layer 201, is doped with electronegative atoms. As shown in fig. 24, a source electrode 206 and a drain electrode 207 are formed on the surface of the barrier layer 202 remote from the channel layer 201. As shown in fig. 10, a stress layer 208 is formed on the surface of the barrier layer 202 away from the channel layer 201 and the surface side of the first insulating dielectric layer 205 away from the gate electrode 204, corresponding to S2901 in fig. 18. Specifically, in fig. 10, a stress layer 208 is formed on the surface of the barrier layer 202 away from the channel layer 201 and the surface side of the second insulating dielectric layer 209 away from the gate electrode 204, and the stress layer 208 also covers the second insulating dielectric layer 209.
Specifically, the second insulating dielectric layer 209 at least covers the side surface of the doped iii-v semiconductor layer 203, and increases the number of protective film layers covering the side surface of the doped iii-v semiconductor layer 203, thereby further reducing the leakage current at the gate 204. Meanwhile, the second insulating dielectric layer 209 is located between the gate 204 and the stress layer 208, and when the surface of the barrier layer 202 corresponding to the channel region is far away from the channel layer 201 and doped with electronegative atoms, the second insulating dielectric layer 209 can perform isolation protection on the doped iii-v semiconductor layer 203, so that when the surface of the barrier layer 202 corresponding to the channel region is far away from the channel layer 201 and doped with electronegative atoms, the leakage current at the gate 204 can be further prevented from being reduced. As shown in fig. 9, a second insulating dielectric layer 209 covers the sides of the doped iii-v semiconductor layer 203. As shown in fig. 10, the second insulating dielectric layer 209 covers the side surface of the doped iii-v semiconductor layer 203 and the first insulating dielectric layer 205, and further increases the number of protective film layers covering the entire gate structure, thereby further reducing the leakage current at the gate 204.
Optionally, on the basis of the above technical solution, forming the first insulating medium layer at the side surface of the gate electrode, the surface of the gate electrode away from the doped iii-v semiconductor layer, and the surface of the doped iii-v semiconductor layer away from the barrier layer in S250 includes:
silicon oxide and/or silicon nitride is formed on the side of the gate electrode, the surface of the gate electrode remote from the doped iii-v semiconductor layer, and the surface of the doped iii-v semiconductor layer remote from the barrier layer.
As shown in fig. 15, silicon oxide and/or silicon nitride is formed on the side of the gate 204, the surface of the gate 204 remote from the doped iii-v semiconductor layer 203, and the surface of the doped iii-v semiconductor layer 203 remote from the barrier layer 202.
Specifically, the silicon oxide and/or silicon nitride may be used as the first insulating dielectric layer 205 to isolate and protect the gate 204, which has a relatively large dielectric constant for reducing the leakage current of the gate 204.
Optionally, as shown in fig. 22, the doped iii-v semiconductor layer 203 is patterned with the first insulating dielectric layer 205 as a mask, exposing the channel region, the source and the barrier layer 202 corresponding to the region where the drain is located. A second insulating dielectric layer 209 is then formed on the side of the doped iii-v semiconductor layer 203 and on the surface of the first insulating dielectric layer 205 remote from the gate 204. The second insulating dielectric layer 209 comprises silicon oxide and/or silicon nitride, and has a relatively high dielectric constant, so as to further isolate and protect the gate structure, and reduce the leakage current of the gate 204.
Optionally, on the basis of the foregoing technical solution, forming the stress layer at the surface of the barrier layer away from the channel layer and the surface side of the first insulating medium layer away from the gate in S290 includes:
Aluminum nitride and/or aluminum oxide is formed on the surface of the barrier layer away from the channel layer and the surface side of the first insulating dielectric layer away from the gate electrode.
As shown in fig. 8, 9, and 10, aluminum nitride is formed on the surface of the barrier layer 202 away from the channel layer 201 and the surface side of the first insulating dielectric layer 205 away from the gate electrode 204.
Specifically, aluminum nitride and/or aluminum oxide are good stress enhancement materials and insulating materials, and meanwhile, damaged interfaces can be repaired, gate leakage is reduced, and device performance is improved. Specifically, aluminum nitride is used as a stress layer 208 to cooperate with the first insulating dielectric layer 205 to protect the gate structure to reduce leakage current; aluminum nitride as the stress layer 208 can be used to improve the surface state of the barrier layer 202 corresponding to the channel region, so as to increase the concentration of the two-dimensional electron gas in the channel region, thereby improving the performance of the gallium nitride semiconductor device. When the gallium nitride semiconductor device further includes the second insulating dielectric layer 209, aluminum nitride is used as the stress layer 208 and the first insulating dielectric layer 205 and the second insulating dielectric layer 209 cooperate to protect the gate structure to reduce leakage current.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A gallium nitride semiconductor device, comprising:
A substrate;
A channel layer located on one side of the substrate;
A barrier layer located on a side of the channel layer remote from the substrate;
A gate structure comprising a doped iii-v semiconductor layer and a gate, the doped iii-v semiconductor layer being located on a surface of the barrier layer remote from the channel layer, the gate being located on a surface of the doped iii-v semiconductor layer remote from the barrier layer, a front projection of the gate on the substrate covering a portion of a front projection of the doped iii-v semiconductor layer on the substrate;
A first insulating dielectric layer covering a side of the gate, a surface of the gate away from the doped iii-v semiconductor layer, and a surface of the doped iii-v semiconductor layer away from the barrier layer;
a source electrode located on a surface of the barrier layer away from the channel layer;
a drain electrode located on a surface of the barrier layer remote from the channel layer;
A stress layer covering a surface of the barrier layer away from the channel layer and a surface side of the first insulating dielectric layer away from the gate electrode;
The surface of the barrier layer far away from the channel layer is doped with electronegative atoms, wherein the positive projection of the barrier layer doped with the electronegative atoms on the substrate and the positive projection of the grid electrode on the substrate are not overlapped, and the electronegativity of the electronegative atoms is greater than or equal to that of sulfur atoms and less than or equal to that of fluorine atoms.
2. The gallium nitride semiconductor device according to claim 1, wherein a surface of the barrier layer remote from the channel layer is doped with at least one of oxygen atoms, nitrogen atoms, fluorine atoms, and sulfur atoms.
3. The gallium nitride semiconductor device of claim 1, further comprising a second insulating dielectric layer covering at least a side of the doped group iii-v semiconductor layer.
4. The gallium nitride semiconductor device of claim 1, wherein the first insulating dielectric layer comprises silicon oxide and/or silicon nitride.
5. Gallium nitride semiconductor device according to claim 1, wherein the stress layer comprises aluminum nitride and/or aluminum oxide.
6. A method for manufacturing a gallium nitride semiconductor device, comprising:
Providing a substrate;
Forming a channel layer on one side of the substrate;
Forming a barrier layer on one side of the channel layer away from the substrate;
forming a doped III-V semiconductor layer on the surface of the barrier layer away from the channel layer;
forming a grid on the surface of the doped III-V semiconductor layer, which is far away from the barrier layer, wherein the grid is positioned on the surface of the doped III-V semiconductor layer, which is far away from the barrier layer, and the orthographic projection of the grid on the substrate covers the orthographic projection of part of the doped III-V semiconductor layer on the substrate;
Forming a first insulating medium layer on the side surface of the grid electrode, the surface of the grid electrode far away from the doped III-V semiconductor layer and the surface of the doped III-V semiconductor layer far away from the barrier layer;
Patterning the doped III-V semiconductor layer by taking the first insulating medium layer as a mask plate so that the doped III-V semiconductor layer and the grid form a grid structure;
Doping electronegative atoms on the surface of the barrier layer far away from the channel layer, wherein the positive projection of the barrier layer doped with the electronegative atoms on the substrate and the positive projection of the grid electrode on the substrate are not overlapped, and the electronegativity of the electronegative atoms is greater than or equal to that of sulfur atoms and less than or equal to that of fluorine atoms;
forming a source electrode and a drain electrode on the surface of the barrier layer away from the channel layer;
And forming a stress layer on the surface of the barrier layer away from the channel layer and the surface side of the first insulating medium layer away from the grid electrode.
7. The method of manufacturing a gallium nitride semiconductor device according to claim 6, wherein doping electronegative atoms in a surface of the barrier layer remote from the channel layer comprises:
At least one of oxygen atoms, nitrogen atoms, fluorine atoms and sulfur atoms is doped on the surface of the barrier layer away from the channel layer through a plasma surface treatment process.
8. The method of manufacturing a gallium nitride semiconductor device according to claim 6, wherein patterning the doped iii-v semiconductor layer using the first insulating medium layer as a mask, so that the doped iii-v semiconductor layer and the gate form a gate structure, further comprises:
and forming a second insulating medium layer at least on the side surface of the doped III-V semiconductor layer.
9. The method of manufacturing a gallium nitride semiconductor device according to claim 6, wherein forming a first insulating medium layer on a side surface of the gate electrode, a surface of the gate electrode away from the doped iii-v semiconductor layer, and a surface of the doped iii-v semiconductor layer away from the barrier layer comprises:
silicon oxide and/or silicon nitride is formed on the side of the gate electrode, the surface of the gate electrode remote from the doped iii-v semiconductor layer, and the surface of the doped iii-v semiconductor layer remote from the barrier layer.
10. The method of manufacturing a gallium nitride semiconductor device according to claim 6, wherein forming a stress layer on a surface of the barrier layer away from the channel layer and a surface side of the first insulating dielectric layer away from the gate electrode comprises:
Aluminum nitride and/or aluminum oxide is formed on the surface of the barrier layer away from the channel layer and the surface side of the first insulating medium layer away from the grid electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410288763.4A CN117894835B (en) | 2024-03-14 | 2024-03-14 | Gallium nitride semiconductor device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410288763.4A CN117894835B (en) | 2024-03-14 | 2024-03-14 | Gallium nitride semiconductor device and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117894835A true CN117894835A (en) | 2024-04-16 |
| CN117894835B CN117894835B (en) | 2024-05-17 |
Family
ID=90639761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410288763.4A Active CN117894835B (en) | 2024-03-14 | 2024-03-14 | Gallium nitride semiconductor device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117894835B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367423A (en) * | 2012-03-29 | 2013-10-23 | 富士通株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| KR101334164B1 (en) * | 2012-06-28 | 2013-11-29 | 순천대학교 산학협력단 | High electron mobility transistors device and method of manufacturing the same |
| CN105895685A (en) * | 2015-12-25 | 2016-08-24 | 苏州捷芯威半导体有限公司 | Power semiconductor device and manufacturing method thereof |
| US20170358495A1 (en) * | 2016-06-14 | 2017-12-14 | Chih-Shu Huang | Epitaxial structure of ga-face group iii nitride, active device, and method for fabricating the same |
| CN116779643A (en) * | 2023-06-09 | 2023-09-19 | 英诺赛科（珠海）科技有限公司 | Gallium nitride HEMT device with gate passivation region and preparation method thereof |
| CN117438455A (en) * | 2023-10-27 | 2024-01-23 | 英诺赛科(苏州)半导体有限公司 | Gallium nitride transistor device with high electron mobility and preparation method thereof |
-
2024
- 2024-03-14 CN CN202410288763.4A patent/CN117894835B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103367423A (en) * | 2012-03-29 | 2013-10-23 | 富士通株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| KR101334164B1 (en) * | 2012-06-28 | 2013-11-29 | 순천대학교 산학협력단 | High electron mobility transistors device and method of manufacturing the same |
| CN105895685A (en) * | 2015-12-25 | 2016-08-24 | 苏州捷芯威半导体有限公司 | Power semiconductor device and manufacturing method thereof |
| US20170358495A1 (en) * | 2016-06-14 | 2017-12-14 | Chih-Shu Huang | Epitaxial structure of ga-face group iii nitride, active device, and method for fabricating the same |
| CN116779643A (en) * | 2023-06-09 | 2023-09-19 | 英诺赛科（珠海）科技有限公司 | Gallium nitride HEMT device with gate passivation region and preparation method thereof |
| CN117438455A (en) * | 2023-10-27 | 2024-01-23 | 英诺赛科(苏州)半导体有限公司 | Gallium nitride transistor device with high electron mobility and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117894835B (en) | 2024-05-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109004027B (en) | Nitrogen polar III-nitride epitaxial structure and active device thereof and integrated polarity inversion manufacturing method thereof | |
| CN102629624B (en) | Metal-insulator-semiconductor (MIS) grid enhanced high electron mobility transistor (HEMT) device based on gallium nitride (GaN) and manufacture method of MIS grid enhanced HEMT device | |
| US20190296139A1 (en) | Transistor and Method for Manufacturing the Same | |
| CN108649071B (en) | Semiconductor devices and its manufacturing method | |
| JP2004221325A (en) | Compound semiconductor device and its manufacturing method | |
| CN102683406B (en) | GaN-based MS grid enhancement type high electron mobility transistor and manufacture method thereof | |
| CN111370300B (en) | Method for manufacturing grid structure of gallium nitride high electron mobility transistor | |
| US8420421B2 (en) | Method for fabricating a GaN-based thin film transistor | |
| JP2007537580A (en) | Field effect transistor with enhanced insulator structure | |
| CN102637726A (en) | MS (Metal-Semiconductor)-grid GaN-based enhanced transistor with high electron mobility and manufacture method thereof | |
| CN117894835B (en) | Gallium nitride semiconductor device and preparation method thereof | |
| CN102646705A (en) | Metal insulated semi-conductor (MIS) grid GaN base enhancing high electro mobility transistor (HEMT) device and manufacture method | |
| CN117438455A (en) | Gallium nitride transistor device with high electron mobility and preparation method thereof | |
| CN111370472A (en) | Mixed gate p-GaN enhanced gallium nitride based transistor structure and manufacturing method thereof | |
| CN115881774A (en) | HEMT device with array side gate structure and preparation method thereof | |
| CN104599957A (en) | Semiconductor device and manufacturing method thereof | |
| CN118136662A (en) | Semiconductor device and preparation method thereof | |
| CN112133739A (en) | High electron mobility transistor and method for adjusting electron density of two-dimensional electron gas | |
| CN117613071B (en) | Enhancement mode gallium nitride high electron mobility transistor device | |
| KR20140131167A (en) | Nitride semiconductor and method thereof | |
| CN117650173B (en) | Gallium nitride transistor with high electron mobility and preparation method thereof | |
| US20240014306A1 (en) | Semiconductor Structure with Features of D-mode and E-mode GaN Devices and Semiconductor Process Thereof | |
| CN108615763B (en) | Epitaxial material structure of silicon substrate GaN semiconductor device | |
| CN117577597A (en) | Gallium nitride device and preparation method thereof | |
| CN112687543A (en) | Preparation method of gallium nitride device and terminal structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |