CN117577597A - Gallium nitride device and preparation method thereof - Google Patents
Gallium nitride device and preparation method thereof Download PDFInfo
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- CN117577597A CN117577597A CN202410057413.7A CN202410057413A CN117577597A CN 117577597 A CN117577597 A CN 117577597A CN 202410057413 A CN202410057413 A CN 202410057413A CN 117577597 A CN117577597 A CN 117577597A
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 39
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 385
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 239000011241 protective layer Substances 0.000 claims abstract description 70
- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 103
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 69
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 68
- 238000002161 passivation Methods 0.000 claims description 14
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000005533 two-dimensional electron gas Effects 0.000 description 18
- 238000000034 method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 5
- 229910002704 AlGaN Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Abstract
The invention discloses a gallium nitride device and a preparation method thereof. The gallium nitride device includes: the epitaxial structure comprises a substrate, an epitaxial layer and a gate structure, wherein the gate structure is positioned on the surface of the epitaxial layer, which is far away from the substrate, and the gate structure comprises a doped III-V semiconductor layer and a gate; the first protective layer covers the gate structure and at least covers the side face of the gate structure; and a second protection layer covering the gate structure, the first protection layer, the channel region between the gate structure and the source electrode, and the channel region between the gate structure and the drain electrode, wherein a portion of the second protection layer covering the channel region between the gate structure and the source electrode, and the channel region between the gate structure and the drain electrode includes a doped semiconductor layer. The technical scheme provided by the embodiment of the invention reduces the grid leakage current and reduces the resistance of the channel region between the grid structure and the source electrode and the channel region between the grid structure and the drain electrode.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gallium nitride device and a preparation method thereof.
Background
Gallium nitride devices have excellent electrical properties due to the presence of a large concentration of two-dimensional electron gas (2 DEG) at the heterojunction formed by the channel layer and the barrier layer.
In the gallium nitride devices currently used, the gate leakage current is excessive and the resistance of the channel region between the gate structure and the source and the channel region between the gate structure and the drain is too great.
Disclosure of Invention
The invention provides a gallium nitride device and a preparation method thereof, which are used for reducing gate leakage current and reducing the resistance of a channel region between a gate structure and a source electrode and a channel region between the gate structure and a drain electrode.
According to an aspect of the present invention, there is provided a gallium nitride device comprising:
a substrate;
the epitaxial layer is positioned on the surface of the substrate;
a gate structure located on a surface of the epitaxial layer remote from the substrate, the gate structure comprising a doped group iii-v semiconductor layer and a gate; the doped III-V semiconductor layer is positioned on the surface of the epitaxial layer far away from the substrate; the grid electrode is positioned on the surface of the doped III-V semiconductor layer, which is far away from the epitaxial layer;
the source electrode is positioned on the surface of the epitaxial layer far away from the substrate;
the drain electrode is positioned on the surface of the epitaxial layer, which is far away from the substrate;
a first protection layer covering the gate structure and covering at least a side surface of the gate structure;
a second protective layer covering the gate structure, the first protective layer, the channel region between the gate structure and the source electrode, and the channel region between the gate structure and the drain electrode, wherein a portion of the second protective layer covering the channel region between the gate structure and the source electrode, and the channel region between the gate structure and the drain electrode includes a doped semiconductor layer.
Optionally, the first protection layer includes a first silicon nitride layer, and the first silicon nitride layer covers a side surface of the gate structure.
Optionally, the first protection layer includes a first silicon nitride layer and a first aluminum nitride layer;
the first aluminum nitride layer covers the side surface of the gate structure and the surface of the gate structure away from the epitaxial layer;
the first silicon nitride layer is positioned on one side of the first aluminum nitride layer far away from the grid structure, and the orthographic projection of the first silicon nitride layer on the substrate covers the orthographic projection of the side surface of the grid structure on the substrate.
Optionally, the second protection layer includes a second aluminum nitride layer, a second silicon nitride layer, and a passivation layer;
the second aluminum nitride layer covers the gate structure, the first protection layer, a channel region between the gate structure and the source electrode and a channel region between the gate structure and the drain electrode, and a portion of the second aluminum nitride layer covering the channel region between the gate structure and the source electrode and the channel region between the gate structure and the drain electrode is a doped second aluminum nitride layer;
the second silicon nitride layer is positioned on the surface of the second aluminum nitride layer, which is far away from the substrate;
the passivation layer is positioned on the surface of the second silicon nitride layer far away from the second aluminum nitride layer.
Optionally, a portion of the second aluminum nitride layer covering the channel region between the gate structure and the source electrode and the channel region between the gate structure and the drain electrode is a second aluminum nitride layer doped with oxygen atoms.
According to another aspect of the present invention, there is provided another method of manufacturing a gallium nitride device, comprising:
providing a substrate;
forming an epitaxial layer on the surface of the substrate;
forming a gate structure on the surface of the epitaxial layer away from the substrate, wherein the gate structure comprises a doped III-V semiconductor layer and a gate; the doped III-V semiconductor layer is positioned on the surface of the epitaxial layer far away from the substrate; the grid electrode is positioned on the surface of the doped III-V semiconductor layer, which is far away from the epitaxial layer;
forming a source electrode on the surface of the epitaxial layer far away from the substrate;
forming a drain electrode on the surface of the epitaxial layer far away from the substrate;
forming a first protection layer, wherein the first protection layer covers the grid structure and at least covers the side face of the grid structure;
forming a second protection layer, wherein the second protection layer covers the gate structure, the first protection layer, a channel region between the gate structure and the source electrode, and a channel region between the gate structure and the drain electrode, and a portion of the second protection layer covering the channel region between the gate structure and the source electrode, and the channel region between the gate structure and the drain electrode comprises a doped semiconductor layer.
Optionally, forming the first protective layer includes:
a first protective layer is formed including a first silicon nitride layer, wherein the first silicon nitride layer covers sides of the gate structure.
Optionally, forming the first protective layer includes:
forming a first aluminum nitride layer on the side surface of the gate structure and the surface of the gate structure away from the epitaxial layer;
and forming a first silicon nitride layer on one side of the first aluminum nitride layer far away from the gate structure, wherein the orthographic projection of the first silicon nitride layer on the substrate covers the orthographic projection of the side surface of the gate structure on the substrate.
Optionally, forming the second protective layer includes:
forming a second aluminum nitride layer, wherein the second aluminum nitride layer covers the gate structure, the first protection layer, a channel region between the gate structure and the source electrode and a channel region between the gate structure and the drain electrode, and a part of the second aluminum nitride layer covering the channel region between the gate structure and the source electrode and the channel region between the gate structure and the drain electrode is a doped second aluminum nitride layer;
forming a second silicon nitride layer on the surface of the second aluminum nitride layer, which is far away from the substrate;
and forming a passivation layer on the surface of the second silicon nitride layer far away from the second aluminum nitride layer.
Optionally, forming the second aluminum nitride layer includes:
forming a second aluminum nitride layer in the gate structure, the first protective layer, a channel region between the gate structure and the source electrode, and a channel region between the gate structure and the drain electrode;
and doping oxygen atoms in a part of the second aluminum nitride layer covering the channel region between the gate structure and the source electrode and the channel region between the gate structure and the drain electrode to form a second aluminum nitride layer doped with oxygen atoms.
According to the technical scheme provided by the embodiment of the invention, the protective layer covering the side surface of the gate structure is not completely the same as the film layer covering the channel region between the gate structure and the source electrode and the protective layer covering the channel region between the gate structure and the drain electrode, and the thicknesses of the protective layers are different, so that the two-dimensional electron gas concentrations of the side surface of the gate structure and the two regions of the channel region can be independently adjusted.
Specifically, the first protective layer covers at least the side surface of the gate structure, the second protective layer covers the gate structure, the first protective layer, the channel region between the gate structure and the source electrode and the channel region between the gate structure and the drain electrode, namely, the protective layer covering the side surface of the gate structure is provided with the first protective layer and the second protective layer, the thickness of the protective layer covering the side surface of the gate structure is increased, the thickness and the resistance of the protective layer covering the side surface of the gate structure are increased, and the gate leakage current is reduced.
The portion of the second protective layer covering the channel region between the gate structure and the source electrode and the channel region between the gate structure and the drain electrode includes a doped semiconductor layer, and the two-dimensional electron gas concentration of the channel region is improved, thereby reducing resistance and device loss.
In summary, the technical scheme of the embodiment of the invention can realize independent adjustment of two-dimensional electron gas concentrations of the side surface of the gate structure and the two areas of the channel region, thereby reducing gate leakage current, reducing the resistance of the channel region between the gate structure and the source electrode and the channel region between the gate structure and the drain electrode, and reducing device loss.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a method for fabricating a gallium nitride device according to the prior art;
FIGS. 2-5 are schematic views of the structure corresponding to the steps in FIG. 1;
fig. 6 is a schematic structural diagram of a gallium nitride device according to an embodiment of the invention;
fig. 7 is a schematic structural diagram of another gallium nitride device according to an embodiment of the invention;
fig. 8 is a flowchart of a method for manufacturing a gallium nitride device according to an embodiment of the invention;
FIGS. 9-11 are schematic views of the structure corresponding to the steps in FIG. 8;
fig. 12 is a flowchart included in S260 of fig. 8;
FIGS. 13-14 are schematic views of the structure corresponding to the steps in FIG. 12;
fig. 15 is a schematic flow chart included in S270 in fig. 8;
FIGS. 16-17 are schematic views of the structure corresponding to the steps in FIG. 15;
fig. 18 is a flowchart included in S2701 in fig. 15.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or means is not necessarily limited to those steps or means that are expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art above, in the gallium nitride device currently used, the gate leakage current is excessive and the resistance of the channel region between the gate structure and the source and the channel region between the gate structure and the drain is too large. The inventor has found through careful study that, as shown in fig. 1 and fig. 2-5, fig. 1 is a flowchart of a preparation method of a gallium nitride device provided in the prior art, and fig. 2-5 are schematic structural diagrams corresponding to each step in fig. 1, where the preparation method of the gallium nitride device includes: s110, providing a substrate; s120, forming an epitaxial layer on the surface of the substrate; s130, forming a gate structure on the surface of the epitaxial layer, which is far away from the substrate, wherein the gate structure comprises a doped III-V semiconductor layer and a gate; the doped III-V semiconductor layer is positioned on the surface of the epitaxial layer far away from the substrate; the grid electrode is positioned on the surface of the doped III-V semiconductor layer, which is far away from the epitaxial layer; s140, forming a source electrode on the surface of the epitaxial layer far away from the substrate; s150, forming a drain electrode on the surface of the epitaxial layer far away from the substrate; and S160, forming a protective layer, wherein the protective layer covers the gate structure, a channel region between the gate structure and the source electrode and a channel region between the gate structure and the drain electrode, the protective layer sequentially comprises an aluminum nitride layer, a silicon nitride layer and a passivation layer, and the aluminum nitride layer is in direct base contact with the gate structure. Wherein fig. 2-include the following reference numerals: 01-substrate, 02-epitaxial layer, 03-gate structure, 031-doped III-V semiconductor layer, 032-gate, 04-source, 05-drain, 06-protective layer, 061-aluminum nitride layer, 062-silicon nitride layer, 063-passivation layer.
For current gallium nitride devices, the channel region between the gate structure 03 and the source 04 and the channel region between the gate structure 03 and the drain 05 need to increase the two-dimensional electron gas concentration to reduce resistance and device loss. The gate structure 03 needs to reduce the gate leakage current, and thus the two-dimensional electron gas concentration covering the side surface of the gate structure 03 needs to be reduced.
Therefore, the preparation method and the gallium nitride device provided in the prior art cannot independently adjust the two-dimensional electron gas concentrations of the side surface of the gate structure 03 and the two regions of the channel region because the protective layers covering the gate structure 03, the channel region between the gate structure 03 and the source electrode 04, and the channel region between the gate structure 03 and the drain electrode 05 are the same protective layer. In fact, in the gallium nitride device used at present, neither the gate leakage current nor the resistance of the channel region is reduced to the use requirement, so that the device loss is relatively large.
Aiming at the technical problems, the embodiment of the invention provides the following technical scheme:
as shown in fig. 6, fig. 6 is a schematic structural diagram of a gallium nitride device according to an embodiment of the present invention, where the gallium nitride device includes: a substrate 100; an epitaxial layer 200, the epitaxial layer 200 being located on the surface of the substrate 100; a gate structure 300, the gate structure 300 being located on a surface of the epitaxial layer 200 remote from the substrate 100, the gate structure 300 comprising a doped iii-v semiconductor layer 301 and a gate 302; the doped group iii-v semiconductor layer 301 is located on the surface of the epitaxial layer 200 remote from the substrate 100; the gate 302 is located on the surface of the doped iii-v semiconductor layer 301 remote from the epitaxial layer 200; a source 400, the source 400 being located on a surface of the epitaxial layer 200 remote from the substrate 100; a drain electrode 500, the drain electrode 500 being located on a surface of the epitaxial layer 200 remote from the substrate 100; a first protection layer 600, wherein the first protection layer 600 covers the gate structure 300 and covers at least a side surface of the gate structure 300; and a second protective layer 700, the second protective layer 700 covering the gate structure 300, the first protective layer 600, the channel region between the gate structure 300 and the source electrode 400, and the channel region between the gate structure 300 and the drain electrode 500, and a portion of the second protective layer 700 covering the channel region between the gate structure 300 and the source electrode 400 and the channel region between the gate structure 300 and the drain electrode 500 including a doped semiconductor layer.
According to the technical scheme provided by the embodiment of the invention, the protective layer covering the side surface of the gate structure 300 is not completely the same as the film layer covering the channel region between the gate structure 300 and the source 400 and the protective layer covering the channel region between the gate structure 300 and the drain 500, and the thicknesses of the protective layers are also different, so that the two-dimensional electron gas concentrations of the side surface of the gate structure 03 and the two regions of the channel region can be independently regulated.
Specifically, the first protection layer 600 covers at least the side of the gate structure 300, the second protection layer 700 covers the gate structure 300, the first protection layer 600, the channel region between the gate structure 300 and the source electrode 400, and the channel region between the gate structure 300 and the drain electrode 500, i.e., the protection layer covering the side of the gate structure 300 has the first protection layer 600 and the second protection layer 700, which increases the thickness of the protection layer covering the side of the gate structure 300, increases the thickness and the resistance of the protection layer covering the side of the gate structure 300, and reduces the gate leakage current.
The portion of the second protective layer 700 covering the channel region between the gate structure 300 and the source electrode 400 and the channel region between the gate structure 300 and the drain electrode 500 includes a doped semiconductor layer, and the two-dimensional electron gas concentration of the channel region is increased, thereby reducing resistance and device loss.
In summary, the technical solution of the embodiment of the present invention can realize independent adjustment of two-dimensional electron gas concentrations of the side surface of the gate structure 300 and the two regions of the channel region, thereby reducing gate leakage current, reducing resistance of the channel region between the gate structure 300 and the source 400 and the channel region between the gate structure 300 and the drain 500, and reducing device loss.
Alternatively, as shown in fig. 6, the first protection layer 600 includes a first silicon nitride layer 601, where the first silicon nitride layer 601 covers the side surface of the gate structure 300.
Specifically, the first silicon nitride layer 601 covers the side surface of the gate structure 300, the second protective layer 700 covers the gate structure 300, the first protective layer 600, the channel region between the gate structure 300 and the source 400, and the channel region between the gate structure 300 and the drain 500, i.e., the first silicon nitride layer 601 and the second protective layer 700 cover the side surface of the gate structure 300, the thickness and the resistance of the protective layer covering the side surface of the gate structure 300 are increased, and the gate leakage current is reduced. Optionally, to further reduce the gate leakage current, the first silicon nitride layer 601 also extends from the side of the gate structure 300 to the surface of the epitaxial layer 200 remote from the substrate 100.
Optionally, on the basis of the above technical solution, as shown in fig. 7, fig. 7 is a schematic structural diagram of another gallium nitride device provided according to an embodiment of the present invention, where the first protection layer 600 includes a first silicon nitride layer 601 and a first aluminum nitride layer 602; the first aluminum nitride layer 602 covers the sides of the gate structure 300 and the surface of the gate structure 300 remote from the epitaxial layer 200; the first silicon nitride layer 601 is located on a side of the first aluminum nitride layer 602 away from the gate structure 300, and an orthographic projection of the first silicon nitride layer 601 on the substrate 100 covers an orthographic projection of a side of the gate structure 300 on the substrate 100.
Specifically, the first silicon nitride layer 601 and the first aluminum nitride layer 602 cover the sides of the gate structure 300, the second protection layer 700 covers the gate structure 300, the first protection layer 600, the channel region between the gate structure 300 and the source 400, and the channel region between the gate structure 300 and the drain 500, i.e., the first silicon nitride layer 601, the first aluminum nitride layer 602, and the second protection layer 700 cover the sides of the gate structure 300, the thickness and the resistance of the protection layer covering the sides of the gate structure 300 are increased, and the gate leakage current is reduced. Optionally, to further reduce the gate leakage current, the first aluminum nitride layer 602 also extends from the side of the gate structure 300 to the surface of the epitaxial layer 200 remote from the substrate 100.
And the first aluminum nitride layer 602 covers the side surface of the gate structure 300 and the surface of the gate structure 300 away from the epitaxial layer 200, in the process of preparing the first silicon nitride layer 601 on the side of the first aluminum nitride layer 602 away from the gate structure 300, patterning the first silicon nitride layer 601 is required, so that the first silicon nitride layer 601 only covers the side surface of the gate structure 300, and when the patterned first silicon nitride layer 601 is formed, the first aluminum nitride layer 602 can be used as a mask pattern for covering the surface of the gate 302 away from the doped iii-v semiconductor layer 301, thereby saving the number of masks and reducing the preparation cost.
Alternatively, on the basis of the above technical solution, as shown in fig. 6 and 7, the second protection layer 700 includes a second aluminum nitride layer 701, a second silicon nitride layer 702, and a passivation layer 703; the second aluminum nitride layer 701 covers the gate structure 300, the first protection layer 600, the channel region between the gate structure 300 and the source electrode 400, and the channel region between the gate structure 300 and the drain electrode 500, and a portion of the second aluminum nitride layer 701 covering the channel region between the gate structure 300 and the source electrode 400 and the channel region between the gate structure 300 and the drain electrode 500 is a doped second aluminum nitride layer 701; the second silicon nitride layer 702 is located on the surface of the second aluminum nitride layer 701 remote from the substrate 100; the passivation layer 703 is located on a surface of the second silicon nitride layer 702 remote from the second aluminum nitride layer 701.
Specifically, the first protection layer 600, the second aluminum nitride layer 701, the second silicon nitride layer 702, and the passivation layer 703 cover the sides of the gate structure 300, increasing the thickness and resistance of the protection layer covering the sides of the gate structure 300, and reducing the gate leakage current.
And the second aluminum nitride layer 701 is a doped second aluminum nitride layer covering the channel region between the gate structure 300 and the source 400 and the channel region between the gate structure 300 and the drain 500, so that the two-dimensional electron gas concentration of the channel region is improved, and the resistance and the device loss are reduced.
Alternatively, as shown in fig. 6 and 7, the portion of the second aluminum nitride layer 701 covering the channel region between the gate structure 300 and the source electrode 400 and the channel region between the gate structure 300 and the drain electrode 500 is a second aluminum nitride layer doped with oxygen atoms.
Specifically, the portion of the second aluminum nitride layer 701 covering the channel region between the gate structure 300 and the source electrode 400 and the channel region between the gate structure 300 and the drain electrode 500 is the second aluminum nitride layer doped with oxygen atoms, which increases the two-dimensional electron gas concentration of the channel region, thereby reducing the resistance and the device loss.
The embodiment of the invention also provides a preparation method of the gallium nitride device. As shown in fig. 8, fig. 8 is a flowchart of a method for manufacturing a gallium nitride device according to an embodiment of the invention, where the method for manufacturing a gallium nitride device includes the following steps:
s210, providing a substrate.
As shown in fig. 9, a substrate 100 is provided.
S220, forming an epitaxial layer on the surface of the substrate.
As shown in fig. 9, an epitaxial layer 200 is formed on the surface of the substrate 100. Optionally, the epitaxial layer 200 includes a buffer layer, a channel layer, and a barrier layer. The buffer layer serves to alleviate the problem of lattice mismatch between the substrate 100 and the channel layer. The channel layer includes one or more of a GaN layer, an AlGaN layer, and an InGaN layer. The barrier layer may be one or more of an AlGaN layer, an AlN layer, and an InGaN layer.
S230, forming a gate structure on the surface of the epitaxial layer, which is far away from the substrate, wherein the gate structure comprises a doped III-V semiconductor layer and a gate; the doped III-V semiconductor layer is positioned on the surface of the epitaxial layer far away from the substrate; the gate is located on a surface of the doped III-V semiconductor layer remote from the epitaxial layer.
As shown in fig. 9, a gate structure 300 is formed on the surface of the epitaxial layer 200 remote from the substrate 100, wherein the gate structure 300 includes a doped iii-v semiconductor layer 301 and a gate 302; the doped group iii-v semiconductor layer 301 is located on the surface of the epitaxial layer 200 remote from the substrate 100; the gate 302 is located on the surface of the doped iii-v semiconductor layer 301 remote from the epitaxial layer 200. Alternatively, the doped iii-v semiconductor layer 301 includes any one of a P-type doped GaN layer, a P-type doped AlGaN layer, and a P-type doped AlN layer. The doped III-V semiconductor layer 301 is used to deplete the two-dimensional electron gas thereunder to form an enhanced gallium nitride device.
S240, forming a source electrode on the surface of the epitaxial layer, which is far away from the substrate.
As shown in fig. 9, a source electrode 400 is formed on the surface of the epitaxial layer 200 remote from the substrate 100 by a metal film forming process.
And S250, forming a drain electrode on the surface of the epitaxial layer, which is far away from the substrate.
As shown in fig. 9, a drain electrode 500 is formed on the surface of the epitaxial layer 200 remote from the substrate 100 by a metal film forming process.
And S260, forming a first protection layer, wherein the first protection layer covers the gate structure and at least covers the side face of the gate structure.
As shown in fig. 9, a first protective layer 600 is formed, wherein the first protective layer 600 covers the gate structure 300 and covers at least the side of the gate structure 300.
S270, forming a second protection layer, wherein the second protection layer covers the gate structure, the first protection layer, the channel region between the gate structure and the source electrode, and the channel region between the gate structure and the drain electrode, and a portion of the second protection layer covering the channel region between the gate structure and the source electrode, and the channel region between the gate structure and the drain electrode includes a doped semiconductor layer.
In forming the second protective layer 700, as shown in fig. 10, 11 and 6, at least one film layer is formed, three film layers are exemplarily shown in the drawings, wherein the second protective layer 700 covers the gate structure 300, the first protective layer 600, a channel region between the gate structure 300 and the source electrode 400, and a channel region between the gate structure 300 and the drain electrode 500, a portion of the second protective layer 700 covering the channel region between the gate structure and the source electrode and the channel region between the gate structure and the drain electrode includes a doped semiconductor layer, and the second protective layer 700 serves to reduce resistance of the channel region between the gate structure 300 and the source electrode 400 and resistance of the channel region between the gate structure 300 and the drain electrode 500; the first and second protective layers 600 and 700 covering the sides of the gate structure 300 serve to reduce gate leakage current.
According to the technical scheme provided by the embodiment of the invention, the protective layer covering the side surface of the gate structure 300 is not completely the same as the film layer covering the channel region between the gate structure 300 and the source 400 and the protective layer covering the channel region between the gate structure 300 and the drain 500, and the thicknesses of the protective layers are also different, so that the two-dimensional electron gas concentrations of the side surface of the gate structure 03 and the two regions of the channel region can be independently regulated.
Specifically, the first protection layer 600 covers at least the side of the gate structure 300, the second protection layer 700 covers the gate structure 300, the first protection layer 600, the channel region between the gate structure 300 and the source electrode 400, and the channel region between the gate structure 300 and the drain electrode 500, i.e., the protection layer covering the side of the gate structure 300 has the first protection layer 600 and the second protection layer 700, which increases the thickness of the protection layer covering the side of the gate structure 300, increases the thickness and the resistance of the protection layer covering the side of the gate structure 300, and reduces the gate leakage current.
The portion of the second protective layer 700 covering the channel region between the gate structure 300 and the source electrode 400 and the channel region between the gate structure 300 and the drain electrode 500 includes a doped semiconductor layer, and the two-dimensional electron gas concentration of the channel region is increased, thereby reducing resistance and device loss.
In summary, the technical solution of the embodiment of the present invention can realize independent adjustment of two-dimensional electron gas concentrations of the side surface of the gate structure 300 and the two regions of the channel region, thereby reducing gate leakage current, reducing resistance of the channel region between the gate structure 300 and the source 400 and the channel region between the gate structure 300 and the drain 500, and reducing device loss.
Optionally, on the basis of the foregoing technical solution, forming the first protection layer in S260 includes:
a first protective layer including a first silicon nitride layer is formed. Wherein the first silicon nitride layer covers the side surface of the gate structure.
As shown in fig. 9, a first protective layer 600 including a first silicon nitride layer 601 is formed, wherein the first silicon nitride layer 601 covers the sides of the gate structure 300. Optionally, to further reduce the gate leakage current, the first silicon nitride layer 601 also extends from the side of the gate structure 300 to the surface of the epitaxial layer 200 remote from the substrate 100.
Specifically, the first silicon nitride layer 601 covers the side surface of the gate structure 300, the second protective layer 700 covers the gate structure 300, the first protective layer 600, the channel region between the gate structure 300 and the source 400, and the channel region between the gate structure 300 and the drain 500, i.e., the first silicon nitride layer 601 and the second protective layer 700 cover the side surface of the gate structure 300, the thickness and the resistance of the protective layer covering the side surface of the gate structure 300 are increased, and the gate leakage current is reduced.
Optionally, on the basis of the above technical solution, as shown in fig. 12, fig. 12 is a flowchart included in S260 in fig. 8, and forming the first protection layer in S260 includes:
s2601, forming a first aluminum nitride layer on a side surface of the gate structure and a surface of the gate structure away from the epitaxial layer.
As shown in fig. 13, a first aluminum nitride layer 602 is formed on the side of the gate structure 300 and the surface of the gate structure 300 remote from the epitaxial layer 200. Optionally, to further reduce the gate leakage current, the first aluminum nitride layer 602 also extends from the side of the gate structure 300 to the surface of the epitaxial layer 200 remote from the substrate 100.
S2602, forming a first silicon nitride layer on one side of the first aluminum nitride layer far away from the gate structure, wherein the orthographic projection of the first silicon nitride layer on the substrate covers the orthographic projection of the side surface of the gate structure on the substrate.
As shown in fig. 14, a first silicon nitride layer 601 is formed on a side of the first aluminum nitride layer 602 remote from the gate structure 300, wherein an orthographic projection of the first silicon nitride layer 601 on the substrate 100 covers an orthographic projection of a side of the gate structure 300 on the substrate 100.
Specifically, the first silicon nitride layer 601 and the first aluminum nitride layer 602 cover the sides of the gate structure 300, the second protection layer 700 covers the gate structure 300, the first protection layer 600, the channel region between the gate structure 300 and the source 400, and the channel region between the gate structure 300 and the drain 500, i.e., the first silicon nitride layer 601, the first aluminum nitride layer 602, and the second protection layer 700 cover the sides of the gate structure 300, the thickness and the resistance of the protection layer covering the sides of the gate structure 300 are increased, and the gate leakage current is reduced.
And the first aluminum nitride layer 602 covers the side surface of the gate structure 300 and the surface of the gate structure 300 away from the epitaxial layer 200, in the process of preparing the first silicon nitride layer 601 on the side of the first aluminum nitride layer 602 away from the gate structure 300, patterning the first silicon nitride layer 601 is required, so that the first silicon nitride layer 601 only covers the side surface of the gate structure 300, and when the patterned first silicon nitride layer 601 is formed, the first aluminum nitride layer 602 can be used as a mask pattern for covering the surface of the gate 302 away from the doped iii-v semiconductor layer 301, thereby saving the number of masks and reducing the preparation cost.
Optionally, on the basis of the above technical solution, as shown in fig. 15, fig. 15 is a schematic flow chart included in S270 in fig. 8, and S270 includes:
s2701, a second aluminum nitride layer is formed, wherein the second aluminum nitride layer covers the gate structure, the first protection layer, the channel region between the gate structure and the source electrode, and the channel region between the gate structure and the drain electrode, and a portion of the second aluminum nitride layer covering the channel region between the gate structure and the source electrode and the channel region between the gate structure and the drain electrode is a doped second aluminum nitride layer.
As shown in fig. 16, a second aluminum nitride layer 701 is formed, wherein the second aluminum nitride layer 701 covers the gate structure 300, the first protection layer 600, the channel region between the gate structure 300 and the source 400, and the channel region between the gate structure 300 and the drain 500, and a portion of the second aluminum nitride layer 701 covering the channel region between the gate structure 300 and the source 400 and the channel region between the gate structure 300 and the drain 500 is a doped second aluminum nitride layer 701.
S2702, a second silicon nitride layer is formed on the surface of the second aluminum nitride layer far from the substrate.
As shown in fig. 17, a second silicon nitride layer 702 is formed on the surface of the second aluminum nitride layer 701 remote from the substrate 100.
S2703, a passivation layer is formed on the surface of the second silicon nitride layer far away from the second aluminum nitride layer.
As shown in fig. 7, a passivation layer 703 is formed on a surface of the second silicon nitride layer 702 remote from the second aluminum nitride layer 701.
Specifically, the first protection layer 600, the second aluminum nitride layer 701, the second silicon nitride layer 702, and the passivation layer 703 cover the sides of the gate structure 300, increasing the thickness and resistance of the protection layer covering the sides of the gate structure 300, and reducing the gate leakage current.
And the second aluminum nitride layer 701 is a doped second aluminum nitride layer covering the channel region between the gate structure 300 and the source 400 and the channel region between the gate structure 300 and the drain 500, so that the two-dimensional electron gas concentration of the channel region is improved, and the resistance and the device loss are reduced.
Optionally, on the basis of the above technical solution, as shown in fig. 18, fig. 18 is a flowchart included in S2701 in fig. 15, and S2701 includes:
s2701a, a second aluminum nitride layer is formed in the gate structure, the first protective layer, the channel region between the gate structure and the source electrode, and the channel region between the gate structure and the drain electrode.
As shown in fig. 16, a second aluminum nitride layer 701 is formed at the gate structure 300, the first protective layer 600, the channel region between the gate structure 300 and the source electrode 400, and the channel region between the gate structure 300 and the drain electrode 500.
S2701b, oxygen atoms are doped to a portion of the second aluminum nitride layer covering the channel region between the gate structure and the source electrode and the channel region between the gate structure and the drain electrode to form a second aluminum nitride layer doped with oxygen atoms.
As shown in fig. 16, oxygen atoms are doped to a portion of the second aluminum nitride layer 701 covering the channel region between the gate structure 300 and the source 400 and the channel region between the gate structure 300 and the drain 500 to form a second aluminum nitride layer doped with oxygen atoms.
Specifically, the portion of the second aluminum nitride layer 701 covering the channel region between the gate structure 300 and the source electrode 400 and the channel region between the gate structure 300 and the drain electrode 500 is the second aluminum nitride layer doped with oxygen atoms, which increases the two-dimensional electron gas concentration of the channel region, thereby reducing the resistance and the device loss.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A gallium nitride device, comprising:
a substrate;
the epitaxial layer is positioned on the surface of the substrate;
a gate structure located on a surface of the epitaxial layer remote from the substrate, the gate structure comprising a doped group iii-v semiconductor layer and a gate; the doped III-V semiconductor layer is positioned on the surface of the epitaxial layer far away from the substrate; the grid electrode is positioned on the surface of the doped III-V semiconductor layer, which is far away from the epitaxial layer;
the source electrode is positioned on the surface of the epitaxial layer far away from the substrate;
the drain electrode is positioned on the surface of the epitaxial layer, which is far away from the substrate;
a first protection layer covering the gate structure and covering at least a side surface of the gate structure;
a second protective layer covering the gate structure, the first protective layer, the channel region between the gate structure and the source electrode, and the channel region between the gate structure and the drain electrode, wherein a portion of the second protective layer covering the channel region between the gate structure and the source electrode, and the channel region between the gate structure and the drain electrode includes a doped semiconductor layer.
2. The gallium nitride device of claim 1, wherein the first protective layer comprises a first silicon nitride layer covering sides of the gate structure.
3. The gallium nitride device of claim 1, wherein the first protective layer comprises a first silicon nitride layer and a first aluminum nitride layer;
the first aluminum nitride layer covers the side surface of the gate structure and the surface of the gate structure away from the epitaxial layer;
the first silicon nitride layer is positioned on one side of the first aluminum nitride layer far away from the grid structure, and the orthographic projection of the first silicon nitride layer on the substrate covers the orthographic projection of the side surface of the grid structure on the substrate.
4. A gallium nitride device according to any of claims 1-3, wherein said second protective layer comprises a second aluminum nitride layer, a second silicon nitride layer, and a passivation layer;
the second aluminum nitride layer covers the gate structure, the first protection layer, a channel region between the gate structure and the source electrode and a channel region between the gate structure and the drain electrode, and a portion of the second aluminum nitride layer covering the channel region between the gate structure and the source electrode and the channel region between the gate structure and the drain electrode is a doped second aluminum nitride layer;
the second silicon nitride layer is positioned on the surface of the second aluminum nitride layer, which is far away from the substrate;
the passivation layer is positioned on the surface of the second silicon nitride layer far away from the second aluminum nitride layer.
5. The gallium nitride device of claim 4, wherein the portion of the second aluminum nitride layer that covers the channel region between the gate structure and the source and the channel region between the gate structure and the drain is a second aluminum nitride layer doped with oxygen atoms.
6. A method of fabricating a gallium nitride device, comprising:
providing a substrate;
forming an epitaxial layer on the surface of the substrate;
forming a gate structure on the surface of the epitaxial layer away from the substrate, wherein the gate structure comprises a doped III-V semiconductor layer and a gate; the doped III-V semiconductor layer is positioned on the surface of the epitaxial layer far away from the substrate; the grid electrode is positioned on the surface of the doped III-V semiconductor layer, which is far away from the epitaxial layer;
forming a source electrode on the surface of the epitaxial layer far away from the substrate;
forming a drain electrode on the surface of the epitaxial layer far away from the substrate;
forming a first protection layer, wherein the first protection layer covers the grid structure and at least covers the side face of the grid structure;
forming a second protection layer, wherein the second protection layer covers the gate structure, the first protection layer, a channel region between the gate structure and the source electrode, and a channel region between the gate structure and the drain electrode, and a portion of the second protection layer covering the channel region between the gate structure and the source electrode, and the channel region between the gate structure and the drain electrode comprises a doped semiconductor layer.
7. The method of manufacturing a gallium nitride device according to claim 6, wherein,
forming the first protective layer includes:
a first protective layer is formed including a first silicon nitride layer, wherein the first silicon nitride layer covers sides of the gate structure.
8. The method of manufacturing a gallium nitride device according to claim 6, wherein,
forming the first protective layer includes:
forming a first aluminum nitride layer on the side surface of the gate structure and the surface of the gate structure away from the epitaxial layer;
and forming a first silicon nitride layer on one side of the first aluminum nitride layer far away from the gate structure, wherein the orthographic projection of the first silicon nitride layer on the substrate covers the orthographic projection of the side surface of the gate structure on the substrate.
9. A method of fabricating a gallium nitride device according to any one of claims 6-8, wherein forming the second protective layer comprises:
forming a second aluminum nitride layer, wherein the second aluminum nitride layer covers the gate structure, the first protection layer, a channel region between the gate structure and the source electrode and a channel region between the gate structure and the drain electrode, and a part of the second aluminum nitride layer covering the channel region between the gate structure and the source electrode and the channel region between the gate structure and the drain electrode is a doped second aluminum nitride layer;
forming a second silicon nitride layer on the surface of the second aluminum nitride layer, which is far away from the substrate;
and forming a passivation layer on the surface of the second silicon nitride layer far away from the second aluminum nitride layer.
10. The method of manufacturing a gallium nitride device according to claim 9, wherein,
forming the second aluminum nitride layer includes:
forming a second aluminum nitride layer in the gate structure, the first protective layer, a channel region between the gate structure and the source electrode, and a channel region between the gate structure and the drain electrode;
and doping oxygen atoms in a part of the second aluminum nitride layer covering the channel region between the gate structure and the source electrode and the channel region between the gate structure and the drain electrode to form a second aluminum nitride layer doped with oxygen atoms.
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| CN116169169A (en) * | 2023-01-03 | 2023-05-26 | 中国电子科技集团公司第五十五研究所 | Enhanced GaN HEMTs with low gate leakage current and preparation method thereof |
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| CN116169169A (en) * | 2023-01-03 | 2023-05-26 | 中国电子科技集团公司第五十五研究所 | Enhanced GaN HEMTs with low gate leakage current and preparation method thereof |
| CN116364538A (en) * | 2023-04-23 | 2023-06-30 | 复旦大学 | Preparation method of enhanced gallium nitride power device |
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