CN117438455A - Gallium nitride transistor device with high electron mobility and preparation method thereof - Google Patents
Gallium nitride transistor device with high electron mobility and preparation method thereof Download PDFInfo
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- CN117438455A CN117438455A CN202311407407.1A CN202311407407A CN117438455A CN 117438455 A CN117438455 A CN 117438455A CN 202311407407 A CN202311407407 A CN 202311407407A CN 117438455 A CN117438455 A CN 117438455A
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 171
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 35
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 230000004888 barrier function Effects 0.000 claims abstract description 141
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 230000008719 thickening Effects 0.000 claims description 71
- 238000002161 passivation Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 229910002704 AlGaN Inorganic materials 0.000 claims description 5
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000005137 deposition process Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000005533 two-dimensional electron gas Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002028 premature Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention provides a gallium nitride high electron mobility transistor device and a preparation method thereof. The device includes: a substrate; a buffer layer located on the surface of the substrate; a channel layer located on a surface of the buffer layer away from the substrate; a barrier layer located on a surface of the channel layer remote from the buffer layer; the P-GaN layer is positioned on the surface of the barrier layer, which is far away from the channel layer; a nonpolar insulating layer covering the sidewall of the P-GaN layer; the grid electrode is positioned on the surface of the P-GaN layer, which is far away from the barrier layer; the source electrode is positioned on the surface of the barrier layer far away from the channel layer; and the drain electrode is positioned on the surface of the barrier layer far away from the channel layer. According to the technical scheme provided by the embodiment of the invention, negative defects are prevented from being introduced into the side wall of the P-GaN layer, the pinch-off voltage of a channel below the side wall of the P-GaN layer is improved, and the device characteristics are further improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gallium nitride transistor device with high electron mobility and a preparation method thereof.
Background
The gallium nitride high electron mobility transistor device includes a P-GaN layer located under the gate electrode and between the source and drain electrodes. Under the control of the gate, holes in the P-GaN layer can deplete the two-dimensional electron gas (2 DEG) in the heterojunction, thereby placing the device in a normally-off state. Wherein the heterojunction is composed of a channel layer and a barrier layer.
In the current preparation process of the gallium nitride transistor device with high electron mobility, a whole P-GaN layer covering the barrier layer is formed first, and then the P-GaN layer is located between the source electrode and the drain electrode through dry etching. After dry etching, the barrier layer has more defect states on the surface. The gallium nitride high electron mobility transistor device is a horizontal structure device, the conducting channel is relatively close to the etched surface of the P-GaN layer, and the device characteristics are seriously affected by the surface state. In the prior art, the side wall of the P-GaN layer is covered by a polar insulating layer to improve the surface quality of the barrier layer under the side wall of the P-GaN layer, but the polar insulating layer introduces negative defects to compensate the side wall of the P-GaN layer, so that a channel under the side wall of the P-GaN layer is pinched off in advance, and the device characteristics are affected.
Disclosure of Invention
The invention provides a gallium nitride transistor device with high electron mobility and a preparation method thereof, which are used for avoiding negative defects from being introduced into the side wall of a P-GaN layer, improving pinch-off voltage of a channel below the side wall of the P-GaN layer and further improving device characteristics.
According to an aspect of the present invention, there is provided a gallium nitride high electron mobility transistor device comprising:
a substrate;
the buffer layer is positioned on the surface of the substrate;
a channel layer located on a surface of the buffer layer remote from the substrate;
a barrier layer located on a surface of the channel layer remote from the buffer layer;
the P-GaN layer is positioned on the surface of the barrier layer, which is far away from the channel layer;
a nonpolar insulating layer covering the sidewall of the P-GaN layer;
the grid electrode is positioned on the surface, far away from the barrier layer, of the P-GaN layer;
a source electrode located on a surface of the barrier layer away from the channel layer;
and a drain electrode positioned on the surface of the barrier layer away from the channel layer, wherein the P-GaN layer is positioned between the source electrode and the drain electrode.
Optionally, the orthographic projection area of the grid electrode on the substrate is smaller than the orthographic projection area of the P-GaN layer on the substrate;
the nonpolar insulating layer also covers the surface of the P-GaN layer away from the barrier layer and the grid electrode;
the nonpolar insulating layer is provided with a first gate trench exposing a portion of a surface of the gate electrode remote from the P-GaN layer.
Optionally, a polar insulating layer is further included, the polar insulating layer covering the barrier layer between the source electrode and the nonpolar insulating layer, and the polar insulating layer covering the barrier layer between the drain electrode and the nonpolar insulating layer.
Optionally, the device further comprises a polar insulating layer, wherein the polar insulating layer covers a barrier layer between the source electrode and the nonpolar insulating layer, a barrier layer between the drain electrode and the nonpolar insulating layer;
the polarity insulating layer is provided with a second gate trench, and the second gate trench is connected with the first gate trench.
Optionally, further comprising a passivation layer, a gate interconnect thickening layer, a source interconnect thickening layer, and a drain interconnect thickening layer;
the passivation layer is positioned on one side of the barrier layer away from the channel layer, and is provided with a third gate groove, a source groove and a drain groove;
the gate interconnect thickening layer is connected to the gate through the third gate trench;
the source interconnect thickening layer is connected to the source through the source trench;
the drain interconnect thickening layer is connected to the drain through the drain trench.
Optionally, the nonpolar insulating layer includes silicon oxide or silicon nitride.
Optionally, the polar insulating layer includes at least one of aluminum nitride, N-GaN, N-AlGaN, and N-InAlGaN.
According to another aspect of the present invention, there is provided a method for manufacturing a gallium nitride high electron mobility transistor device, comprising:
providing a substrate;
sequentially forming a buffer layer, a channel layer, a barrier layer and a P-GaN layer on the surface of the substrate;
forming a grid electrode on the surface of the P-GaN layer far away from the barrier layer;
etching the P-GaN layer;
forming a nonpolar insulating layer on the side wall of the P-GaN layer;
forming a source electrode on the surface of the barrier layer away from the channel layer;
a drain electrode is formed on a surface of the barrier layer remote from the channel layer, wherein the P-GaN layer is located between the source electrode and the drain electrode.
Optionally, forming the gate on the surface of the P-GaN layer remote from the barrier layer includes:
forming a grid electrode on the surface, far away from the barrier layer, of the P-GaN layer, wherein the orthographic projection area of the grid electrode on the substrate is smaller than that of the P-GaN layer on the substrate;
the forming of the nonpolar insulating layer on the side wall of the P-GaN layer further comprises:
forming a nonpolar insulating layer on the surface of the P-GaN layer far away from the barrier layer and the surface and the side surface of the grid electrode;
after forming the drain electrode on the surface of the barrier layer away from the channel layer, the method further comprises:
and forming a first gate trench in the nonpolar insulating layer, wherein the first gate trench exposes a part of the surface of the gate, which is far away from the P-GaN layer.
Optionally, before the source is formed on the surface of the barrier layer away from the channel layer, the method further comprises:
forming a polar insulating layer on one side of the barrier layer away from the channel layer;
and removing part of the polar insulating layer, and only reserving the polar insulating layer covering the barrier layer between the source electrode and the nonpolar insulating layer and the polar insulating layer covering the barrier layer between the drain electrode and the nonpolar insulating layer.
Optionally, before the source is formed on the surface of the barrier layer away from the channel layer, the method further comprises:
forming a polar insulating layer on one side of the barrier layer away from the channel layer;
removing a part of the polar insulating layer, leaving only the polar insulating layer covering the barrier layer between the source electrode and the nonpolar insulating layer, and the polar insulating layer covering the barrier layer between the drain electrode and the nonpolar insulating layer and the polar insulating layer covering the nonpolar insulating layer;
after forming the drain electrode on the surface of the barrier layer away from the channel layer, the method further comprises:
and forming a second gate trench connected with the first gate trench on the polar insulating layer.
Optionally, after forming the drain on a surface of the barrier layer away from the channel layer, the method further includes:
forming a passivation layer on a side of the barrier layer away from the channel layer;
forming a third gate trench, a source trench and a drain trench in the passivation layer;
forming a gate interconnect thickening layer connected to the gate through the third gate trench;
forming a source interconnect thickening layer connected to the source through the source trench;
a drain interconnect thickening layer is formed, the drain interconnect thickening layer being connected to the drain through the drain trench.
According to the technical scheme provided by the embodiment of the invention, the nonpolar insulating layer covers the side wall of the P-GaN layer, so that the surface quality of the barrier layer below the side wall of the P-GaN layer is improved, negative charges are not contained in the nonpolar insulating layer, negative defects are not introduced to compensate the side wall of the P-GaN layer, the pinch-off voltage of a channel below the side wall of the P-GaN layer is improved, and the device characteristics are further improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a method for fabricating a gallium nitride high electron mobility transistor device according to the prior art;
FIGS. 2-8 are schematic views of the structure corresponding to the steps in FIG. 1;
fig. 9 is a schematic structural diagram of a gallium nitride high electron mobility transistor device according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of another gallium nitride high electron mobility transistor device provided according to an embodiment of the invention;
fig. 11 is a flowchart of a method for manufacturing a gallium nitride high electron mobility transistor device according to an embodiment of the present invention;
FIGS. 12-15 are schematic views of the structure corresponding to the steps in FIG. 11;
FIG. 16 is a schematic flow chart included in S260 of FIG. 11;
FIGS. 17-18 are schematic views of the structure corresponding to the steps in FIG. 16;
fig. 19 is a schematic flow chart included in S270 in fig. 11;
fig. 20 is a schematic diagram of a structure corresponding to S2701 in fig. 19;
FIG. 21 is a schematic diagram of another process included in S260 of FIG. 11;
fig. 22 is a schematic diagram of a structure corresponding to S2604 in fig. 21.
Fig. 23 is a schematic diagram of the structure corresponding to S2701 in fig. 19.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or means is not necessarily limited to those steps or means that are expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art above, the channel under the P-GaN layer sidewall of the gallium nitride high electron mobility transistor device of the prior art is pinched off in advance due to the introduction of negative defects, affecting the device characteristics. As shown in fig. 1 and fig. 2-8, the inventors have found through careful study that the method for manufacturing a gallium nitride high electron mobility transistor device according to the prior art is as follows: s110, providing a substrate 10; s120, sequentially forming a buffer layer 20, a channel layer 30, a barrier layer 40, a P-GaN layer 50 and a gate electrode 60 on the surface of the substrate 10; s130, performing a dry etching process on the P-GaN layer 50; s140, forming a polar insulating layer 70 covering the barrier layer 40 and the P-GaN layer 50, wherein the polar insulating layer 70 covers the sidewalls of the P-GaN layer 50; s150, forming a source electrode 61 and a drain electrode 62, wherein the P-GaN layer 50 is positioned between the source electrode 61 and the drain electrode 62; s160, forming a passivation layer 80, and forming a gate groove, a source groove and a drain groove on the passivation layer 80; s170, a gate interconnect thickening layer 90 is formed in the gate trench, a source interconnect thickening layer 91 is formed in the source trench, and a drain interconnect thickening layer 92 is formed in the drain trench.
The P-GaN layer 50 between the source electrode 61 and the drain electrode 62 is formed by dry etching, and after dry etching, the surface of the barrier layer 40 has many defect states. The gallium nitride high electron mobility transistor device is a device with a horizontal structure, the conducting channel is close to the etched surface of the P-GaN layer 50, and the device characteristics are seriously affected by the surface state. The polar insulating layer 70 covers the sidewalls of the P-GaN layer 50 to improve the surface quality of the barrier layer 40 under the sidewalls of the P-GaN layer 50, but the polar insulating layer 70 introduces negative defects to compensate the sidewalls of the P-GaN layer 50, resulting in premature pinch-off of the channel under the sidewalls of the P-GaN layer 50, affecting device characteristics.
In order to avoid negative defects introduced into the side wall of the P-GaN layer, improve pinch-off voltage of a channel below the side wall of the P-GaN layer and further improve device characteristics, the embodiment of the invention provides the following technical scheme:
as shown in fig. 9, fig. 9 is a gallium nitride high electron mobility transistor device according to an embodiment of the invention, including: a substrate 01; a buffer layer 02, the buffer layer 02 being located on the surface of the substrate 01; a channel layer 03, the channel layer 03 being located on a surface of the buffer layer 02 remote from the substrate 01; a barrier layer 04, the barrier layer 04 being located on a surface of the channel layer 03 remote from the buffer layer 02; the P-GaN layer 05, the P-GaN layer 05 is positioned on the surface of the barrier layer 04 away from the channel layer 03; a nonpolar insulating layer 08, the nonpolar insulating layer 08 covering the sidewalls of the P-GaN layer 05; a gate 06, the gate 06 being located on a surface of the P-GaN layer 05 remote from the barrier layer 04; a source electrode 061, the source electrode 061 being located on a surface of the barrier layer 04 remote from the channel layer 03; a drain electrode 062, the drain electrode 062 being located on a surface of the barrier layer 04 remote from the channel layer 03, and a P-GaN layer 05 being located between the source electrode 061 and the drain electrode 062.
According to the technical scheme provided by the embodiment of the invention, the nonpolar insulating layer 07 covers the side wall of the P-GaN layer 05, so that the surface quality of the barrier layer 04 under the side wall of the P-GaN layer 05 is improved, negative charges are not contained in the nonpolar insulating layer 07, negative defects are not introduced to compensate the side wall of the P-GaN layer 05, pinch-off voltage of a channel under the side wall of the P-GaN layer 05 is improved, and the device characteristics are further improved.
Optionally, on the basis of the above technical solution, as shown in fig. 9, the orthographic projection area of the gate 06 on the substrate 01 is smaller than the orthographic projection area of the P-GaN layer 05 on the substrate 01; the nonpolar insulating layer 07 also covers the surface of the P-GaN layer 05 remote from the barrier layer 04 and the gate electrode 06; the nonpolar insulating layer 07 is provided with a first gate trench exposing a portion of the surface of the gate 06 remote from the P-GaN layer 05.
Specifically, in an ideal situation, the orthographic projection area of the gate 06 on the substrate 01 may be equal to the orthographic projection area of the P-GaN layer 05 on the substrate 01. However, in order to avoid the problem that the gate 06 cannot be completely bonded to the preset size of the P-GaN layer 05 during etching, resulting in increased gate leakage, the orthographic projection area of the gate 06 on the substrate 01 is generally smaller than the orthographic projection area of the P-GaN layer 05 on the substrate 01.
In this embodiment, on the basis that the nonpolar insulating layer 07 covers the side wall of the P-GaN layer 05, the nonpolar insulating layer 07 also covers the surface of the P-GaN layer away from the barrier layer 04 and the gate 06, so that the area of the nonpolar insulating layer 07 is increased, negative defects can be further avoided to compensate the side wall of the P-GaN layer 05 and the surface away from the barrier layer 04, pinch-off voltage of a channel below the side wall of the P-GaN layer 05 is further improved, and device characteristics are further improved.
The arrangement of the first gate trench facilitates the fabrication of a conductive structure that leads out the electrical signal of the gate 06.
Optionally, on the basis of the above technical solution, as shown in fig. 9, the gallium nitride high electron mobility transistor device further includes a polar insulating layer 08, the polar insulating layer 08 covers the barrier layer 04 between the source electrode 061 and the nonpolar insulating layer 07, and the polar insulating layer 08 covers the barrier layer 04 between the drain electrode 062 and the nonpolar insulating layer 07.
Specifically, the polar insulating layer 08 covers the barrier layer 04 between the source electrode 061 and the nonpolar insulating layer 07, and the polar insulating layer 08 covers the barrier layer 04 between the drain electrode 062 and the nonpolar insulating layer 07, so that the surface quality of the barrier layer 04 can be improved, and since negative charges are contained in the polar insulating layer 08, the polar insulating layer 08 and the barrier layer 04 can form a two-dimensional electron gas structure, the electron concentration in a channel can be increased, and the device performance is further improved.
Alternatively, on the basis of the above technical solution, as shown in fig. 10, fig. 10 is a schematic structural diagram of another gallium nitride high electron mobility transistor device provided according to an embodiment of the present invention, where the gallium nitride high electron mobility transistor device further includes a polar insulating layer 08, and the polar insulating layer 08 covers the barrier layer 04 between the source electrode 061 and the nonpolar insulating layer 07, the barrier layer 04 between the drain electrode 062 and the nonpolar insulating layer 07, and the nonpolar insulating layer 07; the polar insulating layer 08 is provided with a second gate trench,
the second gate trench is connected to the first gate trench.
Specifically, the area of the polar insulating layer 08 is further increased, and the thickness of the insulating layer above the gate 06 is further increased, so that the etching difficulty of the insulating layer above the gate 06 is reduced, the damage to the gate 06 and the P-GaN layer 05 below the gate 06 during etching of the insulating layer above the gate 06 is avoided, and the device performance is further improved. The arrangement of the second grid groove is convenient for manufacturing a conductive structure for leading out the electric signal of the grid 06.
Optionally, on the basis of the above technical solutions, as shown in fig. 9 and 10, the gallium nitride high electron mobility transistor device further includes a passivation layer 09, a gate interconnection thickening layer 091, a source interconnection thickening layer 092, and a drain interconnection thickening layer 093; the passivation layer 09 is located on one side of the barrier layer 04 away from the channel layer 03, and the passivation layer 09 is provided with a third gate trench, a source trench and a drain trench; the gate interconnect thickening layer 091 is connected to the gate 06 through the third gate trench; source interconnect thickening layer 092 is connected by source trench and source 061; the drain interconnect thickening layer 093 is connected by the drain trench and the drain 062.
Specifically, the passivation layer 09 can function as an insulating gate interconnect thickening layer 091, a source interconnect thickening layer 092, and a drain interconnect thickening layer 093. The gate interconnect thickening layer 091 is used to extract the electrical signal of the gate 06, the source interconnect thickening layer 092 is used to extract the electrical signal of the source 061, and the drain interconnect thickening layer 093 is used to extract the electrical signal of the drain 062.
Alternatively, on the basis of the above technical solution, the nonpolar insulating layer 07 includes silicon oxide or silicon nitride, which does not generate negative charges under polar conditions, and when it covers the sidewall of the P-GaN layer 05, negative defects are not introduced to compensate the sidewall of the P-GaN layer 05, so that pinch-off voltage of a channel under the sidewall of the P-GaN layer 05 is improved, and device characteristics are further improved.
Optionally, based on the above technical solution, the polar insulating layer 08 includes at least one of aluminum nitride, N-GaN, N-AlGaN, and N-InAlGaN. At least one of aluminum nitride, N-GaN, N-AlGaN and N-InAlGaN can generate negative charges under the polar condition, and when it covers the barrier layer 04 between the source electrode 061 and the nonpolar insulating layer 07 and covers the barrier layer 04 between the drain electrode 062 and the nonpolar insulating layer 07, a two-dimensional electron gas structure can be formed with the barrier layer 04 while improving the surface quality of the barrier layer 04, so that the electron concentration in the channel can be increased, and the device performance can be further improved.
The embodiment of the invention also provides a preparation method of the gallium nitride high electron mobility transistor device, as shown in fig. 11, comprising the following steps:
s210, providing a substrate.
As shown in fig. 12, a substrate 01 is provided. By way of example, the substrate 01 may be selected from any one of silicon, gallium nitride, and sapphire.
S220, sequentially forming a buffer layer, a channel layer, a barrier layer and a P-GaN layer on the surface of the substrate.
As shown in fig. 12, a buffer layer 02, a channel layer 03, a barrier layer 04, and a P-GaN layer 05 are sequentially formed on the surface of a substrate 01. Illustratively, the buffer layer 02 includes one or more of AlN, gaN, alGaN and InGaN. The channel layer 03 includes one or more of GaN, alGaN, and InGaN. GaN is preferred. The barrier layer 04 may be AlGaN.
And S230, forming a grid electrode on the surface of the P-GaN layer far away from the barrier layer.
As shown in fig. 13, a gate 06 is formed on the surface of the P-GaN layer 05 remote from the barrier layer 04.
S240, etching the P-GaN layer.
As shown in fig. 14, the P-GaN layer 05 is subjected to an etching process by a dry etching process. Specifically, the channel layer 03 and the barrier layer 04 form a heterojunction, the P-GaN layer 05 contacts the gate 06, and holes in the P-GaN layer 05 can deplete two-dimensional electron gas in the heterojunction, so that the device is in a normally-off state.
S250, forming a nonpolar insulating layer on the side wall of the P-GaN layer.
As shown in fig. 15, a nonpolar insulating layer 07 is formed on the sidewall of the P-GaN layer 05. The drawing does not show the drawing in which the nonpolar insulating layer 07 covers only the side wall of the P-GaN layer 05.
And S260, forming a source electrode on the surface of the barrier layer away from the channel layer.
As shown in fig. 9, a source electrode 061 is formed on the surface of the barrier layer 04 remote from the channel layer 03.
And S270, forming a drain electrode on the surface of the barrier layer, which is far away from the channel layer, wherein the P-GaN layer is positioned between the source electrode and the drain electrode.
As shown in fig. 9, a drain electrode 062 is formed on the surface of the barrier layer 04 remote from the channel layer 03, and a p-GaN layer 05 is located between the source electrode 061 and the drain electrode 062.
According to the technical scheme provided by the embodiment of the invention, the nonpolar insulating layer 07 is formed on the side wall of the P-GaN layer 05, so that the surface quality of the barrier layer 04 under the side wall of the P-GaN layer 05 is improved, negative charges are not contained in the nonpolar insulating layer 07, negative defects are not introduced to compensate the side wall of the P-GaN layer 05, pinch-off voltage of a channel under the side wall of the P-GaN layer 05 is improved, and the device characteristics are further improved.
Optionally, on the basis of the above technical solution, forming the gate electrode on the surface of the P-GaN layer away from the barrier layer in S230 includes:
and forming a grid electrode on the surface of the P-GaN layer far away from the barrier layer, wherein the orthographic projection area of the grid electrode on the substrate is smaller than that of the P-GaN layer on the substrate.
As shown in fig. 13, a gate 06 is formed on a surface of the P-GaN layer 05 away from the barrier layer 04, and as shown in fig. 14, the orthographic projection area of the gate 06 on the substrate 01 is smaller than the orthographic projection area of the P-GaN layer 05 on the substrate 01. The P-GaN layer 05 is in contact with the gate 06, and holes in the P-GaN layer 05 can deplete the two-dimensional electron gas (2 DEG) in the heterojunction, thereby placing the device in a normally-off state. In order to avoid the problems of increased gate leakage and the like caused by the fact that the gate 06 cannot be completely attached to the preset size of the P-GaN layer 05 in the etching process of the gate 06, the orthographic projection area of the gate 06 on the substrate 01 is generally set to be smaller than the orthographic projection area of the P-GaN layer 05 on the substrate 01.
S250 further includes, when forming the nonpolar insulating layer on the sidewall of the P-GaN layer:
and forming nonpolar insulating layers on the surface of the P-GaN layer far away from the barrier layer and the surface and the side surface of the grid electrode.
As shown in fig. 15, the nonpolar insulating layer 07 is formed on the surface of the P-GaN layer 05 away from the barrier layer 04 and the surface and side surfaces of the gate 06, so that the nonpolar insulating layer 07 also covers the surface of the P-GaN layer away from the barrier layer 04 and the gate 06 on the basis that the nonpolar insulating layer 07 covers the side wall of the P-GaN layer 05, thereby increasing the area of the nonpolar insulating layer 07, further avoiding negative defects to compensate the side wall of the P-GaN layer 05 and the surface away from the barrier layer 04, further improving the pinch-off voltage of the channel under the side wall of the P-GaN layer 05, and further improving the device characteristics.
S270 further includes, after the surface of the barrier layer remote from the channel layer forms the drain:
and forming a first gate trench in the nonpolar insulating layer, wherein the first gate trench exposes a part of the surface of the gate away from the P-GaN layer.
As shown in fig. 9, a first gate trench is formed in the nonpolar insulating layer 07, the first gate trench exposing a portion of the surface of the gate 06 remote from the P-GaN layer 05. The arrangement of the first gate trench facilitates the fabrication of a conductive structure that leads out the electrical signal of the gate 06.
Optionally, in an embodiment based on the above technical solution, as shown in fig. 16, fig. 16 is a schematic flow chart included in S260 in fig. 11, and S260 further includes, before the surface of the barrier layer away from the channel layer forms the source electrode:
s2601, forming a polar insulating layer on one side of the barrier layer away from the channel layer.
As shown in fig. 17, a polar insulating layer 08 is formed on the side of the barrier layer 04 remote from the channel layer 03.
S2602, removing a part of the polar insulating layer, leaving only the polar insulating layer covering the barrier layer between the source electrode and the nonpolar insulating layer, and the polar insulating layer covering the barrier layer between the drain electrode and the nonpolar insulating layer.
As shown in fig. 18, a part of the polar insulating layer 08 is removed, and only the polar insulating layer covering the barrier layer between the source electrode and the nonpolar insulating layer and the polar insulating layer covering the barrier layer between the drain electrode and the nonpolar insulating layer remain.
As shown in fig. 18, a source electrode 061 is formed on the surface of the barrier layer 04 remote from the channel layer 03. A drain electrode 062 is formed on the surface of the barrier layer 04 remote from the channel layer 03.
As shown in fig. 19, fig. 19 is a schematic flow chart included in S270 in fig. 11, and S270 further includes, after forming the drain on the surface of the barrier layer away from the channel layer:
s2701, a passivation layer is formed on a side of the barrier layer away from the channel layer.
As shown in fig. 20, a passivation layer 09 is formed on the side of the barrier layer 04 remote from the channel layer 03.
S2702, a third gate trench, a source trench, and a drain trench are formed in the passivation layer.
As shown in fig. 9, a third gate trench, a source trench, and a drain trench are formed in the passivation layer 09. Note that, in fig. 9, the first gate trench in the nonpolar insulating layer 07 and the third gate trench of the passivation layer 09 may be formed at the same time.
S2703, a gate interconnect thickening layer is formed, the gate interconnect thickening layer being connected to the gate through a third gate trench.
As shown in fig. 9, a gate interconnect thickening layer 091 is formed by a metal film layer deposition process, and the gate interconnect thickening layer 091 is connected to the gate 06 through the third gate trench.
S2704, a source interconnect thickening layer is formed, the source interconnect thickening layer being connected to the source via a source trench.
As shown in fig. 9, a source interconnect thickening layer 092 is formed by a metal film layer deposition process, and the source interconnect thickening layer 092 is connected by a source trench and a source 061.
S2705, a drain interconnect thickening layer is formed, the drain interconnect thickening layer being connected to the drain via the drain trench.
As shown in fig. 9, the drain interconnect thickening layer 093 is formed by a metal film layer deposition process, and the drain interconnect thickening layer 093 is connected by the drain trench and the drain 062.
Specifically, the passivation layer 09 in this embodiment may function as an insulating gate interconnect thickening layer 091, a source interconnect thickening layer 092, and a drain interconnect thickening layer 093. The gate interconnect thickening layer 091 is used to extract the electrical signal of the gate 06, the source interconnect thickening layer 092 is used to extract the electrical signal of the source 061, and the drain interconnect thickening layer 093 is used to extract the electrical signal of the drain 062.
In another embodiment, as shown in fig. 21, fig. 21 is another schematic flow chart included in S260 in fig. 11, where S260 further includes, before the surface of the barrier layer away from the channel layer forms the source:
and S2603, forming a polar insulating layer on one side of the barrier layer away from the channel layer.
As shown in fig. 17, a polar insulating layer 08 is formed on the side of the barrier layer 04 remote from the channel layer 03.
S2604, removing a part of the polar insulating layer, and leaving only the polar insulating layer covering the barrier layer between the source electrode and the nonpolar insulating layer, and the polar insulating layer covering the barrier layer between the drain electrode and the nonpolar insulating layer, and the polar insulating layer covering the nonpolar insulating layer.
As shown in fig. 22, a part of the polar insulating layer 08 is removed, and only the polar insulating layer 08 covering the barrier layer 04 between the source electrode 061 and the nonpolar insulating layer 07, and the polar insulating layer 08 covering the barrier layer 04 between the drain electrode 062 and the nonpolar insulating layer 07 and the polar insulating layer 08 covering the nonpolar insulating layer 07 remain.
As shown in fig. 22, a source electrode 061 is formed on the surface of the barrier layer 04 remote from the channel layer 03. A drain electrode 062 is formed on the surface of the barrier layer 04 remote from the channel layer 03.
S270 further includes, after the surface of the barrier layer remote from the channel layer forms the drain:
a second gate trench connected to the first gate trench is formed in the polarity insulating layer.
As shown in fig. 10, a second gate trench connected to the first gate trench is formed in the polarity insulating layer 08.
Specifically, the area of the polar insulating layer 08 is further increased, and the thickness of the insulating layer above the gate 06 is further increased, so that the etching difficulty of the insulating layer above the gate 06 is reduced, the damage to the gate 06 and the P-GaN layer 05 below the gate 06 during etching of the insulating layer above the gate 06 is avoided, and the device performance is further improved. The arrangement of the second grid groove is convenient for manufacturing a conductive structure for leading out the electric signal of the grid 06.
As shown in fig. 19, S270 further includes, after forming the drain electrode on the surface of the barrier layer away from the channel layer:
s2701, a passivation layer is formed on a side of the barrier layer away from the channel layer.
As shown in fig. 23, a passivation layer 09 is formed on the side of the barrier layer 04 remote from the channel layer 03.
S2702, a third gate trench, a source trench, and a drain trench are formed in the passivation layer.
As shown in fig. 10, a third gate trench, a source trench, and a drain trench are formed in the passivation layer 09. In fig. 10, the second gate trench of the polar insulating layer 08, the first gate trench of the nonpolar insulating layer 07, and the third gate trench of the passivation layer 09 may be formed at the same time.
S2703, a gate interconnect thickening layer is formed, the gate interconnect thickening layer being connected to the gate through a third gate trench.
As shown in fig. 10, a gate interconnect thickening layer 091 is formed by a metal film layer deposition process, and the gate interconnect thickening layer 091 is connected to the gate 06 through the third gate trench.
S2704, a source interconnect thickening layer is formed, the source interconnect thickening layer being connected to the source via a source trench.
As shown in fig. 10, a source interconnect thickening layer 092 is formed by a metal film layer deposition process, and the source interconnect thickening layer 092 is connected by a source trench and a source 061.
S2705, a drain interconnect thickening layer is formed, the drain interconnect thickening layer being connected to the drain via the drain trench.
As shown in fig. 10, the drain interconnect thickening layer 093 is formed by a metal film layer deposition process, and the drain interconnect thickening layer 093 is connected by the drain trench and the drain 062.
Specifically, the passivation layer 09 in this embodiment may function as an insulating gate interconnect thickening layer 091, a source interconnect thickening layer 092, and a drain interconnect thickening layer 093. The gate interconnect thickening layer 091 is used to extract the electrical signal of the gate 06, the source interconnect thickening layer 092 is used to extract the electrical signal of the source 061, and the drain interconnect thickening layer 093 is used to extract the electrical signal of the drain 062.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (12)
1. A gallium nitride high electron mobility transistor device, comprising:
a substrate;
the buffer layer is positioned on the surface of the substrate;
a channel layer located on a surface of the buffer layer remote from the substrate;
a barrier layer located on a surface of the channel layer remote from the buffer layer;
the P-GaN layer is positioned on the surface of the barrier layer, which is far away from the channel layer;
a nonpolar insulating layer covering the sidewall of the P-GaN layer;
the grid electrode is positioned on the surface, far away from the barrier layer, of the P-GaN layer;
a source electrode located on a surface of the barrier layer away from the channel layer;
and a drain electrode positioned on the surface of the barrier layer away from the channel layer, wherein the P-GaN layer is positioned between the source electrode and the drain electrode.
2. The gallium nitride high electron mobility transistor device of claim 1, wherein a forward projected area of the gate electrode at the substrate is smaller than a forward projected area of the P-GaN layer at the substrate;
the nonpolar insulating layer also covers the surface of the P-GaN layer away from the barrier layer and the grid electrode;
the nonpolar insulating layer is provided with a first gate trench exposing a portion of a surface of the gate electrode remote from the P-GaN layer.
3. A gallium nitride high electron mobility transistor device according to claim 1 or 2, further comprising a polar insulating layer covering the barrier layer between the source and the non-polar insulating layer, and the polar insulating layer covering the barrier layer between the drain and the non-polar insulating layer.
4. The gallium nitride high electron mobility transistor device of claim 2, further comprising a polar insulating layer covering the barrier layer between the source and the nonpolar insulating layer, the barrier layer between the drain and the nonpolar insulating layer, and the nonpolar insulating layer;
the polarity insulating layer is provided with a second gate trench, and the second gate trench is connected with the first gate trench.
5. The gallium nitride high electron mobility transistor device of claim 1, further comprising a passivation layer, a gate interconnect thickening layer, a source interconnect thickening layer, and a drain interconnect thickening layer;
the passivation layer is positioned on one side of the barrier layer away from the channel layer, and is provided with a third gate groove, a source groove and a drain groove;
the gate interconnect thickening layer is connected to the gate through the third gate trench;
the source interconnect thickening layer is connected to the source through the source trench;
the drain interconnect thickening layer is connected to the drain through the drain trench.
6. The gallium nitride high electron mobility transistor device of claim 1, wherein the nonpolar insulating layer comprises silicon oxide or silicon nitride.
7. A gallium nitride high electron mobility transistor device according to claim 3, wherein said polar insulating layer comprises at least one of aluminum nitride, N-GaN, N-AlGaN, and N-InAlGaN.
8. A method for fabricating a gallium nitride high electron mobility transistor device, comprising:
providing a substrate;
sequentially forming a buffer layer, a channel layer, a barrier layer and a P-GaN layer on the surface of the substrate;
forming a grid electrode on the surface of the P-GaN layer far away from the barrier layer;
etching the P-GaN layer;
forming a nonpolar insulating layer on the side wall of the P-GaN layer;
forming a source electrode on the surface of the barrier layer away from the channel layer;
and forming a drain electrode on the surface of the barrier layer away from the channel layer, wherein the P-GaN layer is positioned between the source electrode and the drain electrode.
9. The method of fabricating a GaN hemt device of claim 8, wherein forming a gate electrode on a surface of said P-GaN layer remote from said barrier layer comprises:
forming a grid electrode on the surface, far away from the barrier layer, of the P-GaN layer, wherein the orthographic projection area of the grid electrode on the substrate is smaller than that of the P-GaN layer on the substrate;
the forming of the nonpolar insulating layer on the side wall of the P-GaN layer further comprises:
forming a nonpolar insulating layer on the surface of the P-GaN layer far away from the barrier layer and the surface and the side surface of the grid electrode;
after forming the drain electrode on the surface of the barrier layer away from the channel layer, the method further comprises:
and forming a first gate trench in the nonpolar insulating layer, wherein the first gate trench exposes a part of the surface of the gate, which is far away from the P-GaN layer.
10. The method of manufacturing a gallium nitride high electron mobility transistor device according to claim 8 or 9, further comprising, before forming a source electrode on a surface of the barrier layer remote from the channel layer:
forming a polar insulating layer on one side of the barrier layer away from the channel layer;
and removing part of the polar insulating layer, and only reserving the polar insulating layer covering the barrier layer between the source electrode and the nonpolar insulating layer and the polar insulating layer covering the barrier layer between the drain electrode and the nonpolar insulating layer.
11. The method of fabricating a gallium nitride high electron mobility transistor device according to claim 9, further comprising, prior to forming a source electrode on a surface of the barrier layer remote from the channel layer:
forming a polar insulating layer on one side of the barrier layer away from the channel layer;
removing a part of the polar insulating layer, leaving only the polar insulating layer covering the barrier layer between the source electrode and the nonpolar insulating layer, and the polar insulating layer covering the barrier layer between the drain electrode and the nonpolar insulating layer and the polar insulating layer covering the nonpolar insulating layer;
after forming the drain electrode on the surface of the barrier layer away from the channel layer, the method further comprises:
and forming a second gate trench connected with the first gate trench on the polar insulating layer.
12. The method of manufacturing a gallium nitride high electron mobility transistor device according to claim 8, further comprising, after forming a drain on a surface of the barrier layer remote from the channel layer:
forming a passivation layer on a side of the barrier layer away from the channel layer;
forming a third gate trench, a source trench and a drain trench in the passivation layer;
forming a gate interconnect thickening layer connected to the gate through the third gate trench;
forming a source interconnect thickening layer connected to the source through the source trench;
a drain interconnect thickening layer is formed, the drain interconnect thickening layer being connected to the drain through the drain trench.
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| CN117894835B (en) * | 2024-03-14 | 2024-05-17 | 英诺赛科(苏州)半导体有限公司 | Gallium nitride semiconductor device and preparation method thereof |
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