CN117373923A - Gallium nitride transistor device with high electron mobility and preparation method thereof - Google Patents
Gallium nitride transistor device with high electron mobility and preparation method thereof Download PDFInfo
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- CN117373923A CN117373923A CN202311446661.2A CN202311446661A CN117373923A CN 117373923 A CN117373923 A CN 117373923A CN 202311446661 A CN202311446661 A CN 202311446661A CN 117373923 A CN117373923 A CN 117373923A
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 146
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 38
- 238000002360 preparation method Methods 0.000 title abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 271
- 239000011241 protective layer Substances 0.000 claims abstract description 126
- 238000005530 etching Methods 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 230000004888 barrier function Effects 0.000 claims abstract description 30
- 238000001039 wet etching Methods 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 238000002161 passivation Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a gallium nitride transistor device with high electron mobility and a preparation method thereof. The preparation method of the gallium nitride high electron mobility transistor device comprises the following steps: providing a substrate, wherein the substrate comprises a gate region; sequentially forming a buffer layer, a channel layer, a barrier layer, a P-GaN layer, a first protective layer and a second protective layer on the surface of the substrate, wherein the P-GaN layer, the first protective layer and the second protective layer are positioned in a grid region; etching the second protective layer to form a first grid groove so as to expose the first protective layer; etching the first protective layer through a wet etching process to form a second grid groove so as to expose the P-GaN layer; forming a grid electrode on the surface of the P-GaN layer far away from the substrate; and forming a source electrode and a drain electrode on the surface of the barrier layer away from the substrate. The technical scheme provided by the embodiment of the invention avoids the damage to the surface of the P-GaN layer.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a gallium nitride transistor device with high electron mobility and a preparation method thereof.
Background
The gallium nitride high electron mobility transistor (GaN HEMT) device has excellent device performance and wide application prospect in the fields of high frequency and high power. The gallium nitride high electron mobility transistor device comprises a heterojunction formed by a channel layer and a barrier layer, wherein a P-GaN layer is positioned in a gate region and is in contact with the gate, and holes in the P-GaN layer can deplete two-dimensional electron gas (2 DEG) in the heterojunction, so that the device is in a normally-off state.
However, the surface of the P-GaN layer is easily damaged by the preparation process in the prior art, so that the problems of surface states and trap states are brought, and the grid leakage current of the device is increased, and the performance of the device is affected.
Disclosure of Invention
The application provides a gallium nitride high electron mobility transistor device and a preparation method thereof, so as to avoid damage to the surface of a P-GaN layer.
According to an aspect of the present invention, there is provided a method for manufacturing a gallium nitride high electron mobility transistor device, comprising:
providing a substrate, wherein the substrate comprises a gate region;
sequentially forming a buffer layer, a channel layer, a barrier layer, a P-GaN layer, a first protective layer and a second protective layer on the surface of the substrate, wherein the P-GaN layer, the first protective layer and the second protective layer are positioned in a grid region;
etching the second protective layer to form a first grid groove so as to expose the first protective layer;
etching the first protective layer through a wet etching process to form a second grid groove so as to expose the P-GaN layer;
forming a grid electrode on the surface of the P-GaN layer, which is far away from the substrate;
and forming a source electrode and a drain electrode on the surface of the barrier layer away from the substrate.
Optionally, the materials of the first protective layer and the second protective layer are the same, and the first protective layer and the second protective layer are prepared simultaneously through the same process.
Optionally, the first protective layer includes at least one first sub-protective layer, and the second protective layer includes at least one second sub-protective layer.
Optionally, performing etching treatment on the second protection layer to form a first gate trench, so as to expose the first protection layer, where the forming includes:
and etching the second protective layer through a dry etching process to form a first grid groove so as to expose the first protective layer.
Optionally, performing etching treatment on the second protection layer to form a first gate trench, so as to expose the first protection layer, where the forming includes:
and etching the second protective layer through a wet etching process to form a first grid groove so as to expose the first protective layer.
Optionally, the substrate further comprises a non-gate region surrounding the gate region;
sequentially forming a buffer layer, a channel layer, a barrier layer, a P-GaN layer, a first protection layer and a second protection layer on the surface of the substrate, wherein the steps comprise:
sequentially forming a buffer layer, a channel layer, a barrier layer, a P-GaN layer, a first protective layer and a second protective layer on the surface of the substrate;
removing the P-GaN layer located in the non-gate region, removing the first protection layer located in the non-gate region, removing the second protection layer located in the non-gate region, and removing the second protection layer located at the edge of the gate region, so that the P-GaN layer, the first protection layer and the second protection layer are located in the gate region.
Optionally, etching the second protection layer to form a first gate trench, and before exposing the first protection layer, further including:
forming a passivation layer on the surface of the barrier layer away from the substrate, wherein the passivation layer is in contact with the side surface of the P-GaN layer, the side surface of the first protection layer and the side surface of the second protection layer;
forming a source and a drain on a surface of the barrier layer remote from the substrate includes:
forming a source trench and a drain trench within the passivation layer;
forming a source electrode in the source electrode groove;
and forming a drain electrode in the drain electrode groove.
Optionally, etching the first protection layer by a wet etching process to form a second gate trench, so as to expose the P-GaN layer, where the forming includes:
and removing the first protection layer positioned in the grid electrode region through a wet etching process, and reserving the first protection layer positioned at the edge of the grid electrode region to form a second grid electrode groove so as to expose part of the P-GaN layer.
Optionally, the second protection layer is an amorphous silicon layer.
Optionally, the first protective layer is an oxide layer.
Optionally, the orthographic projection of the first gate trench on the substrate and the orthographic projection of the second gate trench on the substrate coincide.
According to another aspect of the present invention, there is provided a gallium nitride high electron mobility transistor device, prepared by any one of the preparation methods of gallium nitride high electron mobility transistor devices provided by the present invention.
According to the technical scheme provided by the embodiment of the invention, the first grid groove and the second grid groove are sequentially obtained by etching the second protective layer and the first protective layer on the surface of the P-GaN layer step by step, so that the grid groove with the grid placed in the grid area is obtained. When the second protective layer is etched, the first protective layer covers the P-GaN layer, and the first protective layer can protect the surface of the P-GaN layer from being damaged; and etching the first protective layer by adopting a wet etching process to obtain a second grid groove, and selecting etching solutions with different etching ratios because materials of the first protective layer and the P-GaN layer are different, so that the damage of the etching solution to the surface of the P-GaN layer can be avoided. In summary, the preparation method provided by the embodiment of the invention can avoid the damage of the corrosive liquid to the surface of the P-GaN layer, thereby avoiding the problems of the surface state and the trap state of the P-GaN layer, reducing the gate leakage current of the device and improving the performance of the device.
It should be understood that the description of this section is not intended to identify key or critical features of the embodiments of the application or to delineate the scope of the application. Other features of the present application will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a gallium nitride high electron mobility transistor device according to the prior art;
fig. 2 to fig. 5 are schematic structural diagrams corresponding to each step of a flow chart of a method for manufacturing a gallium nitride high electron mobility transistor device according to the prior art;
fig. 6 is a schematic flow chart of a method for manufacturing a gallium nitride high electron mobility transistor device according to an embodiment of the present invention;
fig. 7-14 are flowcharts corresponding to steps in a method for manufacturing a gallium nitride high electron mobility transistor device according to an embodiment of the present invention;
fig. 15 is a schematic flow chart included in S220 in fig. 6;
fig. 16 is a schematic flow chart included in S260 in fig. 6.
Detailed Description
In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or means is not necessarily limited to those steps or means that are expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, the surface of the P-GaN layer is easily damaged by the preparation process in the prior art, so that the problems of the surface state and the trap state are brought, and the gate leakage current of the device is increased, thereby affecting the performance of the device. The inventors have found through careful study that the method for manufacturing the gallium nitride high electron mobility transistor device in the prior art, as shown in fig. 1 and fig. 2 to 5, comprises the following steps: s110, providing a substrate 01, wherein the substrate 01 comprises a gate region. S120, sequentially forming a buffer layer 02, a channel layer 03, a barrier layer 04 and a P-GaN layer 05 on the surface of the substrate 01, wherein the P-GaN layer 05 is located in the gate region. S130, forming a passivation layer 06 to cover the barrier layer 04 and the P-GaN layer 05. And S140, etching the passivation layer 06 by adopting a dry etching process to form a gate trench T1, a source trench T2 and a drain trench T3. And S150, forming a gate G in the gate groove T1, forming a source S in the source groove T2, and forming a drain D in the drain groove T3. In the above steps, in the process of etching the passivation layer 06, a dry etching process is adopted to form the gate trench T1, damage is inevitably caused to the surface of the P-GaN layer 05 located in the gate region, so that the problems of surface states and trap states are brought, and the gate leakage current of the device is increased, so that the performance of the device is affected.
Aiming at the technical problems, the embodiment of the invention provides the following technical scheme:
as shown in fig. 6, fig. 6 is a schematic flow chart of a method for manufacturing a gallium nitride high electron mobility transistor device according to an embodiment of the invention, wherein the method for manufacturing a gallium nitride high electron mobility transistor device includes the following steps:
s210, providing a substrate, wherein the substrate comprises a gate region.
As shown in fig. 7, a substrate 10 is provided, the substrate 10 including a gate region P1. By way of example, the substrate 10 may be selected from any one of a silicon-based substrate, a gallium nitride-based substrate, and sapphire. The gate formed in the subsequent step is located in the gate region P1.
S220, sequentially forming a buffer layer, a channel layer, a barrier layer, a P-GaN layer, a first protective layer and a second protective layer on the surface of the substrate, wherein the P-GaN layer, the first protective layer and the second protective layer are located in the grid region.
As shown in fig. 8, a buffer layer 20, a channel layer 30, a barrier layer 40, a P-GaN layer 50, a first protective layer 60, and a second protective layer 70 are sequentially formed on the surface of a substrate 10. As shown in fig. 9, the P-GaN layer 50, the first protective layer 60, and the second protective layer 70 are etched such that the P-GaN layer 50, the first protective layer 60, and the second protective layer 70 are located at the gate region P1. During the etching process, the first protective layer 60 and the second protective layer 70 cover the P-GaN layer 50, and damage to the surface of the P-GaN layer 50 can be prevented.
Illustratively, the buffer layer 20 is selected from one or more of AlN, gaN, alGaN and InGaN. The channel layer 30 material is selected from one or more of GaN, alGaN and InGaN. GaN is preferred. The barrier layer 40 may be AlGaN. The heterojunction is formed by the channel layer 30 and the barrier layer 40, the P-GaN layer 50 is located in the gate region P1, and the holes in the P-GaN layer 50 can deplete the two-dimensional electron gas (2 DEG) in the heterojunction, so that the device is in a normally-off state. The first protective layer 60 and the second protective layer 70 are two film layers of different materials.
And S230, etching the second protective layer to form a first grid groove so as to expose the first protective layer.
As shown in fig. 10, a passivation layer 80 may be formed on the surface of the barrier layer 40 remote from the substrate 10 before the etching process is performed on the second protective layer 70. As shown in fig. 11, the second protective layer 70 is etched to form a first gate trench T100 to expose the first protective layer 60.
Since the first protection layer 60 covers the P-GaN layer 50 when the second protection layer 70 is etched, the first protection layer 60 may protect the surface of the P-GaN layer 50 from being damaged, and thus the second protection layer 70 may be etched by a dry etching process or a wet etching process to form the first gate trench T100 to expose the first protection layer 60. Preferably, a wet etching process is selected to etch the second protective layer 70 to form the first gate trench T100, and due to different materials of the first protective layer 60 and the second protective layer 70, etching solutions with different etching ratios are selected, and the etching solutions do not damage the first protective layer 60 while etching the second protective layer 70, so that damage to the surface of the P-GaN layer 50 is further avoided, and further the problems of surface states and trap states of the P-GaN layer 50 are avoided, thereby reducing gate leakage current of the device and improving device performance.
And S240, etching the first protective layer through a wet etching process to form a second grid groove so as to expose the P-GaN layer.
As shown in fig. 12, the first protective layer 60 is subjected to an etching process by a wet etching process to form a second gate trench T200 to expose the P-GaN layer 50. Compared with the technical scheme that the first protection layer 60 is subjected to dry etching to obtain the second gate trench T200, the embodiment of the invention adopts wet etching technology to etch the first protection layer 60, and etching solutions with different etching ratios are selected to obtain the second gate trench T200 because materials of the first protection layer 60 and the P-GaN layer 50 are different, so that the damage of the etching solution to the surface of the P-GaN layer 50 can be avoided, the problems of surface states and trap states of the P-GaN layer 50 are further avoided, the gate leakage current of a device is reduced, and the device performance is improved.
S250, forming a grid electrode on the surface of the P-GaN layer far away from the substrate.
As shown in fig. 13, a gate G10 may be formed on a surface of the P-GaN layer 50 remote from the substrate 10 through a metal deposition process.
And S260, forming a source electrode and a drain electrode on the surface of the barrier layer away from the substrate.
As shown in fig. 14, the source electrode S10 and the drain electrode D10 may be formed on the surface of the barrier layer 40 remote from the substrate 10 through a metal deposition process.
According to the technical scheme provided by the embodiment of the invention, the first grid groove T100 and the second grid groove T200 are sequentially obtained by etching the second protective layer 70 and the first protective layer 60 on the surface of the P-GaN layer 50 step by step, so that the grid groove of the grid G10 placed in the grid region P1 is obtained. Wherein, when etching the second protective layer 70, the first protective layer 60 covers the P-GaN layer 50, and the first protective layer 60 can protect the surface of the P-GaN layer 50 from being damaged; in the process of etching the first protection layer 60 by a wet etching process to obtain the second gate trench T200, due to different materials of the first protection layer 60 and the P-GaN layer 50, the etching solutions with different etching ratios are selected, so that damage of the etching solution to the surface of the P-GaN layer 50 can be avoided. In summary, the preparation method provided by the embodiment of the invention can avoid the damage of the etching solution to the surface of the P-GaN layer 50, thereby avoiding the problems of the surface state and the trap state of the P-GaN layer 50, reducing the gate leakage current of the device and improving the device performance.
Alternatively, on the basis of the above technical solution, the materials of the first protective layer 60 and the second protective layer 70 are the same, and are prepared simultaneously by the same process, that is, the first protective layer 60 and the second protective layer 70 are the same film layer.
Optionally, on the basis of the above technical solution, the first protection layer 60 includes at least one first sub protection layer, and the second protection layer 70 includes at least one second sub protection layer. The total film layer number of the first protective layer 60 and the second protective layer 70 is increased according to the number of layers by increasing the number of first sub-protective layers in the first protective layer 60 and by increasing the number of layers of the second sub-protective layers in the second protective layer 70.
Optionally, on the basis of the above technical solution, as shown in fig. 15, fig. 15 is a schematic flow chart included in S220 in fig. 6, and forming, in order, a buffer layer, a channel layer, a barrier layer, a P-GaN layer, a first protection layer, and a second protection layer on a surface of a substrate in S220 includes:
s2201, sequentially forming a buffer layer, a channel layer, a barrier layer, a P-GaN layer, a first protective layer and a second protective layer on the surface of the substrate.
As shown in fig. 8, the substrate 10 further includes a non-gate region P2 surrounding the gate region P1. A buffer layer 20, a channel layer 30, a barrier layer 40, a P-GaN layer 50, a first protective layer 60, and a second protective layer 70 are sequentially formed on the surface of the substrate 10.
S2202, removing the P-GaN layer located in the non-gate region, removing the first protection layer located in the non-gate region, removing the second protection layer located in the non-gate region and removing the second protection layer located at the edge of the gate region, so that the P-GaN layer, the first protection layer and the second protection layer are located in the gate region.
As shown in fig. 9, the P-GaN layer 50, the first protective layer 60, and the second protective layer 70 are etched to remove the P-GaN layer located at the non-gate region P2, to remove the first protective layer located at the non-gate region P2, to remove the second protective layer 70 located at the non-gate region P2, and to remove the second protective layer 70 located at the edge of the gate region P1, such that the P-GaN layer 50, the first protective layer 60, and the second protective layer 70 are located at the gate region P1. During the etching process, the first protective layer 60 and the second protective layer 70 cover the P-GaN layer 50, and damage to the surface of the P-GaN layer 50 can be prevented.
It should be noted that, in the present embodiment, the second protection layer 70 located at the edge of the gate region P1 is also removed, so that the front projection area of the second protection layer 70 on the substrate 10 is smaller than the front projection area of the P-GaN layer 50 on the substrate 10 and the front projection area of the first protection layer 60 on the substrate 10, respectively. When the second protective layer 70 is etched, the middle area and the edge of the P-GaN layer 50 are covered by the first protective layer 60, and the second protective layer 70 does not contact with the side surface of the P-GaN layer 50 through the edge of the P-GaN layer 50, so that damage to the surface and the side surface of the P-GaN layer 50 caused by the etching process can be avoided, further, the problems of surface states and trap states of the P-GaN layer 50 are avoided, and therefore, the gate leakage current of the device is reduced, and the device performance is improved.
Optionally, on the basis of the above technical solution, S230 performs etching treatment on the second protection layer to form a first gate trench, and before exposing the first protection layer, the method further includes:
and forming a passivation layer on the surface of the barrier layer, which is far away from the substrate, wherein the passivation layer is contacted with the side surface of the P-GaN layer, the side surface of the first protection layer and the side surface of the second protection layer.
As shown in fig. 10, a passivation layer 80 is formed on the surface of the barrier layer 40 remote from the substrate 10 before the etching process is performed on the second protective layer 70. Since the passivation layer 80 contacts the side surface of the P-GaN layer 50, the side surface of the first protection layer 60 and the side surface of the second protection layer 70, as shown in fig. 11 and 12, the passivation layer 80 can protect the side surface of the P-GaN layer 50 and the edge of the first protection layer 60 during the etching treatment of the second protection layer 70 and the etching treatment of the first protection layer 60, so as to avoid damage to the surface and the side surface of the P-GaN layer 50, and further avoid the problems of the surface state and the trap state of the P-GaN layer 50, thereby reducing the gate leakage current of the device and improving the device performance.
Optionally, on the basis of the above technical solution, as shown in fig. 16, fig. 16 is a schematic flow chart included in S260 in fig. 6, and forming, at S260, a source electrode and a drain electrode on a surface of the barrier layer away from the substrate includes:
s2601, forming a source trench and a drain trench in the passivation layer.
As shown in fig. 13, a source trench T300 and a drain trench T400 are formed in the passivation layer 80 by an etching process.
S2602, forming a source electrode in the source electrode groove.
As shown in fig. 14, a source S10 is formed in the source trench T300 by a metal deposition process.
S2603, forming a drain in the drain trench.
As shown in fig. 14, a drain D10 is formed in the drain trench T400 by a metal deposition process.
On the basis of the above technical solution, the passivation layer 80 may realize electrical insulation between the gate electrode G10, the source electrode S10, and the drain electrode D10.
Optionally, on the basis of the above technical solution, S240, performing etching treatment on the first protection layer by a wet etching process to form a second gate trench to expose the P-GaN layer includes:
and removing the first protective layer positioned in the gate region by a wet etching process, and reserving the first protective layer positioned at the edge of the gate region to form a second gate trench so as to expose part of the P-GaN layer.
As shown in fig. 12, the first protection layer 60 located in the gate region P1 is removed by a wet etching process, the first protection layer 60 located at the edge of the gate region P1 is remained, and a second gate trench T200 is formed to expose a portion of the P-GaN layer 50.
Specifically, when the first protection layer 60 located in the gate region P1 is removed by the wet etching process, the edge of the P-GaN layer 50 is covered by the first protection layer 60, and the etching solution does not contact the side surface of the P-GaN layer 50 through the edge of the P-GaN layer 50, so that damage to the side surface of the P-GaN layer 50 caused by the etching process can be avoided. Since the materials of the first protection layer 60 and the P-GaN layer 50 are different, the etching solutions with different etching ratios are selected to obtain the second gate trench T200, and damage of the etching solution to the surface of the P-GaN layer 50 can be avoided. In summary, the above technical solution can avoid damage to the side and the surface of the P-GaN layer 50, thereby avoiding the problems of the surface state and the trap state of the P-GaN layer 50, and thus reducing the gate leakage current of the device and improving the device performance. And the first protection layer 60 located in the gate region P1 is removed by a wet etching process, the first protection layer 60 located at the edge of the gate region P1 is reserved, the gate G10 can only contact with the surface of the P-GaN layer 50, and cannot contact with the side surface of the P-GaN layer 50 through the edge of the P-GaN layer 50, so that the increase of gate leakage current can be avoided, and the controllability of the gate G10 is ensured.
Optionally, on the basis of the above technical solution, the second protection layer 70 is an amorphous silicon layer.
Specifically, the second protective layer 70 is an amorphous silicon layer, amorphous silicon is not crystallized, the hardness is low, the etching difficulty of the second protective layer 70 is reduced, and the manufacturing cost of the gallium nitride high electron mobility transistor device is further reduced.
Alternatively, on the basis of the above technical solution, the first protection layer 60 is an oxide layer of silicon.
Specifically, the first protection layer 60 is an oxide layer of silicon, and the HF etching solution can be selected for wet etching, so that the preparation cost of the oxide layer of silicon is low, and the cost of the HF etching solution is low, thereby reducing the preparation cost of the gallium nitride high electron mobility transistor device.
Optionally, on the basis of the above technical solution, the orthographic projection of the first gate trench T100 on the substrate 10 and the orthographic projection of the second gate trench T200 on the substrate 10 coincide, so as to reduce the difficulty of film deposition of the gate G10, and further reduce the manufacturing cost of the gallium nitride high electron mobility transistor device.
The embodiment of the invention also provides a gallium nitride high electron mobility transistor device, the structure of which is shown in fig. 14, and the gallium nitride high electron mobility transistor device is prepared by the preparation method of the gallium nitride high electron mobility transistor device according to any of the embodiments of the invention. Therefore, the gallium nitride high electron mobility transistor device provided by the embodiment of the invention has the beneficial effects of any one of the preparation methods of the gallium nitride high electron mobility transistor device, and the description is omitted herein.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present application may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solutions of the present application are achieved, and the present application is not limited herein.
The above embodiments do not limit the scope of the application. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application are intended to be included within the scope of the present application.
Claims (12)
1. A method for fabricating a gallium nitride high electron mobility transistor device, comprising:
providing a substrate, wherein the substrate comprises a gate region;
sequentially forming a buffer layer, a channel layer, a barrier layer, a P-GaN layer, a first protective layer and a second protective layer on the surface of the substrate, wherein the P-GaN layer, the first protective layer and the second protective layer are positioned in a grid region;
etching the second protective layer to form a first grid groove so as to expose the first protective layer;
etching the first protective layer through a wet etching process to form a second grid groove so as to expose the P-GaN layer;
forming a grid electrode on the surface of the P-GaN layer, which is far away from the substrate;
and forming a source electrode and a drain electrode on the surface of the barrier layer away from the substrate.
2. The method of manufacturing a gallium nitride high electron mobility transistor device according to claim 1, wherein the first protective layer and the second protective layer are made of the same material and are manufactured simultaneously by the same process.
3. The method of fabricating a gallium nitride high electron mobility transistor device according to claim 1, wherein the first protective layer comprises at least one first sub-protective layer and the second protective layer comprises at least one second sub-protective layer.
4. The method of fabricating a gan hemt device of claim 1, wherein etching the second protective layer to form a first gate trench to expose the first protective layer comprises:
and etching the second protective layer through a dry etching process to form a first grid groove so as to expose the first protective layer.
5. The method of fabricating a gan hemt device of claim 1, wherein etching the second protective layer to form a first gate trench to expose the first protective layer comprises:
and etching the second protective layer through a wet etching process to form a first grid groove so as to expose the first protective layer.
6. The method of fabricating a gallium nitride high electron mobility transistor device of claim 1, wherein the substrate further comprises a non-gate region surrounding the gate region;
sequentially forming a buffer layer, a channel layer, a barrier layer, a P-GaN layer, a first protection layer and a second protection layer on the surface of the substrate, wherein the steps comprise:
sequentially forming a buffer layer, a channel layer, a barrier layer, a P-GaN layer, a first protective layer and a second protective layer on the surface of the substrate;
removing the P-GaN layer located in the non-gate region, removing the first protection layer located in the non-gate region, removing the second protection layer located in the non-gate region, and removing the second protection layer located at the edge of the gate region, so that the P-GaN layer, the first protection layer and the second protection layer are located in the gate region.
7. The method for manufacturing a gallium nitride high electron mobility transistor device according to claim 1 or 4, wherein etching the second protective layer to form a first gate trench, before exposing the first protective layer, further comprises:
forming a passivation layer on the surface of the barrier layer away from the substrate, wherein the passivation layer is in contact with the side surface of the P-GaN layer, the side surface of the first protection layer and the side surface of the second protection layer;
forming a source and a drain on a surface of the barrier layer remote from the substrate includes:
forming a source trench and a drain trench within the passivation layer;
forming a source electrode in the source electrode groove;
and forming a drain electrode in the drain electrode groove.
8. The method of manufacturing a gallium nitride high electron mobility transistor device according to claim 1 or 6, wherein etching the first protective layer by a wet etching process to form a second gate trench to expose the P-GaN layer comprises:
and removing the first protection layer positioned in the grid electrode region through a wet etching process, and reserving the first protection layer positioned at the edge of the grid electrode region to form a second grid electrode groove so as to expose part of the P-GaN layer.
9. The method of manufacturing a gallium nitride high electron mobility transistor device according to claim 1, wherein the second protective layer is an amorphous silicon layer.
10. The method of manufacturing a gallium nitride high electron mobility transistor device according to claim 1, wherein the first protective layer is an oxide layer.
11. The method of manufacturing a gallium nitride high electron mobility transistor device of claim 1, wherein the orthographic projection of the first gate trench on the substrate and the orthographic projection of the second gate trench on the substrate coincide.
12. A gallium nitride high electron mobility transistor device, characterized in that it is prepared by the method for preparing a gallium nitride high electron mobility transistor device according to any one of claims 1-1.
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