JP5682098B2 - Well structure, method for forming the same, and semiconductor device - Google Patents

Description

  The present invention relates to a well structure, a method for forming the same, and a semiconductor device having the well structure, and more particularly to measures for improving the breakdown voltage characteristics.

  Conventionally, for example, a semiconductor device disclosed in Patent Document 1 is known as a high-voltage, high-power semiconductor device. In the technique of this document, a vertical MOSFET is provided on a c-plane SiC substrate having a dense hexagonal lattice crystal structure (see FIG. 1 of that document). As disclosed in FIG. 1 of the same document, a first epi layer 21 and a second epi layer 22 are sequentially epitaxially grown on the SiC substrate 1. A p-type well 3 is formed in the second epi layer 22, and a high-concentration n-type source region 4 is formed in the p-type well 3. A gate insulating film 5 and a gate electrode G are formed on the second epi layer 22 and the surrounding well 3.

When the vertical MOSFET is turned on, a current flows in the vertical direction in the order of SiC substrate 1 → first epi layer 21 → second epi layer 22 → p-type well → source region 4. Since a large amount of current can flow in the vertical direction of the substrate in this way, the structure is suitable as a power transistor.
JP 2000-286415 A

In the technique of this document, the dopant concentration of the first epi layer 21 is increased and the layer thickness is decreased. On the other hand, the dopant concentration of the second epi layer 22 is lowered and the layer thickness is increased. Accordingly, a vertical MOSFET having a high withstand voltage and a low on-resistance is provided while suppressing drift resistance.
However, with such a structure, there is a limit to improving the breakdown voltage. In general, a dislocation or a damage layer during processing exists in each part of the vertical MOSFET. These defects cause a leak path. In particular, when a leak path is generated via a pn junction between the p-type well 3 and the second epi layer 22, a breakdown voltage as designed cannot be obtained.

  An object of the present invention is to provide a semiconductor device having good characteristics such as withstand voltage by improving the well structure.

Well structure of the present invention, {0 0 0 1} plane of the hexagonal nitride semiconductor (hereinafter, using conventional designations, as "c-plane") enclose the side to the first conductivity type semiconductor region on a substrate or And a high-concentration first conductivity type semiconductor region that is surrounded by the well and is laterally surrounded by the well and includes a first conductivity type impurity having a concentration higher than that of the first conductivity type semiconductor region. ing. The side surface of the second conductivity type well and the side surface of the high-concentration first conductivity type semiconductor region are ({1-1 100 } planes (hereinafter referred to as “m-plane” using conventional names)). And the surface of the first conductivity type semiconductor region or the surface of the well forming the boundary surface between the well and the first conductivity type semiconductor region is anisotropic wet etched, and the high concentration first conductivity type semiconductor region and the well The surface of the well, which forms a boundary surface between the first conductive type semiconductor region and the first conductive type semiconductor region, is an active region such as a field effect transistor or IGBT.

  With this structure, the following effects can be obtained in the present invention. A pn junction is formed at the boundary layer between the well, which is the second conductivity type semiconductor region, and the first conductivity type semiconductor region. The side surface of the well is an m-plane, which is a plane perpendicular to the c-plane in the crystal structure. The m plane is a plane substantially perpendicular to the substrate plane. Thereby, compared with the case where the unevenness | corrugation in the side of a well is large, the local concentration of an electric field is relieve | moderated. Therefore, the leakage current through the pn junction between the well and the first conductivity type semiconductor region is reduced. By reducing the leakage current, the breakdown voltage of the semiconductor device provided with the well is improved.

  The interface between the first conductivity type semiconductor region and the well is anisotropic wet etched. Since the etching speed of the m-plane is slow, when wet etching is performed, anisotropic wet etching is performed, and the m-plane becomes a plane that is perpendicular to the substrate surface. It is only necessary that one side surface of the first conductive type semiconductor region or the well is anisotropic wet etched. Since the side surface is anisotropic wet etched, processing damage during patterning is removed. Further, since the smoothness becomes extremely high, the concentration of the electric field is further eased. Therefore, the occurrence of a leak path in the active region is more effectively suppressed, and the above-described effect can be obtained remarkably.

The semiconductor device of the present invention has the above-described well structure and uses the first conductivity type region as an active region. Thereby, a high breakdown voltage semiconductor device is obtained. Semiconductor devices include field effect transistors, IGBTs, and the like.
Thereby, the above-mentioned operation effect is obtained, and a high breakdown voltage semiconductor device is realized.

Examples of semiconductor devices, a gate insulating film formed on the first conductivity type semiconductor region and its surrounding wells, and a gate electrode formed on the gate insulating film, there is a power transistor having a. Examples of power transistors include MOSFETs and IGBTs. In the MOSFET, the high-concentration first conductivity type semiconductor region is a source region. In the IGBT, the high concentration first conductivity type semiconductor region is an emitter region.

  With this structure, the leakage current is reduced in the well in the vicinity of the gate insulating film serving as the channel region, and the on-operation characteristics are improved in addition to the breakdown voltage.

The first well structure forming method of the present invention includes the following procedures.
First, a mask film having a side surface along the m-plane is formed on the first conductivity type semiconductor region on the substrate with the c-plane of the hexagonal nitride semiconductor as the upper surface (step (a)) . Next, the first conductive semiconductor region is etched using the mask film to form a recess (step (b)) . Further, the well is formed by embedding the second conductivity type semiconductor in the recess (step (c)) . Furthermore, a step (a2) of forming a mask film having a side surface along the m-plane of the well on the well, and a step of etching the well using the mask film to form a recess (b2) And a step (c2) of forming a high concentration first conductivity type semiconductor containing a first conductivity type impurity at a concentration higher than that of the first conductivity type semiconductor region in the recess. In the step (b) and the step (b2) for forming the recesses, the anisotropic wet etching is performed after the plasma etching.

The method for forming the second well structure of the present invention includes the following procedures.
First, a second conductivity type semiconductor region to be a well is epitaxially grown on a first conductivity type semiconductor region on a substrate whose upper surface is a c-plane of a hexagonal nitride semiconductor (step (A)) . Next, a mask film having a side surface along the m-plane is formed on the second conductivity type semiconductor region (step (B)) . Next, using the mask film, the second conductive type semiconductor region is etched to form an opening (step (C)) . Further, a first conductivity type semiconductor is embedded in the opening ( D ). After the step (D), a step (B2) of forming a mask film having an opening having a side surface along the m-plane on the second conductivity type semiconductor region, and the second conductivity type using the mask film Etching the semiconductor region to form an opening in the second conductivity type semiconductor region (C2), and the opening includes a first high-concentration first impurity containing a higher concentration of the first conductivity type impurity than the first conductivity type semiconductor region. And a step (D2) of embedding a conductive semiconductor. In the steps (C) and (C2) of forming the opening, anisotropic wet etching is performed after performing plasma etching.

  The well structure of the present invention can be obtained by the method for forming the first or second well structure. Therefore, the breakdown voltage characteristic of the semiconductor device having this well structure is improved.

  According to the well structure, the method of forming the semiconductor device and the semiconductor device of the present invention, a high breakdown voltage semiconductor device having a small leakage current can be realized.

  1A and 1B are a cross-sectional view and a plan view showing the structure of a vertical MOSFET 10 according to an embodiment of the present invention. FIG. 1A shows a cross-sectional structure of one transistor cell of the vertical MOSFET 10. FIG. 1B shows a part of the planar structure of the vertical MOSFET 10.

  The vertical MOSFET 10 includes a GaN substrate 11 and a buffer layer 14 and a GaN layer 13 formed on the GaN substrate 11. The GaN substrate 11 is a free-standing substrate and has a thickness of about 400 μm. The thickness of the GaN layer 13 is about 7 μm.

The main body of the GaN substrate 11 includes a relatively high concentration of n-type dopant of about 3 × 10 ¹⁸ cm ⁻³ . The GaN layer 13 (drift layer) is a first conductivity type semiconductor region containing a low concentration n-type (first conductivity type) dopant of about 1 × 10 ¹⁶ cm ⁻³ . A region having a thickness of about 1 μm between the GaN layer 13 and the GaN substrate 11 is the buffer layer 14. The buffer layer 14 includes an n-type dopant of about 1 × 10 ¹⁷ cm ⁻³ .

In the GaN layer 13, a well 15 that is a second conductivity type semiconductor region containing a p-type (second conductivity type) dopant is formed. In the present embodiment, the well 15 includes a p-type dopant of about 3 × 10 ¹⁷ cm ⁻³ .

A source region 16 containing a high concentration n-type dopant is formed in the well 15. In the present embodiment, the source region 16 includes a high concentration n-type dopant of about 5 × 10 ¹⁹ cm ⁻³ .

  A gate insulating film 21 made of a silicon oxide film is formed on the GaN layer 13 and the surrounding well 15. On the gate insulating film 21, a gate electrode 25 made of Ni / Au is formed. A source electrode 23 made of a Ti / Al / Ti / Au film is formed across the source region 16 and the well 15. On the back surface of the GaN substrate 11, a back electrode 26 which is an ohmic electrode made of Ti / Al / Ti / Au is formed. The GaN substrate 11 functions as a drain region, and the back electrode 26 functions as a drain electrode.

  In each transistor cell of the vertical MOSFET 10, the uppermost portion of the well region 15 is a channel region Rch. When turned on, current flows in the vertical direction from the back electrode 26 in the order of the GaN substrate 11 → the buffer layer 14 → the GaN layer 13. Further, the current reaches the source region 16 from the GaN layer 13 through the uppermost channel region Rch of the well region 15. In the channel region Rch, electrons as carriers travel from the source region 16 toward the GaN layer 13. This electron mobility in the channel region Rch is called channel mobility.

  As shown in FIG. 1B, the planar shape of the well 15 is a regular hexagonal ring. The well 15 has a longest inner diameter of about 4 μm, a ring width of about 15 μm, and a depth of about 0.5 μm. Similarly, the planar shape of the source region 16 is a regular hexagonal ring. The source region 16 has a longest inner diameter of about 10 μm, a ring width of about 7 μm, and a depth of about 0.1 μm. Although not shown in FIG. 1B, the planar shape of the gate electrode 25 is a regular hexagon. The planar shape of the source electrode 23 is a regular hexagonal ring.

  Here, the GaN substrate 11, the GaN layer 13, and the well 15 are made of GaN having a dense hexagonal lattice crystal structure. As shown in the left diagram of FIG. 1B, the plane orientation of the GaN substrate 11, the GaN layer 13, and the well 15 is the c-plane ({0 0 0 1} plane). The boundary surfaces 15a and 15b between the well 15 and the GaN layer 13 are m-planes ({1-1 0 0} plane). In the present embodiment, the boundary surfaces 15c and 15d between the well 15 and the source region 16 are also m-planes.

-Manufacturing method 1
FIGS. 2A to 2F and FIGS. 3A to 3D are cross-sectional views illustrating the manufacturing process of the vertical MOSFET according to the manufacturing method 1 of the embodiment.
First, the buffer layer 14 and the GaN layer 13 are grown on the GaN substrate 11 in the step shown in FIG. In the growth, a known organometallic growth method is used. The buffer layer 14 contains an n-type dopant having a carrier concentration of about 1 × 10 ¹⁷ cm ⁻³ . The GaN layer 13 contains an n-type dopant having a carrier concentration of about 1 × 10 ¹⁶ cm ⁻³ (or 1 × 10 ¹⁶ cm ⁻³ or less).

Subsequently, a SiO ₂ film and a resist film are sequentially deposited on the GaN layer 13, and a resist mask 35 is formed by photolithography. The resist mask 35 has a substantially regular hexagonal ring opening in plan view. The side surfaces 35 a and 35 b of the resist mask 35 are formed along the m-plane of the GaN layer 13.

  Note that the entire side surfaces 35 a and 35 b of the resist mask 35 may not be parallel to the m-plane of the GaN layer 13. It is only necessary that the lower end portions of the side surfaces 35 a and 35 b of the resist mask 35 are along the m-plane of the GaN layer 13. Thereby, the well 15 whose boundary surfaces 15a and 15b are m-planes is formed in a later process.

Then, the mask pattern 30 is formed by patterning the SiO ₂ film using the resist mask 35. That is, the side surfaces 30 a and 30 b of the mask pattern 30 are along the m-plane of the GaN layer 13.

Next, in the step shown in FIG. 2B, the GaN layer 13 is plasma etched with the resist mask 35 and the mask pattern 30 attached. At that time, using a parallel plate plasma apparatus (RIE), Cl ₂ and BCl ₂ are allowed to flow as etching gases. The etching conditions in this example are a power density of 0.004 W / mm ² , a chamber internal pressure of 10 mTorr to 200 mTorr, an electrode temperature of 25 ° C. to 40 ° C., and gas flow rates of Cl ₂ of 40 sccm and BCl ₂ of 4 sccm. However, it is not limited to the above conditions. Plasma etching is terminated at the point where the GaN layer 13 is dug to a depth of 0.5 μm.

  As a result, a concave portion Rrc having a substantially hexagonal ring shape in plan view is formed. The recess Rrc constitutes the contour of the well 15 shown in FIG. The side surface of the recess Rrc is the m-plane ({1-1 0 0} plane) of the GaN crystal. The bottom surface of the recess Rrc is the c-plane ({0 0 0 1} plane) of the GaN crystal. At this point, an etching damage layer is generated over the surface of the recess Rrc over a depth of several nm (about 1 nm to 20 nm).

The etching gas may be Cl ₂ alone, Cl ₂ and Ar, Cl ₂ and N ₂ , Cl ₂ and BCl ₂ , N ₂ , or the like. By using these etching gases, damage to the GaN layer 13 can be suppressed as much as possible. The plasma generator is not limited to the RIE type. It is also possible to use other types of plasma generators such as ICP as the plasma generator.

  When the plasma etching is completed, organic cleaning is performed, and the resist mask 35 is completely removed by ashing or the like.

  Subsequently, GaN wet etching is performed. At that time, the entire substrate is immersed in a 25% TMAH aqueous solution (tetramethylammonium hydroxide aqueous solution) having a temperature of about 85 ° C. By this treatment, the damaged layer generated on the surface portion of the GaN layer 13 is removed by plasma etching. The depth of the damaged layer varies depending on the plasma generator used and the plasma etching conditions. Therefore, the wet etching process is performed until the damaged layer is substantially removed. “Substantially removed” means that the damaged layer is removed to an extent that does not affect the leakage current described later.

  The etching solution for performing the wet etching is not limited to the TMAH aqueous solution. As the etchant, an appropriate one can be used according to the material of the substrate (in this embodiment, GaN). Even when a TMAH aqueous solution is used, the concentration is not limited to 25%. Conditions such as the concentration and temperature of the TMAH aqueous solution can also be selected as appropriate.

Next, in the step shown in FIG. 2C, the GaN crystal is epitaxially grown while leaving the mask pattern 30 to form the p-type GaN growth layer 15x. The p-type GaN growth layer 15x includes a p-type dopant having a carrier concentration of about 3 × 10 ¹⁷ cm ⁻³ . At this time, a GaN crystal grows in a portion of the p-type GaN growth layer 15x that is in contact with the GaN layer 13 (a portion of the recess Rrc). Polycrystalline GaN or amorphous GaN grows on the portion in contact with the mask pattern 30 made of SiO ₂ .

Next, in the step shown in FIG. 2D, the mask pattern 30 made of the SiO ₂ film is removed by hydrofluoric acid. By this lift-off, the portion made of polycrystalline GaN or amorphous GaN in the p-type GaN growth layer 15x is removed. The well 15 is left in the recess Rrc.

  The boundary surfaces 15a and 15b between the well 15 and the GaN layer 13 are m-planes. The upper surface of the well 15 is generally a rough surface, although it depends on lift-off conditions. Therefore, it is preferable to planarize. For planarization, for example, there is CMP (Chemical Mechanical Polishing) or an etch back method. Thereafter, it is preferable to wet-etch the upper surfaces of the GaN layer 13 and the well 15.

Next, in the step shown in FIG. 2E, a source region 16 containing a high concentration n- type dopant is formed in the well 15. In the present embodiment, the formation of the source region 16 is performed using the formation of the recesses and the epitaxial growth similarly to the formation of the well 15. At that time, as in the case of forming the concave portion Rrc shown in FIG. 2B, the side surface of the concave portion serving as the outline of the source region 16 is the m plane.

The source region 16 is shallow . Also, in order to apply efficient voltage from the source electrode 23 to the well 15 may be formed p ⁺ contact region in the well 15.

  Next, in the step shown in FIG. 2F, a gate insulating film 21 made of a silicon oxide film having a thickness of about 50 nm is formed on the substrate by thermal oxidation or CVD.

  Next, a back electrode 26 is formed on the back surface of the GaN substrate 11 in the step shown in FIG. The formation procedure of the back electrode 26 is as follows. After cleaning with 10% hydrochloric acid for 3 minutes as a pre-deposition cleaning, a multilayer Ti / Al / Ti / Au film (thickness 20/100/20/200 nm) is deposited by a vapor deposition method.

  Next, in the step shown in FIG. 3B, a portion of the gate insulating film 21 located above the source region 13 and the well region 15 is opened. Further, the source electrode 23 is formed on the exposed source region 13 and well region 15 by using, for example, a lift-off method. The source electrode 23 is made of, for example, a Ti / Al / Ti / Au film (thickness 20/100/20/200 nm).

Next, in the step shown in FIG. 3C, alloying heat treatment is performed between the GaN substrate 11, the source electrode 23, and the back electrode 26 in a nitrogen atmosphere at 600 ° C. for 2 minutes. Thereby, the back electrode 26 and the GaN substrate 13 are in ohmic contact, and the source electrode 23 and the source region 16 are in ohmic contact.

Next, in the step shown in FIG. 3D, a gate electrode 25 made of Ni / Au is formed on the gate insulating film 21 at a position separated from the source electrode 23.
Through the above processing, the vertical MOSFET 10 shown in FIGS. 1A and 1B is formed.

-Manufacturing method 2-
4A to 4F are cross-sectional views illustrating the manufacturing process of the vertical MOSFET according to the manufacturing method 2 of the embodiment.
First, in the step shown in FIG. 4A, the buffer layer 14 and the lower GaN layer 13x are grown under the same conditions as in manufacturing method 1. Further, a well GaN layer 15y (second conductivity type semiconductor region) containing a p-type dopant is formed on the lower GaN layer 13x. The concentration of the p-type dopant in the well GaN layer 15y is the same as in manufacturing method 1. A value obtained by adding the thicknesses of the well GaN layer 15 y and the lower GaN layer 13 x corresponds to the thickness of the entire GaN layer 13.

Subsequently, an SiO ₂ film and a resist film are sequentially deposited on the well GaN layer 15y, and a resist mask 35 is formed by photolithography. The planar shape of the resist mask 35 is a substantially regular hexagonal ring. The side surfaces 35 a and 35 b of the resist mask 35 are formed along the m-plane of the GaN layer 13.

  For the same reason as in manufacturing method 1, the entire side surfaces 35 a and 35 b of the resist mask 35 may not be parallel to the m-plane of the GaN layer 13.

Then, the mask pattern 30 is formed by patterning the SiO ₂ film using the resist mask 35. That is, the side surfaces 30a and 30b of the mask pattern 30 are along the m-plane of the well GaN layer 15y.

  Next, in the step shown in FIG. 4B, the well GaN layer 15y is plasma etched under the same conditions as in the manufacturing method 1. The etching gas, etching conditions, and plasma apparatus used are the same as those in the first embodiment. Plasma etching is terminated at the point where the well GaN layer 15y is dug until it is removed in the depth direction.

  As a result, a well 15 having a substantially hexagonal ring shape in plan view is formed, and a recess Rrc is formed on the side of the well 15. The side surfaces (boundary surfaces 15a and 15b) of the well 15 are m-planes ({1-1 0 0} planes) of the GaN crystal. The bottom surface of the recess Rrc is the c-plane ({0 0 0 1} plane) of the GaN crystal. At this time, an etching damage layer is generated over the depth of several nm (about 1 nm to 20 nm) on the side surface of the well 15 and the bottom surface of the recess Rrc.

Next, in the step shown in FIG. 4C, the upper GaN layer 13y is formed by epitaxial growth of the GaN crystal with the mask pattern 30 left. The upper GaN layer 13y includes an n-type dopant having the same carrier concentration as that of the lower GaN layer 13x. At this time, a GaN crystal grows in a portion of the upper GaN layer 13y that is in contact with the lower GaN layer 13x (a portion of the recess Rrc). Polycrystalline GaN or amorphous GaN grows on the portion in contact with the mask pattern 30 made of SiO ₂ . Next, the mask pattern 30 made of the SiO ₂ film is removed with hydrofluoric acid.

  Next, in the step shown in FIG. 4D, for example, CMP (Chemical Mechanical Polishing) using an alkaline solution containing fine particles of chromium oxide is performed. By this CMP, a portion made of polycrystalline GaN or amorphous GaN in the upper GaN layer 15y is removed. The GaN layer 13 is formed by the upper GaN layer 13y and the lower GaN layer 13x remaining in the recess Rrc. An etch back method may be used.

Next, in the steps shown in FIGS. 4E and 4F, the same processing as in FIGS. 2E and 2F in the manufacturing method 1 is performed. It is shown that after step is omitted, performs the same processing as FIG. 3 in the preparation method 1 (a) ~ (d) .

  In the manufacturing methods 1 and 2, the process of removing the resist mask 20 by ashing or the like is not necessarily required. This is because the resist mask 20 can be removed depending on the time of wet etching with a 25% TMAH aqueous solution.

According to the present embodiment, the following effects can be obtained by setting the boundary surfaces 15a and 15b between the well 15 and the GaN layer 13 to the m-plane.
A pn junction is formed in the vicinity of boundary surfaces 15a and 15b between the GaN layer 15 that is the first conductivity type semiconductor region and the well 15 that is the second conductivity type semiconductor region. The boundary surfaces 15a and 15b are m-planes, and are planes perpendicular to the c-plane in the crystal structure (see the left figure in FIG. 1 (b)).
The m-plane has a slower etching rate than the a-plane. Accordingly, when patterning is performed by etching, the boundary surfaces 15a and 15b become flat surfaces with small unevenness. Thereby, compared with the case where the unevenness | corrugation in the side of boundary surface 15a, 15b is large, the local concentration of an electric field is relieve | moderated. Therefore, the leakage current between the well 15 and the GaN layer 13 of the vertical MOSFET 10 is reduced. By reducing the leakage current, the breakdown voltage of the vertical MOSFET 10 is improved.

  Further, since the unevenness of the pn junctions on both sides of the channel region Rch is small, the scattering received by the carriers (electrons) is also small. Therefore, the channel mobility is increased and the operating characteristics of the vertical MOSFET 10 which is a power device are improved.

  In the present embodiment, the boundary surfaces 15c and 15d between the well 15 and the source region 16 are also m-planes. Therefore, by the same operation as described above, the occurrence of a leak path between the well 15 and the source region 16 is suppressed, and the breakdown voltage is further improved.

  FIGS. 5A and 5B are SEM photographs showing the side surface during plasma etching of GaN and the side surface after wet etching in order. As shown in FIG. 5A, the c-plane GaN substrate is patterned by plasma etching so that the m-plane and the a-plane appear.

  On the other hand, as shown in FIG. 5B, the m-plane also appears in the portion that was the a-plane after wet etching for 2 hours. A wide m-plane appears at the corner where the m-plane and the a-plane intersect. The m-plane is extremely flat and the surface is smooth.

  Therefore, if the patterning is performed so that the boundary surfaces 15a and 15b between the well 15 and the GaN layer 13 become the m-plane of the GaN layer 13, smooth boundary surfaces 15a and 15b can be obtained. Therefore, the boundary surfaces 15a and 15b approach the GaN layer 13 more perpendicularly by wet etching. Therefore, the above-mentioned pressure resistance improvement effect can be obtained more reliably.

  Moreover, the processing damage caused during plasma etching is reduced by wet etching. Therefore, the occurrence of a leak path through the defect is suppressed. By further reducing the leak path, the breakdown voltage characteristics of the vertical MOSFET 10 are further improved.

  In the above embodiment, the example in which the GaN substrate and the GaN epitaxial growth layer are provided as the semiconductor layer has been described. However, the vertical MOSFET of the present invention can also be applied to semiconductor substrates having other dense hexagonal crystal structures such as SiC and AlN.

  In the above embodiment, the semiconductor device of the present invention is a vertical MOSFET, but the present invention is not limited to this. The present invention can be applied to other semiconductor devices as long as they have a well structure on a c-plane substrate. Examples of other semiconductor devices include lateral MOSFETs, IGBTs, JFETs, thyristors, and the like. Even in these semiconductor devices, a flat surface with small irregularities can be obtained because the side surface of the well is an m-plane. Therefore, a high breakdown voltage characteristic with a small leakage current at the boundary with other regions can be exhibited.

  The structures of the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to the scope of these descriptions. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

  The semiconductor device manufactured according to the present invention can be used as a circuit element in various electronic devices.

(A), (b) is sectional drawing and the top view of the vertical MOSFET which concerns on embodiment in order. (A)-(f is sectional drawing which shows the first half part of the manufacturing process of the vertical MOSFET which concerns on the manufacturing method 1 of embodiment. (A)-(d) is sectional drawing which shows the latter half part of the manufacturing process of the vertical MOSFET which concerns on the manufacturing method 1 of embodiment. (A)-(f) is sectional drawing which shows the first half part of the manufacturing process of the vertical MOSFET which concerns on the manufacturing method 2 of embodiment. (A), (b) is a SEM photograph figure which shows the side surface at the time of the plasma etching of a GaN substrate, and the side surface after wet etching in order.

Rrc recess Rch channel region 10 vertical MOSFET
11 GaN substrate 13 GaN layer (first conductivity type semiconductor region)
13x lower GaN layer 13y upper GaN layer 14 buffer layer 15 well (second conductivity type semiconductor region)
15a inner side surface 15b outer side surface 15c, 15b interface 15x p-type GaN growth layer 15y GaN layer for well 16 source region 21 gate insulating film 23 source electrode 25 gate electrode 26 back electrode 30 mask pattern 30a, 30b side surface 35 resist mask 35a, 35b side view

Claims (5)

A first conductivity type semiconductor region which is an active region provided on a {0 0 0 1} plane of a hexagonal nitride semiconductor;
It made a second conductivity type semiconductor, and the circumference Murrell well laterally to said first conductivity type semiconductor region,
A high concentration first conductivity type semiconductor region that is surrounded by the well in the well and includes a first conductivity type impurity having a concentration higher than that of the first conductivity type semiconductor region ;
The side surface of the well and the side surface of the high-concentration first conductivity type semiconductor region are {1-1 0 0} planes,
The surface of the first conductivity type semiconductor region or the surface of the well, which forms the boundary surface between the well and the first conductivity type semiconductor region, is anisotropically etched, and the high concentration first conductivity type semiconductor region A well structure in which a surface of the well forming a boundary surface with the well is subjected to anisotropic wet etching.   A semiconductor device comprising the well structure according to claim 1. The semiconductor device according to claim 2, wherein
A gate insulating film formed on the first conductive type semiconductor region and its surrounding well;
And a gate electrode formed on the gate insulating film,
A semiconductor device that functions as a power transistor. Forming a mask film having a side surface along the m-plane on the first conductivity type semiconductor region on the substrate having the c-plane of the hexagonal nitride semiconductor as an upper surface;
After the step (a), using the mask film, the first conductive type semiconductor region is etched to form a recess (b);
(C) forming a well by embedding a second conductivity type semiconductor in the recess;
Forming a mask film having a side surface along the m-plane of the well on the well (a2);
Etching the well using the mask film to form a recess (b2);
A step (c2) of forming a high-concentration first conductive semiconductor containing a first conductive impurity in a concentration higher than that of the first conductive semiconductor region in the recess ;
In the steps (b) and (b2) , after forming plasma etching, anisotropic wet etching is performed. A step ( A ) of epitaxially growing a second conductivity type semiconductor region to be a well on the first conductivity type semiconductor region on the substrate having the c-plane of the hexagonal nitride semiconductor as an upper surface;
Forming a mask film having an opening having a side surface along the m-plane on the second conductive type semiconductor region ( B );
Etching the second conductive type semiconductor region using the mask film to form an opening in the second conductive type semiconductor region ( C );
Burying a first conductivity type semiconductor in the opening ( D );
After the step (D), a step (B2) of forming a mask film having an opening having a side surface along the m-plane on the second conductivity type semiconductor region;
Etching the second conductive semiconductor region using the mask film to form an opening in the second conductive semiconductor region (C2);
Burying a high concentration first conductivity type semiconductor containing a first conductivity type impurity in a concentration higher than that of the first conductivity type semiconductor region in the opening (D2) ,
In the step (C) and the step (C2) , after forming plasma etching, anisotropic wet etching is performed.

Images