JP2000286415A - Mosfet element and manufacture thereof - Google Patents

Mosfet element and manufacture thereof

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Publication number
JP2000286415A
JP2000286415A JP11086825A JP8682599A JP2000286415A JP 2000286415 A JP2000286415 A JP 2000286415A JP 11086825 A JP11086825 A JP 11086825A JP 8682599 A JP8682599 A JP 8682599A JP 2000286415 A JP2000286415 A JP 2000286415A
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JP
Japan
Prior art keywords
epi layer
layer
doping concentration
epi
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11086825A
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Japanese (ja)
Inventor
Tetsuya Yamamoto
哲也 山本
Original Assignee
Sanyo Electric Co Ltd
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Sanyo Electric Co Ltd, 三洋電機株式会社 filed Critical Sanyo Electric Co Ltd
Priority to JP11086825A priority Critical patent/JP2000286415A/en
Publication of JP2000286415A publication Critical patent/JP2000286415A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a MOSFET element having a high withstand voltage and a low on-resistance while suppressing a drift resistance, and a method of manufacturing the same. SOLUTION: In a MOSFET element having an epi layer between a source 4 and a drain (substrate 1), the on-resistance relative to the withstand voltage is uniquely determined according to the doping concentration of the epi-layer. In order to reduce the thickness, the first layer having a high doping concentration and a small layer thickness is used.
The second layer having a low doping concentration and a large layer thickness
It was constituted by the epi layer 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET device and a method of manufacturing the same, and more particularly, to a MOSFET device in which the doping concentration of an epi layer is determined so as to reduce the on-resistance with respect to a breakdown voltage, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view showing a power Si-MOSFET as a conventional MOSFET device. This M
The OSFET includes a substrate 1 serving as a common drain, an epi layer 2 formed on the substrate 1, a plurality of wells 3 provided at predetermined intervals above the epi layer 2, and provided in each of the wells 3. A source 4, a well 3, a source 4 and an oxide insulating film 5 provided over the epi layer 2 in the center of each well 3, and an electrode S provided on the source, drain and gate. , D and G are provided.

The epi layer 2 is doped on the substrate 1 with an n-type impurity so as to have a uniform concentration. From the source 4 to the substrate (drain) 1, an equivalent resistance circuit for each gate in FIG. As shown, the channel resistance Rch of the well 3, the storage layer resistance Ra of the storage layer formed on the epi layer 2, and the JF of the epi layer between the wells
A resistance circuit (hereinafter referred to as on-resistance) is formed by serially connecting the ET resistance Rj and the drift resistance Repi of the epi layer below the wells.

It is desired that such a power transistor has a high withstand voltage and a low on-resistance. FIG.
On-resistance R with respect to withstand voltage of Si-MOSFET described above
It is a calculation result showing the relationship of on with that of the SiC-MOSFET. According to FIG.
Has a higher on-resistance with respect to the withstand voltage than that of SiC, and thus has a high withstand voltage and a small on-resistance.
In order to obtain OSFET, practical development of SiC-MOSFET is desired.

FIG. 6 shows the Si-MO described above.
Each resistance Rch, Ra, Rj, and Repi when the configuration of the SFET is applied to the SiC-MOSFET as it is is shown together.
If the voltage is increased to 0 V or more, as shown in FIG. 7, the ratio of the drift resistance Repi of the epi layer to the on-resistance becomes extremely high. Therefore, in order to obtain a more excellent power SiC-MOSFET, it is necessary to suppress the drift resistance at a high withstand voltage.

The present invention has been made in order to solve the conventional problems, and has as its object to provide a MOSFET device having a high withstand voltage and a low on-resistance while suppressing a drift resistance, and a method of manufacturing the same. .

[0007]

In order to solve the above-mentioned problems, the present invention comprises an epilayer between a source and a drain, and the on-resistance with respect to the breakdown voltage is uniquely determined according to the doping concentration of the epilayer. Wherein the doping concentration of the epi layer is changed between the source and the drain so that the on-resistance with respect to the breakdown voltage is reduced.

Conventionally, the doping concentration of the epi layer has been determined to be uniform, but the on-resistance can be changed by changing the doping concentration of the epi layer at the same breakdown voltage. Therefore, if the doping concentration of the epi layer is changed so as to reduce the on-resistance, the on-resistance can be reduced at the same breakdown voltage.

This change in doping concentration can be obtained, for example, as follows.

Assuming that a position variable from the source side to the drain side of the epi layer is x and a doping concentration corresponding to the position is N (x), an ideal doping concentration that can reduce the on-resistance with respect to the breakdown voltage is expressed by the following equation. Assume that they can be approximated.

N (x) = A / (1−x / W) B (1) 0 ≦ B <1, W is the epilayer width. Poisson equation is solved for this equation to obtain the electric field distribution. A and W are obtained as a function of the withstand voltage VB from the withstand voltage condition expression of (2).

Β∫ | E (x) | 7 dx = 1 (2) (where the integration range is 0 to W, β is a constant determined by the semiconductor material, and 1.12 × 10 -40 in 3C-SiC. ) Then, the mobility μ = μ 0 N (x) - γ (γ = 0.34: Si
C), the on-resistance R is calculated, and R = ∫dx / (qμN (x)) (3) The value of B that minimizes R in the above equation is obtained (for example, B = 0.
478). As a result, when the breakdown voltage VB is determined, N and W are determined, and the equation (1) is determined, and a change in the concentration distribution that can reduce the on-resistance can be obtained. The above example is an example in which the doping concentration is continuously changed. However, as described later, the doping concentration may be changed discretely.

According to the present invention, there is provided a MOS transistor according to the first aspect.
In the FET element, the MOSFET element is SiC-M
This is constituted by an OSFET element.

As shown in FIG. 6, SiC-MOSFE
As for T, the relationship between the breakdown voltage and the on-resistance is superior to that of the Si-MOSFET, and therefore, a power MOSFET element having a small on-resistance at a high breakdown voltage can be obtained. Note that SiC has larger physical properties such as a melting point, an energy gap, a dielectric breakdown electric field, a thermal conductivity, and a saturation speed than other semiconductors (e.g., Si) generally used at present. Development is expected.

Further, according to the present invention, in the MOSFET device according to claim 1 or 2, the breakdown voltage is 1000
V or more.

For example, in the case of a SiC-MOSFET, as shown in FIG. 7, at a withstand voltage of 1000 V or more, the drift resistance Repi of the epi layer appears remarkably. Accordingly, the present invention provides a MOSFET for withstand voltage of 1000 V or more.
The effect can be made remarkable by applying to.

According to the present invention, in the MOSFET device according to any one of claims 1 to 3, the epi layer is formed by stacking a plurality of epi layers having different doping concentrations.

It is difficult to change the doping concentration to an ideal value which can be obtained theoretically. Therefore, if this ideal value is approximated to a discrete value and an epi layer having the doping concentration is provided in a stepwise manner, it is possible to manufacture a MOSFET element having a high withstand voltage and a low on-resistance close to the ideal value. Becomes possible.

Here, the doping concentration and the layer thickness of each layer may be obtained by using, for example, an approximate value (representative value) of the equation (1), or may be shown in an equation (4) described later. So that the doping concentration and the layer thickness of each layer are represented using the related variables, the Poisson equation is solved based thereon, and the variables and constants are obtained from the withstand voltage condition, and the doping concentration and the layer thickness of each layer are obtained. Is also good.

According to the present invention, there is provided a MOS transistor comprising:
In the FET, each of the plurality of epi layers having different doping concentrations has a different thickness.

When the ideal doping concentration is given discretely to each layer and the change of the ideal doping concentration is gradual, one doping concentration representative thereof is taken as the doping concentration of the change region and one layer is used as the doping concentration. Is more efficient in manufacturing.

According to the present invention, in the MOSFET device according to claim 4 or 5, the epi layer has a low doping concentration and a thick second epi layer, and a high doping concentration and a thin layer. This is constituted by the first epi layer.

In the present invention, the doping concentration is divided into two stages,
The withstand voltage is ensured by the second epi layer, and the on-resistance (drift resistance) is reduced by the first epi layer. Even with such a simple structure, the on-resistance for the same withstand voltage can be significantly reduced. Becomes possible.

In this case, the doping concentration and the layer thickness can be obtained by using the following equation (4) instead of, for example, using the approximate values of the above-mentioned equation (1).

N (x) = D 0 ≦ x <αW N (x) = cD αW ≦ x <W (4) Then, similarly, Poisson equation is solved, and
D and W are determined as a function of the breakdown voltage VB, the on-resistance R is determined assuming the mobility μ, α and c that minimize the R are determined, the constants D and W are determined, and the thickness of the two layers and the doping are determined. The concentration can be determined.

According to the present invention, there is provided a MOS transistor comprising:
In the FET element, the second epi layer of the first epi layer and the second epi layer is provided on a side closer to a channel portion.

The on-resistance can be efficiently reduced by lowering the doping concentration of the epi layer near the channel where the current density becomes uneven, while increasing the doping concentration on the drain (for example, common drain) side where the current density is less likely to be uneven. To the ideal value.

Further, according to the present invention, in the MOSFET device according to claim 6 or 7, the breakdown voltage is 1000
V, the doping concentration of the first epi layer is 3 to 6 times the doping concentration of the second epi layer,
The thickness of the epi layer is 1 / to 1 of the thickness of the second epi layer.
/ 5 times.

The present invention relates to a MOSFET for 1000V withstand voltage.
In the case of T, when the doping concentration is divided into two stages, it shows an example of the possible range of the doping concentration and the layer thickness of each layer. According to such a value, the on-resistance can be effectively reduced. .

Further, according to the present invention, in the MOSFET device according to any one of the first to eighth aspects, the doping concentration is a variable that indicates a position of the epi layer in the layer thickness direction x, and the variable at the position is x. Assuming that the doping concentration is N (x) and the width of the epi layer is W, A and B are constants, and the following equation is expressed as N (x) = A / (1-x / W) B (5) The doping concentration or an approximate value thereof. The above equation is the same as the above equation (1), and assumes a condition that minimizes the on-resistance by continuously changing the doping concentration with respect to the determined withstand voltage. If the doping concentration of the epi layer is provided continuously or stepwise on the basis of the value obtained by the above or the approximate value of the value obtained by the above equation, a MOSFET having a low on-resistance for the same withstand voltage can be obtained. be able to. In claim 6, the value can be obtained on the premise of equation (4). However, as an approximate value of equation (5), the layer thickness and the doping concentration of each of the two layers can be determined. .

According to the present invention, there is provided a MOSFET device according to any one of claims 6 to 8, wherein
The doping concentration and the layer thickness of the epi layer and the second epi layer are represented by x as a variable representing the position of the epi layer in the layer thickness direction and doping concentration N (x) at the position as N (x) = D 0 ≦ x <αW N (x) = cD αW ≦ x <W, the Poisson equation is solved, D and W are obtained as functions of the breakdown voltage VB, and the on-resistance R is obtained by assuming the mobility μ.
The constants D and W are found by finding α and c that minimize this R, the doping concentration of the first epi layer is set to cD or an approximate value thereof, and the layer thickness of the first epi layer is (W−αW) or The doping concentration of the second epi layer is set to D or its approximate value, and the layer thickness of the second epi layer is set to αW or its approximate value.

In this method, each layer thickness and each doping concentration are obtained by the above-described equation (4). Even with such values, a low on-resistance with respect to a high withstand voltage can be obtained.

The present invention also relates to a method of manufacturing a MOSFET device having an epi layer provided on a semiconductor substrate, a source and a drain interposed between the epi layer, and having a predetermined breakdown voltage. Providing a first epi layer having a predetermined doping concentration and a predetermined layer thickness and having a first drift resistance on the semiconductor substrate; and providing the first epi layer on the first epi layer with the predetermined doping concentration. Providing a second epi layer having a dope concentration different from that of the first epi layer and having the same or different layer thickness as that of the first epi layer, and having a second drift resistance. The doping concentration and layer thickness of one epi layer and the doping concentration and layer thickness of the second epi layer are such that the series resistance value of the first drift resistor and the second drift resistor is smaller than the predetermined withstand voltage. Yo It is those that have been set.

According to the present invention, the doping concentration of the epi layer is set to 2
High breakdown voltage, low on-resistance MOSFET when divided into stages
Can be easily manufactured.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a MOS according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing an FET.

This MOSFET is composed of a SiC semiconductor, for example, a power MOSF for a withstand voltage of 1000 V.
ET, an epi layer (first epi layer 21 and second epi layer 22) having two different doping concentrations on the n-type substrate 1 serving as a common drain, and a predetermined interval above the second epi layer 22 A plurality of wells 3, a source 4 provided in each of the wells 3, and a source 4 in the center of the well on the second epi layer.
, An oxide insulating film 5 provided over the substrate 1, the substrate 1, each source 4, each electrode D provided on the oxide insulating film 5,
S and G are provided.

In the epi layer, a second epi layer having a low doping concentration is provided on the channel portion side formed below the gate, and a first epi layer having a high doping concentration is provided below the second epi layer. FIG. 2A shows the doping concentration and the layer thickness of the second epi layer, and the doping concentration and the layer thickness of the first epi layer.

FIG. 2 shows the distance x from the upper end of the epi layer on the horizontal axis, and the doping concentration N (x) on the vertical axis. In this embodiment, the doping concentration of the second epi layer is N, the thickness is 0.88 W, and the doping concentration of the first epi layer is 4.82.
N, and its thickness is 0.12 W. In addition,
FIG. 2 also shows an ideal doping concentration (b) for minimizing the on-resistance and a doping concentration (c) according to a conventional design method. Here, W is the width of the epi layer in the direction perpendicular to the paper, and N and W are the breakdown voltage VB (for example, 1000 V).
Is given by

N = 7.36 × 10 19 · VB -4/3 (1) W = 2.79 × 10 -7 · VB 7/6 (2) The values of these equations differ for the epi layer in two stages. This is obtained from the withstand voltage condition which is a boundary condition for satisfying the withstand voltage VB when the layer is formed from a layer having a doped concentration. That is,
In the embodiment, the doping concentration and the layer thickness of the first epi layer and the second epi layer are determined by the above equation (4). N (x) = D0 ≦ x <αW N (x) = cD αW ≦ x <W (4) is solved by solving the Poisson equation under the conditions of equation (4), D and W are found as functions of the withstand voltage VB, and the mobility μ = μ 0 Nγ is assumed. Then, the on-resistance R is obtained, α and c that minimize this R are obtained, constants D and W are obtained, and the doping concentration of the first epi layer is set to cD.
And the thickness of the first epi layer is (W−αW),
The doping concentration of the epi layer is D, and the thickness of the second epi layer is αW
It is set as. As a result, γ = 0.34, α = 0.88, and c = 4.82 were obtained.

As described above, in the embodiment, (4)
The layer thickness and the doping concentration were determined using the equations. (1) A, B, and W were obtained from the equation N (x) = A / (1-x / W) B (1), and the epi layer was determined. When providing in two stages, the respective doping concentrations and layer thicknesses may be obtained as approximate values (representative values) of the equation (1).

In the equation (1), for example, 5.513 × 10 19 · VB -4/3 is used as the value of A,
2.774 × 10 −7 · VB 7/6 is used for the value of, and 0.478 is used for the value of B.

According to the embodiment of the present invention described above, for VB = 1000 V, the doping concentration N of the first epi layer, the first and second epi layer widths W, and the on-resistance R are: The values N 0 , W 0 , and R 0 obtained by the conventional design method are as follows. In this case, the doping concentration of the second epi layer is 4.82 N, and the on-resistance is 83% of the conventional one, and the on-resistance is greatly reduced.

N = 7.36 × 10 15 (cm −3 ) N 0 = 8.79 × 10 15 (cm −3 ) W = 0.88 × 10 −3 (cm) W 0 = 1.10 × 10 −3 (cm) R = 8.88 × 10 −4 (Ωcm 2 ) R 0 = 1.07 × 10 −3 (Ωcm 2 ) Next, a method for manufacturing the above-described MOSFET will be described with reference to FIG. First, an n-type substrate is manufactured. This n-type substrate desirably satisfies the following conditions.

Polymorph: 4H Plane orientation: (0001) Off angle: 8 degrees Off direction: [1 (bar) 120] However, the following may be used.

Polymorph: 4H, 6H Plane orientation: (0001), (0001 (bar)) Off angle: 1 degree to 10 degrees Off direction: [1 (bar) 120] Doping concentration Nd is 1 × 10 17 cm -3 to 1 × 10 20 cm
It is -3 .

Next, cleaning of the substrate is performed under the following conditions. First, perform organic washing with acetone and ethanol,
Next, acid cleaning with an acid of sulfuric acid: hydrogen peroxide = 1: 1 is performed, and etching is performed with HF (5%). After that, a SiO 2 film having a thickness of 60 nm or more in oxygen at 1200 degrees for 200 minutes is used.
2 After forming (oxide film), etch the oxide film.

After the cleaning of the substrate, a film having the same polymorphism as the substrate is grown by the CVD method to form the first epi layer 21 (c). At this time, for a withstand voltage of 1000 V, the film thickness is 1.1 μm, and the doping concentration is 3.55 × 10 16 cm −3 using nitrogen N as a doping element.

After the formation of the first epi layer 21, the second epi layer 2
2 is formed (d). In this case, for a withstand voltage of 1000 V, the film thickness is 7.7 μm, and nitrogen N is used as a doping element.
The doping concentration is set to 7.36 × 10 15 cm −3 .

After the formation of the second epi layer, a p-well and an n-source are formed, and then an oxide insulating film is formed to
A gate is formed by etching (e). In forming the p-well, aluminum Al or boron B is doped. The doping temperature is 500-1000 deg. C, and the doping amount is 10 16 to 10 19 cm −3 , and the doping amount is an intermediate value between the concentration of the second epi layer 22 and the concentration of the source. After the completion of the doping, 800-1000 deg. Anneal at a temperature of C.

In forming the source, nitrogen N and phosphorus P are doped into a part of the formed p-well. The doping temperature is 500-1000 deg. C, and the doping amount is 10 19 to 10 21 cm −3. After the completion of the doping, 800-1500 d in an argon Ar atmosphere.
eg. Anneal at a temperature of C.

After the formation of the p well and the n source, a gate oxide film is formed. First, acid cleaning is performed as pretreatment.
As the cleaning acid, a solution obtained by mixing sulfuric acid and hydrogen peroxide at a ratio of 1: 1 is used. After the acid washing, thermal oxidation is performed after etching with HF (5%). This thermal oxidation
Performed in oxygen at 1200 degrees for 200 minutes, 60 nm
The above oxide film (SiO 2 ) is formed.

After the completion of the thermal oxidation, the gate oxide film is patterned using photolithography and HF or dry etching. The width of the obtained gate oxide film is 20 μm.
m and the length is 10 μm.

After the formation of the gate oxide film, a source, a drain, and a gate electrode are formed. Source, the drain electrode, first forming a nickel (Ni) layer, followed by patterning in hydrogen H 2, 900-1000deg. C
Is performed. In forming the gate electrode, a film thickness of 2
A polysilicon layer having a thickness of 00 nm-2 μm is formed and patterned to form a gate electrode.

The SiC-MOSFET thus obtained
Is composed of a second epi layer having a low doping concentration and a thick layer and a first epi layer having a high doping concentration and a thin layer, and has a high withstand voltage and a small on-resistance.

[0056]

As described in detail above, according to the present invention, an epi layer is provided between a source and a drain, and the on-resistance with respect to the breakdown voltage is uniquely determined according to the doping concentration of the epi layer. In the MOSFET element, the doping concentration of the epi layer is changed between the source and the drain so that the on-resistance with respect to the withstand voltage is reduced, so that drift resistance is suppressed, and high withstand voltage and low on-resistance are realized. It has the effect of being able to do so.

[Brief description of the drawings]

FIG. 1 shows a power SiC-M according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of an OSFET.

FIG. 2 is a diagram showing a layer thickness and a doping concentration of a first epi layer and a second epi layer in the embodiment.

FIG. 3 is a view showing a manufacturing process of the present invention.

FIG. 4 is a sectional view showing a conventional power MOSFET.

FIG. 5 is a diagram showing an equivalent resistance circuit of a conventional power MOSFET.

FIG. 6 shows an MO using a silicon Si semiconductor and a SiC semiconductor.
FIG. 4 is a diagram illustrating a relationship between a withstand voltage and an on-resistance of an SFET.

FIG. 7 is a diagram showing a variation of each resistance value with respect to a withstand voltage in a SiC-MOSFET.

[Explanation of symbols]

 Reference Signs List 1 substrate (common drain) 3 p well 4 source 5 oxide insulating film 21 first epi layer 22 second epi layer

Claims (11)

[Claims]
1. A MOSFET device having an epi layer between a source and a drain, wherein an on-resistance with respect to a withstand voltage is uniquely determined according to a doping concentration of the epi-layer, wherein the on-resistance with respect to the withstand voltage is reduced. And a doping concentration of the epi layer is changed between the source and the drain.
2. The MOSFET device according to claim 1, wherein the MOSFET device is a SiC-MOSFET.
3. The MOSF according to claim 1 or 2,
In the ET element, the MOSFET element whose withstand voltage is 1000 V or more.
4. The MOSFET device according to claim 1, wherein the epi layer is formed by stacking a plurality of epi layers having different doping concentrations.
5. The MOSFET device according to claim 4, wherein the plurality of epi layers having different doping concentrations have different layer thicknesses.
6. The MOSF according to claim 4 or claim 5.
In the ET device, the epitaxial layer includes a second epi layer having a low doping concentration and a thick layer and a first epi layer having a high doping concentration and a thin layer.
7. The MOSFET device according to claim 6, wherein, of the second epi layer and the first epi layer, the second epi layer is provided on a side closer to a channel portion.
8. The MOSF according to claim 6 or claim 7.
In the ET element, when the withstand voltage is 1000 V, the doping concentration of the first epi layer is 3 to 6 times the doping concentration of the second epi layer.
A MOSFET device wherein the thickness of the first epi layer is 1/8 to 1/5 times the thickness of the second epi layer.
9. The MOSFET device according to claim 1, wherein the doping concentration is a variable indicating a position of the epi layer in the layer thickness direction, and the doping concentration at the position is N. (X), assuming that the width of the epi layer is W, assuming that A and B are constants, and a doping concentration represented by the following equation N (x) = A / (1-x / W) B or an approximate value thereof. MOSFET element to be set.
10. The MOSFET device according to claim 6, wherein a doping concentration and a layer thickness of the first epi layer and the second epi layer are in a thickness direction of the epi layer. A variable representing a position is x, and a doping concentration N (x) at the position is N (x) = D0 ≦ x <αW N (x) = cD αW ≦ x <W, and the Poisson equation is solved to obtain constants D, W is the withstand voltage VB
, The on-resistance R is determined by assuming the mobility μ, and the constants α and c that minimize the R are determined to obtain the constants D and W.
The doping concentration of the first epi layer is set to cD or its approximate value, the layer thickness of the first epi layer is set to (W-αW) or its approximate value, and the doping concentration of the second epi layer is set to D or its approximate value. Wherein the thickness of the second epi layer is set to αW or an approximate value thereof.
11. A method for manufacturing a MOSFET device having an epi layer provided on a semiconductor substrate, a source and a drain interposed between the epi layers, and having a predetermined breakdown voltage, wherein the step of providing the epi layer comprises: Providing a first epi layer having a predetermined doping concentration, a predetermined layer thickness, and a first drift resistance on the semiconductor substrate; and forming the first doping concentration on the first epi layer. Providing a second epi layer having a different doping concentration and having the same or different layer thickness as the first epi layer and having a second drift resistance. The concentration and the layer thickness, and the doping concentration and the layer thickness of the second epi layer, are such that the series resistance value of the first drift resistor and the second drift resistor is minimum or close to the predetermined withstand voltage. A method for manufacturing a MOSFET device.
JP11086825A 1999-03-29 1999-03-29 Mosfet element and manufacture thereof Pending JP2000286415A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6639278B2 (en) 2001-01-25 2003-10-28 Nec Electronics Corporation Semiconductor device
DE112006003742T5 (en) 2006-02-07 2008-12-24 Mitsubishi Electric Corp. Semiconductor device and method of making the same
JP2009158788A (en) * 2007-12-27 2009-07-16 Oki Semiconductor Co Ltd Vertical mosfet and manufacturing method of the vertical mosfet
JP2010067670A (en) * 2008-09-09 2010-03-25 Sumitomo Electric Ind Ltd Well structure, method for generating the same, and semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6639278B2 (en) 2001-01-25 2003-10-28 Nec Electronics Corporation Semiconductor device
DE112006003742T5 (en) 2006-02-07 2008-12-24 Mitsubishi Electric Corp. Semiconductor device and method of making the same
US8222649B2 (en) 2006-02-07 2012-07-17 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing the same
JP2009158788A (en) * 2007-12-27 2009-07-16 Oki Semiconductor Co Ltd Vertical mosfet and manufacturing method of the vertical mosfet
JP2010067670A (en) * 2008-09-09 2010-03-25 Sumitomo Electric Ind Ltd Well structure, method for generating the same, and semiconductor device

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