JP2012204503A - Compound semiconductor device and method of manufacturing the same - Google Patents

Compound semiconductor device and method of manufacturing the same Download PDF

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JP2012204503A
JP2012204503A JP2011066273A JP2011066273A JP2012204503A JP 2012204503 A JP2012204503 A JP 2012204503A JP 2011066273 A JP2011066273 A JP 2011066273A JP 2011066273 A JP2011066273 A JP 2011066273A JP 2012204503 A JP2012204503 A JP 2012204503A
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gate electrode
electrode
layer
low
gate
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JP5866782B2 (en
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Michihito Nishimori
Tadahiro Imada
忠紘 今田
理人 西森
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Fujitsu Ltd
富士通株式会社
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Abstract

The present invention provides a compound semiconductor device and a method for manufacturing the same that can improve the operation efficiency while maintaining the pinch-off characteristics.
A substrate, an electron transit layer formed above the substrate, an electron supply layer formed above the electron transit layer, and a source electrode and a drain formed above the electron supply layer. Above the electron supply layer 13, an electrode 15d and a first gate electrode 15g-1 and a second gate electrode 15g-2 formed between the source electrode 15s and the drain electrode 15d are provided. The work function of the gate electrode 15g-1 is lower than the work function of the second gate electrode 15g-2.
[Selection] Figure 1

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  In a GaN-based high electron mobility transistor (HEMT), a heterojunction between an AlGaN layer and a GaN layer is used, and the GaN layer functions as an electron transit layer. GaN has a wide band gap, high breakdown field strength, and a large saturation electron velocity. Therefore, GaN is extremely promising as a material that realizes a large current operation, a high voltage operation, and a low on-resistance operation. Various studies have been conducted on the application of GaN-based HEMTs to next-generation high-efficiency amplifiers used in base stations and the like, and high-efficiency switching elements for power control.

  In order to improve the operation efficiency of such a GaN-based HEMT, it is important to improve the maximum current amount Imax and the mutual conductance gm. In order to improve the maximum current amount Imax and the mutual conductance gm, shortening the gate length is effective.

  However, when the gate length is shortened in the conventional GaN-based HEMT, the width of the depletion layer at the time of OFF is narrowed, and the pinch-off characteristic is deteriorated. That is, it is difficult to achieve both high efficiency and maintaining pinch-off characteristics.

JP-A-6-283725

  An object of the present invention is to provide a compound semiconductor device capable of improving the operation efficiency while maintaining the pinch-off characteristic, and a method for manufacturing the same.

  One aspect of the compound semiconductor device includes a substrate, an electron transit layer formed above the substrate, an electron supply layer formed above the electron transit layer, a source electrode formed above the electron supply layer, and A drain electrode and a first gate electrode and a second gate electrode formed between the source electrode and the drain electrode are provided above the electron supply layer. The work function of the first gate electrode is lower than the work function of the second gate electrode.

  In the compound semiconductor device manufacturing method, an electron transit layer is formed above a substrate, an electron supply layer is formed above the electron transit layer, and a first gate electrode, a second gate electrode, A source electrode and a drain electrode are formed. The first gate electrode and the second gate electrode are located between the source electrode and the drain electrode. The work function of the first gate electrode is lower than the work function of the second gate electrode.

  According to the above compound semiconductor device or the like, the operation efficiency can be improved while maintaining the pinch-off characteristics by the action of the first gate electrode and the second gate electrode having different work functions.

It is a figure which shows the structure of GaN-type HEMT which concerns on 1st Embodiment. It is a band figure which shows the conduction band in an OFF state. It is a band figure which shows the conduction band in an ON state. It is a figure which shows the structure of GaN-type HEMT which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of GaN-type HEMT which concerns on 2nd Embodiment to process order. It is sectional drawing which shows the manufacturing method of GaN-type HEMT which concerns on 2nd Embodiment in order of a process following FIG. 5A. It is sectional drawing which shows the other manufacturing method of GaN-type HEMT which concerns on 2nd Embodiment in process order. It is sectional drawing which shows the modification of 2nd Embodiment. It is sectional drawing which shows the other modification of 2nd Embodiment. It is a figure which shows the structure of GaN-type HEMT which concerns on 3rd Embodiment. It is sectional drawing which shows the manufacturing method of GaN-type HEMT which concerns on 3rd Embodiment in process order. It is a figure which shows the structure of GaN-type HEMT which concerns on 4th Embodiment. It is sectional drawing which shows the manufacturing method of GaN-type HEMT which concerns on 4th Embodiment in process order. It is sectional drawing which shows the modification of 4th Embodiment. It is sectional drawing which shows the manufacturing method of the modification of 4th Embodiment to process order. It is a figure which shows the example of GaN-type HEMT with a short gate length. It is a figure which shows the example of GaN-type HEMT with a long gate length. It is a figure which shows the example of the GaN-type HEMT according to 3rd Embodiment. It is a figure which shows the example of the GaN-type HEMT according to 2nd Embodiment. It is a figure which shows the example of the external appearance of a high output amplifier. It is a figure which shows a power supply device.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. FIG. 1 is a diagram illustrating a structure of a GaN-based HEMT (compound semiconductor device) according to the first embodiment.

In the first embodiment, as shown in FIG. 1, an electron transit layer 12 is formed above the substrate 11, an electron supply layer 13 is formed above the electron transit layer 12, and an insulating film 14 is provided above the electron supply layer 13. Is formed. Further, a source electrode 15s and a drain electrode 15d are formed above the electron supply layer 13, and a low work function (WF) gate electrode 15g-1 is sandwiched between the source electrode 15s and the drain electrode 15d above the insulating film 14. In addition, a high work function (WF) gate electrode 15g-2 is formed. The work function φ m1 of the low WF gate electrode 15g-1 is lower than the work function φ m2 of the high WF gate electrode 15g-2, and the low WF gate electrode 15g-1 is closer to the source electrode 15s than the high WF gate electrode 15g-2. Is located.

  FIG. 2 is a band diagram showing the conduction band in the off state, and FIG. 3 is a band diagram showing the conduction band in the on state. 2A and 3A show the conduction band in the thickness direction from the low WF gate electrode 15g-1 to the electron transit layer 12, and FIGS. 2B and 3B show the high conduction band. The conduction band in the thickness direction from the WF gate electrode 15g-2 to the electron transit layer 12 is shown.

  In the off-state, as shown in FIG. 2, a two-dimensional electron gas (2DEG) exists below the low WF gate electrode 15g-1, but below the low WF gate electrode 15g-1 and the high WF gate electrode 15g-2. A depletion layer is formed. That is, a wide depletion layer is formed. The depletion layer below the high WF gate electrode 15g-2 is deep. Therefore, good pinch-off characteristics can be obtained.

On the other hand, in the ON state, as shown in FIG. 3, since the lower band of the low WF gate electrode 15g-1 is pushed down, a high maximum current amount Imax and a mutual conductance gm can be obtained. This is because the work function φ m1 of the low WF gate electrode 15g-1 is lower than the work function φ m2 of the high WF gate electrode 15g-2 and is lower than the on-voltage of the high WF gate electrode 15g-2. This is because the channel is formed deeply below the electrode 15g-1.

  As described above, according to the first embodiment, it is possible to improve the operating efficiency by improving the maximum current amount Imax and the mutual conductance gm while maintaining the pinch-off characteristic.

  Note that the same voltage may be applied to the low WF gate electrode 15g-1 and the high WF gate electrode 15g-2, or different voltages may be applied to each other. When different voltages are applied, it is preferable to apply a higher voltage to the high WF gate electrode 15g-2 than to the low WF gate electrode 15g-1.

  The low WF gate electrode 15g-1 may be positioned closer to the drain electrode 15d than the high WF gate electrode 15g-2. However, in order to reduce the source resistance and obtain a high transconductance gm, The electrode 15g-1 is preferably located on the source electrode 15s side.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 4 is a diagram illustrating a structure of a GaN-based HEMT (compound semiconductor device) according to the second embodiment.

In the second embodiment, a nucleation layer 26 is formed on a substrate 21 as shown in FIG. For example, the substrate 21 is a SiC substrate and the nucleation layer 26 is an AlN layer. An electron transit layer 22 is formed on the nucleation layer 26. The electron transit layer 22 is, for example, a non-doped i-GaN layer having a thickness of about 1 μm to 4 μm (for example, 3 μm). A spacer layer 26 and an electron supply layer 23 are formed on the electron transit layer 22. The spacer layer 26 is a non-doped i-AlGaN layer having a thickness of, for example, about 1 nm to 30 nm (for example, 3 nm), and the electron supply layer 23 is an n-type n having a thickness of, for example, about 3 nm to 30 nm (for example, 20 nm). -An AlGaN layer. The Al composition of these i-AlGaN layer and n-AlGaN layer is about 0.1 to 0.5 (for example, 0.25). The n-AlGaN layer is doped with Si at about 1 × 10 18 cm −3 to 1 × 10 20 cm −3 (for example, 2 × 10 18 cm −3 ). A protective layer 28 is formed on the electron supply layer 23. The protective layer 28 is an n-type n-GaN layer having a thickness of about 2 nm to 20 nm (for example, 10 nm), for example. The n-GaN layer is doped with Si at about 1 × 10 18 cm −3 to 1 × 10 20 cm −3 (for example, 2 × 10 18 cm −3 ).

Recesses 29-1 and 29-2 reaching the middle of the electron supply layer 23 in the depth direction are formed in the protective layer 28 and the electron supply layer 23. An insulating film 24 that covers the inner surfaces of the recesses 29-1 and 29-2 is formed on the protective layer 28. The insulating film 24 is, for example, an Al 2 O 3 film having a thickness of about 30 nm. Concave portions 29s and 29d are formed in the insulating film 24 and the protective layer 28 so that the recesses 29-1 and 29-2 are sandwiched therebetween. The recess 29s is located on the recess 29-1 side, and the recess 29d is located on the recess 29-2 side. A source electrode 25s is formed in the recess 29s, and a drain electrode 25d is formed in the recess 29d. The source electrode 25s and the drain electrode 25d include, for example, a stacked body of a Ta film and an Al film thereon. On the insulating film 24, a low WF gate electrode 25g-1 entering the recess 29-1 and a high WF gate electrode 25g-2 entering the recess 29-2 are formed. The low WF gate electrode 25g-1 includes, for example, a stacked body of a Ta film and an Al film thereon, and the high WF gate electrode 25g-2 includes, for example, a stacked body of a Pt film and an Au film thereon. Including. The work function of Ta is 4.25 eV, and the work function of Al is 4.28 eV. The work function of Pt is 5.65 eV, and the work function of Au is 5.1 eV. Therefore, the work function of the low WF gate electrode 25g-1 is lower than the work function of the high WF gate electrode 25g-2.

  In the second embodiment configured as described above, the relationship between the low WF gate electrode 25g-1 and the high WF gate electrode 25g-2 is the same as the low WF gate electrode 15g-1 and the high WF gate of the first embodiment. Since the relationship with the electrode 15g-2 is the same, it is possible to improve the operating efficiency by improving the maximum current amount Imax and the mutual conductance gm while maintaining the pinch-off characteristic by the same mechanism as in the first embodiment. it can. Further, since the gate recess structure is adopted for the low WF gate electrode 25g-1 and the high WF gate electrode 25g-2, better pinch-off characteristics can be obtained.

  Next, a method for manufacturing a GaN-based HEMT (compound semiconductor device) according to the second embodiment will be described. 5A to 5B are cross-sectional views showing a method of manufacturing a GaN-based HEMT (compound semiconductor device) according to the second embodiment in the order of steps.

First, as shown in FIG. 5A (a), a nucleation layer 26, an electron transit layer 22, an electron supply layer 23, a spacer layer 26, an electron supply layer 23, and a protective layer 28 are formed on a substrate 21. The nucleation layer 26, the electron transit layer 22, the electron supply layer 23, the spacer layer 26, the electron supply layer 23, and the protective layer 28 are formed by a crystal growth method such as a metal organic chemical vapor deposition (MOVPE) method. In this case, these layers can be formed continuously by selecting a source gas. As a raw material of aluminum (Al) and a raw material of gallium (Ga), for example, trimethylaluminum (TMA) and trimethylgallium (TMG) can be used, respectively. Further, for example, ammonia (NH 3 ) can be used as a raw material for nitrogen (N). Moreover, as a raw material of silicon (Si) contained as an impurity in the n-AlGaN layer and the n-GaN layer, for example, silane (SiH 4 ) can be used.

After the formation of the protective layer 28, as shown in FIG. 5A (b), recesses 29-1 and 29-2 that reach the middle of the electron supply layer 23 in the depth direction are formed in the protective layer 28 and the electron supply layer 23. . In forming the recesses 29-1 and 29-2, first, a photoresist agent is applied on the protective layer 28, and the photoresist 29 is irradiated with ultraviolet rays and developed to form the recess 29-1. And a resist pattern having an opening in a region where the recess 29-2 is to be formed. Next, recesses 29-1 and 29-2 are formed by dry etching using the resist pattern as an etching mask. Then, the resist pattern is removed. In dry etching, for example, a Cl 2 gas may be used.

After the formation of the recesses 29-1 and 29-2, as shown in FIG. 5B (c), an insulating film 24 that covers the inner surfaces of the recesses 29-1 and 29-2 is formed on the protective layer 28. When an Al 2 O 3 film is formed as the insulating film 24, for example, a TMA gas and an O 3 gas may be alternately supplied into an atomic layer deposition (ALD) apparatus.

  Next, as shown in FIG. 5B (d), a high WF gate electrode 25 g-2 that enters the recess 29-2 is formed on the insulating film 24. The high WF gate electrode 25g-2 can be formed by, for example, a lift-off method. In this case, first, a photoresist agent is applied on the insulating film 24, and the photoresist agent is irradiated with ultraviolet rays and developed, and a resist having an opening in a region where the high WF gate electrode 25g-2 is to be formed. Form a pattern. Next, vapor deposition of Pt and Au is performed in a reduced pressure atmosphere using the resist pattern as a film formation mask, and then the Pt and Au attached on the resist pattern are removed together with the resist pattern.

After the formation of the high WF gate electrode 25g-2, as shown in FIG. 5B (e), the recesses 29s and 29d are formed in the insulating film 24 and the protective layer 28 with the recesses 29-1 and 29-2 interposed therebetween. To do. In forming the recesses 29s and 29d, first, a photoresist agent is applied on the insulating film 24 and the high WF gate electrode 25g-2, and the photoresist agent is irradiated with ultraviolet rays and developed to form the recess 29s. And a resist pattern having an opening in a region where the recess 29d is to be formed. Next, recesses 29s and 29d are formed by etching using the resist pattern as an etching mask. For example, the etching of the insulating film 24 may be performed by wet etching using a KOH solution, and the etching of the protective layer 28 may be performed by dry etching using a Cl 2 gas.

  After the formation of the recesses 29s and 29d, as shown in FIG. 5B (f), the low WF gate electrode 25g-1 entering the recess 29-1 is formed, the source electrode 25s is formed in the recess 29s, and the recess 29d A drain electrode 25d is formed on the substrate. The low WF gate electrode 25g-1, the source electrode 25s, and the drain electrode 25d can be formed by, for example, a lift-off method. In this case, first, a photoresist agent is applied onto the insulating film 24 and the high WF gate electrode 25g-2, and the photoresist agent is irradiated with ultraviolet rays and developed to form the low WF gate electrode 25g-1. In this region, a resist pattern having an opening is formed in the region where the source electrode 25s is to be formed and the region where the drain electrode 25d is to be formed. Next, Ta and Al are vapor-deposited in a reduced pressure atmosphere using the resist pattern as a film formation mask, and then the Ta and Al attached on the resist pattern are removed together with the resist pattern. Then, heat treatment is performed at 400 ° C. to 1000 ° C. (for example, 600 ° C.) in a nitrogen atmosphere to establish ohmic characteristics of the source electrode 25s and the drain electrode 25d. The ohmic characteristics may be established by implanting and activating ions before forming the source electrode 25s and the drain electrode 25d.

  In this way, a GaN-based HEMT having the structure shown in FIG. 4 can be obtained.

  Note that the low WF gate electrode 25g-1, the source electrode 25s, and the drain electrode 25d may be formed before the high WF gate electrode 25g-2. This method is shown in FIG.

  In this method, after forming the insulating film 24 (FIG. 5B (c)), as shown in FIG. 6 (a), recesses 29s and 29d are formed. Next, as shown in FIG. 6B, for example, a low WF gate electrode 25g-1, a source electrode 25s, and a drain electrode 25d are formed by a lift-off method. Then, the ohmic characteristics of the source electrode 25s and the drain electrode 25d are established. Thereafter, as shown in FIG. 6C, a high WF gate electrode 25g-2 is formed.

  The low WF gate electrode 25g-1 and the high WF gate electrode 25g-2 of the second embodiment may be connected to each other. The structure in this case is, for example, as shown in FIG. That is, an insulating film 30a covering the low WF gate electrode 25g-1, the high WF gate electrode 25g-2, the source electrode 25s, and the drain electrode 25d is formed, and a hole reaching the low WF gate electrode 25g-1 and a high WF A hole reaching the gate electrode 25g-2 is formed. A wiring 31 for connecting the low WF gate electrode 25g-1 and the high WF gate electrode 25g-2 to each other through these holes is formed. Further, an insulating film 30b covering the wiring 31 is formed on the insulating film 30a. Similar wiring may be provided in the first embodiment.

  Further, as shown in FIG. 8, in the second embodiment, the recesses 29 s and 29 d may be formed only in the insulating film 24 without being formed in the protective layer 28. Even when the recesses 29 s and 29 d are formed also in the protective layer 28, a part of the protective layer 28 may be left, or a part of the electron supply layer 23 may be removed. That is, the depths of the recesses 29 s and 29 d do not need to match the total thickness of the insulating film 24 and the protective layer 28.

(Third embodiment)
Next, a third embodiment will be described. FIG. 9 is a diagram illustrating a structure of a GaN-based HEMT (compound semiconductor device) according to the third embodiment.

  In the third embodiment, the recess 29-1 is not formed in the protective layer 28 and the insulating film 24. Instead of the low WF gate electrode 25g-1 having a gate recess structure, the low WF gate electrode 35g- having a flat bottom surface is used. 1 is formed on the insulating film 24. Other configurations are the same as those of the second embodiment.

  In the third embodiment configured as described above, the maximum current amount Imax and the mutual conductance gm can be further improved, although the pinch-off characteristics are slightly lowered as compared with the second embodiment.

  Next, a method for manufacturing a GaN-based HEMT (compound semiconductor device) according to the third embodiment will be described. FIG. 10 is a cross-sectional view showing a GaN-based HEMT (compound semiconductor device) manufacturing method according to the third embodiment in the order of steps.

  First, similarly to the second embodiment, processing up to the formation of the protective layer 28 is performed (FIG. 5A (a)). Next, as shown in FIG. 10A, a recess 29-2 is formed. Thereafter, as shown in FIG. 10B, the insulating film 24 is formed on the protective layer 28. Subsequently, as shown in FIG. 10C, a high WF gate electrode 25 g-2 is formed on the insulating film 24. Next, as shown in FIG. 10D, recesses 29s and 29d are formed, and a low WF gate electrode 25g-1, a source electrode 25s, and a drain electrode 25d are formed. Then, the ohmic characteristics of the source electrode 25s and the drain electrode 25d are established.

  In this way, a GaN-based HEMT having the structure shown in FIG. 9 can be obtained.

(Fourth embodiment)
Next, a fourth embodiment will be described. FIG. 11 is a diagram illustrating a structure of a GaN-based HEMT (compound semiconductor device) according to the fourth embodiment.

  In the fourth embodiment, instead of the high WF gate electrode 25g-2, the high WF gate electrode 45g-2 is formed on the insulating film 24 so as to run over the low WF gate electrode 25g-1. Other configurations are the same as those of the second embodiment.

  In the fourth embodiment configured as described above, a signal having the same potential can be easily applied to the low WF gate electrode 25g-1 and the high WF gate electrode 45g-2. That is, a signal having the same potential can be applied to the low WF gate electrode 25g-1 and the high WF gate electrode 45g-2 without forming the wiring 31.

  Next, a method for manufacturing a GaN-based HEMT (compound semiconductor device) according to the fourth embodiment will be described. FIG. 12 is a cross-sectional view showing a GaN-based HEMT (compound semiconductor device) manufacturing method according to the fourth embodiment in the order of steps.

  First, similarly to the second embodiment, processing up to the formation of the insulating film 24 is performed (FIG. 5B (c)). Next, as shown in FIG. 12A, recesses 29s and 29d are formed. Thereafter, as shown in FIG. 12B, a low WF gate electrode 25g-1, a source electrode 25s, and a drain electrode 25d are formed. Then, the ohmic characteristics of the source electrode 25s and the drain electrode 25d are established. Subsequently, as shown in FIG. 12C, a high WF gate electrode 45g-2 is formed on the insulating film 24 so as to run over the low WF gate electrode 25g-1. The high WF gate electrode 45g-2 can be formed by, for example, a lift-off method.

  In this way, a GaN-based HEMT having the structure shown in FIG. 11 can be obtained.

  As shown in FIG. 13, instead of the low WF gate electrode 25g-1, the low WF gate electrode 45g-1 may be formed on the insulating film 24 so as to run over the high WF gate electrode 25g-2. Good.

  FIG. 14 shows a method of manufacturing a GaN-based HEMT having such a structure in the order of steps. First, as shown in FIG. 14A, similarly to the second embodiment, processing up to the formation of the recesses 29s and 29d is performed (FIG. 5B (e)). Next, as shown in FIG. 14B, the low WF gate electrode 45g-1 is formed on the insulating film 24 so as to run over the high WF gate electrode 25g-2, and the source electrode 25s is formed in the recess 29s. Then, the drain electrode 25d is formed in the recess 29d. The low WF gate electrode 45g-1, the source electrode 25s, and the drain electrode 25d can be formed by, for example, a lift-off method. Note that before the source electrode 25s and the drain electrode 25d are formed, it is preferable to establish ohmic characteristics by ion implantation and activation. That is, it is desirable to establish ohmic characteristics without performing heat treatment by using a technique such as ion implantation at this time. This is because when the heat treatment is performed, the work function of the high WF gate electrode 25g-2 may change due to the reaction between the already formed high WF gate electrode 25g-2 and the low WF gate electrode 45g-1. .

  In this way, a GaN-based HEMT having the structure shown in FIG. 13 can be obtained.

  Here, the relationship between the work function and dimensions of the gate electrode and the voltage-current characteristics will be described.

  FIG. 15A shows an example of a GaN-based HEMT in which only the high WF gate electrode 115g-2 is provided as the gate electrode, and FIG. 15B shows only the low WF gate electrode 115g-1 provided as the gate electrode. An example of a GaN-based HEMT is shown. The work function of the high WF gate electrode 115g-2 is higher than the work function of the low WF gate electrode 115g-1. In any example, the GaN layer 112, the AlGaN layer 113, and the n-GaN layer 118 are formed on the substrate 111, and the high WF gate electrode 115g- having a gate recess structure is formed on the n-GaN layer 118 via the alumina film 114. 2 or a low WF gate electrode 115g-1. A source electrode 115 s and a drain electrode 115 d are formed on the AlGaN layer 113. Further, in any example, the gate length Lg is 0.7 μm, and the distance between the source electrode 115s and the high WF gate electrode 115g-2 or the low WF gate electrode 115g-1 is 2 μm. In these examples, the voltage-current characteristics between the gate voltage Vg and the drain current Id are as shown in FIG. Here, the source resistance is 1 Ωmm and the sheet resistance is 500 Ω / □.

  The example shown in FIG. 16 is an example in which the gate length Lg is larger than the example shown in FIG. 15, and the gate length Lg is 2.2 μm. FIG. 16A shows an example of a GaN-based HEMT in which only the high WF gate electrode 125g-2 is provided as a gate electrode, and FIG. 16B shows only the low WF gate electrode 125g-1 provided as a gate electrode. An example of a GaN-based HEMT is shown. The material of the high WF gate electrode 125g-2 is the same as the material of the high WF gate electrode 115g-2, and the material of the low WF gate electrode 125g-1 is the same as the material of the low WF gate electrode 115g-1. In these examples, the voltage-current characteristics between the gate voltage Vg and the drain current Id are as shown in FIG. Here again, the source resistance is 1 Ωmm and the sheet resistance is 500 Ω / □.

  The example shown in FIG. 17 is an example following the third embodiment (FIG. 9), and a low WF gate electrode 135g-1 and a high WF gate electrode 115g-2 are provided as gate electrodes. The material of the low WF gate electrode 135g-1 is the same as the material of the low WF gate electrode 115g-1. The low WF gate electrode 135g-1 and the high WF gate electrode 115g-2 are connected to each other. The distance between the source electrode 115s and the high WF gate electrode 115g-2 is 2 μm, and the dimension of the low WF gate electrode 135g-1 in the gate length direction is 1.5 μm. In this example, the voltage-current characteristic between the gate voltage Vg and the drain current Id is as shown in FIG. Here, the source resistance is 0.7 Ωmm, the sheet resistance below the low WF gate electrode 135g-1 is 300 Ω / □, and the sheet resistance in other regions is 500 Ω / □.

  The example shown in FIG. 18 is an example following the second embodiment (FIG. 4), and a low WF gate electrode 115g-1 and a high WF gate electrode 115g-2 are provided as gate electrodes. The low WF gate electrode 115g-1 and the high WF gate electrode 115g-2 are connected to each other. The distance between the source electrode 115s and the high WF gate electrode 115g-2 is 2 μm, and the dimension of the low WF gate electrode 115g-1 in the gate length direction is 0.8 μm. In this example, the voltage-current characteristic between the gate voltage Vg and the drain current Id is as shown in FIG. Here, the source resistance when the on-voltage is not applied is 1.3 Ωmm, the source resistance when the on-voltage is applied is 0.84 Ωmm, and the sheet resistance below the low WF gate electrode 115g-1 is 1000Ω. / □, sheet resistance in other regions is 500Ω / □. The reason why such a condition is used is that a recess gate structure is adopted for the low WF gate electrode 115g-1, and a two-dimensional electron gas is generated deeply. Further, the threshold voltage of the high WF gate electrode 115g-2 is 3V, and the threshold voltage of the low WF gate electrode 115g-1 is 1V.

  In any of the embodiments, a resistor, a capacitor, and the like may be mounted on a substrate to form a monolithic microwave integrated circuit (MMIC).

  The GaN-based HEMT according to these embodiments can be used as, for example, a high-power amplifier. FIG. 19 shows an example of the appearance of the high-power amplifier. In this example, a source terminal 81s connected to the source electrode is provided on the surface of the package. A gate terminal 81g connected to the gate electrode and a drain terminal 81d connected to the drain electrode extend from the side surface of the package.

  In addition, the GaN-based HEMTs according to these embodiments can be used for, for example, a power supply device. FIG. 20A is a diagram illustrating a PFC (power factor correction) circuit, and FIG. 20B is a diagram illustrating a server power supply (power supply device) including the PFC circuit illustrated in FIG.

  As shown in FIG. 20A, the PFC circuit 90 is provided with a capacitor 92 connected to a diode bridge 91 to which an AC power supply (AC) is connected. One terminal of the capacitor 92 is connected to one terminal of the choke coil 93, and the other terminal of the choke coil 93 is connected to one terminal of the switch element 94 and the anode of the diode 96. The switch element 94 corresponds to the HEMT in the above embodiment, and the one terminal corresponds to the drain electrode of the HEMT. The other terminal of the switch element 94 corresponds to a source electrode of the HEMT. One terminal of a capacitor 95 is connected to the cathode of the diode 96. The other terminal of the capacitor 92, the other terminal of the switch element 94, and the other terminal of the capacitor 95 are grounded. Then, a direct current power supply (DC) is taken out between both terminals of the capacitor 95.

  Then, as shown in FIG. 20B, the PFC circuit 90 is used by being incorporated in the server power supply 100 or the like.

  It is also possible to construct a power supply device that can operate at a higher speed, similar to the server power supply 100. A switch element similar to the switch element 94 can be used for a switch power supply or an electronic device. Further, these semiconductor devices can be used as components for a full-bridge power supply circuit such as a server power supply circuit.

  In any embodiment, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, a GaN substrate, a GaAs substrate, or the like may be used as the substrate. The substrate may be conductive, semi-insulating, or insulating.

  Further, the structures of the gate electrode, the source electrode, and the drain electrode are not limited to those of the above-described embodiment. For example, these may be composed of a single layer. Moreover, these formation methods are not limited to the lift-off method. Furthermore, if ohmic characteristics can be obtained, the heat treatment after the formation of the source electrode and the drain electrode may be omitted. Further, heat treatment may be performed on the gate electrode.

  Further, the thickness and material of each layer are not limited to those of the above-described embodiment.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A substrate,
An electron transit layer formed above the substrate;
An electron supply layer formed above the electron transit layer;
A source electrode and a drain electrode formed above the electron supply layer;
A first gate electrode and a second gate electrode formed between the source electrode and the drain electrode above the electron supply layer;
Have
A compound semiconductor device, wherein a work function of the first gate electrode is lower than a work function of the second gate electrode.

(Appendix 2)
The compound semiconductor device according to appendix 1, wherein the first gate electrode and the second gate electrode are connected to each other.

(Appendix 3)
The compound semiconductor device according to appendix 1 or 2, wherein the first gate electrode is located closer to the source electrode than the second gate electrode.

(Appendix 4)
An insulating film formed above the electron supply layer;
The compound semiconductor device according to any one of appendices 1 to 3, wherein the first gate electrode and the second gate electrode are formed above the insulating film.

(Appendix 5)
5. The compound semiconductor device according to any one of appendices 1 to 4, wherein a gate recess structure is used for the second gate.

(Appendix 6)
6. The compound semiconductor device according to any one of appendices 1 to 5, wherein a gate recess structure is used for the first gate.

(Appendix 7)
Forming an electron transit layer above the substrate;
Forming an electron supply layer above the electron transit layer;
Forming a first gate electrode, a second gate electrode, a source electrode, and a drain electrode above the electron supply layer;
Have
The first gate electrode and the second gate electrode are located between the source electrode and the drain electrode,
A method of manufacturing a compound semiconductor device, wherein a work function of the first gate electrode is lower than a work function of the second gate electrode.

(Appendix 8)
The method of manufacturing a compound semiconductor device according to appendix 7, wherein the first gate electrode and the second gate electrode are connected to each other.

(Appendix 9)
9. The method of manufacturing a compound semiconductor device according to appendix 7 or 8, wherein the first gate electrode is positioned closer to the source electrode than the second gate electrode.

(Appendix 10)
Forming an insulating film above the electron supply layer before forming the first gate electrode and the second gate electrode;
10. The method of manufacturing a compound semiconductor device according to any one of appendices 7 to 9, wherein the first gate electrode and the second gate electrode are formed above the insulating film.

11, 21: Substrate 12, 22: Electron traveling layer 13, 23: Electron supply layer 14, 24: Insulating film 15g-1, 25g-1, 35g-1, 45g-1: Low WF gate electrode 15g-2, 25g -2, 45g-2: High WF gate electrode 15s, 25s: Source electrode 15d, 25d: Drain electrode 29-1, 29-2: Recess 31: Wiring

Claims (6)

  1. A substrate,
    An electron transit layer formed above the substrate;
    An electron supply layer formed above the electron transit layer;
    A source electrode and a drain electrode formed above the electron supply layer;
    A first gate electrode and a second gate electrode formed between the source electrode and the drain electrode above the electron supply layer;
    Have
    A compound semiconductor device, wherein a work function of the first gate electrode is lower than a work function of the second gate electrode.
  2.   The compound semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are connected to each other.
  3.   3. The compound semiconductor device according to claim 1, wherein the first gate electrode is located closer to the source electrode than the second gate electrode. 4.
  4. An insulating film formed above the electron supply layer;
    4. The compound semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are formed above the insulating film. 5.
  5. Forming an electron transit layer above the substrate;
    Forming an electron supply layer above the electron transit layer;
    Forming a first gate electrode, a second gate electrode, a source electrode, and a drain electrode above the electron supply layer;
    Have
    The first gate electrode and the second gate electrode are located between the source electrode and the drain electrode,
    A method of manufacturing a compound semiconductor device, wherein a work function of the first gate electrode is lower than a work function of the second gate electrode.
  6.   6. The method of manufacturing a compound semiconductor device according to claim 5, further comprising a step of connecting the first gate electrode and the second gate electrode to each other.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103474455A (en) * 2013-08-21 2013-12-25 电子科技大学 Gallium nitride based high electron mobility transistor with composite metal gate
JP2015130436A (en) * 2014-01-08 2015-07-16 富士通株式会社 Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06140356A (en) * 1992-10-23 1994-05-20 Fujitsu Ltd Semiconductor device
JPH10107043A (en) * 1996-09-30 1998-04-24 Sanyo Electric Co Ltd Field effect semiconductor device and its manufacture
JP2004273501A (en) * 2003-03-05 2004-09-30 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06140356A (en) * 1992-10-23 1994-05-20 Fujitsu Ltd Semiconductor device
JPH10107043A (en) * 1996-09-30 1998-04-24 Sanyo Electric Co Ltd Field effect semiconductor device and its manufacture
JP2004273501A (en) * 2003-03-05 2004-09-30 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103474455A (en) * 2013-08-21 2013-12-25 电子科技大学 Gallium nitride based high electron mobility transistor with composite metal gate
JP2015130436A (en) * 2014-01-08 2015-07-16 富士通株式会社 Semiconductor device

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