TWI726282B - Semiconductor devices and methods for fabricating the same - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, and a nitride layer disposed over the barrier layer. The semiconductor device also includes a compound semiconductor layer including an upper portion and a lower portion, wherein the lower portion penetrates through the nitride layer and a portion of the barrier layer. The semiconductor device also includes a spacer layer conformally disposed on a portion of barrier layer and extending over the nitride layer. The semiconductor device further includes a gate electrode disposed over the compound semiconductor layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extends through the spacer layer, the nitride layer, and at least a portion of the barrier layer.

Description

Semiconductor device and manufacturing method thereof

The embodiments of the present invention are related to semiconductor devices, and in particular, to high electron mobility transistors and manufacturing methods thereof.

High electron mobility transistor (HEMT), also known as heterostructure FET (HFET) or modulation-doped FET (MODFET), is a kind of A field effect transistor (FET) is composed of semiconductor materials with different energy gaps. A two-dimensional electron gas (2DEG) layer is generated adjacent to the formed interface of different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, the high electron mobility transistor can have the advantages of high breakdown voltage, high electron mobility, low on-resistance and low input capacitance, and is therefore suitable for high-power devices.

When designing high electron mobility transistors, the main considerations are low on-resistance (R _on ) and high switching voltage (threshold voltage, V _th ). However, the two-dimensional electron gas of GaN high electron mobility transistors does not need to be doped. The carrier sources are mainly surface state and unintentional doping, which are essentially caused by defects. The free carrier comes. Therefore, the two-dimensional electron gas of the gallium nitride high electron mobility transistor is very sensitive to electric field changes, and electrical dispersion occurs during the switching operation.

Therefore, although existing gallium nitride high electron mobility transistors generally meet their intended purpose, they are not completely satisfactory in all aspects. How to effectively solve the impact of electrical scattering on component performance is the current focus of technological development.

The embodiment of the present invention provides a semiconductor device. The semiconductor device includes a channel layer provided on a substrate, a barrier layer provided on the channel layer, and a nitride layer provided on the barrier layer. The semiconductor device also includes a compound semiconductor layer having an upper portion and a lower portion, wherein the lower portion passes through the nitride layer and a part of the barrier layer. The semiconductor device also includes a spacer layer compliantly disposed on a part of the barrier layer and extending to the nitride layer. In addition, the above-mentioned semiconductor device further includes a gate electrode provided on the compound semiconductor layer, and a pair of source/drain electrodes provided on both sides of the gate electrode. The source/drain electrode extends through the spacer layer, the nitride layer and at least a part of the barrier layer.

The embodiment of the present invention provides a method for manufacturing a semiconductor device. The method includes forming a channel layer on the substrate, forming a barrier layer on the channel layer, forming a nitride layer on the barrier layer, etching the nitride layer and the barrier layer to form a notch, wherein the notch is Passing through the nitride layer and a part of the barrier layer, a spacer layer is conformably formed on the nitride layer and in the recess, and a compound semiconductor layer is formed on the spacer layer. The compound semiconductor layer has an upper portion and a lower portion, and the lower portion of the compound semiconductor layer is filled in the recess. The method further includes forming a gate electrode on the compound semiconductor layer, and forming a pair of source/drain electrodes on both sides of the gate electrode, wherein the source/drain electrode extends through the spacer layer, the nitride layer and at least Part of the barrier layer.

The following embodiments and accompanying reference drawings will provide a detailed description.

The following disclosure provides many different embodiments or examples to illustrate the different components of the embodiments of the present invention. The following will disclose specific examples of the components and their arrangement in this specification to simplify the description of this disclosure. Of course, these specific examples are not used to limit the disclosure. For example, if the following invention content of this specification describes that the first part is formed on or above the second part, it means that it includes an embodiment in which the formed first and second parts are in direct contact, and also includes Additional components can be formed between the above-mentioned first and second components, and the first and second components are embodiments that are not in direct contact. In addition, the various examples in this disclosure may use repeated reference symbols and/or words. The purpose of these repeated symbols or words is for simplification and clarity, and is not used to limit the relationship between the various embodiments and/or the configurations.

Furthermore, in order to facilitate the description of the relationship between one element or component and another element or component(s) in the diagram, spatial relative terms can be used, such as "below", "below", "lower", "above" , "Upper" and the like. In addition to the orientation shown in the diagram, the relative terms of space also cover different orientations of the device in use or operation. When the device is turned in different directions (for example, rotated by 90 degrees or other directions), the spatially relative adjectives used therein will also be interpreted according to the turned position. It should be understood that additional operations may be provided before, during, and/or after the method described in the embodiments of the present invention, and in other embodiments of the method, some of the operations described may be replaced or omitted.

Here, the terms "about", "approximately", and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantity provided in the manual is an approximate quantity, that is, without specifying "about", "approximately", "approximately", "about", "approximately" and "approximately" can still be implied. The meaning of "probably".

Some changes to the example method and structure are described here. Those with ordinary knowledge in the art will easily understand that other modifications can be made within the scope of other embodiments. Although some of the method embodiments discussed are performed in a specific order, various other method embodiments can be performed in another logical order, and may include fewer or more steps than those discussed herein. In some illustrations, the symbol of some components or parts shown therein may be omitted to avoid confusion with other components or parts; this is for the convenience of depicting these illustrations.

The embodiments of the present invention provide a semiconductor device and a manufacturing method thereof, which are particularly suitable for high electron mobility transistors (HEMT). In some embodiments of the present invention, by disposing a nitride layer and a spacer layer on the barrier layer, and cutting the two layers in the gate region to form a notch, the electrical dispersion problem of the device can be eliminated. At the same time, the barrier layer outside the gate area can be made thicker to reduce the on-resistance, and the gate doping can be reduced without reducing the switching voltage. In this way, the deadlock between on-resistance (R _on ), switching voltage (threshold voltage, V _th ), and tripartite trade-off (tripartite trade-off) can be lifted.

FIGS. 1-5 are schematic cross-sectional views illustrating various intermediate stages of an exemplary method for forming the semiconductor device 10 of FIG. 6, according to some embodiments.

FIG. 1 illustrates the initial steps of a method of forming a semiconductor device 10 according to an embodiment of the present invention. As shown in Figure 1, a substrate 100 is provided. Next, a buffer layer 104 is formed on the substrate 100, a channel layer 106 is formed on the buffer layer 104, and a barrier layer 108 is formed on the channel layer 106. In some embodiments, a nucleation layer 102 may be formed between the substrate 100 and the buffer layer 104, as shown in FIG. 1.

The above-mentioned substrate 100 may be or include a bulk semiconductor (bulk semiconductor) substrate, a semiconductor-on-insulator (SOI) substrate or the like, which may be doped (for example, using p-type or n-type Dopant) or undoped. Generally speaking, the semiconductor-on-insulator substrate includes a film layer of semiconductor material formed on the insulator. For example, the insulating layer can be a silicon oxide (silicon oxide) layer, a silicon nitride (silicon nitride) layer, a poly-silicon (poly-silicon) layer, or a stack combination of the above-mentioned film layers. The above-mentioned insulating layer is provided on a substrate, which is usually a silicon or aluminum nitride (AlN) substrate. Other substrates, such as multi-layered or gradient substrates, can also be used. In some embodiments, the semiconductor material of the semiconductor substrate may include silicon with different crystal planes, including Si(111) or Si(110). In some embodiments, the substrate 100 may be a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a sapphire (Sapphire) substrate.

The above-mentioned nucleation layer 102 can alleviate the crystal lattice difference between the substrate 100 and the film layer grown thereon, so as to improve the crystal quality. The nucleation layer 102 is selective. In some embodiments, the material of the nucleation layer 102 may be or include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), other suitable materials, or a combination thereof. For example, the thickness of the nucleation layer 102 may range from about 1 nanometer (nm) to about 500 nanometers, such as about 200 nanometers. In some embodiments, the nucleation layer 102 may be formed by a deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), and molecular beam epitaxy. Crystal (Molecular Beam Epitaxy, MBE), Liquid Phase Epitaxy (LPE), other appropriate processes, or a combination of the foregoing.

The buffer layer 104 can reduce the strain of the channel layer 106 subsequently formed above the buffer layer 104 to prevent defects from being formed in the channel layer 106 above. The strain is caused by the mismatch between the channel layer 106 and the substrate 102. In other embodiments, as mentioned previously, the nucleation layer 102 may not be provided, and the buffer layer 104 may be formed directly on the substrate to simplify the process steps and achieve improved effects. In some embodiments, the material of the buffer layer 104 may include a group III-V compound semiconductor material, such as a group III nitride. For example, the material of the buffer layer 104 may be or include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), or other suitable materials. , Or a combination of the foregoing. For example, the thickness of the buffer layer 104 may range from about 500 nanometers to about 50,000 nanometers. In some embodiments, the buffer layer 104 may be formed by a deposition process, such as metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE) , Other appropriate manufacturing processes, or a combination of the above.

The piezoelectric polarization effect and the respective spontaneous polarization induced by the different lattice constants between the channel layer 106 and the barrier layer 108 can be between the channel layer 106 and the barrier layer 108 Two-dimensional electron gas (2DEG) (not shown) is formed on the heterogeneous interface. The semiconductor device 10 shown in FIG. 6 is a high electron mobility transistor (HEMT) that uses a two-dimensional electron gas (2DEG) as a conductive carrier. In some embodiments, there are no dopants in the channel layer 106 and the barrier layer 108. In some other embodiments, the channel layer 106 and the barrier layer 108 may have dopants, such as n-type dopants or p-type dopants. In a specific embodiment of the present invention, the channel layer 106 serves as the source of the two-dimensional electron gas by its own unintentional doping. For example, the aforementioned unintentional doping may be defects in the background, free donors, and the like. In some embodiments, the dopant concentration of the aforementioned non-intentional doping is in the range of about 5× ^{10 16} to about 5× ^{10 17} cm ⁻³ .

In some embodiments, the material of the channel layer 106 may include one or more group III-V compound semiconductor materials, such as group III nitrides. For example, the material of the channel layer 106 may be or include GaN, AlGaN, AlInN, InGaN, InAlGaN, other suitable materials, or a combination thereof. In some embodiments, the thickness of the channel layer 106 may range between about 0.05 micrometer (micrometer, µm) and about 1 micrometer, for example, about 0.2 micrometer. According to some embodiments, the channel layer 106 may be formed by a deposition process, such as metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), Other appropriate manufacturing processes, or combinations of the above.

In some embodiments, the material of the barrier layer 108 may include a group III-V compound semiconductor material, such as a group III nitride. For example, the barrier layer 108 may be or include AlN, AlGaN, AlInN, AlGaInN, other suitable materials, or a combination thereof. The barrier layer 108 may include a single-layer or multi-layer structure. Compared with general high electron mobility transistors, the high electron mobility transistors of the embodiments of the present invention have a thicker barrier layer, so the on-resistance (R _on ) of the device can be significantly reduced. For example, the barrier layer 108 has a maximum thickness W1, and the maximum thickness W1 may be in the range of about 10 nanometers to about 60 nanometers, for example, about 40 nanometers. In some embodiments, the barrier layer 108 may be formed by a deposition process, such as metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE) ), other appropriate manufacturing processes, or a combination of the foregoing.

Continuing to refer to FIG. 1, a nitride layer 110 is formed on the barrier layer 108. The nitride layer 110 can protect the barrier layer 108 from oxidation in the subsequent process. In addition, the nitride layer 110 can also eliminate the electrical scattering problem of the device, and the details will be described later. In some embodiments, the material of the nitride layer 110 may be or include gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlGaInN), nitride Indium gallium (InGaN), other suitable materials, or a combination of the above. In some embodiments, the thickness of the nitride layer 110 may range from about 1 nanometer to about 20 nanometers, for example, about 5 nanometers. According to some embodiments, the nitride layer 110 may be formed by a deposition process, such as metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE) , Other appropriate manufacturing processes, or a combination of the above.

Next, as shown in FIG. 2, the nitride layer 110 and the barrier layer 108 are etched back to form a notch 112, wherein the notch 112 passes through the nitride layer 110 and a part of the barrier layer 108. The above-mentioned notch 112 corresponds to a position where the gate electrode 118 (not shown in FIG. 3, but can be referred to the description of FIG. 5 below) is scheduled to be formed. The notch 112 is formed so that a part of the barrier layer 108 located below the notch 112 has a reduced thickness W2. This reduced thickness W2 is located below the gate electrode 118 to be formed later (not shown in Figure 2, but refer to the description of Figure 5 below), which helps to increase the switching voltage of the device ( V _th ). In some embodiments, this reduced thickness W2 may be in the range of about 5 nanometers to about 15 nanometers, for example, about 10 nanometers.

Generally speaking, there are two main sources of two-dimensional electron gas in GaN high-electron mobility transistors, one is from the free carriers in the surface states, and the other is from the unintentional doping of the channel layer. ; And because of the heterostructure and polarization electric field between the barrier layer and the channel layer, the source of the two-dimensional electron gas is usually the former. Therefore, when the semiconductor device is in the off state, the carriers in the channel layer will be drawn by the high electric field on the surface and be confined. When the semiconductor device is switched from the off state to the on state, the carriers trapped in the channel layer 106 are too late to be released (ie, the relaxation time is too long), resulting in a decrease in current, which is the electrical property Scattering problem. In the embodiment of the present invention, since the nitride layer contains most of the free carriers from the surface state, the underlying channel layer must be unintentionally doped to absorb the carriers, thus avoiding the problem when the channel layer is closed. High electric field influence. In addition, the nitride layer 110 is cut off by the notch 112. Therefore, when the semiconductor device 10 is turned on, the nitride layer 110 will not participate in current conduction, so there will be no electrical scattering problem. In this way, the nitride layer 110 can replace the channel layer 116 to withstand the high electric field of the surface state, so as to avoid the problem of electrical scattering of the semiconductor device 10.

In some embodiments, the nitride layer 110 and the barrier layer 108 may be etched by a patterning process to form the recess 112. For example, the above-mentioned patterning process may include a photolithography process (for example, photoresist coating, soft baking, mask aligning, exposure, post-exposure baking, photoresist development, etc. Appropriate process, or a combination of the foregoing), etching process (for example, wet etching process, dry etching process, other appropriate process, or combination of the foregoing), other appropriate process, or combination of the foregoing. In some embodiments, a patterned photoresist layer (not shown) having an opening corresponding to the notch 112 may be formed on the nitride layer 110 by a lithography process, and then an etching process may be performed to remove the patterning. Part of the nitride layer 110 and the barrier layer 108 exposed by the opening of the photoresist layer to form a notch 112 in the nitride layer 110 and the barrier layer 108. Then, the patterned photoresist layer can be removed by a process such as ashing or wet stripping.

Referring to FIG. 3, the spacer layer 114 is conformably formed on the nitride layer 110 and in the notch 112, so the spacer layer 114 is conformably formed on the bottom surface and sidewalls of the notch 112. In some embodiments, the bandgap of the spacer layer 114 is larger than that of the subsequently formed compound semiconductor layer 116 (not shown in FIG. 3, but please refer to the description of FIG. 5 below). Therefore, the spacer layer 114 can prevent the dopants in the compound semiconductor layer 116 from diffusing into other components of the semiconductor device 10 to avoid an increase in on-resistance and reduce electrical scattering problems of the device. In addition, during the subsequent etching process for forming the compound semiconductor layer 116, the spacer layer 114 may also serve as an etch stop layer (ESL) to stop the etching process.

The spacer layer 114 may be formed of a material having a different etching selectivity from an adjacent film layer or member (ie, the compound semiconductor layer 116). In some embodiments, the spacer layer 114 is aluminum-containing nitride. For example, the material of the spacer layer 114 may be or include AlN, AlGaN, AlInN, AlGaInN, other suitable materials, or a combination thereof. In a specific embodiment, the spacer layer 114 is AlN. In addition, in some embodiments, the thickness of the spacer layer 114 may range from about 1 nanometer to about 7 nanometers, for example, about 2 nanometers.

FIG. 4 illustrates the formation of the compound semiconductor layer 116. In some embodiments, the compound semiconductor layer 116 is conformably formed on the spacer layer 114, and the pattern is defined by photolithography. The compound semiconductor layer has an upper portion 116a and a lower portion 116b, and the lower portion 116b of the compound semiconductor layer 116 defines The portion of the compound semiconductor layer 116 filled in the recess 112 is as shown in FIG. 4. In other words, the compound semiconductor layer 116 corresponds to the position where the gate electrode 118 (not shown in FIG. 3 is not shown, but please refer to the description of FIG. 5 below) where the gate electrode 118 is scheduled to be formed. The compound semiconductor layer 116 can suppress the generation of two-dimensional electron gas (2DEG) under the gate electrode 118 to achieve a normally-off state of the semiconductor device.

In some embodiments, the material of the compound semiconductor layer 116 may be p-type doped or n-type doped gallium nitride (GaN). For example, the thickness of the upper portion 116a of the compound semiconductor layer 116 may be in the range of about 5 to about 100 nanometers, for example, about 60 nanometers, and the thickness of the lower portion 116b of the compound semiconductor layer 116 may be about 7 to about 72 nanometers. The range is, for example, about 40 nanometers. In some embodiments, the doping concentration of the upper portion 116 a of the compound semiconductor layer 116 may be different from the doping concentration of the lower portion 116 b of the compound semiconductor layer 116.

In some embodiments, the compound semiconductor layer 116 may be formed by a deposition process and a patterning process. For example, a deposited material layer can be formed on the spacer layer 114 by a deposition process, and part of the deposited material layer is filled in the recess 112. In some embodiments, the patterning process includes forming a patterned mask layer (not shown) on the deposited material layer, and then etching the portion of the deposited material layer that is not covered by the patterned mask layer, and forming a compound semiconductor layer 116.

In some embodiments, the deposition process may include metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), similar processes, or a combination of the foregoing .

In some embodiments, the patterned mask layer may be a photoresist, such as a positive photoresist or a negative photoresist. In other embodiments, the patterned mask layer may be a hard mask, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, similar materials, or a combination of the foregoing. In some embodiments, spin-on coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), other appropriate processes, or the above To form the patterned mask layer described above.

In some embodiments, the deposited material layer may be etched by a dry etching process, a wet etching process, or a combination of the foregoing. For example, the etching of the deposited material layer includes reactive ion etch (RIE), inductively-coupled plasma (ICP) etching, neutron beam etch (NBE), Electron cyclotron resonance (ERC) etching, other suitable etching processes, or a combination of the above.

In some embodiments, the upper portion 116a of the compound semiconductor layer 116 may extend to the surface of the spacer layer 114 outside the recess, that is, the compound semiconductor layer 116 has a T-shape in the schematic cross-sectional view, as shown in FIG. 4. In other embodiments, the upper portion 116a of the compound semiconductor layer 116 does not extend to the surface of the spacer layer 114 outside the recess, and the compound semiconductor layer 116 has a rectangular shape (not shown) in the schematic cross-sectional view. In some embodiments, the upper surface of the compound semiconductor layer 116 may be uneven. In some embodiments, the length of the upper portion 116a of the compound semiconductor layer 116 extending to the surface of the spacer layer 114 outside the recess may be asymmetric.

In some embodiments, the formation of the compound semiconductor layer 116 further includes doping with dopants to increase the switching voltage (V _th ) of the semiconductor device 10. For example, if the material of the compound semiconductor layer 116 is p-type doped gallium nitride, the dopant may include magnesium (Mg). Generally speaking, during the manufacturing process of a semiconductor device, multiple heat treatments are usually performed, so that the dopant heat diffuses out of the compound semiconductor layer and enters other components, thereby affecting the performance of the semiconductor device, such as increasing the on-resistance and causing electrical The problem of sexual scattering. However, in the embodiment of the present invention, since the compound semiconductor layer 116 is separated from other components by the spacer layer 114, the dopants in the compound semiconductor layer 116 can be prevented from thermally diffusing into other components. In this way, the problem of increased on-resistance and electrical scattering of the device can be avoided, and the performance of the semiconductor device 10 can be improved.

In addition, in the embodiment of the present invention, since the barrier layer 108 located below the predetermined position of the gate electrode 118 has a reduced thickness W2 (see FIG. 5), this reduced thickness W2 helps to improve the semiconductor device 10 Switching voltage. In other words, under the same switching voltage, the compound semiconductor layer 116 can have a smaller dopant concentration, which reduces the influence of the dopant thermal diffusion to other components, which also helps to reduce the electrical scattering problem of the device.

Referring to FIG. 5, a gate electrode 118 is formed on the compound semiconductor layer 116. In some embodiments, the material of the gate electrode 118 may be or include a conductive material, such as a metal, a metal silicide, a semiconductor material, or a combination thereof. For example, the metal can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al ), copper (Cu), titanium nitride (TiN), similar materials, the above alloy, the above multilayer structure, or a combination of the above, and the semiconductor material can be polycrystalline silicon (poly-Si) or polycrystalline germanium (poly-Ge ). In some embodiments, the step of forming the gate electrode 118 may include fully depositing a conductive material layer (not shown) for the gate electrode 118 on the substrate 100, and performing a patterning process on the conductive material layer to form The gate electrode 118 is on the compound semiconductor layer 116. The deposition process for forming the conductive material may be atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD) (for example, sputtering), a combination of the foregoing, or similar processes.

Next, referring to FIG. 6, a pair of source/drain electrodes 120 are provided on both sides of the gate electrode 118, wherein the pair of source/drain electrodes 120 extend through the spacer layer 114, the nitride layer 110, and Part of the barrier layer 108. In some embodiments, the formation of the pair of source/drain electrodes 120 includes performing a patterning process to etch the spacer layer 114, the nitride layer 110, and a part of the barrier layer 108 on both sides of the compound semiconductor layer 116, A pair of notches passing through the spacer layer 114 and the nitride layer 110 and extending to the barrier layer 108 are formed, and then a conductive material is deposited over the pair of notches, and a patterning process is performed on the deposited conductive material to achieve the desired The position forms the pair of source/drain electrodes 120. The deposition process and materials used to form the pair of source/drain electrodes 120 can be similar to the deposition process and materials of the gate electrode 118, which will not be repeated here.

Although in the embodiment depicted in FIG. 6, the pair of source/drain electrodes 120 are located on the spacer layer 114, pass through the spacer layer 114 and the nitride layer 110 and extend to the barrier layer 108, the present invention is not limited to this The depth of extension of the pair of source/drain electrodes 120 can be adjusted according to the characteristics required by the actual product. For example, the pair of source/drain electrodes 120 may also pass through the barrier layer 108 and extend into the channel layer 106.

Although it is described here that the source/drain electrode 120 and the gate electrode 118 are formed in different steps, the present invention is not limited thereto. For example, before forming the gate electrode 118, a notch for the source/drain electrode 120 can be formed first, and then the source/drain electrode 120 and the gate electrode can be formed simultaneously by a deposition process and a patterning process. Electrode 118. Moreover, the formation of the source/drain electrode 120 and the gate electrode 118 may independently include the same or different processes and materials. In addition, the shape of the source/drain electrode 120 and the gate electrode 118 is not limited to the vertical sidewalls in the figure, and may also be inclined sidewalls or have other shapes.

As shown in FIG. 6, the semiconductor device 10 includes a channel layer 106 provided on the substrate 100, a barrier layer 108 provided on the channel layer 106, and a nitride layer 110 provided on the barrier layer 108. In some embodiments, the barrier layer 108 has a maximum thickness W1 ranging from about 10 nanometers to about 60 nanometers. Compared with general high electron mobility transistors, the semiconductor device 10 has a thicker barrier layer 108, so the on-resistance (R _on ) can be significantly reduced. In addition, the above-mentioned nitride layer 110 can replace the channel layer 116 to withstand the high electric field of the surface state, thereby avoiding the problem of electrical scattering of the semiconductor device 10.

The semiconductor device 10 also includes a compound semiconductor layer 116 having an upper portion 116a and a lower portion 116b, wherein the lower portion 116b passes through the nitride layer 110 and a part of the barrier layer 108. In addition, the semiconductor device 10 also includes a spacer layer 114 compliantly disposed on the lower portion 116 b of the compound semiconductor layer 116 and extending to the nitride layer 110. The spacer layer 114 can prevent the dopants in the compound semiconductor layer 116 from diffusing into other components of the semiconductor device 10, so as to avoid the increase of on-resistance and electrical scattering of the device, thereby improving the performance of the semiconductor device 10.

The semiconductor device 10 further includes a gate electrode 118 disposed on the compound semiconductor layer 116, and a pair of source/drain electrodes 120 disposed on both sides of the gate electrode 118, and the source/drain electrodes 120 extend through Pass the spacer layer 114, the nitride layer 110, and at least a part of the barrier layer 108. The barrier layer 108 has a reduced thickness W2 below the gate electrode 118 (see FIG. 5), and this reduced thickness W2 helps to increase the switching voltage (V _th ) of the semiconductor device 10. In other words, under the same switching voltage, the compound semiconductor layer 116 can have a smaller dopant concentration, which reduces the influence of the dopant thermal diffusion to other components, which also helps to reduce the electrical scattering problem of the device. In some embodiments, this reduced thickness W2 ranges from about 5 nanometers to about 15 nanometers.

In some embodiments, the semiconductor device 10 further includes a buffer layer 104 located between the substrate 100 and the channel 106. The buffer layer 104 can reduce the strain of the channel layer 106 subsequently formed above the buffer layer 104 to prevent defects. It is formed in the channel layer 106 above.

In summary, the semiconductor device of the embodiment of the present invention includes a nitride layer disposed on the barrier layer, whereby the nitride layer can eliminate the electrical dispersion problem of the semiconductor device. In this way, the deadlock between the on-resistance (R _on ), the switching voltage (V _th ), and the three-way tradeoff of electrical scattering can be lifted.

The above briefly describes the features of several embodiments of the present invention, so that those with ordinary knowledge in the technical field can more easily understand the present disclosure. Anyone with ordinary knowledge in the relevant technical field should understand that this specification can easily be used as a basis for modification or design of other structures or processes to perform the same purpose and/or obtain the same advantages as the embodiments of the present disclosure. Anyone with ordinary knowledge in the technical field can also understand that the structure or process equivalent to the above-mentioned structure or process does not deviate from the spirit and scope of this disclosure, and can be changed or substituted without departing from the spirit and scope of this disclosure. And retouch.

10: semiconductor device 100: substrate 102: nucleation layer 104: buffer layer 106: channel layer 108: barrier layer 110: nitride layer 112: notch 114: spacer layer 116: compound semiconductor layer 116a: upper part 116b: lower part 118 : Gate electrode 120: source/drain electrode W1, W2: thickness

Hereinafter, some embodiments of the present invention will be described in detail with the accompanying drawings. It should be noted that, according to standard practices in the industry, various components are not drawn to scale and are only used for illustration and illustration. In fact, the size of the element may be arbitrarily enlarged or reduced to clearly show the components of the embodiment of the present invention. FIGS. 1-5 are schematic cross-sectional views illustrating various intermediate stages of an exemplary method for forming the semiconductor device of FIG. 6, according to some embodiments.

10: Semiconductor device

100: substrate

102: Nucleation layer

104: buffer layer

106: Channel layer

108: barrier layer

110: Nitride layer

114: Interval layer

116: compound semiconductor layer

116a: upper part

116b: lower part

118: gate electrode

120: source/drain electrode

Claims (22)

A semiconductor device includes: a channel layer arranged on a substrate; a barrier layer arranged on the channel layer; a nitride layer arranged on the barrier layer; a compound semiconductor layer having An upper part and a lower part, wherein the lower part passes through the nitride layer and only a part of the barrier layer; a spacer layer is compliantly disposed on the remaining part of the barrier layer and extends to the nitride layer A gate electrode, disposed on the compound semiconductor layer; and a pair of source/drain electrodes disposed on both sides of the gate electrode, wherein the pair of source/drain electrodes extend through the spacer layer, The nitride layer and at least a part of the barrier layer. The semiconductor device described in item 1 of the scope of patent application, wherein the nitride layer includes gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlGaInN) , Indium Gallium Nitride (InGaN), or a combination of the above. In the semiconductor device described in claim 1, wherein the thickness of the nitride layer ranges from about 1 nanometer to about 20 nanometers. The semiconductor device described in claim 1, wherein the spacer layer has a bandgap larger than that of the compound semiconductor layer and the nitride layer. The semiconductor device described in item 4 of the scope of patent application, wherein the spacer layer includes aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlGaInN), Or a combination of the above. For the semiconductor device described in item 1 of the scope of the patent application, the intermediate The thickness of the interlayer ranges from about 1 nanometer to about 7 nanometers. The semiconductor device described in claim 1, wherein the pair of source/drain electrodes pass through the barrier layer and extend to the channel layer. The semiconductor device described in claim 1, wherein the barrier layer has a maximum thickness, wherein the maximum thickness ranges from about 10 nanometers to about 60 nanometers. The semiconductor device described in claim 8, wherein the remaining part of the barrier layer has a minimum thickness directly below the lower portion of the compound semiconductor layer, and the minimum thickness ranges from about 5 nanometers to about 15 nanometers Meter. The semiconductor device described in item 1 of the scope of the patent application further includes a buffer layer located between the substrate and the channel layer. According to the semiconductor device described in claim 1, wherein the upper and lower portions of the compound semiconductor layer have different doping concentrations. A method for manufacturing a semiconductor device includes: forming a channel layer on a substrate; forming a barrier layer on the channel layer; forming a nitride layer on the barrier layer; and etching the nitride layer And the barrier layer to form a notch, wherein the notch passes through the nitride layer and only a part of the barrier layer; a spacer layer is conformably formed on the nitride layer and in the notch Forming a compound semiconductor layer on the spacer layer, the compound semiconductor layer having an upper portion and a lower portion, wherein the lower portion of the compound semiconductor layer is filled in the recess; a gate electrode is formed on the compound semiconductor layer; And forming a pair of source/drain electrodes on both sides of the gate electrode, wherein the pair of source/drain electrodes The electrode extends through the spacer layer, the nitride layer and at least a part of the barrier layer. The method for manufacturing a semiconductor device as described in item 12 of the scope of the patent application, wherein the nitride layer includes gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlGaInN), indium gallium nitride (InGaN), or a combination of the above. According to the method of manufacturing a semiconductor device described in the scope of the patent application, the thickness of the nitride layer ranges from about 1 nanometer to about 20 nanometers. According to the method of manufacturing a semiconductor device described in claim 12, the spacer layer has a bandgap larger than that of the compound semiconductor layer and the nitride layer. According to the method of manufacturing a semiconductor device described in item 15 of the scope of the patent application, the spacer layer includes aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInN) AlGaInN), or a combination of the above. According to the method of manufacturing a semiconductor device described in claim 12, the thickness of the spacer layer ranges from about 1 nanometer to about 7 nanometers. According to the manufacturing method of the semiconductor device described in claim 12, the pair of source/drain electrodes pass through the barrier layer and extend to the channel layer. According to the method of manufacturing a semiconductor device described in claim 12, the barrier layer has a maximum thickness, and the maximum thickness ranges from about 10 nanometers to about 60 nanometers. According to the method of manufacturing a semiconductor device described in claim 19, wherein the etched portion of the barrier layer has a minimum thickness directly below the notch, and the minimum thickness ranges from about 5 nm to about 15 nm Meter. As described in item 12 of the scope of patent application, the method for manufacturing a semiconductor device further includes forming a buffer layer between the substrate and the channel layer. According to the method of manufacturing a semiconductor device described in claim 12, the upper and lower portions of the compound semiconductor layer have different doping concentrations.

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