TW202021126A - Semiconductor devices and methods for fabricating the same - Google Patents

Abstract

A semiconductor device includes a channel layer, a first barrier layer, a second barrier layer, a source electrode, a drain electrode and a gate structure. The channel layer, the first barrier layer, the second barrier layer sequentially stacked over a substrate. The source electrode, a drain electrode and the gate structure at least extend through a portion of the second barrier layer. The source electrode, a drain electrode and the gate structure have respective bottom surfaces located at substantially the same level and adjacent to the first barrier layer.

Description

Semiconductor device and its manufacturing method

The present invention relates to semiconductor devices, and in particular to high electron mobility transistors and methods of manufacturing the same.

GaN-based semiconductor materials have many excellent material characteristics, such as high heat resistance, wide band-gap, and high electron saturation rate. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light emitting diode (LED) devices and high-frequency devices, such as high electron mobility transistors (HEMTs) with heterointerface structures ).

The on-resistance (R _on ) is an important factor affecting the power consumption of the semiconductor device, and its resistance value is proportional to the power consumption of the semiconductor device. The on-resistance (R _on ) includes source/drain contact resistance (R _contact ) and channel resistance (R _channel ). High Electron Mobility Transistor (HEMT) Two-dimensional electron gas (2DEG) with high electron mobility and high carrier density is formed on the heterogeneous interface, so that the high electron mobility transistor (HEMT) has Low channel resistance (R _channel ). The size of the source/drain contact resistance (R _contact ) of the high electron mobility transistor (HEMT) will affect the overall performance of the _on- resistance (R _on ).

With the development of GaN-based semiconductor materials, these use of nitride Semiconductor devices of gallium-based semiconductor materials are used in more severe working environments, such as higher frequencies, higher temperatures, or higher voltages. Therefore, the process conditions for GaN-based semiconductor devices also face many new challenges.

Some embodiments of the present invention provide a semiconductor device including a channel layer disposed on a substrate, a first barrier layer disposed on the channel layer, and a second resistor disposed on the first barrier layer Barrier. The semiconductor device further includes a source electrode extending at least through a portion of the second barrier layer, a drain electrode, and a gate structure interposed between the source electrode and the drain electrode. The source electrode, the drain electrode, and the gate structure have respective bottom surfaces located at approximately the same level and adjacent to the first barrier layer.

Some embodiments of the present invention provide a method for manufacturing a semiconductor device. The method includes sequentially forming a channel layer, a first barrier layer, and a second barrier layer on a substrate, and etching the second barrier layer and the first barrier A barrier layer to form a source recess, a drain recess, and a gate recess between the source recess and the drain recess at least through a portion of the first barrier layer, and the source recess and the drain recess The source electrode, the drain electrode, and the gate structure are respectively formed in the gate depression. The source recess, the drain recess, and the gate recess have respective bottom surfaces located at approximately the same level.

In order to make the features and advantages of the present invention more comprehensible, some embodiments are given below, and in conjunction with the accompanying drawings, detailed descriptions are as follows.

10A, 10B, 100, 200, 300 ‧‧‧ semiconductor device

12, 102‧‧‧ base

14, 104‧‧‧ buffer layer

16, 106‧‧‧ Channel layer

18.110‧‧‧Second barrier layer

20A, 20B, 114‧‧‧Source depression

22A, 22B, 116‧‧‧ Jiji depression

24A, 24B, 118‧‧‧ Gate depression

26A, 26B, 122 ‧‧‧ source electrode

28A, 28B, 124‧‧‧ Drain electrode

30A, 30B, 130 ‧‧‧ gate structure

50A‧‧‧District 1

50B‧‧‧District 2

108‧‧‧The first barrier layer

112‧‧‧cover

120‧‧‧lining

126‧‧‧dielectric layer

128‧‧‧Gate electrode

132‧‧‧Interlayer dielectric layer

134‧‧‧Contact

D1, D1’‧‧‧ First etching depth

D2, D2’‧‧‧Second etching depth

D3, D4‧‧‧ size

Through the following detailed description and examples in conjunction with the accompanying drawings, the embodiments of the present invention can be better understood. In order to make the diagram clear, the diagrams are different The elements may not be drawn to scale, wherein: FIG. 1 is a schematic cross-sectional view of a semiconductor device in different regions of a substrate according to some embodiments of the present invention.

2A-2G are schematic cross-sectional views illustrating various stages of forming a semiconductor device according to some embodiments of the present invention.

3 and 4 are schematic cross-sectional views of semiconductor devices according to other embodiments of the present invention.

The following disclosure provides many embodiments or examples for implementing different elements of the provided semiconductor device. Specific examples of components and their configurations are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the first element is formed on the second element in the description, it may include an embodiment where the first and second elements are in direct contact, or may include additional elements formed between the first and second elements , So that they do not directly contact the embodiment. In addition, the embodiments of the present invention may repeat reference numerals and/or letters in different examples. This repetition is for conciseness and clarity, not for expressing the relationship between the different embodiments discussed.

Some variations of the embodiments are described below. In the different drawings and illustrated embodiments, similar element symbols are used to indicate similar elements. It can be understood that additional steps may be provided before, during, and after the method, and some of the described steps may be replaced or deleted for other embodiments of the method.

Please refer to FIG. 1, which is a schematic cross-sectional view of a semiconductor device 10A and a semiconductor device 10B in different regions of a substrate 102 according to some embodiments of the present invention. In this embodiment, the semiconductor devices 10A and 10B are high electrons Mobility Transistor (HEMT).

Referring to FIG. 1, a substrate 12 is provided. The substrate 12 includes multiple regions, for example, a first region 50A and a second region 50B. Although not shown, the substrate 12 may include any other area. The buffer layer 14, the channel layer 16, and the barrier layer 18 are formed on the substrate 12 in this order. The heterogeneous interface between the channel layer 16 and the barrier layer 18 can generate two-dimensional electron gas (2DEG) as conductive carriers of the semiconductor devices 10A and 10B. In some embodiments, the material of the channel layer 16 may be a binary group III-V compound semiconductor, such as GaN. The material of the barrier layer 18 may be a ternary III-V compound semiconductor, such as AlGaN. Generally speaking, two-dimensional electron gas (2DEG) exists in the lateral direction parallel to the heterogeneous interface, but hardly exists in the longitudinal direction perpendicular to the heterogeneous interface.

Next, through the first etching process, the source recess 20A and the drain recess 22A are formed in the first region 50A, and the source recess 20B and the drain recess 22B are formed in the second region 50B. The source recesses 20A, 20B and the drain recesses 22A, 22B pass through the barrier layer 18 and extend into the channel layer 16. The source recess 20A and the drain recess 22A in the first region 50A have a first etching depth D1, and the source recess 20B and the drain recess 22B in the second region 50B have a first etching depth D1'. The etching depth in different regions of the substrate 12 has a certain degree of variation (ie, etching depth uniformity), for example, the first etching depth D1 in the first region 50A may not be equal to the first etching depth D1' in the second region 50B , This mainly depends on the ability of the etching process.

Next, the source electrode 26A and the drain electrode 28A are formed in the source recess 20A and the drain recess 22A, respectively, and the source electrode 26B and the drain electrode 28B are formed in the source recess 20B and the drain recess 22B, respectively.

Next, through the second etching process, a gate recess 24A is formed on the first In one area 50A, the gate recess 24B is in the second area 50B. The gate recesses 24A and 24B pass through the barrier layer 18 and extend into the channel layer 16. The gate recess 24A of the first region 50A has a second etching depth D2, and the gate recess 24B of the second region 50B has a second etching depth D2'. Similarly, the second etch depth D2 in the first region 50A may not be equal to the second etch depth D2' in the second region 50B.

Next, a gate structure 30A is formed in the gate recess 24A, and a gate structure 30B is formed in the gate recess 24B. After forming the gate structures 30A and 30B, the semiconductor devices 10A and 10B are formed.

It is worth noting that when the semiconductor device is operating, current E or E'flows from the drain electrode to the source electrode. Two-dimensional electron gas (2DEG) is almost absent in the longitudinal path of current E or E'(dashed line), which leads to an increase in the contact resistance (Rc) of the drain and source of the semiconductor device, which together leads to the overall conduction of the semiconductor device The resistance (R _on ) increases.

Furthermore, the source recess and the drain recess are formed by the first etching process, and the gate recess is formed by the second etching process, so that the bottom surfaces of the formed source and drain electrodes and the bottom surface of the gate electrode may not be located at the same On the level. The difference in level of the bottom surface causes a channel coupling effect, which further increases the channel resistance (R _channel ) of the semiconductor device. Furthermore, the two etching processes have respective etching uniformities, which leads to an increase in the difference in channel resistance (R _channel ) between semiconductor devices in different regions (eg, semiconductor device 10A and semiconductor device 10B), thereby reducing the semiconductor device Manufacturing stability.

FIGS. 2A-2G are schematic cross-sectional views illustrating various stages of the process of forming the semiconductor device 100 shown in FIG. 2G according to some embodiments of the present invention. In the embodiment of FIGS. 2A-2G, the source recess, the drain recess, and the gate recess are simultaneously formed through an etching process to have respective bottom surfaces located at approximately the same level. Therefore, the channel coupling effect is avoided, and the channel resistance (R _channel ) of the semiconductor device is reduced, and the difference in channel resistance (R _channel ) between semiconductor devices in different regions is reduced.

Please refer to FIG. 2A to provide the substrate 102. In some embodiments, the substrate 102 may be a doped (eg, doped with p-type or n-type dopant) or an undoped semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, or a similar semiconductor substrate. In some embodiments, the substrate 102 may be a semiconductor-on-insulator substrate, such as a silicon on insulator (SOI) substrate. In some embodiments, the substrate 102 may be a glass substrate or a ceramic substrate, such as a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a sapphire (Sapphire) substrate.

A buffer layer 104, a channel layer 106, a first barrier layer 108, a second barrier layer 110, and a cap layer 112 are formed on the substrate 102 in this order. In some embodiments, a seed layer (not shown) may be formed between the substrate 102 and the buffer layer 104.

The buffer layer 104 can reduce the strain of the channel layer 106 formed subsequently on the buffer layer 104 to prevent defects from being formed in the channel layer 106. The strain is caused by the mismatch between the channel layer 106 and the substrate 102. In some embodiments, the material of the buffer layer 104 may include or be AlN, GaN, AlGaN, AlInN, a combination of the foregoing, or similar materials. The buffer layer 104 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing, or similar methods. Although the buffer layer 104 has a single-layer structure in the embodiment shown in FIG. 1A, the buffer layer 104 may have a multi-layer structure. In addition, in some embodiments, the material of the buffer layer 104 is determined by the material of the seed layer and the gas introduced during the epitaxial process set.

In some embodiments, the material of the channel layer 106 may include a binary group III-V compound semiconductor material, for example, a group III nitride. In some embodiments, the material of the channel layer 106 is GaN. In some embodiments, the thickness of the channel layer 106 may range from about 0.01 micrometer (μm) to about 10 micrometers. In some embodiments, the channel layer 106 may have dopants, such as n-type dopants or p-type dopants. The channel layer 106 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing, or similar methods.

In some embodiments, the material of the first barrier layer 108 may include a binary group III-V compound semiconductor material, such as aluminum nitride (AlN). In some embodiments, the first barrier layer 108 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), Combination of the foregoing, or similar methods. In some embodiments, the thickness of the first barrier layer 108 is in the range of about 0.5 nanometer (nm) to about 10 nanometers, for example, 2 nanometers. The first barrier layer 108 can also serve as an etch stop layer, which will be described later.

In some embodiments, the material of the second barrier layer 110 may include a ternary group III-V compound semiconductor, for example, a group III nitride. In some embodiments, the material of the second barrier layer 110 may be AlGaN, AlInN, or a combination of the foregoing. In some embodiments, the second barrier layer 110 may have dopants, such as n-type dopants or p-type dopants. The second barrier layer 110 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing, or the like method . In some embodiments, the thickness of the second barrier layer 110 is greater than the thickness of the first barrier layer 108, and the thickness of the second barrier layer 110 is in the range of about 1 nanometer to about 80 nanometers.

Through the spontaneous polarization and piezoelectric polarization effects caused by different energy bands between the channel layer 106 and the first and second barrier layers 108 and 110, a two-dimensional electron gas (2DEG) (not shown) is formed on the channel layer 106 On the hetero interface with the first barrier layer 108. The semiconductor device 100 shown in FIG. 2G is a high electron mobility transistor (HEMT) using two-dimensional electron gas (2DEG) as a conductive carrier. In addition, compared to the ternary ternary compound semiconductor, the material selection of the first barrier layer 108 is the ternary ternary compound semiconductor, which can cause lower alloy scattering and can form a two-dimensional electron gas (2DEG). It has a higher electron mobility to reduce the channel resistance (R _channel ) of semiconductor devices.

In some embodiments, the material of the capping layer 112 may include or be gallium nitride (GaN), such as undoped gallium nitride. In some embodiments, the cap layer 112 is disposed on the second barrier layer 110 to prevent the surface of the second barrier layer 110 containing aluminum (Al) from oxidizing. In some embodiments, the thickness of the cap layer 112 is in the range of about 1 nanometer to about 100 nanometers. In some embodiments, the cap layer 112 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing , Or similar methods.

In some embodiments, the buffer layer 104, the channel layer 106, the first barrier layer 108, the second barrier layer 110, and the cap layer 112 may be deposited in-situ in the same deposition chamber.

Next, the cap layer 112, the second barrier layer 110, and the first barrier The layer 108 performs a patterning process.

Referring to FIG. 2B, the capping layer 112, the second barrier layer 110, and the first barrier layer 108 are etched through the patterning process to form the capping layer 112, the second barrier layer 110, and the first resistance The source recess 114, the drain recess 116, and the gate recess 118 of the barrier layer 108 are between the source recess 114 and the drain recess 116. After the patterning process, the source recess 114, the drain recess 116, and the gate recess 118 expose the upper surface of the portion of the channel layer 106.

In some embodiments, the patterning process performed on the cap layer 112, the second barrier layer 110, and the first barrier layer 108 includes forming a patterned mask layer (not shown) on the cap layer 112, wherein the pattern The mask layer has an opening that exposes a portion of the upper surface of the cap layer 112, and an etching process is performed on the cap layer 112, the second barrier layer 110, and the first barrier layer 108 through the patterned mask layer opening to remove the cap The portions of the layer 112, the second barrier layer 110, and the first barrier layer 108 that are not covered by the patterned mask layer to form the source recess 114, the drain recess 116, and the gate recess 118 at the same time, and then removed The mask layer is patterned, for example, through an ashing process or a stripping process. In some embodiments, the etching process may be a dry etching process, such as reactive ion etching (RIE), electron cyclotron resonance (ERC) etching, or inductively-coupled plasma , ICP) etching, neutron beam etching (neutral beam etch, NBE), a combination of the foregoing, or a similar dry etching process.

In the embodiment of the present invention, the source recess 114, the drain recess 116, and the gate recess 118 are simultaneously formed through an etching process, so that the source recess 114, the drain recess 116, and the gate recess 118 may have substantially the same The respective bottom surface of the level.

Here, the term "approximately the same level" means that the difference in the level of the bottom surface of these depressions 114, 116, 118 is within a range of 2 nm, or within a range of 1 nm, or within a range of 0.5 nm. Or, the phrase "approximately the same level" means that the difference in the level of the bottom surfaces of these recesses 114, 116, 118 is within 5% of the depth of the recess 114.

The first barrier layer 108 may serve as an etch stop layer. For example, in some embodiments, the first barrier layer 108 includes aluminum nitride (AlN), and the second barrier layer 110 includes aluminum gallium nitride (AlGaN). In the etching process, the second barrier layer 110 has a higher etching speed than the first barrier layer 108. For example, in an etching process performed with Cl ₂ or SF ₆ as an etchant, the ratio of the etching rate of the second barrier layer 110 to the etching rate of the first barrier layer 108 is in the range of about 1.5 to about 50 . The first barrier layer 108 slows down the etching rate of the etching process to control where the bottom surfaces of the source recess 114, the drain recess 116, and the gate recess 118 stop. Therefore, after the etching process, the source recess 114, the drain recess 116, and the gate recess 118 just pass through the first barrier layer 108, but do not extend into the channel layer 106. In other words, the horizontal height of the respective bottom surfaces of the source recess 114, the drain recess 116, and the gate recess 118 is equal to the horizontal height of the bottom surface of the first barrier layer 108.

Although the embodiment in FIG. 2B shows that these recesses 114, 116, and 118 just pass through the first barrier layer 108, but do not extend into the channel layer 106, the embodiments of the present invention are not limited thereto. In other embodiments, these recesses 114, 116, 118 may extend slightly into the channel layer 106 (as shown in FIG. 3). In other embodiments, the recesses 114, 116, and 118 may only pass through a portion of the first barrier layer 108 without exposing the channel layer 106 (as shown in FIG. 4).

Please refer to FIG. 2C, on the upper surface of the cap layer 112 and the source electrode is concave The liner 120 is conformally formed in the recess 114, the drain recess 116, and the gate recess 118. The liner 120 is compliantly formed on the bottom and side walls of the source recess 114, the bottom and side walls of the drain recess 116, and the bottom and side walls of the gate recess 118, and partially fills the source recess 114 and the drain recess 116, and the gate depression 118. In some embodiments, the thickness of the liner 120 may be in the range of about 0.5 nanometers to about 4 nanometers, such as 2 nanometers. In some embodiments, the material of the liner layer 120 may include or be a binary compound semiconductor of a hexagonal crystal system (for example, aluminum nitride (AlN), zinc oxide (ZnO), indium nitride ( InN), the aforementioned combination, or similar materials, and can form a liner layer 120 on the substrate 102 through atomic layer deposition (ALD) or epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD).

Please refer to FIG. 2D, the source electrode 122 and the drain electrode 124 are formed on the liner layer 120 in the respective remaining portions of the source recess 114 and the drain recess 116. The source electrode 122 has an upper portion located above the upper surface of the cap layer 112 and a lower portion located in the source recess 114. The drain electrode 124 has an upper portion above the upper surface of the cap layer 112. And the lower portion located in the dip recess 116.

In some embodiments, the materials of the source and drain electrodes 122 and 124 may include or be conductive materials, such as metals, metal silicides, semiconductor materials, or a combination of the foregoing. The metal can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper ( Cu), titanium nitride (TiN), the aforementioned combination, the aforementioned alloy, or the aforementioned multilayer. The semiconductor material may be polycrystalline silicon or polycrystalline germanium. In some embodiments, the step of forming the source and drain electrodes 122 and 124 may include depositing a conductive material (not shown) for the source and drain electrodes 122 and 124 on the substrate 102 and filling the source recess 114 and Jiji depression In the remaining part of 116, a patterning process is performed on the conductive material to form source and drain electrodes 122 and 124. The deposition process for forming the conductive material may be atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), such as sputtering, a combination of the foregoing, or a similar process.

Referring to FIG. 2E, a dielectric layer 126 is compliantly formed on the liner layer 120 in the remaining portion of the gate recess 118 as a gate dielectric layer. The dielectric layer 126 is also formed on the liner layer 120 above the upper surface of the cap layer 120. The dielectric layer 126 is also formed on the upper surface and sidewalls of the source electrode 122 and the upper surface and sidewalls of the drain electrode 124. In some embodiments, the material of the dielectric layer 126 may include or be silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), hafnium oxide (HfO ₂ ), the aforementioned combination, the aforementioned multiple layers, or similar materials, and may be through atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), such as sputtering, on the substrate 102 The dielectric layer 126 is formed comprehensively.

Referring to FIG. 2F, a gate electrode 128 is formed on the dielectric layer 126 in the remaining portion of the gate recess 118. The gate electrode 128 has an upper portion located above the upper surface of the cap layer 112 and a lower portion located in the gate recess 118. The gate electrode 128 and the dielectric layer 126 together serve as the gate structure 130. In some embodiments, the material of the gate electrode 128 may include or be a conductive material, such as metal, metal silicide, semiconductor material, or a combination of the foregoing. The metal can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper ( Cu), titanium nitride (TiN), the aforementioned combination, the aforementioned alloy, or the aforementioned multilayer. The semiconductor material may be polycrystalline silicon or polycrystalline germanium. The step of forming the gate electrode 128 may include depositing a conductive material layer (not shown) for the gate electrode 128 on the substrate 102 and performing a patterning process on the conductive material layer to form the gate electrode Electrode 128. The deposition process for forming the conductive material may be atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), such as sputtering, a combination of the foregoing, or a similar process.

Referring to FIG. 2G, an interlayer dielectric (ILD) 132 is formed on the substrate 102, and the interlayer dielectric layer 132 covers the gate structure 130, the source electrode 122, and the drain electrode 124. Next, a plurality of contacts 134 are formed in the interlayer dielectric layer 132. These contacts 134 are electrically connected to the gate structure 130, the source electrode 122 and the drain electrode 124, respectively.

In some embodiments, the material of the interlayer dielectric layer 132 may be silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, a combination of the foregoing, the foregoing multilayer, or the like. An interlayer dielectric layer can be formed on the substrate 102 by chemical vapor deposition (CVD), such as plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or similar methods 132.

In some embodiments, the material of the contact 134 may be a metal material, such as gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr ), tungsten (W), aluminum (Al), copper (Cu), a combination of the foregoing, or a multilayer of the foregoing. The step of forming the contact 134 may include forming a plurality of openings (not shown) corresponding to the source electrode 122, the drain electrode 124, and the gate electrode 128 through the patterning process, which pass through the interlayer dielectric layer 132 and the source The dielectric layer 126 above the electrode 122, the drain electrode 124, and a portion of the upper surface of the source electrode 122, the drain electrode 124, and the gate electrode 128 are exposed, and a metal material (not shown) is deposited on the interlayer dielectric The layer 132 is filled with these openings, and a planarization process such as chemical mechanical polish (CMP) is performed to remove the metal material above the interlayer dielectric layer 130.

After forming the interlayer dielectric layer 132 and the contact 134, the semiconductor device 100 is formed. The semiconductor device 100 may also be referred to as a metal-insulator-semiconductor field effect transistor (MIS-FET).

In the embodiment shown in FIGS. 2A-2G, the semiconductor device 100 includes a channel layer 106, a first barrier layer 108, and a second barrier layer 110 sequentially stacked on the substrate 102. The semiconductor device 100 further includes a source electrode 122, a drain electrode 124, and a gate structure 130 interposed between the source electrode 122 and the drain electrode 124. The source electrode 124, the drain electrode 124, and the gate structure 130 extend at least through a portion of the second barrier layer 110. The source electrode 124, the drain electrode 124, and the gate structure 130 have respective bottom surfaces located at approximately the same level. The semiconductor device 100 further includes a liner layer 120 compliantly disposed on the respective lower portions of the source electrode 122, the drain electrode 124, and the gate structure 130. The horizontal height of the bottom surface of the liner layer 120 is equal to the horizontal height of the bottom surface of the first barrier layer 108.

In the embodiment shown in FIGS. 2A-2G, the recesses 114, 116, and 118 for forming the source electrode 122, the drain electrode 124, and the gate structure 130 pass through the first and second barrier layers 108 and 110, so that the heterogeneous interface between the first barrier layer 108 and the channel layer 106 does not exist in this area, and the formed source electrode 122, the drain electrode 124, and the gate structure 130 are reduced or eliminated Two-dimensional electron gas (2DEG). It is worth noting that since the liner layer 120 includes a hexagonal binary compound semiconductor, and the liner layer 120 is formed between the source electrode 122, the drain electrode 124, and the bottom of the gate structure 130 and the channel layer 106, the liner layer The spontaneous polarization and piezoelectric polarization effects can be induced between the layer 120 and the channel layer 106 to restore the 2D electron gas (2DEG) reduced by the disappearance of the aforementioned heterogeneous interface. Therefore, the liner layer 120 can serve as a two-dimensional electron gas recovery (2DEG recovery) layer to improve the contact resistance (R _contact ) between the source electrode 122 and the drain electrode 124 and the channel layer 106, and improve the underside of the gate structure 130 On resistance (R _on ).

In addition, in the embodiment shown in FIGS. 2A-2G, the source recess 114, the drain recess 116, and the gate recess 118 are simultaneously formed through an etching process, which reduces the channel resistance between semiconductor devices in different regions ( R _channel ), which further improves the manufacturing stability of semiconductor devices. Furthermore, reducing the patterning process to form the gate recesses not only improves the manufacturing efficiency of the semiconductor device, but also reduces the damage of chemicals (such as photoresist or developer in the patterning process) to the gate structure, thereby improving the semiconductor device 100 effectiveness.

Furthermore, the source recess 114, the drain recess 116, and the gate recess 118 have respective bottom surfaces at approximately the same level, which avoids the channel coupling effect described in FIG. 1 and reduces the semiconductor device Channel resistance (R _channel ) to further improve the performance of the semiconductor device 100.

Furthermore, a first barrier layer 108 is provided between the channel layer 106 and the second barrier layer 110 as an etch stop layer, so that the respective bottom surfaces of the source recess 114, the drain recess 116, and the gate recess 118 are The horizontal height is equal to the horizontal height of the bottom surface of the first barrier layer 108. Therefore, when the semiconductor device 100 is operating, the current E flowing from the drain electrode 124 to the source electrode 122 may be a horizontal path parallel to the heterointerface, and hardly have a longitudinal path perpendicular to the heterointerface, which further reduces the semiconductor device 100 The channel resistance (R _channel ).

The embodiment shown in FIGS. 2A-2G is an example, and the embodiment of the present invention is not limited thereto. In addition to the embodiments shown in FIGS. 2A-2G described above, the method of the embodiments of the present invention can also be applied to other semiconductor devices.

FIG. 3 is a schematic cross-sectional view of a semiconductor device 200 according to some other embodiments of the present invention, in which components identical to those in the foregoing embodiments of FIGS. 2A-2G are denoted by the same reference numerals and their descriptions are omitted. The difference between the embodiment shown in FIG. 3 and the previous embodiment shown in FIG. 2G is that the bottom surface of liner 120 in source recess 114, drain recess 116, and gate recess 118 in FIG. 3 is horizontal The height is lower than the horizontal height of the bottom surface of the first barrier layer 108.

Please refer to FIG. 3, through a patterning process similar to the aforementioned FIG. 2B, the capping layer 112, the second barrier layer 110, the first barrier layer 108, and the channel layer 106 are etched to form the source recess 114, The drain recess 116 and the gate recess 118 pass through the capping layer 112, the second barrier layer 110, and the first barrier layer 108, and further extend into the channel layer 106 to a dimension D3, for example, about 1 nanometer Meters to about 50 nanometers.

In the embodiment of FIG. 3, the horizontal heights of the respective bottom surfaces of the source recess 114, the drain recess 116, and the gate recess 118 are slightly lower than the horizontal height of the bottom surface of the first barrier layer 108. Therefore, when the semiconductor device 200 is operating, the current E flowing from the drain electrode 124 to the source electrode 122 has a vertical path perpendicular to the hetero interface, so that the channel resistance (R _channel ) of the semiconductor device 200 is slightly higher than that shown in FIG. 2G Channel resistance of the semiconductor device 100. However, the etching process extends the recesses 116, 118, and 120 into the channel layer 106 to create a deeper etching depth, so that the recesses 116, 118, and 120 in different regions of the substrate 102 can have better etching depth uniformity ( That is, the value of uniformity is lower). The better uniformity of the etching depth can reduce the difference in the channel resistance (R _channel ) of the semiconductor device between different regions of the substrate 102, thereby improving the manufacturing stability of the semiconductor device.

Figure 4 is a semiconductor device according to other embodiments of the present invention A schematic cross-sectional view of the device 300, wherein the same components as those in the foregoing embodiments of FIGS. 2A-2G are denoted by the same reference numerals and their description is omitted. The difference between the embodiment shown in FIG. 4 and the previous embodiment shown in FIG. 2G is that the bottom surface of the liner 120 in the source recess 114, the drain recess 116, and the gate recess 118 in FIG. 4 is horizontal The height is higher than the horizontal height of the bottom surface of the first barrier layer 108. In detail, the horizontal height of the bottom surfaces of the recesses 114, 116, and 118 is between the bottom surface and the upper surface of the first barrier layer 108.

Please refer to FIG. 4, through a patterning process similar to the aforementioned FIG. 2B, the capping layer 112, the second barrier layer 110, and the first barrier layer 108 are etched to form the source recess 114 and the drain recess 116 , And the gate recess 118, which passes through the capping layer 112, the second barrier layer 110, and part of the first barrier layer 108. The bottom surfaces of these recesses 114, 116, and 118 stop in the first barrier layer 108, and the portion of the first barrier layer 108 below these recesses 114, 116, and 118 has a dimension D4, for example, about 0.5 nm to about 5 Nano range. After the etching process of the patterning process, the bottom surfaces of the source recess 114, the drain recess 116, and the gate recess 118 are higher than the horizontal height of the bottom surface of the first barrier layer 108.

In summary, in the embodiment of the present invention, the source recess, the drain recess, and the gate recess are simultaneously formed through an etching process to have respective bottom surfaces located at approximately the same level. Therefore, the channel coupling effect is avoided, and the channel resistance (R _channel ) of the semiconductor device is reduced, and the difference in channel resistance (R _channel ) between semiconductor devices in different regions is reduced.

In addition, in the embodiment of the present invention, the liner provided on the bottom of the source electrode, the drain electrode, and the gate electrode can restore or enhance the two-dimensional electron gas under the source electrode, the drain electrode, and the gate electrode (2DEG), thereby reducing the on-resistance (R _on ) and channel resistance (R _channel ) of the semiconductor device.

Several embodiments are summarized above, so that those with ordinary knowledge in the technical field to which the present invention belongs can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and they can do so without departing from the spirit and scope of the present invention, Do all kinds of changes, substitutions, and replacements.

100‧‧‧Semiconductor device

102‧‧‧ base

104‧‧‧buffer layer

106‧‧‧Channel layer

108‧‧‧The first barrier layer

110‧‧‧The second barrier

112‧‧‧cover

114‧‧‧Source depression

116‧‧‧ Jiji depression

118‧‧‧Gate depression

120‧‧‧lining

122‧‧‧Source electrode

124‧‧‧Drain electrode

126‧‧‧dielectric layer

128‧‧‧Gate electrode

130‧‧‧Gate structure

132‧‧‧Interlayer dielectric layer

134‧‧‧Contact

Claims (20)

A semiconductor device includes: a channel layer disposed on a substrate; a first barrier layer disposed on the channel layer; a second barrier layer disposed on the first barrier layer; And a source electrode, a drain electrode, and a gate structure interposed between the source electrode and the drain electrode, extending at least through a portion of the second barrier layer, wherein the source electrode, The drain electrode and the gate structure have respective bottom surfaces located at approximately the same level and adjacent to the first barrier layer. The semiconductor device as described in item 1 of the patent application scope further includes: a liner layer compliantly disposed on the respective lower portions of the source electrode, the drain electrode, and the gate structure, wherein the liner layer The horizontal height of the bottom surface is equal to or lower than the horizontal height of the bottom surface of the first barrier layer. The semiconductor device as described in item 2 of the patent application scope further includes: a liner layer compliantly disposed on the respective lower portions of the source electrode, the drain electrode, and the gate structure, wherein the liner layer The horizontal height of the bottom surface is higher than the horizontal height of the bottom surface of the first barrier layer. The semiconductor device as described in item 2 of the patent application range, wherein the horizontal height of the bottom surface of the liner layer is between the bottom surface and the upper surface of the first barrier layer. The semiconductor device as described in item 2 of the patent application range, wherein the liner layer is further formed on the upper surface of the second barrier layer. The semiconductor device as described in item 2 of the patent application range, wherein the material of the underlayer comprises a hexagonal crystal (binary compound semiconductor). The semiconductor device as described in item 6 of the patent application scope, wherein the binary compound The semiconductor includes aluminum nitride (AlN), zinc oxide (ZnO), or indium nitride (InN). The semiconductor device as described in item 2 of the patent application scope, wherein the gate structure includes: a dielectric layer; and a gate electrode disposed on the dielectric layer, wherein the dielectric layer is interposed between the liner layer and Between the gate electrodes. The semiconductor device as described in item 8 of the patent application range, wherein the dielectric layer is further disposed on the upper surface and the side wall of the source electrode, and the upper surface and the side wall of the drain electrode. The semiconductor device as described in item 1 of the patent application range, wherein the material of the first barrier layer is aluminum nitride (AlN). A method for manufacturing a semiconductor device includes: sequentially forming a channel layer, a first barrier layer, and a second barrier layer on a substrate; etching the second barrier layer and the first barrier Layer to form a source recess, a drain recess, and a gate recess between the source recess and the drain recess at least through a portion of the first barrier layer, wherein the source electrode The recess, the drain recess, and the gate recess have respective bottom surfaces at approximately the same level; and a source electrode, a drain, and a drain are formed in the source recess, the drain recess, and the gate recess, respectively Pole electrode, and a gate structure. The method for manufacturing a semiconductor device as described in item 11 of the patent application range, wherein the step of etching the second barrier layer and the first barrier layer includes: the second barrier layer and the first barrier layer Perform an etching process to simultaneously form the The source recess, the drain recess, and the gate recess. The method of manufacturing a semiconductor device as described in item 11 of the patent application range, wherein the respective bottom surfaces of the source recess, the drain recess, and the gate recess are equal to or lower than the first barrier layer The horizontal height of the bottom surface. The method for manufacturing a semiconductor device as described in item 11 of the patent application range, wherein the respective bottom surfaces of the source recess, the drain recess, and the gate recess are between the bottom surfaces of the first barrier layer With the upper surface. The method for manufacturing a semiconductor device as described in item 11 of the patent application scope further includes: on the bottom surface and side walls of the source recess, on the bottom surface and side walls of the drain recess, and on the bottom surface and side walls of the gate recess A lining is formed compliantly. The method for manufacturing a semiconductor device as described in item 15 of the patent application range, wherein the material of the liner layer includes a hexagonal crystal (hexagonal crystal) binary compound semiconductor. The method for manufacturing a semiconductor device as described in item 16 of the patent application range, wherein the binary compound semiconductor includes aluminum nitride (AlN), zinc oxide (ZnO), or indium nitride (InN). The method for manufacturing a semiconductor device as described in item 15 of the patent application range, wherein the step of forming the gate structure includes: conformally forming a dielectric layer on the liner layer in the gate recess; and the gate A gate electrode is formed on the dielectric layer in the pole recess. The method for manufacturing a semiconductor device as described in item 18 of the patent application range, wherein the dielectric layer is further formed on the upper surface and the side wall of the source electrode, and the The upper surface and the side wall of the drain electrode. The method for manufacturing a semiconductor device as described in item 11 of the patent application range, wherein the material of the first barrier layer is aluminum nitride (AlN).

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